{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"pyfive-mpw1-postmortem","owner":"PyFive-RISC-V","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":0,"issueCount":3,"starsCount":4,"forksCount":4,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-08-16T16:15:37.601Z"}},{"type":"Public","name":"openlane-baremetal","owner":"PyFive-RISC-V","isFork":true,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Shell","color":"#89e051"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":3,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-12-30T08:24:42.684Z"}},{"type":"Public","name":"pyfive_top_202011","owner":"PyFive-RISC-V","isFork":false,"description":"Top level for the November shuttle","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":11,"forksCount":2,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-11-20T20:03:34.009Z"}},{"type":"Public","name":"pyfive-mpw1-pcb","owner":"PyFive-RISC-V","isFork":false,"description":"Breakout carrier for the MPW1 PyFive chip","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":null,"pullRequestCount":1,"issueCount":7,"starsCount":3,"forksCount":2,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-09-29T13:20:55.413Z"}},{"type":"Public","name":"pyfive-spi","owner":"PyFive-RISC-V","isFork":false,"description":"SPI peripheral for Pyfive","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":0,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-09-15T09:22:33.021Z"}},{"type":"Public","name":"pyfive-risc-v.github.io","owner":"PyFive-RISC-V","isFork":true,"description":"Pyfive Docs","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"SCSS","color":"#c6538c"},"pullRequestCount":0,"issueCount":1,"starsCount":0,"forksCount":417,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-09-08T08:12:40.593Z"}},{"type":"Public","name":"circuitpython","owner":"PyFive-RISC-V","isFork":true,"description":"CircuitPython - a Python implementation for teaching coding with microcontrollers","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":7394,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-07-09T20:34:14.448Z"}},{"type":"Public","name":"caravel_pyfive","owner":"PyFive-RISC-V","isFork":true,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":7,"forksCount":134,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-12-20T15:08:38.609Z"}},{"type":"Public","name":"pyfive_no2usb","owner":"PyFive-RISC-V","isFork":false,"description":"OpenLane design for the no2usb core","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":5,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-11-20T22:35:25.513Z"}},{"type":"Public","name":"openlane","owner":"PyFive-RISC-V","isFork":true,"description":"OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":357,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-07-31T00:26:20.474Z"}},{"type":"Public","name":"open_pdks","owner":"PyFive-RISC-V","isFork":true,"description":"PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":83,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-07-30T21:05:58.961Z"}},{"type":"Public","name":"magic","owner":"PyFive-RISC-V","isFork":true,"description":"Magic VLSI Layout Tool","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":96,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-07-30T07:00:14.059Z"}},{"type":"Public","name":"skywater-pdk","owner":"PyFive-RISC-V","isFork":true,"description":"Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":375,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-07-28T18:57:27.719Z"}},{"type":"Public","name":"VexRiscv-netlist","owner":"PyFive-RISC-V","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-07-08T14:38:32.702Z"}},{"type":"Public","name":"pyfive","owner":"PyFive-RISC-V","isFork":false,"description":"PyFive - RISC-V libre silicon microcontroller design leveraging the new Google/SkyWater 130nm PDK","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":7,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-07-03T23:29:49.851Z"}}],"repositoryCount":15,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}