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    21 repositories

    • news

      Public
      VHDL related news.
      newsvhdl
      newsvhdl
      Python
      •0•27•31•0•Updated Sep 7, 2026Sep 7, 2026

    • pyVHDLModel

      Public
      An abstract language model of VHDL written in Python.
      pythondomvhdl
      pythondomvhdlabstractlanguage-model
      Python
      •
      Other
      •18•65•6•10•Updated Sep 2, 2026Sep 2, 2026

    • PoC

      Public
      IP Core Library - Published and maintained by the Open Source VHDL Group
      libraryasiccollection
      libraryasiccollectionfpgavhdldiamondverificationxilinxsynthesisvivado
      VHDL
      •
      Other
      •114•91•8•1•Updated Jul 14, 2026Jul 14, 2026

    • VHDLDomain

      Public
      A Sphinx domain providing VHDL language support.
      vhdlrestructured-textpython3
      vhdlrestructured-textpython3sphinx-docsphinxcontribsphinx-extension
      Python
      •
      Other
      •5•21•2•2•Updated Jul 11, 2026Jul 11, 2026

    • OSVVM

      Public
      OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
      VHDL
      •
      Other
      •75•0•0•0•Updated Jun 22, 2026Jun 22, 2026

    • OSVVM-AXI4

      Public
      AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver…
      VHDL
      •
      Other
      •27•1•0•0•Updated Jun 22, 2026Jun 22, 2026

    • OSVVM-Common

      Public
      Packages that implement OSVVM's model independent transactions and other shared verification component support packages. Required for all OSVVM verification c…
      VHDL
      •
      Other
      •12•0•0•0•Updated Jun 22, 2026Jun 22, 2026

    • OSVVM-UART

      Public
      OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verification component with error…
      VHDL
      •
      Other
      •12•0•0•0•Updated Jun 22, 2026Jun 22, 2026

    • OSVVM-Ethernet

      Public
      OSVVM Ethernet Library
      VHDL
      •
      Other
      •9•1•0•0•Updated Jun 22, 2026Jun 22, 2026

    • OSVVM-Scripts

      Public
      OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation
      Tcl
      •
      Other
      •25•0•0•0•Updated Jun 22, 2026Jun 22, 2026

    • Interfaces

      Public
      Interface definitions for VHDL-2019.
      interfacei2cvhdl
      interfacei2cvhdluartethernetrecordi2smipiaxi4axi4-lite
      VHDL
      •
      Other
      •5•36•9•1•Updated May 13, 2026May 13, 2026

    • Synchronize

      Public
      Auto Synchronize forked repositories.
      0•0•0•0•Updated Feb 16, 2026Feb 16, 2026

    • Compliance-Tests

      Public
      Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
      fpgasimulationvhdl
      fpgasimulationvhdlvunitcosimulation
      VHDL
      •
      Apache License 2.0
      •10•32•11•3•Updated Jan 30, 2025Jan 30, 2025

    • Package-Tests

      Public
      VHDL
      •
      Apache License 2.0
      •0•1•0•0•Updated Jul 20, 2023Jul 20, 2023

    • ANTLR4-Grammars

      Public
      Grammars written for ANTLR v4; expectation that the grammars are free of actions.
      ANTLR
      •
      MIT License
      •3.8k•1•0•0•Updated Jul 22, 2022Jul 22, 2022

    • PoC-Examples

      Public
      This repository contains synthesizable examples which use the PoC-Library.
      VHDL
      •
      Apache License 2.0
      •16•1•0•0•Updated Dec 24, 2020Dec 24, 2020

    • vhdl.github.io

      Public
      0•0•1•0•Updated Jul 4, 2020Jul 4, 2020

    • awesome-vhdl

      Public archive
      A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
      awesomecollectionvhdl
      awesomecollectionvhdlvhdl-libraryvhdl-collectionvhdl-ip-core
      Creative Commons Zero v1.0 Universal
      •6•85•2•1•Updated Feb 8, 2020Feb 8, 2020

    • Book

      Public
      1•3•0•0•Updated Jul 1, 2017Jul 1, 2017

    • CoreLib

      Public
      A VHDL Core Library.
      librarysimulationvhdl
      librarysimulationvhdlverificationsynthesis
      2•18•3•0•Updated Mar 29, 2017Mar 29, 2017

    • Playground

      Public
      Develop the directors structure and testing infrastructure for CoreLib
      VHDL
      •1•4•1•0•Updated Aug 26, 2016Aug 26, 2016
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