From 97acc0e154ceb32be66c284f3ebca0b591478a94 Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Fri, 28 Jun 2024 05:08:47 -0700 Subject: [PATCH] Support Gearbox peer setting --- .../apis/config_attributes.mapping.json | 27 +++ .../ModelConfig/golden/model_config.ppdb.json | 44 +++-- .../model_config_io_bitstream.backdoor.txt | 44 ++--- .../model_config_io_bitstream.detail.bit | 74 ++++---- ...el_config_io_bitstream.negative.detail.bit | 48 +++--- .../model_config_netlist.negative.ppdb.json | 115 +++++++------ .../model_config_netlist.ppdb.json | 162 +++++++++--------- tests/unittest/ModelConfig/ric/I_BUF.api.json | 14 +- .../ModelConfig/ric/I_BUF_DS.api.json | 14 +- tests/unittest/ModelConfig/ric/O_BUF.api.json | 14 +- .../unittest/ModelConfig/ric/O_BUFT.api.json | 14 +- .../ModelConfig/ric/O_BUFT_DS.api.json | 14 +- .../ModelConfig/ric/O_BUF_DS.api.json | 14 +- .../ModelConfig/ric/gbox_mode.api.json | 10 +- tests/unittest/ModelConfig/ric/gbox_top.tcl | 2 +- 15 files changed, 329 insertions(+), 281 deletions(-) diff --git a/tests/unittest/ModelConfig/apis/config_attributes.mapping.json b/tests/unittest/ModelConfig/apis/config_attributes.mapping.json index eb22d8ef6..e1c7ad684 100644 --- a/tests/unittest/ModelConfig/apis/config_attributes.mapping.json +++ b/tests/unittest/ModelConfig/apis/config_attributes.mapping.json @@ -76,8 +76,18 @@ }, "I_SERDES.BYPASS" : { "rules" : { + "WIDTH" : "__arg0__" }, "results" : { + "__other__" : [ + { + "__define__" : "parse_serdes_width", + "PEER_IS_ON" : "__peer_is_on__", + "RX_BYPASS" : "RX_gear_on" + } + ] + }, + "neg_results" : { "RX_BYPASS" : "RX_gear_on" } }, @@ -105,8 +115,18 @@ }, "O_SERDES.BYPASS" : { "rules" : { + "WIDTH" : "__arg0__" }, "results" : { + "__other__" : [ + { + "__define__" : "parse_serdes_width", + "PEER_IS_ON" : "__peer_is_on__", + "TX_BYPASS" : "TX_gear_on" + } + ] + }, + "neg_results" : { "TX_BYPASS" : "TX_gear_on" } }, @@ -649,6 +669,13 @@ "__fclk_buf_root_mux_sel__ = (40 + fabric_clock_buffer_slot - 4) if (fabric_clock_buffer_slot >= 4) else (44 + fabric_clock_buffer_slot)", "__fclk_buf_root_mux_sel__ = '%d' % __fclk_buf_root_mux_sel__" ] + }, + "parse_serdes_width" : { + "__args__" : ["__peer_is_on__"], + "__equation__" : [ + "width = int('__arg0__')", + "__peer_is_on__ = 'PEER_on' if width <= 5 else 'PEER_off'" + ] } } } \ No newline at end of file diff --git a/tests/unittest/ModelConfig/golden/model_config.ppdb.json b/tests/unittest/ModelConfig/golden/model_config.ppdb.json index 8dfdbbf5f..538b221ed 100644 --- a/tests/unittest/ModelConfig/golden/model_config.ppdb.json +++ b/tests/unittest/ModelConfig/golden/model_config.ppdb.json @@ -6,8 +6,8 @@ "Merge properties into instances", " Assign Property:IOSTANDARD value:LVCMOS_18_HP to \"$iopadmap$top.clk0\"", " Assign Property:PACKAGE_PIN value:HR_1_CC_38_19P to \"$iopadmap$top.clk0\"", - " Assign Property:IOSTANDARD value:LVCMOS_18_HP to \"$auto$clkbufmap.cc:284:execute$458\"", - " Assign Property:PACKAGE_PIN value:HR_1_CC_38_19P to \"$auto$clkbufmap.cc:284:execute$458\"", + " Assign Property:IOSTANDARD value:LVCMOS_18_HP to \"$auto$clkbufmap.cc:284:execute$507\"", + " Assign Property:PACKAGE_PIN value:HR_1_CC_38_19P to \"$auto$clkbufmap.cc:284:execute$507\"", " Assign Property:IOSTANDARD value:LVCMOS_18_HR to \"$iopadmap$top.din\"", " Assign Property:PACKAGE_PIN value:HR_1_4_2P to \"$iopadmap$top.din\"", " Assign Property:IOSTANDARD value:LVCMOS_18_HR to \"i_delay\"", @@ -18,7 +18,7 @@ " Assign Property:PACKAGE_PIN value:HR_1_6_3P to \"o_delay\"", "Re-location instances", " Overwrite location value:$iopadmap$top.clk0 to \"HR_1_CC_38_19P\" (value existing: HR_1_CC_18_9P)", - " Overwrite location value:$auto$clkbufmap.cc:284:execute$458 to \"HR_1_CC_38_19P\" (value existing: HR_1_CC_18_9P)", + " Overwrite location value:$auto$clkbufmap.cc:284:execute$507 to \"HR_1_CC_38_19P\" (value existing: HR_1_CC_18_9P)", " Overwrite location value:$iopadmap$top.din to \"HR_1_4_2P\" (value existing: HP_1_20_10P)", " Overwrite location value:i_delay to \"HR_1_4_2P\" (value existing: HP_1_20_10P)", " Overwrite location value:$iopadmap$top.dout to \"HR_1_6_3P\" (value existing: HP_2_20_10P)", @@ -32,7 +32,7 @@ " Object: FABRIC_CLKBUF#0", " Assign location for child from instance-without-location", "Allocate FCLK routing resource", - " CLKBUF $auto$clkbufmap.cc:284:execute$458 (location:HR_1_CC_38_19P)", + " CLKBUF $auto$clkbufmap.cc:284:execute$507 (location:HR_1_CC_38_19P)", " Route to gearbox module i_delay (location:HR_1_4_2P)", " Use FCLK: hvl_fclk_0_A", " CLKBUF clk_buf (location:HP_1_CC_18_9P)", @@ -47,10 +47,10 @@ " Use FCLK: hvl_fclk_1_A", " Route to gearbox module o_serdes_clk (location:HR_2_4_2P)", " Use FCLK: hvl_fclk_1_A", - " CLKBUF $auto$clkbufmap.cc:284:execute$463 (location:HR_5_CC_38_19P)", + " CLKBUF $auto$clkbufmap.cc:284:execute$512 (location:HR_5_CC_38_19P)", "Set CLKBUF configuration attributes", " Set FCLK configuration attributes", - " CLKBUF $auto$clkbufmap.cc:284:execute$458 (location:HR_1_CC_38_19P) use hvl_fclk_0_A", + " CLKBUF $auto$clkbufmap.cc:284:execute$507 (location:HR_1_CC_38_19P) use hvl_fclk_0_A", " Set FCLK configuration attributes", " Skip for HR_5_CC_38_19P", "Allocate PLL resource (and set PLLREF configuration attributes)", @@ -79,7 +79,7 @@ " Property", " Rule I_BUF.IOSTANDARD", " Match", - " Module: CLK_BUF ($auto$clkbufmap.cc:284:execute$458)", + " Module: CLK_BUF ($auto$clkbufmap.cc:284:execute$507)", " Object: clk0", " Parameter", " Property", @@ -123,7 +123,7 @@ " Property", " Rule I_BUF.IOSTANDARD", " Mismatch", - " Module: CLK_BUF ($auto$clkbufmap.cc:284:execute$463)", + " Module: CLK_BUF ($auto$clkbufmap.cc:284:execute$512)", " Object: clk2", " Parameter", " Property", @@ -218,6 +218,7 @@ " Parameter", " Rule I_SERDES.BYPASS", " Match", + " Defined function: parse_serdes_width", " Rule I_SERDES.DDR_MODE", " Match", " Rule I_SERDES.DPA_MODE", @@ -252,6 +253,7 @@ " Parameter", " Rule O_SERDES.BYPASS", " Match", + " Defined function: parse_serdes_width", " Rule O_SERDES.DDR_MODE", " Match", " Property", @@ -357,7 +359,7 @@ " Rule O_DDR", " Match", " Property", - " Module: FCLK_BUF ($auto$clkbufmap.cc:282:execute$461)", + " Module: FCLK_BUF ($auto$clkbufmap.cc:282:execute$510)", " Object: FABRIC_CLKBUF#0", " Parameter", " Rule FCLK_BUF", @@ -410,7 +412,7 @@ }, { "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:284:execute$458", + "name" : "$auto$clkbufmap.cc:284:execute$507", "linked_object" : "clk0", "linked_objects" : { "clk0" : { @@ -450,7 +452,7 @@ }, "connectivity" : { "I" : "$iopadmap$clk0", - "O" : "$auto$clkbufmap.cc:317:execute$460" + "O" : "$auto$clkbufmap.cc:317:execute$509" }, "parameters" : { "ROUTE_TO_FABRIC_CLK" : "0" @@ -627,7 +629,7 @@ "connectivity" : { "CLK_IN" : "clk1_buf", "CLK_OUT" : "pll_clk", - "CLK_OUT_DIV4" : "$delete_wire$487" + "CLK_OUT_DIV4" : "$delete_wire$540" }, "parameters" : { "OUT0_ROUTE_TO_FABRIC_CLK" : "1", @@ -706,7 +708,7 @@ }, { "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:284:execute$463", + "name" : "$auto$clkbufmap.cc:284:execute$512", "linked_object" : "clk2", "linked_objects" : { "clk2" : { @@ -732,7 +734,7 @@ }, "connectivity" : { "I" : "$iopadmap$clk2", - "O" : "$auto$clkbufmap.cc:317:execute$465" + "O" : "$auto$clkbufmap.cc:317:execute$514" }, "parameters" : { "ROUTE_TO_FABRIC_CLK" : "2" @@ -1091,7 +1093,7 @@ } }, "connectivity" : { - "CLK_IN" : "$auto$clkbufmap.cc:317:execute$460", + "CLK_IN" : "$auto$clkbufmap.cc:317:execute$509", "I" : "$iopadmap$din", "O" : "din_delay" }, @@ -1194,6 +1196,9 @@ "properties" : { }, "config_attributes" : [ + { + "PEER_IS_ON" : "PEER_off" + }, { "RX_BYPASS" : "RX_gear_on" }, @@ -1382,6 +1387,9 @@ "properties" : { }, "config_attributes" : [ + { + "PEER_IS_ON" : "PEER_on" + }, { "TX_BYPASS" : "TX_gear_on" }, @@ -1398,7 +1406,7 @@ }, "parameters" : { "DATA_RATE" : "DDR", - "WIDTH" : "8" + "WIDTH" : "4" }, "pre_primitive" : "O_BUF", "post_primitives" : [ @@ -1866,7 +1874,7 @@ }, { "module" : "FCLK_BUF", - "name" : "$auto$clkbufmap.cc:282:execute$461", + "name" : "$auto$clkbufmap.cc:282:execute$510", "linked_object" : "FABRIC_CLKBUF#0", "linked_objects" : { "FABRIC_CLKBUF#0" : { @@ -1884,7 +1892,7 @@ } }, "connectivity" : { - "I" : "$auto$clkbufmap.cc:285:execute$462", + "I" : "$auto$clkbufmap.cc:285:execute$511", "O" : "clk0_div" }, "parameters" : { diff --git a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.backdoor.txt b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.backdoor.txt index ccfc819b1..6def92b98 100644 --- a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.backdoor.txt +++ b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.backdoor.txt @@ -122,7 +122,7 @@ force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_A[0].control force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[19].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_19 [Customer Name: HR_5_CC_38_19P] -force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[19].control = 42'b000100000110000000000100000000001000000011; +force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[19].control = 42'b000100000110000000000100000000001000100011; // u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_B_18 [Customer Name: HR_5_37_18N] force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[18].control = 42'b000000000000000000000000000000000000000000; @@ -233,10 +233,10 @@ force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[1].control force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[1].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_B_0 [Customer Name: HR_5_1_0N] -force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[0].control = 42'b000100000001000000000000000000001000000011; +force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[0].control = 42'b000100000001000000000000000000001000100011; // u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_0 [Customer Name: HR_5_0_0P] -force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[0].control = 42'b000100000010000000000100000000000000000011; +force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[0].control = 42'b000100000010000000000100000000000000100011; // u_GBOX_HV_40X2_VR.u_HV_PGEN_dummy [Customer Name: ] force u_dut.u_gbox_hv_VR_EW_BANK_x2.u_gbox_pgen_cfg.control = 2'b00; @@ -299,10 +299,10 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_1.u_gbox_io_cfg_B[12].control = force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_1.u_gbox_io_cfg_A[12].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HP_40X2.u_HP_GBOX_BK1_B_11 [Customer Name: HP_2_23_11N] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_1.u_gbox_io_cfg_B[11].control = 42'b000100001001000000000000000000001010000011; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_1.u_gbox_io_cfg_B[11].control = 42'b000100001001000000000000000000001010100011; // u_GBOX_HP_40X2.u_HP_GBOX_BK1_A_11 [Customer Name: HP_2_22_11P] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_1.u_gbox_io_cfg_A[11].control = 42'b000100001001000000000000000000001010000011; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_1.u_gbox_io_cfg_A[11].control = 42'b000100001001000000000000000000001010100011; // u_GBOX_HP_40X2.u_HP_GBOX_BK1_B_10 [Customer Name: HP_2_21_10N] force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_1.u_gbox_io_cfg_B[10].control = 42'b000000000000000000000000000000000000000000; @@ -434,7 +434,7 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[10].control = force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[9].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_9 [Customer Name: HP_1_CC_18_9P] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[9].control = 42'b000100000010000000000100000000000000000011; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[9].control = 42'b000100000010000000000100000000000000100011; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_8 [Customer Name: HP_1_17_8N] force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[8].control = 42'b000000000000000000000000000000000000000000; @@ -461,10 +461,10 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[5].control = force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[5].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_4 [Customer Name: HP_1_9_4N] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[4].control = 42'b000100001001000000000000000000001010000011; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[4].control = 42'b000100001001000000000000000000001010100011; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_4 [Customer Name: HP_1_8_4P] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[4].control = 42'b000100001001000000000000000000001010000011; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[4].control = 42'b000100001001000000000000000000001010100011; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_3 [Customer Name: HP_1_7_3N] force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[3].control = 42'b000000000000000000000000000000000000000000; @@ -473,10 +473,10 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[3].control = force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[3].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_2 [Customer Name: HP_1_5_2N] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[2].control = 42'b000110001010000000000101000000000000000011; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[2].control = 42'b000110001010000000000101000000000000100011; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_2 [Customer Name: HP_1_4_2P] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[2].control = 42'b000110001010000000000101000000000000000011; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[2].control = 42'b000110001010000000000101000000000000100011; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_1 [Customer Name: HP_1_3_1N] force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[1].control = 42'b000000000000000000000000000000000000000000; @@ -488,7 +488,7 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[1].control = force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[0].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_0 [Customer Name: HP_1_0_0P] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[0].control = 42'b000100000010000000000100000000000000000011; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[0].control = 42'b000100000010000000000100000000000000100011; // u_GBOX_HP_40X2.u_HP_PGEN_dummy [Customer Name: ] force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_pgen_cfg0.control = 6'b000000; @@ -569,7 +569,7 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_pll_cfg.control[155:147] = 9'b110000000; force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_B[19].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_19 [Customer Name: HR_1_CC_38_19P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_A[19].control = 42'b000100000110000000000100000000001000000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_A[19].control = 42'b000100000110000000000100000000001000100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_18 [Customer Name: HR_1_37_18N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_B[18].control = 42'b000000000000000000000000000000000000000000; @@ -665,13 +665,13 @@ force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_A[4].control force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_B[3].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_3 [Customer Name: HR_1_6_3P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_A[3].control = 42'b000100000001000000000000111100001000000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_A[3].control = 42'b000100000001000000000000111100001000100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_2 [Customer Name: HR_1_5_2N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_B[2].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_2 [Customer Name: HR_1_4_2P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_A[2].control = 42'b000100000010000110010100000000000000000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_A[2].control = 42'b000100000010000110010100000000000000100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_1 [Customer Name: HR_1_3_1N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_0.u_gbox_io_cfg_B[1].control = 42'b000000000000000000000000000000000000000000; @@ -713,37 +713,37 @@ force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[16].contro force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[15].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_15 [Customer Name: HR_2_30_15P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[15].control = 42'b000100000001000000000000000000001000000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[15].control = 42'b000100000001000000000000000000001000100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_14 [Customer Name: HR_2_29_14N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[14].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_14 [Customer Name: HR_2_28_14P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[14].control = 42'b000100000001000000000000000000001000000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[14].control = 42'b000100000001000000000000000000001000100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_13 [Customer Name: HR_2_27_13N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[13].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_13 [Customer Name: HR_2_26_13P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[13].control = 42'b000100000001000000000000000000001000000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[13].control = 42'b000100000001000000000000000000001000100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_12 [Customer Name: HR_2_25_12N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[12].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_12 [Customer Name: HR_2_24_12P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[12].control = 42'b000100000001000000000000000000001000000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[12].control = 42'b000100000001000000000000000000001000100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_11 [Customer Name: HR_2_23_11N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[11].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_11 [Customer Name: HR_2_22_11P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[11].control = 42'b000100000001000000000000000000001000000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[11].control = 42'b000100000001000000000000000000001000100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_10 [Customer Name: HR_2_21_10N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[10].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_10 [Customer Name: HR_2_20_10P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[10].control = 42'b000100000001000000000000000000001000000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[10].control = 42'b000100000001000000000000000000001000100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_9 [Customer Name: HR_2_CC_19_9N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[9].control = 42'b000000000000000000000000000000000000000000; @@ -791,13 +791,13 @@ force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[3].control force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[2].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_2 [Customer Name: HR_2_4_2P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[2].control = 42'b000100000001000000000000000000111100000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[2].control = 42'b000100000001000000000000000000111100100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_1 [Customer Name: HR_2_3_1N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[1].control = 42'b000000000000000000000000000000000000000000; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_1 [Customer Name: HR_2_2_1P] -force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[1].control = 42'b000100000001000000000000000000000010000011; +force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_A[1].control = 42'b000100000001000000000000000000000010100011; // u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_0 [Customer Name: HR_2_1_0N] force u_dut.u_gbox_hv_VL_EW_BANK_x2.u_gbox_hv_40_EW_1.u_gbox_io_cfg_B[0].control = 42'b000000000000000000000000000000000000000000; diff --git a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit index e3160d37f..30fea3f54 100644 --- a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit +++ b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit @@ -991,20 +991,20 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_19 [HR_5_CC_38_19P] Attributes: RATE - Addr: 0x000006BA, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000006BE, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000006BF, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000006BF, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x000006C0, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x000006C1, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x000006C3, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $auto$clkbufmap.cc:284:execute$463 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + TX_BYPASS - Addr: 0x000006C3, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $auto$clkbufmap.cc:284:execute$512 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x000006C4, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x000006C6, Size: 6, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } RX_DDR_MODE - Addr: 0x000006CC, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x000006CE, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $auto$clkbufmap.cc:284:execute$463 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_BYPASS - Addr: 0x000006CE, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $auto$clkbufmap.cc:284:execute$512 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } RX_DLY - Addr: 0x000006CF, Size: 6, Value: (0x00000000) 0 RX_DPA_MODE - Addr: 0x000006D5, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } RX_MIPI_MODE - Addr: 0x000006D7, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x000006D8, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } RX_MODE - Addr: 0x000006D9, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000006DA, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $auto$clkbufmap.cc:284:execute$463 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000006DA, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $auto$clkbufmap.cc:284:execute$512 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } DFEN - Addr: 0x000006DB, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x000006DC, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x000006DD, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk2 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -1879,7 +1879,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_B_0 [HR_5_1_0N] Attributes: RATE - Addr: 0x00000CCC, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00000CD0, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00000CD1, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00000CD1, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00000CD2, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00000CD3, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000CD5, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -1903,7 +1903,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_0 [HR_5_0_0P] Attributes: RATE - Addr: 0x00000CF6, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00000CFA, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00000CFB, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00000CFB, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00000CFC, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00000CFD, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000CFF, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -1951,7 +1951,7 @@ Block u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x00000D42, Size: 5, Value: (0x00000000) 0 CDR_CLK_ROOT_SEL_A - Addr: 0x00000D47, Size: 5, Value: (0x00000000) 0 - CORE_CLK_ROOT_SEL_B - Addr: 0x00000D4C, Size: 5, Value: (0x00000012) 18 { $auto$clkbufmap.cc:284:execute$463 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==B --#MUX=18] [from HR_5_CC_38_19P] } + CORE_CLK_ROOT_SEL_B - Addr: 0x00000D4C, Size: 5, Value: (0x00000012) 18 { $auto$clkbufmap.cc:284:execute$512 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==B --#MUX=18] [from HR_5_CC_38_19P] } CORE_CLK_ROOT_SEL_A - Addr: 0x00000D51, Size: 5, Value: (0x00000000) 0 Block u_GBOX_HP_40X2.u_HP_GBOX_BK1_B_19 [HP_2_CC_39_19N] Attributes: @@ -2341,7 +2341,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK1_B_11 [HP_2_23_11N] Attributes: RATE - Addr: 0x00000FF6, Size: 4, Value: (0x00000003) 3 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00000FFA, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00000FFB, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00000FFB, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00000FFC, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00000FFD, Size: 2, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT], o_ddr_osc [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x00000FFF, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } @@ -2365,7 +2365,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK1_A_11 [HP_2_22_11P] Attributes: RATE - Addr: 0x00001020, Size: 4, Value: (0x00000003) 3 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001024, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001025, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001025, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001026, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001027, Size: 2, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT], o_ddr_osc [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x00001029, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } @@ -3421,7 +3421,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_9 [HP_1_CC_18_9P] Attributes: RATE - Addr: 0x00001758, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000175C, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000175D, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000175D, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000175E, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x0000175F, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001761, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -3637,7 +3637,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_4 [HP_1_9_4N] Attributes: RATE - Addr: 0x000018D2, Size: 4, Value: (0x00000003) 3 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000018D6, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000018D7, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000018D7, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x000018D8, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x000018D9, Size: 2, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT], o_ddr [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x000018DB, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } @@ -3661,7 +3661,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_4 [HP_1_8_4P] Attributes: RATE - Addr: 0x000018FC, Size: 4, Value: (0x00000003) 3 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001900, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001901, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001901, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001902, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001903, Size: 2, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT], o_ddr [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x00001905, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } @@ -3733,7 +3733,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_2 [HP_1_5_2N] Attributes: RATE - Addr: 0x0000197A, Size: 4, Value: (0x00000003) 3 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000197E, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000197F, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000197F, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001980, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001981, Size: 2, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001983, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -3757,7 +3757,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_2 [HP_1_4_2P] Attributes: RATE - Addr: 0x000019A4, Size: 4, Value: (0x00000003) 3 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000019A8, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000019A9, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000019A9, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x000019AA, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x000019AB, Size: 2, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000019AD, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -3853,7 +3853,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_0 [HP_1_0_0P] Attributes: RATE - Addr: 0x00001A4C, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001A50, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001A51, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001A51, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001A52, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001A53, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001A55, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -3909,19 +3909,19 @@ Block u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_1 [] CORE_CLK_ROOT_SEL_A - Addr: 0x00001AAB, Size: 5, Value: (0x00000000) 0 Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0 [] Attributes: - ROOT_MUX_SEL - Addr: 0x00001AB0, Size: 6, Value: (0x00000009) 9 { $auto$clkbufmap.cc:284:execute$458 [CLK_BUF] [ROOT_MUX_SEL:9] [from HR_1_CC_38_19P] } + ROOT_MUX_SEL - Addr: 0x00001AB0, Size: 6, Value: (0x00000009) 9 { $auto$clkbufmap.cc:284:execute$507 [CLK_BUF] [ROOT_MUX_SEL:9] [from HR_1_CC_38_19P] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1 [] Attributes: ROOT_MUX_SEL - Addr: 0x00001AB6, Size: 6, Value: (0x00000020) 32 { pll [PLL] [ROOT_MUX_SEL:32] [from HP_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2 [] Attributes: - ROOT_MUX_SEL - Addr: 0x00001ABC, Size: 6, Value: (0x00000013) 19 { $auto$clkbufmap.cc:284:execute$463 [CLK_BUF] [ROOT_MUX_SEL:19] [from HR_5_CC_38_19P] } + ROOT_MUX_SEL - Addr: 0x00001ABC, Size: 6, Value: (0x00000013) 19 { $auto$clkbufmap.cc:284:execute$512 [CLK_BUF] [ROOT_MUX_SEL:19] [from HR_5_CC_38_19P] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3 [] Attributes: ROOT_MUX_SEL - Addr: 0x00001AC2, Size: 6, Value: (0x00000024) 36 { pll_osc [PLL] [ROOT_MUX_SEL:36] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4 [] Attributes: - ROOT_MUX_SEL - Addr: 0x00001AC8, Size: 6, Value: (0x0000002C) 44 { $auto$clkbufmap.cc:282:execute$461 [FCLK_BUF] [ROOT_MUX_SEL:44] [from __SKIP_LOCATION_CHECK__:FABRIC_CLKBUF#0] } + ROOT_MUX_SEL - Addr: 0x00001AC8, Size: 6, Value: (0x0000002C) 44 { $auto$clkbufmap.cc:282:execute$510 [FCLK_BUF] [ROOT_MUX_SEL:44] [from __SKIP_LOCATION_CHECK__:FABRIC_CLKBUF#0] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5 [] Attributes: ROOT_MUX_SEL - Addr: 0x00001ACE, Size: 6, Value: (0x0000003F) 63 @@ -4038,20 +4038,20 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_19 [HR_1_CC_38_19P] Attributes: RATE - Addr: 0x00001BE5, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } MASTER_SLAVE - Addr: 0x00001BE9, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } - PEER_IS_ON - Addr: 0x00001BEA, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } + PEER_IS_ON - Addr: 0x00001BEA, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } TX_CLOCK_IO - Addr: 0x00001BEB, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } TX_DDR_MODE - Addr: 0x00001BEC, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } - TX_BYPASS - Addr: 0x00001BEE, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP], $auto$clkbufmap.cc:284:execute$458 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + TX_BYPASS - Addr: 0x00001BEE, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP], $auto$clkbufmap.cc:284:execute$507 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001BEF, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } TX_DLY - Addr: 0x00001BF1, Size: 6, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } RX_DDR_MODE - Addr: 0x00001BF7, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } - RX_BYPASS - Addr: 0x00001BF9, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP], $auto$clkbufmap.cc:284:execute$458 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_BYPASS - Addr: 0x00001BF9, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP], $auto$clkbufmap.cc:284:execute$507 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } RX_DLY - Addr: 0x00001BFA, Size: 6, Value: (0x00000000) 0 RX_DPA_MODE - Addr: 0x00001C00, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } RX_MIPI_MODE - Addr: 0x00001C02, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } TX_MODE - Addr: 0x00001C03, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } RX_MODE - Addr: 0x00001C04, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } - RX_CLOCK_IO - Addr: 0x00001C05, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP], $auto$clkbufmap.cc:284:execute$458 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001C05, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP], $auto$clkbufmap.cc:284:execute$507 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } DFEN - Addr: 0x00001C06, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } SR - Addr: 0x00001C07, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } PE - Addr: 0x00001C08, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk0 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -4806,7 +4806,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_3 [HR_1_6_3P] Attributes: RATE - Addr: 0x00002125, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } MASTER_SLAVE - Addr: 0x00002129, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - PEER_IS_ON - Addr: 0x0000212A, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } + PEER_IS_ON - Addr: 0x0000212A, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } TX_CLOCK_IO - Addr: 0x0000212B, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } TX_DDR_MODE - Addr: 0x0000212C, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } TX_BYPASS - Addr: 0x0000212E, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } @@ -4854,7 +4854,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_2 [HR_1_4_2P] Attributes: RATE - Addr: 0x00002179, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } MASTER_SLAVE - Addr: 0x0000217D, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } - PEER_IS_ON - Addr: 0x0000217E, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } + PEER_IS_ON - Addr: 0x0000217E, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } TX_CLOCK_IO - Addr: 0x0000217F, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } TX_DDR_MODE - Addr: 0x00002180, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } TX_BYPASS - Addr: 0x00002182, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } @@ -5190,7 +5190,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_15 [HR_2_30_15P] Attributes: RATE - Addr: 0x000023C5, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000023C9, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000023CA, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000023CA, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x000023CB, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x000023CC, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000023CE, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -5238,7 +5238,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_14 [HR_2_28_14P] Attributes: RATE - Addr: 0x00002419, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000241D, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000241E, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000241E, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000241F, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00002420, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002422, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -5286,7 +5286,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_13 [HR_2_26_13P] Attributes: RATE - Addr: 0x0000246D, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002471, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00002472, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00002472, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00002473, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00002474, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002476, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -5334,7 +5334,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_12 [HR_2_24_12P] Attributes: RATE - Addr: 0x000024C1, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000024C5, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000024C6, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000024C6, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x000024C7, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x000024C8, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000024CA, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -5382,7 +5382,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_11 [HR_2_22_11P] Attributes: RATE - Addr: 0x00002515, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002519, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x0000251C, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x0000251E, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -5430,7 +5430,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_10 [HR_2_20_10P] Attributes: RATE - Addr: 0x00002569, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000256D, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000256E, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000256E, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000256F, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00002570, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002572, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -5814,7 +5814,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_2 [HR_2_4_2P] Attributes: RATE - Addr: 0x00002809, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000280D, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000280E, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000280E, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000280F, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00002810, Size: 2, Value: (0x00000002) 2 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [O_SERDES_CLK:DDR_MODE==SDR] } TX_BYPASS - Addr: 0x00002812, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -5862,7 +5862,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_1 [HR_2_2_1P] Attributes: RATE - Addr: 0x0000285D, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002861, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00002862, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00002862, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [PEER_IS_ON:PEER_on] } TX_CLOCK_IO - Addr: 0x00002863, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00002864, Size: 2, Value: (0x00000001) 1 { $iopadmap$top.dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [O_SERDES:DDR_MODE==DDR] } TX_BYPASS - Addr: 0x00002866, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [TX_BYPASS:TX_gear_on] } @@ -5910,7 +5910,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_0 [HR_2_0_0P] Attributes: RATE - Addr: 0x000028B1, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000028B5, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000028B6, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000028B6, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], i_serdes [I_SERDES] [PEER_IS_ON:PEER_off] } TX_CLOCK_IO - Addr: 0x000028B7, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x000028B8, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000028BA, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -5938,21 +5938,21 @@ Block u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all [] Attributes: cfg_rxclk_phase_sel_B_0 - Addr: 0x000028DD, Size: 1, Value: (0x00000000) 0 cfg_rxclk_phase_sel_B_1 - Addr: 0x000028DE, Size: 1, Value: (0x00000000) 0 - cfg_rxclk_phase_sel_A_0 - Addr: 0x000028DF, Size: 1, Value: (0x00000001) 1 { $auto$clkbufmap.cc:284:execute$458 [CLK_BUF] [cfg_rxclk_phase_sel_A_0:1] [from HR_1_CC_38_19P] } + cfg_rxclk_phase_sel_A_0 - Addr: 0x000028DF, Size: 1, Value: (0x00000001) 1 { $auto$clkbufmap.cc:284:execute$507 [CLK_BUF] [cfg_rxclk_phase_sel_A_0:1] [from HR_1_CC_38_19P] } cfg_rxclk_phase_sel_A_1 - Addr: 0x000028E0, Size: 1, Value: (0x00000000) 0 { pll [PLL] [cfg_rxclk_phase_sel_A_1:0] [from HP_1_CC_18_9P] } cfg_rx_fclkio_sel_B_0 - Addr: 0x000028E1, Size: 1, Value: (0x00000000) 0 cfg_rx_fclkio_sel_B_1 - Addr: 0x000028E2, Size: 1, Value: (0x00000000) 0 - cfg_rx_fclkio_sel_A_0 - Addr: 0x000028E3, Size: 1, Value: (0x00000001) 1 { $auto$clkbufmap.cc:284:execute$458 [CLK_BUF] [cfg_rx_fclkio_sel_A_0:1] [from HR_1_CC_38_19P] } + cfg_rx_fclkio_sel_A_0 - Addr: 0x000028E3, Size: 1, Value: (0x00000001) 1 { $auto$clkbufmap.cc:284:execute$507 [CLK_BUF] [cfg_rx_fclkio_sel_A_0:1] [from HR_1_CC_38_19P] } cfg_rx_fclkio_sel_A_1 - Addr: 0x000028E4, Size: 1, Value: (0x00000000) 0 { pll [PLL] [cfg_rx_fclkio_sel_A_1:0] [from HP_1_CC_18_9P] } cfg_vco_clk_sel_B_0 - Addr: 0x000028E5, Size: 1, Value: (0x00000000) 0 cfg_vco_clk_sel_B_1 - Addr: 0x000028E6, Size: 1, Value: (0x00000000) 0 - cfg_vco_clk_sel_A_0 - Addr: 0x000028E7, Size: 1, Value: (0x00000000) 0 { $auto$clkbufmap.cc:284:execute$458 [CLK_BUF] [cfg_vco_clk_sel_A_0:0] [from HR_1_CC_38_19P] } + cfg_vco_clk_sel_A_0 - Addr: 0x000028E7, Size: 1, Value: (0x00000000) 0 { $auto$clkbufmap.cc:284:execute$507 [CLK_BUF] [cfg_vco_clk_sel_A_0:0] [from HR_1_CC_38_19P] } cfg_vco_clk_sel_A_1 - Addr: 0x000028E8, Size: 1, Value: (0x00000001) 1 { pll [PLL] [cfg_vco_clk_sel_A_1:1] [from HP_1_CC_18_9P] } Block u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x000028E9, Size: 5, Value: (0x00000000) 0 CDR_CLK_ROOT_SEL_A - Addr: 0x000028EE, Size: 5, Value: (0x00000000) 0 - CORE_CLK_ROOT_SEL_B - Addr: 0x000028F3, Size: 5, Value: (0x00000012) 18 { $auto$clkbufmap.cc:284:execute$458 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==B --#MUX=18] [from HR_1_CC_38_19P] } + CORE_CLK_ROOT_SEL_B - Addr: 0x000028F3, Size: 5, Value: (0x00000012) 18 { $auto$clkbufmap.cc:284:execute$507 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==B --#MUX=18] [from HR_1_CC_38_19P] } CORE_CLK_ROOT_SEL_A - Addr: 0x000028F8, Size: 5, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1 [] Attributes: diff --git a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit index 8dbb219e2..f2e6b0da9 100644 --- a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit +++ b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit @@ -31,7 +31,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK0_A_19 [HR_3_CC_38_19P] Attributes: RATE - Addr: 0x0000002A, Size: 4, Value: (0x00000003) 3 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000002E, Size: 1, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000002F, Size: 1, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000002F, Size: 1, Value: (0x00000001) 1 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00000030, Size: 1, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00000031, Size: 2, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000033, Size: 1, Value: (0x00000001) 1 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf31 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } @@ -1375,7 +1375,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_11 [HR_5_22_11P] Attributes: RATE - Addr: 0x0000095A, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000095E, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000095F, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000095F, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00000960, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00000961, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000963, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -1423,7 +1423,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_10 [HR_5_20_10P] Attributes: RATE - Addr: 0x000009AE, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000009B2, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000009B3, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000009B3, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x000009B4, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x000009B5, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000009B7, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -1807,7 +1807,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_2 [HR_5_4_2P] Attributes: RATE - Addr: 0x00000C4E, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00000C52, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00000C53, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00000C53, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00000C54, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00000C55, Size: 2, Value: (0x00000001) 1 { $iopadmap$top.dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_ddr11 [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x00000C57, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -1855,7 +1855,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_1 [HR_5_2_1P] Attributes: RATE - Addr: 0x00000CA2, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00000CA6, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00000CA7, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00000CA7, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00000CA8, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00000CA9, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000CAB, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -2941,7 +2941,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_19 [HP_1_CC_38_19P] Attributes: RATE - Addr: 0x00001410, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001414, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001415, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001415, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001416, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001417, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001419, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $auto$clkbufmap.cc:284:execute$706 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } @@ -3325,7 +3325,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_11 [HP_1_22_11P] Attributes: RATE - Addr: 0x000016B0, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000016B4, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000016B5, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000016B5, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x000016B6, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x000016B7, Size: 2, Value: (0x00000001) 1 { $iopadmap$top.dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_ddr00 [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x000016B9, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -3373,7 +3373,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_10 [HP_1_20_10P] Attributes: RATE - Addr: 0x00001704, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001708, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001709, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001709, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000170A, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x0000170B, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x0000170D, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -3421,7 +3421,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_9 [HP_1_CC_18_9P] Attributes: RATE - Addr: 0x00001758, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000175C, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000175D, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000175D, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000175E, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x0000175F, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001761, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf00 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } @@ -4038,7 +4038,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_19 [HR_1_CC_38_19P] Attributes: RATE - Addr: 0x00001BE5, Size: 4, Value: (0x00000003) 3 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001BE9, Size: 1, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001BEA, Size: 1, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001BEA, Size: 1, Value: (0x00000001) 1 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001BEB, Size: 1, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001BEC, Size: 2, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001BEE, Size: 1, Value: (0x00000001) 1 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf30 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } @@ -4230,7 +4230,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_15 [HR_1_30_15P] Attributes: RATE - Addr: 0x00001D35, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001D39, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001D3A, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001D3A, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001D3B, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001D3C, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001D3E, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -4326,7 +4326,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_13 [HR_1_26_13P] Attributes: RATE - Addr: 0x00001DDD, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001DE1, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001DE2, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001DE2, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001DE3, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001DE4, Size: 2, Value: (0x00000001) 1 { $iopadmap$top.dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_ddr12 [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x00001DE6, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -4374,7 +4374,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_12 [HR_1_24_12P] Attributes: RATE - Addr: 0x00001E31, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001E35, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001E36, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001E36, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001E37, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001E38, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001E3A, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -4422,7 +4422,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_11 [HR_1_22_11P] Attributes: RATE - Addr: 0x00001E85, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001E89, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001E8A, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001E8A, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001E8B, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001E8C, Size: 2, Value: (0x00000001) 1 { $iopadmap$top.dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_ddr01 [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x00001E8E, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -4470,7 +4470,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_10 [HR_1_20_10P] Attributes: RATE - Addr: 0x00001ED9, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001EDD, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001EDE, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001EDE, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001EDF, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001EE0, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001EE2, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -4518,7 +4518,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_9 [HR_1_CC_18_9P] Attributes: RATE - Addr: 0x00001F2D, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001F31, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001F32, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001F32, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00001F33, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00001F34, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001F36, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -4998,7 +4998,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_19 [HR_2_CC_38_19P] Attributes: RATE - Addr: 0x00002275, Size: 4, Value: (0x00000003) 3 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002279, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000227A, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000227A, Size: 1, Value: (0x00000001) 1 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000227B, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x0000227C, Size: 2, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x0000227E, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -5382,7 +5382,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_11 [HR_2_22_11P] Attributes: RATE - Addr: 0x00002515, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002519, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x0000251C, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x0000251E, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -5430,7 +5430,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_10 [HR_2_20_10P] Attributes: RATE - Addr: 0x00002569, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000256D, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000256E, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000256E, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000256F, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00002570, Size: 2, Value: (0x00000000) 0 { $iopadmap$top.dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002572, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -5718,7 +5718,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_4 [HR_2_8_4P] Attributes: RATE - Addr: 0x00002761, Size: 4, Value: (0x00000003) 3 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002765, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00002766, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00002766, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00002767, Size: 1, Value: (0x00000000) 0 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00002768, Size: 2, Value: (0x00000002) 2 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [O_SERDES_CLK:DDR_MODE==SDR] } TX_BYPASS - Addr: 0x0000276A, Size: 1, Value: (0x00000001) 1 { $iopadmap$top.clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } @@ -5838,7 +5838,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_1 [HR_2_3_1N] Attributes: RATE - Addr: 0x00002833, Size: 4, Value: (0x00000003) 3 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002837, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00002838, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00002838, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00002839, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x0000283A, Size: 2, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x0000283C, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -5862,7 +5862,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_1 [HR_2_2_1P] Attributes: RATE - Addr: 0x0000285D, Size: 4, Value: (0x00000003) 3 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002861, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00002862, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00002862, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x00002863, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x00002864, Size: 2, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002866, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -5886,7 +5886,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_0 [HR_2_1_0N] Attributes: RATE - Addr: 0x00002887, Size: 4, Value: (0x00000003) 3 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000288B, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000288C, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000288C, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x0000288D, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x0000288E, Size: 2, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002890, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -5910,7 +5910,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_0 [HR_2_0_0P] Attributes: RATE - Addr: 0x000028B1, Size: 4, Value: (0x00000003) 3 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000028B5, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000028B6, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000028B6, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLOCK_IO - Addr: 0x000028B7, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_DDR_MODE - Addr: 0x000028B8, Size: 2, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000028BA, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } diff --git a/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json b/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json index 4090c219c..15cb3dad1 100644 --- a/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json +++ b/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json @@ -465,46 +465,53 @@ " | *********************************************************** |", " |-----------------------------------------------------------------------------------------------|", " Final checking is good", - " Assign location HR_2_22_11P (and properties) to Port dinoutosc", + " Assign location HP_1_CC_18_9P (and properties) to Port clk00", + " Assign location HR_1_CC_18_9P (and properties) to Port clk10", + " Assign location HP_1_CC_38_19P (and properties) to Port clk20", + " Assign location HR_1_CC_38_19P (and properties) to Port clk30", + " Assign location HR_3_CC_38_19P (and properties) to Port clk31", + " Assign location HR_2_CC_38_19P (and properties) to Port clk40", + " Assign location HR_2_20_10P (and properties) to Port dinosc0", + " Assign location HR_5_20_10P (and properties) to Port dinosc1", " Assign location HR_5_22_11P (and properties) to Port dinosc3", + " Assign location HR_1_30_15P (and properties) to Port dinosc4", + " Assign location HR_2_22_11P (and properties) to Port dinoutosc", " Assign location HP_1_20_10P (and properties) to Port din00", - " Assign location HR_1_22_11P (and properties) to Port dout01", - " Assign location HR_5_20_10P (and properties) to Port dinosc1", - " Assign location HR_2_CC_38_19P (and properties) to Port clk40", - " Assign location HR_2_4_2P (and properties) to Port dout30_p", - " Assign location HR_3_CC_38_19P (and properties) to Port clk31", - " Assign location HP_1_CC_38_19P (and properties) to Port clk20", " Assign location HP_1_22_11P (and properties) to Port dout00", - " Assign location HR_1_30_15P (and properties) to Port dinosc4", - " Assign location HR_2_20_10P (and properties) to Port dinosc0", - " Assign location HR_2_9_4N (and properties) to Port clk_out_osc", - " Assign location HR_1_24_12P (and properties) to Port din12", + " Assign location HR_1_20_10P (and properties) to Port din01", + " Assign location HR_1_22_11P (and properties) to Port dout01", + " Assign location HR_5_2_1P (and properties) to Port din11", " Assign location HR_5_4_2P (and properties) to Port dout11", - " Assign location HR_2_7_3N (and properties) to Port dout30_n", - " Assign location HR_2_3_1N (and properties) to Port din31_n", - " Assign location HR_2_1_0N (and properties) to Port din30_n", - " Assign location HR_2_0_0P (and properties) to Port din30_p", - " Assign location HP_1_CC_18_9P (and properties) to Port clk00", + " Assign location HR_1_24_12P (and properties) to Port din12", " Assign location HR_1_26_13P (and properties) to Port dout12", - " Assign location HR_5_2_1P (and properties) to Port din11", - " Assign location HR_1_CC_38_19P (and properties) to Port clk30", - " Assign location HR_2_8_4P (and properties) to Port clk_out", - " Assign location HR_1_20_10P (and properties) to Port din01", + " Assign location HR_2_0_0P (and properties) to Port din30_p", + " Assign location HR_2_1_0N (and properties) to Port din30_n", " Assign location HR_2_2_1P (and properties) to Port din31_p", - " Assign location HR_1_CC_18_9P (and properties) to Port clk10", + " Assign location HR_2_3_1N (and properties) to Port din31_n", + " Assign location HR_2_4_2P (and properties) to Port dout30_p", + " Assign location HR_2_7_3N (and properties) to Port dout30_n", + " Assign location HR_2_8_4P (and properties) to Port clk_out", + " Assign location HR_2_9_4N (and properties) to Port clk_out_osc", " Cross-check instances vs wrapped-instances", " Generate SDC", " Determine data signals", " Pin object=clk00, location: HP_1_CC_18_9P", - " Skip this because 'Temporarily disable all clock constraint'", + " Data signal from object clk00", + " Failure reason: Object clk00 is primitive \\PLL but data signal is not defined", " Pin object=clk10, location: HR_1_CC_18_9P", - " Skip this because 'Temporarily disable all clock constraint'", + " Data signal from object clk10", + " Module=I_BUF Linked-object=clk10 Port=O Net=$flatten$auto$rs_design_edit.cc:1146:execute$809.$iopadmap$clk10 - Not found", + " Failure reason: Clock data from object clk10 port O is not routed to fabric", " Pin object=clk20, location: HP_1_CC_38_19P", - " Skip this because 'Temporarily disable all clock constraint'", + " Data signal from object clk20", + " Module=I_BUF Linked-object=clk20 Port=O Net=$flatten$auto$rs_design_edit.cc:1146:execute$809.$iopadmap$clk20 - Not found", + " Failure reason: Clock data from object clk20 port O is not routed to fabric", " Pin object=clk_out, location: HR_2_8_4P", - " Skip this because 'The clock is Gearbox internal fast clock'", + " Data signal from object clk_out", + " Failure reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", " Pin object=clk_out_osc, location: HR_2_9_4N", - " Skip this because 'The clock is Gearbox internal fast clock'", + " Data signal from object clk_out_osc", + " Failure reason: Object clk_out_osc is primitive \\O_SERDES_CLK but data signal is not defined", " Pin object=din00, location: HP_1_20_10P", " Data signal from object din00", " Module=I_DDR Linked-object=din00 Port=Q Net=din_iddr00[0] - Found", @@ -548,12 +555,12 @@ " Module=O_BUF Linked-object=dinoutosc Port=I Net=$iopadmap$dinoutosc - Found", " Pin object=dout00, location: HP_1_22_11P", " Data signal from object dout00", - " Module=O_DDR Linked-object=dout00 Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$797 - Found", - " Module=O_DDR Linked-object=dout00 Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$798 - Found", + " Module=O_DDR Linked-object=dout00 Port=D Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$797 - Found", + " Module=O_DDR Linked-object=dout00 Port=D Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$798 - Found", " Pin object=dout01, location: HR_1_22_11P", " Data signal from object dout01", - " Module=O_DDR Linked-object=dout01 Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$799 - Found", - " Module=O_DDR Linked-object=dout01 Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$800 - Found", + " Module=O_DDR Linked-object=dout01 Port=D Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$799 - Found", + " Module=O_DDR Linked-object=dout01 Port=D Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$800 - Found", " Pin object=dout10, location: ", " Pin location is not assigned", " Pin object=dout11, location: HR_5_4_2P", @@ -567,11 +574,15 @@ " Pin object=dout20, location: ", " Pin location is not assigned", " Pin object=clk30, location: HR_1_CC_38_19P", - " Skip this because 'The clock is not used by fabric'", + " Data signal from object clk30", + " Failure reason: Object clk30 is primitive \\PLL but data signal is not defined", " Pin object=clk31, location: HR_3_CC_38_19P", - " Skip this because 'The clock is not used by fabric'", + " Data signal from object clk31", + " Failure reason: Object clk31 is primitive \\PLL but data signal is not defined", " Pin object=clk40, location: HR_2_CC_38_19P", - " Skip this because 'The clock is not used by fabric'", + " Data signal from object clk40", + " Module=I_BUF Linked-object=clk40 Port=O Net=$auto$rs_design_edit.cc:1146:execute$809.ibuf40 - Not found", + " Failure reason: Clock data from object clk40 port O is not routed to fabric", " Pin object=din30_n, location: HR_2_1_0N", " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=din30_p, location: HR_2_0_0P", @@ -591,54 +602,54 @@ " Module=O_DDR Linked-object=dout30_n+dout30_p Port=D Net=$abc$214$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test_negative/./top.v:380$14_Y[0] - Found", " Module=O_DDR Linked-object=dout30_n+dout30_p Port=D Net=$abc$214$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test_negative/./top.v:380$14_Y[1] - Found", " Determine internal control signals", - " Module=I_BUF LinkedObject=clk00 Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=clk00 Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=PLL LinkedObject=clk00 Location=HP_1_CC_18_9P Port=LOCK Signal=out:TO_BE_DETERMINED", " User design does not utilize linked-object clk00 wrapped-instance port LOCK", " Module=PLL LinkedObject=clk00 Location=HP_1_CC_18_9P Port=PLL_EN Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=clk10 Location=HR_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{X}", - " Module=I_BUF LinkedObject=clk20 Location=HP_1_CC_38_19P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=clk10 Location=HR_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=clk20 Location=HP_1_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=O_SERDES_CLK LinkedObject=clk_out Location=HR_2_8_4P Port=CLK_EN Signal=in:TO_BE_DETERMINED", " Module=O_SERDES_CLK LinkedObject=clk_out Location=HR_2_8_4P Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", " User design does not utilize linked-object clk_out wrapped-instance port PLL_LOCK", " Module=O_SERDES_CLK LinkedObject=clk_out_osc Location=HR_2_9_4N Port=CLK_EN Signal=in:TO_BE_DETERMINED", " Module=O_SERDES_CLK LinkedObject=clk_out_osc Location=HR_2_9_4N Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", " User design does not utilize linked-object clk_out_osc wrapped-instance port PLL_LOCK", - " Module=I_BUF LinkedObject=din00 Location=HP_1_20_10P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=din00 Location=HP_1_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din00 Location=HP_1_20_10P Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din00 Location=HP_1_20_10P Port=R Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=din01 Location=HR_1_20_10P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=din01 Location=HR_1_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din01 Location=HR_1_20_10P Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din01 Location=HR_1_20_10P Port=R Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=din10 Location= Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=din10 Location= Port=EN Signal=in:f2g_in_en_{A|B}", " Location does not have any mode to begin with", " Module=I_DDR LinkedObject=din10 Location= Port=E Signal=in:TO_BE_DETERMINED", " Location does not have any mode to begin with", " Module=I_DDR LinkedObject=din10 Location= Port=R Signal=in:TO_BE_DETERMINED", " Location does not have any mode to begin with", - " Module=I_BUF LinkedObject=din11 Location=HR_5_2_1P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=din11 Location=HR_5_2_1P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din11 Location=HR_5_2_1P Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din11 Location=HR_5_2_1P Port=R Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=din12 Location=HR_1_24_12P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=din12 Location=HR_1_24_12P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din12 Location=HR_1_24_12P Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din12 Location=HR_1_24_12P Port=R Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=din20 Location= Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=din20 Location= Port=EN Signal=in:f2g_in_en_{A|B}", " Location does not have any mode to begin with", - " Module=I_BUF LinkedObject=dinosc0 Location=HR_2_20_10P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=dinosc0 Location=HR_2_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=dinosc0 Location=HR_2_20_10P Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=dinosc0 Location=HR_2_20_10P Port=R Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=dinosc1 Location=HR_5_20_10P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=dinosc1 Location=HR_5_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=dinosc1 Location=HR_5_20_10P Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=dinosc1 Location=HR_5_20_10P Port=R Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=dinosc2 Location= Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=dinosc2 Location= Port=EN Signal=in:f2g_in_en_{A|B}", " Location does not have any mode to begin with", " Module=I_DDR LinkedObject=dinosc2 Location= Port=E Signal=in:TO_BE_DETERMINED", " Location does not have any mode to begin with", " Module=I_DDR LinkedObject=dinosc2 Location= Port=R Signal=in:TO_BE_DETERMINED", " Location does not have any mode to begin with", - " Module=I_BUF LinkedObject=dinosc3 Location=HR_5_22_11P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=dinosc3 Location=HR_5_22_11P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=dinosc3 Location=HR_5_22_11P Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=dinosc3 Location=HR_5_22_11P Port=R Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=dinosc4 Location=HR_1_30_15P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=dinosc4 Location=HR_1_30_15P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=dinosc4 Location=HR_1_30_15P Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=dinosc4 Location=HR_1_30_15P Port=R Signal=in:TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout00 Location=HP_1_22_11P Port=E Signal=in:TO_BE_DETERMINED", @@ -665,22 +676,22 @@ " Location does not have any mode to begin with", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=PLL_EN Signal=in:TO_BE_DETERMINED", " Location does not have any mode to begin with", - " Module=I_BUF LinkedObject=clk30 Location=HR_1_CC_38_19P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=clk30 Location=HR_1_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", " User design does not utilize linked-object clk30 wrapped-instance port EN", " Module=PLL LinkedObject=clk30 Location=HR_1_CC_38_19P Port=LOCK Signal=out:TO_BE_DETERMINED", " User design does not utilize linked-object clk30 wrapped-instance port LOCK", " Module=PLL LinkedObject=clk30 Location=HR_1_CC_38_19P Port=PLL_EN Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=clk31 Location=HR_3_CC_38_19P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=clk31 Location=HR_3_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", " User design does not utilize linked-object clk31 wrapped-instance port EN", " Module=PLL LinkedObject=clk31 Location=HR_3_CC_38_19P Port=LOCK Signal=out:TO_BE_DETERMINED", " User design does not utilize linked-object clk31 wrapped-instance port LOCK", " Module=PLL LinkedObject=clk31 Location=HR_3_CC_38_19P Port=PLL_EN Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=clk40 Location=HR_2_CC_38_19P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=clk40 Location=HR_2_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", " User design does not utilize linked-object clk40 wrapped-instance port EN", - " Module=I_BUF_DS LinkedObject=din30_n+din30_p Location=HR_2_0_0P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF_DS LinkedObject=din30_n+din30_p Location=HR_2_0_0P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din30_n+din30_p Location=HR_2_1_0N Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din30_n+din30_p Location=HR_2_1_0N Port=R Signal=in:TO_BE_DETERMINED", - " Module=I_BUF_DS LinkedObject=din31_n+din31_p Location=HR_2_2_1P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF_DS LinkedObject=din31_n+din31_p Location=HR_2_2_1P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din31_n+din31_p Location=HR_2_3_1N Port=E Signal=in:TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din31_n+din31_p Location=HR_2_3_1N Port=R Signal=in:TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout30_n+dout30_p Location=HR_2_7_3N Port=E Signal=in:TO_BE_DETERMINED", diff --git a/tests/unittest/ModelConfig/model_config_netlist.ppdb.json b/tests/unittest/ModelConfig/model_config_netlist.ppdb.json index 950ce035c..dd412699e 100644 --- a/tests/unittest/ModelConfig/model_config_netlist.ppdb.json +++ b/tests/unittest/ModelConfig/model_config_netlist.ppdb.json @@ -104,14 +104,14 @@ " Cell port \\O_P is connected to output port \\dout_osc_p", " Data Width: 1", " Trace \\I_BUF --> \\CLK_BUF", - " Try \\I_BUF $iopadmap$top.clk0 out connection: $iopadmap$clk0 -> $auto$clkbufmap.cc:284:execute$458", - " Connected $auto$clkbufmap.cc:284:execute$458", + " Try \\I_BUF $iopadmap$top.clk0 out connection: $iopadmap$clk0 -> $auto$clkbufmap.cc:284:execute$507", + " Connected $auto$clkbufmap.cc:284:execute$507", " Data Width: -2", " Try \\I_BUF $iopadmap$top.clk1 out connection: $iopadmap$clk1 -> \\clk_buf", " Connected \\clk_buf", " Data Width: -2", - " Try \\I_BUF $iopadmap$top.clk2 out connection: $iopadmap$clk2 -> $auto$clkbufmap.cc:284:execute$463", - " Connected $auto$clkbufmap.cc:284:execute$463", + " Try \\I_BUF $iopadmap$top.clk2 out connection: $iopadmap$clk2 -> $auto$clkbufmap.cc:284:execute$512", + " Connected $auto$clkbufmap.cc:284:execute$512", " Data Width: -2", " Trace \\I_BUF_DS --> \\CLK_BUF", " Trace \\CLK_BUF --> \\PLL", @@ -160,8 +160,8 @@ " Try \\O_BUF $iopadmap$top.dout_serdes out connection: $iopadmap$dout_serdes -> \\o_serdes", " Connected \\o_serdes", " Parameter \\DATA_RATE: \"DDR\"", - " Parameter \\WIDTH: 8", - " Data Width: 8", + " Parameter \\WIDTH: 4", + " Data Width: 4", " Trace \\O_BUFT --> \\O_DELAY", " Trace \\O_BUFT --> \\O_DDR", " Trace \\O_BUFT --> \\O_SERDES", @@ -190,11 +190,11 @@ " Trace \\O_BUFT_DS --> \\O_SERDES_CLK", " Trace fabric clock buffer", " Detect fabric clock buffer", - " \\I : $auto$clkbufmap.cc:285:execute$462", + " \\I : $auto$clkbufmap.cc:285:execute$511", " \\O : \\clk0_div", " Trace gearbox clock source", - " \\I_DELAY \\i_delay port \\CLK_IN: $auto$clkbufmap.cc:317:execute$460", - " Connected to \\CLK_BUF $auto$clkbufmap.cc:284:execute$458 port \\O", + " \\I_DELAY \\i_delay port \\CLK_IN: $auto$clkbufmap.cc:317:execute$509", + " Connected to \\CLK_BUF $auto$clkbufmap.cc:284:execute$507 port \\O", " \\I_SERDES \\i_serdes port \\PLL_CLK: \\pll_clk", " Connected to \\PLL \\pll port \\CLK_OUT", " \\I_DDR \\i_ddr port \\C: \\pll_clk", @@ -206,8 +206,8 @@ " \\O_SERDES_CLK \\o_serdes_clk port \\PLL_CLK: \\pll_clk", " Connected to \\PLL \\pll port \\CLK_OUT", " Trace Fabric Clock", - " Module \\CLK_BUF $auto$clkbufmap.cc:284:execute$458: clock port \\O, net $auto$clkbufmap.cc:317:execute$460", - " Connected to cell \\DFFRE $abc$205$auto$blifparse.cc:377:parse_blif$206", + " Module \\CLK_BUF $auto$clkbufmap.cc:284:execute$507: clock port \\O, net $auto$clkbufmap.cc:317:execute$509", + " Connected to cell \\DFFRE $abc$218$auto$blifparse.cc:377:parse_blif$219", " Which is not a IO primitive. Send to fabric", " Module \\CLK_BUF \\clk_buf: clock port \\O, net \\clk1_buf", " Connected to cell \\O_DELAY \\o_delay", @@ -226,9 +226,9 @@ " Connected to cell \\O_DDR \\o_ddr", " Which is a primitive", " This is core_clk. Send to fabric", - " Module \\PLL \\pll: clock port \\CLK_OUT_DIV4, net $delete_wire$487", - " Module \\CLK_BUF $auto$clkbufmap.cc:284:execute$463: clock port \\O, net $auto$clkbufmap.cc:317:execute$465", - " Connected to cell \\DFFRE $abc$209$auto$blifparse.cc:377:parse_blif$210", + " Module \\PLL \\pll: clock port \\CLK_OUT_DIV4, net $delete_wire$540", + " Module \\CLK_BUF $auto$clkbufmap.cc:284:execute$512: clock port \\O, net $auto$clkbufmap.cc:317:execute$514", + " Connected to cell \\DFFRE $abc$222$auto$blifparse.cc:377:parse_blif$223", " Which is not a IO primitive. Send to fabric", " Module \\BOOT_CLOCK \\boot_clock: clock port \\O, net \\osc", " Connected to cell \\PLL \\pll_osc", @@ -238,8 +238,8 @@ " Connected to cell \\O_DDR \\o_ddr_osc", " Which is a primitive", " This is core_clk. Send to fabric", - " Module \\FCLK_BUF $auto$clkbufmap.cc:282:execute$461: clock port \\O, net \\clk0_div", - " Connected to cell \\DFFRE $abc$201$auto$blifparse.cc:377:parse_blif$202", + " Module \\FCLK_BUF $auto$clkbufmap.cc:282:execute$510: clock port \\O, net \\clk0_div", + " Connected to cell \\DFFRE $abc$210$auto$blifparse.cc:377:parse_blif$211", " Which is not a IO primitive. Send to fabric", " Summary", " |---------------------------------------------------------------------------------------------------|", @@ -270,58 +270,64 @@ " | *********************************************************** |", " |---------------------------------------------------------------------------------------------------|", " Final checking is good", - " Assign location HR_2_26_13P (and properties) to Port delay_tap[3]", - " Assign location HP_2_23_11N (and properties) to Port dout_osc_n", - " Assign location HR_2_4_2P (and properties) to Port clk_out", + " Assign location HR_1_CC_18_9P (and properties) to Port clk0", + " Assign location HP_1_CC_18_9P (and properties) to Port clk1", + " Assign location HP_1_0_0P (and properties) to Port reset", + " Assign location HP_1_20_10P (and properties) to Port din", + " Assign location HP_1_4_2P (and properties) to Port din_p", + " Assign location HP_1_5_2N (and properties) to Port din_n", + " Assign location HP_2_20_10P (and properties) to Port dout", " Assign location HP_1_8_4P (and properties) to Port dout_p", - " Assign location HR_5_0_0P (and properties) to Port din_clk2", - " Assign location HR_5_CC_38_19P (and properties) to Port clk2", - " Assign location HR_2_20_10P (and properties) to Port delay_tap[0]", - " Assign location HR_2_2_1P (and properties) to Port dout_serdes", " Assign location HP_1_9_4N (and properties) to Port dout_n", - " Assign location HR_2_22_11P (and properties) to Port delay_tap[1]", - " Assign location HR_2_0_0P (and properties) to Port din_serdes", " Assign location HP_2_22_11P (and properties) to Port dout_osc_p", - " Assign location HP_2_20_10P (and properties) to Port dout", - " Assign location HP_1_0_0P (and properties) to Port reset", + " Assign location HP_2_23_11N (and properties) to Port dout_osc_n", + " Assign location HR_5_CC_38_19P (and properties) to Port clk2", + " Assign location HR_5_0_0P (and properties) to Port din_clk2", " Assign location HR_5_1_0N (and properties) to Port dout_clk2", - " Assign location HR_2_30_15P (and properties) to Port delay_tap[5]", - " Assign location HR_1_CC_18_9P (and properties) to Port clk0", - " Assign location HP_1_4_2P (and properties) to Port din_p", - " Assign location HR_2_28_14P (and properties) to Port delay_tap[4]", + " Assign location HR_2_0_0P (and properties) to Port din_serdes", + " Assign location HR_2_2_1P (and properties) to Port dout_serdes", + " Assign location HR_2_4_2P (and properties) to Port clk_out", + " Assign location HR_2_20_10P (and properties) to Port delay_tap[0]", + " Assign location HR_2_22_11P (and properties) to Port delay_tap[1]", " Assign location HR_2_24_12P (and properties) to Port delay_tap[2]", - " Assign location HP_1_CC_18_9P (and properties) to Port clk1", - " Assign location HP_1_20_10P (and properties) to Port din", - " Assign location HP_1_5_2N (and properties) to Port din_n", + " Assign location HR_2_26_13P (and properties) to Port delay_tap[3]", + " Assign location HR_2_28_14P (and properties) to Port delay_tap[4]", + " Assign location HR_2_30_15P (and properties) to Port delay_tap[5]", " Cross-check instances vs wrapped-instances", " Generate SDC", " Determine data signals", " Pin object=clk0, location: HR_1_CC_18_9P", - " Skip this because 'Temporarily disable all clock constraint'", + " Data signal from object clk0", + " Module=I_BUF Linked-object=clk0 Port=O Net=$flatten$auto$rs_design_edit.cc:1146:execute$593.$iopadmap$clk0 - Not found", + " Failure reason: Clock data from object clk0 port O is not routed to fabric", " Pin object=clk1, location: HP_1_CC_18_9P", - " Skip this because 'The clock is not used by fabric'", + " Data signal from object clk1", + " Failure reason: Object clk1 is primitive \\PLL but data signal is not defined", " Pin object=clk2, location: HR_5_CC_38_19P", - " Skip this because 'Temporarily disable all clock constraint'", + " Data signal from object clk2", + " Module=I_BUF Linked-object=clk2 Port=O Net=$flatten$auto$rs_design_edit.cc:1146:execute$593.$iopadmap$clk2 - Not found", + " Failure reason: Clock data from object clk2 port O is not routed to fabric", " Pin object=clk_out, location: HR_2_4_2P", - " Skip this because 'The clock is Gearbox internal fast clock'", + " Data signal from object clk_out", + " Failure reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", " Pin object=delay_tap[0], location: HR_2_20_10P", " Data signal from object delay_tap[0]", - " Module=O_BUF Linked-object=delay_tap[0] Port=I Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$514 - Found", + " Module=O_BUF Linked-object=delay_tap[0] Port=I Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$567 - Found", " Pin object=delay_tap[1], location: HR_2_22_11P", " Data signal from object delay_tap[1]", - " Module=O_BUF Linked-object=delay_tap[1] Port=I Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$515 - Found", + " Module=O_BUF Linked-object=delay_tap[1] Port=I Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$568 - Found", " Pin object=delay_tap[2], location: HR_2_24_12P", " Data signal from object delay_tap[2]", - " Module=O_BUF Linked-object=delay_tap[2] Port=I Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$516 - Found", + " Module=O_BUF Linked-object=delay_tap[2] Port=I Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$569 - Found", " Pin object=delay_tap[3], location: HR_2_26_13P", " Data signal from object delay_tap[3]", - " Module=O_BUF Linked-object=delay_tap[3] Port=I Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$517 - Found", + " Module=O_BUF Linked-object=delay_tap[3] Port=I Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$570 - Found", " Pin object=delay_tap[4], location: HR_2_28_14P", " Data signal from object delay_tap[4]", - " Module=O_BUF Linked-object=delay_tap[4] Port=I Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$518 - Found", + " Module=O_BUF Linked-object=delay_tap[4] Port=I Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$571 - Found", " Pin object=delay_tap[5], location: HR_2_30_15P", " Data signal from object delay_tap[5]", - " Module=O_BUF Linked-object=delay_tap[5] Port=I Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$519 - Found", + " Module=O_BUF Linked-object=delay_tap[5] Port=I Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$572 - Found", " Pin object=din, location: HP_1_20_10P", " Data signal from object din", " Module=I_DELAY Linked-object=din Port=O Net=din_delay - Found", @@ -346,14 +352,10 @@ " Module=O_BUF Linked-object=dout_clk2 Port=I Net=$iopadmap$dout_clk2 - Found", " Pin object=dout_serdes, location: HR_2_2_1P", " Data signal from object dout_serdes", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$528 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$529 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$530 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$531 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$532 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$533 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$534 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$535 - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$abc$194$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test/./top.v:199$5_Y[0] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$abc$194$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test/./top.v:199$5_Y[1] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$abc$194$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test/./top.v:199$5_Y[2] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$abc$194$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test/./top.v:199$5_Y[3] - Found", " Pin object=enable, location: ", " Pin location is not assigned", " Pin object=reset, location: HP_1_0_0P", @@ -369,33 +371,33 @@ " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=dout_p, location: HP_1_8_4P", " Data signal from object dout_p", - " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$520 - Found", - " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$521 - Found", + " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$573 - Found", + " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$574 - Found", " Pin object=dout_osc_n, location: HP_2_23_11N", " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=dout_osc_p, location: HP_2_22_11P", " Data signal from object dout_osc_p", - " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$524 - Found", - " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto$rs_design_edit.cc:606:add_wire_btw_prims$525 - Found", + " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$577 - Found", + " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto$rs_design_edit.cc:614:add_wire_btw_prims$578 - Found", " Determine internal control signals", - " Module=I_BUF LinkedObject=clk0 Location=HR_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{X}", - " Module=I_BUF LinkedObject=clk1 Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=clk0 Location=HR_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=clk1 Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=PLL LinkedObject=clk1 Location=HP_1_CC_18_9P Port=LOCK Signal=out:TO_BE_DETERMINED", " User design does not utilize linked-object clk1 wrapped-instance port LOCK", " Module=PLL LinkedObject=clk1 Location=HP_1_CC_18_9P Port=PLL_EN Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=clk2 Location=HR_5_CC_38_19P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=clk2 Location=HR_5_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=O_SERDES_CLK LinkedObject=clk_out Location=HR_2_4_2P Port=CLK_EN Signal=in:TO_BE_DETERMINED", " Module=O_SERDES_CLK LinkedObject=clk_out Location=HR_2_4_2P Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", " User design does not utilize linked-object clk_out wrapped-instance port PLL_LOCK", - " Module=I_BUF LinkedObject=din Location=HP_1_20_10P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=din Location=HP_1_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DELAY LinkedObject=din Location=HP_1_20_10P Port=DLY_ADJ Signal=in:rule=half-first:f2g_trx_dly_adj", " Module=I_DELAY LinkedObject=din Location=HP_1_20_10P Port=DLY_INCDEC Signal=in:rule=half-first:f2g_trx_dly_inc", " Module=I_DELAY LinkedObject=din Location=HP_1_20_10P Port=DLY_LOAD Signal=in:rule=half-first:f2g_trx_dly_ld", " Module=I_DELAY LinkedObject=din Location=HP_1_20_10P Port=DLY_TAP_VALUE Signal=out:rule=half-first:g2f_trx_dly_tap", - " Module=I_BUF LinkedObject=din_clk2 Location=HR_5_0_0P Port=EN Signal=in:f2g_in_en_{X}", - " Module=I_BUF LinkedObject=din_serdes Location=HR_2_0_0P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=din_clk2 Location=HR_5_0_0P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=I_BUF LinkedObject=din_serdes Location=HR_2_0_0P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=BITSLIP_ADJ Signal=in:TO_BE_DETERMINED", - " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=DATA_VALID Signal=out:TO_BE_DETERMINED", + " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=DATA_VALID Signal=out:g2f_rx_dvalid_{A|B}", " User design does not utilize linked-object din_serdes wrapped-instance port DATA_VALID", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=DPA_ERROR Signal=out:TO_BE_DETERMINED", " User design does not utilize linked-object din_serdes wrapped-instance port DPA_ERROR", @@ -404,7 +406,7 @@ " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=EN Signal=in:TO_BE_DETERMINED", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", " User design does not utilize linked-object din_serdes wrapped-instance port PLL_LOCK", - " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=RX_RST Signal=in:TO_BE_DETERMINED", + " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=RX_RST Signal=in:f2g_trx_reset_n_{A|B}", " Module=O_DELAY LinkedObject=dout Location=HP_2_20_10P Port=DLY_ADJ Signal=in:rule=half-first:f2g_trx_dly_adj", " Module=O_DELAY LinkedObject=dout Location=HP_2_20_10P Port=DLY_INCDEC Signal=in:rule=half-first:f2g_trx_dly_inc", " Module=O_DELAY LinkedObject=dout Location=HP_2_20_10P Port=DLY_LOAD Signal=in:rule=half-first:f2g_trx_dly_ld", @@ -414,25 +416,25 @@ " User design does not utilize linked-object dout_serdes wrapped-instance port CHANNEL_BOND_SYNC_IN", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=CHANNEL_BOND_SYNC_OUT Signal=out:TO_BE_DETERMINED", " User design does not utilize linked-object dout_serdes wrapped-instance port CHANNEL_BOND_SYNC_OUT", - " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=LOAD_WORD Signal=in:TO_BE_DETERMINED", + " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=LOAD_WORD Signal=in:f2g_tx_dvalid_{A|B}", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=OE_IN Signal=in:TO_BE_DETERMINED", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=OE_OUT Signal=out:TO_BE_DETERMINED", " User design does not utilize linked-object dout_serdes wrapped-instance port OE_OUT", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", " User design does not utilize linked-object dout_serdes wrapped-instance port PLL_LOCK", - " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=RST Signal=in:TO_BE_DETERMINED", - " Module=I_BUF LinkedObject=enable Location= Port=EN Signal=in:f2g_in_en_{X}", + " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=RST Signal=in:f2g_trx_reset_n_{A|B}", + " Module=I_BUF LinkedObject=enable Location= Port=EN Signal=in:f2g_in_en_{A|B}", " Location does not have any mode to begin with", - " Module=I_BUF LinkedObject=reset Location=HP_1_0_0P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF LinkedObject=reset Location=HP_1_0_0P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=LOCK Signal=out:TO_BE_DETERMINED", " Location does not have any mode to begin with", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=PLL_EN Signal=in:TO_BE_DETERMINED", " Location does not have any mode to begin with", - " Module=I_BUF_DS LinkedObject=din_n+din_p Location=HP_1_4_2P Port=EN Signal=in:f2g_in_en_{X}", + " Module=I_BUF_DS LinkedObject=din_n+din_p Location=HP_1_4_2P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din_n+din_p Location=HP_1_5_2N Port=E Signal=in:TO_BE_DETERMINED", - " Fail to trace fabric module connection: $flatten$auto$rs_design_edit.cc:1139:execute$556.$iopadmap$enable", + " Fail to trace fabric module connection: $flatten$auto$rs_design_edit.cc:1146:execute$593.$iopadmap$enable", " Module=I_DDR LinkedObject=din_n+din_p Location=HP_1_5_2N Port=R Signal=in:TO_BE_DETERMINED", - " Fail to trace fabric module connection: $flatten$auto$rs_design_edit.cc:1139:execute$556.$iopadmap$reset", + " Fail to trace fabric module connection: $flatten$auto$rs_design_edit.cc:1146:execute$593.$iopadmap$reset", " Module=O_DDR LinkedObject=dout_n+dout_p Location=HP_1_9_4N Port=E Signal=in:TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout_n+dout_p Location=HP_1_9_4N Port=R Signal=in:TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout_osc_n+dout_osc_p Location=HP_2_23_11N Port=E Signal=in:TO_BE_DETERMINED", @@ -469,7 +471,7 @@ }, { "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:284:execute$458", + "name" : "$auto$clkbufmap.cc:284:execute$507", "linked_object" : "clk0", "linked_objects" : { "clk0" : { @@ -481,7 +483,7 @@ }, "connectivity" : { "I" : "$iopadmap$clk0", - "O" : "$auto$clkbufmap.cc:317:execute$460" + "O" : "$auto$clkbufmap.cc:317:execute$509" }, "parameters" : { "ROUTE_TO_FABRIC_CLK" : "0" @@ -568,7 +570,7 @@ "connectivity" : { "CLK_IN" : "clk1_buf", "CLK_OUT" : "pll_clk", - "CLK_OUT_DIV4" : "$delete_wire$487" + "CLK_OUT_DIV4" : "$delete_wire$540" }, "parameters" : { "OUT0_ROUTE_TO_FABRIC_CLK" : "1", @@ -619,7 +621,7 @@ }, { "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:284:execute$463", + "name" : "$auto$clkbufmap.cc:284:execute$512", "linked_object" : "clk2", "linked_objects" : { "clk2" : { @@ -631,7 +633,7 @@ }, "connectivity" : { "I" : "$iopadmap$clk2", - "O" : "$auto$clkbufmap.cc:317:execute$465" + "O" : "$auto$clkbufmap.cc:317:execute$514" }, "parameters" : { "ROUTE_TO_FABRIC_CLK" : "2" @@ -886,7 +888,7 @@ } }, "connectivity" : { - "CLK_IN" : "$auto$clkbufmap.cc:317:execute$460", + "CLK_IN" : "$auto$clkbufmap.cc:317:execute$509", "I" : "$iopadmap$din", "O" : "din_delay" }, @@ -1105,7 +1107,7 @@ }, "parameters" : { "DATA_RATE" : "DDR", - "WIDTH" : "8" + "WIDTH" : "4" }, "pre_primitive" : "O_BUF", "post_primitives" : [ @@ -1411,7 +1413,7 @@ }, { "module" : "FCLK_BUF", - "name" : "$auto$clkbufmap.cc:282:execute$461", + "name" : "$auto$clkbufmap.cc:282:execute$510", "linked_object" : "FABRIC_CLKBUF#0", "linked_objects" : { "FABRIC_CLKBUF#0" : { @@ -1423,7 +1425,7 @@ } }, "connectivity" : { - "I" : "$auto$clkbufmap.cc:285:execute$462", + "I" : "$auto$clkbufmap.cc:285:execute$511", "O" : "clk0_div" }, "parameters" : { diff --git a/tests/unittest/ModelConfig/ric/I_BUF.api.json b/tests/unittest/ModelConfig/ric/I_BUF.api.json index 7b747ca53..89ba13108 100644 --- a/tests/unittest/ModelConfig/ric/I_BUF.api.json +++ b/tests/unittest/ModelConfig/ric/I_BUF.api.json @@ -11,7 +11,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -89,7 +89,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -167,7 +167,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -245,7 +245,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -323,7 +323,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -401,7 +401,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -479,7 +479,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", diff --git a/tests/unittest/ModelConfig/ric/I_BUF_DS.api.json b/tests/unittest/ModelConfig/ric/I_BUF_DS.api.json index 669b2af3d..8ac03ee7a 100644 --- a/tests/unittest/ModelConfig/ric/I_BUF_DS.api.json +++ b/tests/unittest/ModelConfig/ric/I_BUF_DS.api.json @@ -11,7 +11,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -89,7 +89,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -167,7 +167,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -245,7 +245,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -323,7 +323,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -401,7 +401,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -479,7 +479,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", diff --git a/tests/unittest/ModelConfig/ric/O_BUF.api.json b/tests/unittest/ModelConfig/ric/O_BUF.api.json index 881cf7838..2c8c6c89e 100644 --- a/tests/unittest/ModelConfig/ric/O_BUF.api.json +++ b/tests/unittest/ModelConfig/ric/O_BUF.api.json @@ -11,7 +11,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -97,7 +97,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -183,7 +183,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -269,7 +269,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -355,7 +355,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -441,7 +441,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -527,7 +527,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", diff --git a/tests/unittest/ModelConfig/ric/O_BUFT.api.json b/tests/unittest/ModelConfig/ric/O_BUFT.api.json index 134a7d87b..b29e5c46d 100644 --- a/tests/unittest/ModelConfig/ric/O_BUFT.api.json +++ b/tests/unittest/ModelConfig/ric/O_BUFT.api.json @@ -11,7 +11,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -97,7 +97,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -183,7 +183,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -269,7 +269,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -355,7 +355,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -441,7 +441,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -527,7 +527,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", diff --git a/tests/unittest/ModelConfig/ric/O_BUFT_DS.api.json b/tests/unittest/ModelConfig/ric/O_BUFT_DS.api.json index 2b44f6b9d..dbc68e1d5 100644 --- a/tests/unittest/ModelConfig/ric/O_BUFT_DS.api.json +++ b/tests/unittest/ModelConfig/ric/O_BUFT_DS.api.json @@ -11,7 +11,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -97,7 +97,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -183,7 +183,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -269,7 +269,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -355,7 +355,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -441,7 +441,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -527,7 +527,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", diff --git a/tests/unittest/ModelConfig/ric/O_BUF_DS.api.json b/tests/unittest/ModelConfig/ric/O_BUF_DS.api.json index f86339fbc..c45ac5b62 100644 --- a/tests/unittest/ModelConfig/ric/O_BUF_DS.api.json +++ b/tests/unittest/ModelConfig/ric/O_BUF_DS.api.json @@ -11,7 +11,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -97,7 +97,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -183,7 +183,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -269,7 +269,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -355,7 +355,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -441,7 +441,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -527,7 +527,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", diff --git a/tests/unittest/ModelConfig/ric/gbox_mode.api.json b/tests/unittest/ModelConfig/ric/gbox_mode.api.json index 7d318cf0f..2d2439b1b 100644 --- a/tests/unittest/ModelConfig/ric/gbox_mode.api.json +++ b/tests/unittest/ModelConfig/ric/gbox_mode.api.json @@ -11,7 +11,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -101,7 +101,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -191,7 +191,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -281,7 +281,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", @@ -371,7 +371,7 @@ }, { "attr": "PEER_IS_ON", - "value": "PEER_off" + "value": "PEER_on" }, { "attr": "TX_CLOCK_IO", diff --git a/tests/unittest/ModelConfig/ric/gbox_top.tcl b/tests/unittest/ModelConfig/ric/gbox_top.tcl index 4190c7b0b..3160b4ffb 100644 --- a/tests/unittest/ModelConfig/ric/gbox_top.tcl +++ b/tests/unittest/ModelConfig/ric/gbox_top.tcl @@ -6,7 +6,7 @@ define_block -name GBOX_TOP #################################### define_attr -block GBOX_TOP -name RATE -addr 0 -width 4 -enumname GBOX_ATT_0 -enum {Three 3} {Four 4} {Five 5} {Six 6} {Seven 7} {Eight 8} {Night 9} {Ten 10} define_attr -block GBOX_TOP -name MASTER_SLAVE -addr 4 -width 1 -enumname GBOX_ATT_1 -enum {Slave 0} {Master 1} -define_attr -block GBOX_TOP -name PEER_IS_ON -addr 5 -width 1 -enumname GBOX_ATT_2 -enum {PEER_off 0} {PEER_ON 1} +define_attr -block GBOX_TOP -name PEER_IS_ON -addr 5 -width 1 -enumname GBOX_ATT_2 -enum {PEER_off 0} {PEER_on 1} define_attr -block GBOX_TOP -name TX_CLOCK_IO -addr 6 -width 1 -enumname GBOX_ATT_3 -enum {TX_normal_IO 0} {TX_clock_IO 1} define_attr -block GBOX_TOP -name TX_DDR_MODE -addr 7 -width 2 -enumname GBOX_ATT_4 -enum {TX_direct 0} {TX_ddr 1} {TX_sdr 2} define_attr -block GBOX_TOP -name TX_BYPASS -addr 9 -width 1 -enumname GBOX_ATT_5 -enum {TX_gear_on 0} {TX_bypass 1}