diff --git a/src/Compiler/CompilerOpenFPGA.cpp b/src/Compiler/CompilerOpenFPGA.cpp index d0b9f1427..fd31b7e1c 100644 --- a/src/Compiler/CompilerOpenFPGA.cpp +++ b/src/Compiler/CompilerOpenFPGA.cpp @@ -3703,6 +3703,11 @@ bool CompilerOpenFPGA::GenerateBitstream() { std::filesystem::path config_mapping = datapath / "configuration" / device_data.series / (device_name + "_config_attributes.mapping.json"); + std::filesystem::path routing_exe = + datapath / "configuration" / "routing_configurator.py"; + std::filesystem::path routing_model = datapath / "configuration" / + device_data.series / + (device_name + "_routing.py"); std::filesystem::path backdoor_script = datapath / "configuration" / device_data.series / "icb_backdoor.py"; if (!std::filesystem::exists(config_mapping)) { @@ -3713,6 +3718,15 @@ bool CompilerOpenFPGA::GenerateBitstream() { FilePath(Action::Synthesis, "io_config.json"); std::vector api_files = FOEDAG::FileUtils::FindFilesByExtension(ric_folder.string(), ".json"); + if (!std::filesystem::exists(routing_exe) || + !std::filesystem::exists(routing_model)) { +#if 0 + printf("Debug Routing exe: %s\n", routing_exe.c_str()); + printf("Debug Routing model: %s\n", routing_model.c_str()); +#endif + routing_exe = ""; + routing_model = ""; + } if (std::filesystem::exists(ric_model) && std::filesystem::exists(config_mapping) && std::filesystem::exists(netlist_ppdb)) { @@ -3770,21 +3784,27 @@ bool CompilerOpenFPGA::GenerateBitstream() { if (CFG_find_string_in_vector({"Gemini", "Virgo"}, device_data.series) >= 0) { command = CFG_print( - "%s\nmodel_config gen_ppdb -netlist_ppdb %s -config_mapping %s " - "-property_json model_config.property.json -pll_workaround 0 " + "%s\nmodel_config gen_ppdb -netlist_ppdb \"%s\" -config_mapping " + "\"%s\" -property_json model_config.property.json -routing_config " + "\"%s\" -routing_config_model \"%s\" -pll_workaround 0 " "model_config.ppdb.json", - command.c_str(), netlist_ppdb.c_str(), config_mapping.c_str()); + command.c_str(), netlist_ppdb.c_str(), config_mapping.c_str(), + routing_exe.c_str(), routing_model.c_str()); command = CFG_print( - "%s\nmodel_config gen_ppdb -netlist_ppdb %s -config_mapping %s " - "-property_json model_config.property.json -pll_workaround 1 " + "%s\nmodel_config gen_ppdb -netlist_ppdb \"%s\" -config_mapping " + "\"%s\" -property_json model_config.property.json -routing_config " + "\"%s\" -routing_config_model \"%s\" -pll_workaround 1 " "model_config.post.ppdb.json", - command.c_str(), netlist_ppdb.c_str(), config_mapping.c_str()); + command.c_str(), netlist_ppdb.c_str(), config_mapping.c_str(), + routing_exe.c_str(), routing_model.c_str()); gen_bitstream_count = 2; } else { command = CFG_print( - "%s\nmodel_config gen_ppdb -netlist_ppdb %s -config_mapping %s " - "-property_json model_config.property.json model_config.ppdb.json", - command.c_str(), netlist_ppdb.c_str(), config_mapping.c_str()); + "%s\nmodel_config gen_ppdb -netlist_ppdb \"%s\" -config_mapping " + "\"%s\" -property_json model_config.property.json -routing_config " + "\"%s\" -routing_config_model \"%s\" model_config.ppdb.json", + command.c_str(), netlist_ppdb.c_str(), config_mapping.c_str(), + routing_exe.c_str(), routing_model.c_str()); } std::string design = "model_config.ppdb.json"; std::string bit_file = "io_bitstream.bit"; diff --git a/src/Configuration/CFGCommon/CFGCommon.cpp b/src/Configuration/CFGCommon/CFGCommon.cpp index 3d83d2144..81eb913e1 100644 --- a/src/Configuration/CFGCommon/CFGCommon.cpp +++ b/src/Configuration/CFGCommon/CFGCommon.cpp @@ -800,7 +800,7 @@ static void CFG_Python_get_result(PyObject* list, } std::map CFG_Python( - std::vector commands, std::vector results, + std::vector commands, const std::vector results, void* dict_ptr) { PyObject* dict = nullptr; if (dict_ptr == nullptr) { @@ -935,26 +935,38 @@ std::vector CFG_Python_OBJ::get_strs(const std::string& name) { return strs; } -CFG_Python_MGR::CFG_Python_MGR() { +CFG_Python_MGR::CFG_Python_MGR(const std::string& filepath, + const std::vector results) { Py_Initialize(); - PyObject* dict = PyDict_New(); - dict_ptr = dict; + if (filepath.size()) { + main_module = set_file(filepath, results); + CFG_ASSERT(main_module.size()); + CFG_ASSERT(module_objs.find(main_module) != module_objs.end()); + dict_ptr = PyModule_GetDict((PyObject*)(module_objs[main_module])); + } else { + CFG_ASSERT(main_module.empty()); + PyObject* dict = PyDict_New(); + dict_ptr = dict; + } } CFG_Python_MGR::~CFG_Python_MGR() { - if (dict_ptr != nullptr) { + if (main_module.empty() && dict_ptr != nullptr) { PyObject* dict = static_cast(dict_ptr); Py_DECREF(dict); - dict_ptr = nullptr; } + dict_ptr = nullptr; for (auto& iter : module_objs) { Py_XDECREF((PyObject*)(iter.second)); } Py_Finalize(); + main_module = ""; } -std::string CFG_Python_MGR::set_file(const std::string& file) { - CFG_ASSERT(dict_ptr != nullptr); +std::string CFG_Python_MGR::get_main_module() { return main_module; } + +std::string CFG_Python_MGR::set_file(const std::string& file, + const std::vector results) { std::filesystem::path fullpath = std::filesystem::absolute(file.c_str()); CFG_ASSERT_MSG(std::filesystem::exists(fullpath), "Python file %s does not exist", fullpath.c_str()); @@ -963,9 +975,11 @@ std::string CFG_Python_MGR::set_file(const std::string& file) { std::filesystem::path dir = fullpath.parent_path(); std::filesystem::path filename = fullpath.filename(); std::string standard_dir = CFG_change_directory_to_linux_format(dir.string()); - run({"import sys", - CFG_print("sys.path.insert(0, '%s')", standard_dir.c_str())}, - {}); + PyRun_SimpleString(CFG_print("import sys\n" + "if '%s' not in sys.path:\n" + " sys.path.insert(0, '%s')\n", + standard_dir.c_str(), standard_dir.c_str()) + .c_str()); std::string module = filename.string().substr(0, filename.string().size() - 3); CFG_ASSERT(module_objs.find(module) == module_objs.end()); @@ -982,11 +996,18 @@ std::string CFG_Python_MGR::set_file(const std::string& file) { module.c_str()); } Py_XDECREF(pName); + if (results.size()) { + result_objs.clear(); + PyObject* globals = PyModule_GetDict((PyObject*)(module_objs[module])); + for (auto key : results) { + CFG_Python_get_result(globals, key, result_objs); + } + } return module; } void CFG_Python_MGR::run(std::vector commands, - std::vector results) { + const std::vector results) { CFG_ASSERT(dict_ptr != nullptr); result_objs = CFG_Python(commands, results, dict_ptr); } diff --git a/src/Configuration/CFGCommon/CFGCommon.h b/src/Configuration/CFGCommon/CFGCommon.h index bfdf4c252..bb15e8ece 100644 --- a/src/Configuration/CFGCommon/CFGCommon.h +++ b/src/Configuration/CFGCommon/CFGCommon.h @@ -83,10 +83,14 @@ struct CFG_Python_OBJ { class CFG_Python_MGR { public: - CFG_Python_MGR(); + CFG_Python_MGR(const std::string& filepath = "", + const std::vector results = {}); ~CFG_Python_MGR(); - std::string set_file(const std::string& file); - void run(std::vector commands, std::vector results); + std::string get_main_module(); + std::string set_file(const std::string& file, + const std::vector results = {}); + void run(std::vector commands, + const std::vector results); std::vector run_file(const std::string& module, const std::string& function, std::vector args); @@ -99,6 +103,7 @@ class CFG_Python_MGR { std::vector result_strs(const std::string& result); private: + std::string main_module = ""; void* dict_ptr = nullptr; std::map result_objs; std::map module_objs; @@ -250,7 +255,7 @@ bool CFG_compare_two_binary_files(const std::string& filepath1, const std::string& filepath2); std::map CFG_Python( - std::vector commands, std::vector results, + std::vector commands, const std::vector results, void* dict_ptr = nullptr); #define CFG_POST_MSG(...) \ diff --git a/src/Configuration/ModelConfig/CMakeLists.txt b/src/Configuration/ModelConfig/CMakeLists.txt index b97d948f8..b11ee93aa 100644 --- a/src/Configuration/ModelConfig/CMakeLists.txt +++ b/src/Configuration/ModelConfig/CMakeLists.txt @@ -51,7 +51,6 @@ endif() add_library( ${subsystem} ${CFG_LIB_TYPE} ModelConfig.cpp - ModelConfig_IO_resource.cpp ModelConfig_IO.cpp ModelConfig_BITSTREAM_SETTING_XML.cpp ) diff --git a/src/Configuration/ModelConfig/ModelConfig.cpp b/src/Configuration/ModelConfig/ModelConfig.cpp index 1713cc4c9..31067fec0 100644 --- a/src/Configuration/ModelConfig/ModelConfig.cpp +++ b/src/Configuration/ModelConfig/ModelConfig.cpp @@ -29,6 +29,36 @@ along with this program. If not, see . #define DEBUG_PRINT_API 0 +void ModelConfig_post_msg(uint8_t type, uint32_t space, bool post, + nlohmann::json& messages, std::string msg) { + CFG_ASSERT(type == 0 || type == 1 || type == 2); + CFG_ASSERT(messages.is_array()); + while (space) { + msg = " " + msg; + space--; + } + if (post) { + if (type == 0) { + CFG_POST_MSG(msg.c_str()); + } else if (type == 1) { + CFG_POST_WARNING(msg.c_str()); + } else { + CFG_POST_ERR(msg.c_str()); + } + } + if (type == 0) { + msg = "Info: " + msg; + } else if (type == 1) { + msg = "Warning: " + msg; + } else { + msg = "Error: " + msg; + } + messages.push_back(msg); +} + +#define ModelConfig_POST_MSG(type, space, post, messages, ...) \ + { ModelConfig_post_msg(type, space, post, messages, CFG_print(__VA_ARGS__)); } + namespace FOEDAG { bool is_none_config_block(const device_block* block) { @@ -279,10 +309,10 @@ class ModelConfig_DEVICE { name.c_str(), value.c_str()); #endif ModelConfig_BITFIELD* bitfield = get_bitfield(instance, name); - if (bitfield == nullptr) { - CFG_POST_WARNING("Could not find bitfield '%s' for block instance '%s'", - name.c_str(), instance.c_str()); - } else if (value != "__DONT__") { + CFG_ASSERT_MSG(bitfield != nullptr, + "Could not find bitfield '%s' for block instance '%s'", + name.c_str(), instance.c_str()); + if (value != "__DONT__") { uint32_t v = 0; if (!is_number(value, v)) { CFG_ASSERT(bitfield->m_type != nullptr); @@ -338,49 +368,20 @@ class ModelConfig_DEVICE { CFG_ASSERT(object["location"].is_string()); CFG_ASSERT(object.contains("config_attributes")); } - } else { - CFG_ASSERT(instance.contains("location")); - CFG_ASSERT(instance["location"].is_string()); - CFG_ASSERT(instance.contains("config_attributes")); } + CFG_ASSERT(instance.contains("location")); + CFG_ASSERT(instance["location"].is_string()); + CFG_ASSERT(instance.contains("config_attributes")); } void set_design_attribute(const std::string& instance, nlohmann::json& attributes, const std::string& description) { CFG_ASSERT(attributes.is_object()); CFG_ASSERT(attributes.size()); - std::map object; - if (attributes.contains("__comment__")) { - attributes.erase("__comment__"); - CFG_ASSERT(attributes.size()); - } - for (auto& str : - std::vector({"__location__", "__optional__"})) { - if (attributes.contains(str)) { - CFG_ASSERT(attributes[str].is_string()); - object[str] = std::string(attributes[str]); - attributes.erase(str); - } - } std::string final_instance = instance; - bool optional = false; - if (object.find("__location__") != object.end()) { - std::string location = object.at("__location__"); - optional = object.size() == 2 && object.at("__optional__") == "1"; -#if 0 - // Maybe leave this to "true" to relax the checking to prevent assertion, - // this will make future out-of-sync update between RIC model and C++ - // easier - optional = true; -#endif - final_instance = get_mapped_block_name(instance, location, optional); - } else { - CFG_ASSERT(object.size() == 0); - } - if (optional) { - CFG_POST_WARNING("Skip %s [from %s]", final_instance.c_str(), - instance.c_str()); - return; + if (attributes.contains("__location__")) { + std::string location = attributes["__location__"]; + final_instance = get_mapped_block_name(instance, location); } for (auto& iter : attributes.items()) { nlohmann::json key = iter.key(); @@ -388,6 +389,10 @@ class ModelConfig_DEVICE { CFG_ASSERT(key.is_string()); CFG_ASSERT(value.is_string()); std::string key_str = (std::string)(key); + if (CFG_find_string_in_vector({"__location__", "__comment__"}, key_str) >= + 0) { + continue; + } std::string value_str = (std::string)(value); std::string reason = CFG_print("%s [%s:%s]", description.c_str(), key_str.c_str(), value_str.c_str()); @@ -404,10 +409,12 @@ class ModelConfig_DEVICE { reason); } } - void set_design_attributes(const std::string& instance, + bool set_design_attributes(const std::string& instance, nlohmann::json& attributes, + nlohmann::json& messages, const std::string& description) { CFG_ASSERT(attributes.is_array() || attributes.is_object()); + bool status = true; if (instance.size()) { if (instance.find("__SKIP_LOCATION_CHECK__") == 0 || is_valid_block(instance)) { @@ -421,17 +428,22 @@ class ModelConfig_DEVICE { set_design_attribute(instance, attributes, description); } } else { - CFG_POST_WARNING("Skip %s because the config attribute is empty", - description.c_str()); + ModelConfig_POST_MSG(1, 1, false, messages, + "Skip %s because the config attribute is empty", + description.c_str()); } } else { - CFG_POST_WARNING("Skip %s because the block/location %s is invalid", - description.c_str(), instance.c_str()); + ModelConfig_POST_MSG(1, 1, false, messages, + "Skip %s because the block/location %s is invalid", + description.c_str(), instance.c_str()); + status = false; } } else { - CFG_POST_WARNING("Skip %s because the location is not set", - description.c_str()); + ModelConfig_POST_MSG(1, 1, false, messages, + "Skip %s because the location is not set", + description.c_str()); } + return status; } void set_design(const std::string& filepath) { std::ifstream file(filepath.c_str()); @@ -442,6 +454,27 @@ class ModelConfig_DEVICE { // Must start with a dict/map CFG_ASSERT(api.is_object()); CFG_ASSERT(api.size()); + bool write_back = api.contains("status") && api.contains("feature") && + api.contains("messages") && api.contains("instances"); + bool status = true; + std::string feature = "unknown-model-config"; + if (api.contains("status")) { + CFG_ASSERT(api["status"].is_boolean()); + status = api["status"]; + } + if (api.contains("feature")) { + // Currently only support IO + CFG_ASSERT( + CFG_find_string_in_vector({"IO"}, std::string(api["feature"])) >= 0); + feature = api["feature"]; + } + if (api.contains("messages")) { + CFG_ASSERT(api["messages"].is_array()); + } else { + api["messages"] = nlohmann::json::array(); + } + ModelConfig_POST_MSG(0, 0, true, api["messages"], + "Model bitstream generation: %s", filepath.c_str()); // If there is instances defined, then use it if (api.contains("instances")) { nlohmann::json& instances = api["instances"]; @@ -459,28 +492,43 @@ class ModelConfig_DEVICE { std::string location = std::string(object["location"]); std::string description = CFG_print("%s [%s]", name.c_str(), module.c_str()); - set_design_attributes(location, object["config_attributes"], - description); + status &= + set_design_attributes(location, object["config_attributes"], + api["messages"], description); } - } else { - std::string location = std::string(instance["location"]); - std::string description = - CFG_print("%s [%s]", name.c_str(), module.c_str()); - set_design_attributes(location, instance["config_attributes"], - description); } + std::string location = std::string(instance["location"]); + std::string description = + CFG_print("%s [%s]", name.c_str(), module.c_str()); + status &= + set_design_attributes(location, instance["config_attributes"], + api["messages"], description); } } else { - CFG_POST_WARNING( + ModelConfig_POST_MSG( + 1, 1, true, api["messages"], "\"instances\" object is defined but empty, skip the design file " "\"%s\"", filepath.c_str()); } } else { - CFG_POST_WARNING( + ModelConfig_POST_MSG( + 1, 1, true, api["messages"], "\"instances\" object is not defined, skip the design file \"%s\"", filepath.c_str()); } + // Print warning + if (!status) { + ModelConfig_POST_MSG(1, 1, true, api["messages"], + "Generated %s bitstream is invalid", + feature.c_str()); + } + if (write_back) { + if (feature == "IO") { + ModelConfig_IO::write_json(filepath, status, feature, api["messages"], + api["instances"]); + } + } } void write(const std::map& options, const std::string& filename) { @@ -621,8 +669,7 @@ class ModelConfig_DEVICE { return block_name; } std::string get_mapped_block_name(const std::string& instance, - const std::string& mapped_location, - bool& optional) { + const std::string& mapped_location) { std::string mapped_block_name = mapped_location; if (instance.find("__SKIP_LOCATION_CHECK__") != 0) { std::vector block_names = @@ -632,11 +679,8 @@ class ModelConfig_DEVICE { mapped_block_name = CFG_replace_string( mapped_block_name, CFG_print("__{[%d]}__", i), block_names[i]); } - CFG_ASSERT_MSG(is_valid_block(mapped_block_name) || optional, + CFG_ASSERT_MSG(is_valid_block(mapped_block_name), "%s is invalid block name", mapped_block_name.c_str()); - if (is_valid_block(mapped_block_name)) { - optional = false; - } } return mapped_block_name; } @@ -916,7 +960,9 @@ void model_config_entry(CFGCommon_ARG* cmdarg) { CFGArg::parse("model_config|gen_ppdb", cmdarg->raws.size(), &cmdarg->raws[0], flag_options, options, positional_options, {"is_unittest"}, {"netlist_ppdb", "config_mapping"}, - {"property_json", "pll_workaround"}, 1); + {"routing_config", "routing_config_model", "property_json", + "pll_workaround"}, + 1); ModelConfig_IO io(flag_options, options, positional_options[0]); } else if (cmdarg->raws[0] == "gen_bitstream_setting_xml") { CFGArg::parse("model_config|gen_bitstream_setting_xml", cmdarg->raws.size(), diff --git a/src/Configuration/ModelConfig/ModelConfig_IO.cpp b/src/Configuration/ModelConfig/ModelConfig_IO.cpp index 8bb691fc1..c7f406295 100644 --- a/src/Configuration/ModelConfig/ModelConfig_IO.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_IO.cpp @@ -39,6 +39,8 @@ along with this program. If not, see . { post_msg(MCIO_MSG_TYPE::IS_DEBUG, space, CFG_print(__VA_ARGS__)); } const bool g_enable_python = true; +const std::string PLLREF_RE = "(*s*)pll_refmux[(*d*)]"; +const std::string PLL_RE = "(*s*)pll[(*d*)]"; struct ModelConfig_IO_MSG { ModelConfig_IO_MSG(uint32_t o, const std::string& m) : offset(o), msg(m) { @@ -75,6 +77,13 @@ ModelConfig_IO::ModelConfig_IO( const std::string& output) { std::string netlist_ppdb = options.at("netlist_ppdb"); std::string config_mapping = options.at("config_mapping"); + std::string routing_config = options.find("routing_config") != options.end() + ? options.at("routing_config") + : ""; + std::string routing_config_model = + options.find("routing_config_model") != options.end() + ? options.at("routing_config_model") + : ""; std::string property_json = options.find("property_json") != options.end() ? options.at("property_json") : ""; @@ -86,6 +95,8 @@ ModelConfig_IO::ModelConfig_IO( if (!is_unittest) { POST_INFO_MSG(0, "Netlist PPDB: %s", netlist_ppdb.c_str()); POST_INFO_MSG(0, "Config Mapping: %s", config_mapping.c_str()); + POST_INFO_MSG(0, "Routing Configurator: %s", routing_config.c_str()); + POST_INFO_MSG(0, "Routing Config Model: %s", routing_config_model.c_str()); POST_INFO_MSG(0, "Property JSON: %s", property_json.c_str()); } std::ifstream input; @@ -102,8 +113,7 @@ ModelConfig_IO::ModelConfig_IO( CFG_ASSERT(m_config_mapping.is_object()); CFG_ASSERT(m_config_mapping.contains("parameters")); CFG_ASSERT(m_config_mapping.contains("properties")); - CFG_ASSERT(m_config_mapping.contains("__resources__")); - CFG_ASSERT(m_config_mapping.contains("__file__")); + CFG_ASSERT(m_config_mapping.contains("__init_file__")); // Read the property JSON if it exists nlohmann::json property_instances = nlohmann::json::object(); if (property_json.size()) { @@ -112,11 +122,8 @@ ModelConfig_IO::ModelConfig_IO( property_instances = nlohmann::json::parse(input); input.close(); } - m_python = new CFG_Python_MGR; // Prepare python file - python_file(is_unittest); - // Read resource from the config file - read_resources(); + initialize_python(is_unittest, routing_config); // Validate instances validate_instances(netlist_instances); // Merge the property @@ -125,7 +132,7 @@ ModelConfig_IO::ModelConfig_IO( locate_instances(); // Prepare for validation for location if (g_enable_python) { - initialization(); + // initialization(); } else { POST_WARN_MSG(0, "Skip pin assignment legality check"); } @@ -137,28 +144,18 @@ ModelConfig_IO::ModelConfig_IO( invalidate_childs(); // Assign location to instance that naturally does not location assign_no_location_instance(); - // Allocate FCLK routing - allocate_fclk_routing(); - // Allocate Root Bank routing - allocate_and_set_root_bank_routing(); - // Set CLKBUF configuration attributes - set_clkbuf_config_attributes(); - // Allocate PLL - allocate_pll(); - // Set PLL (mainly on fclk) - set_pll_config_attributes(); - // Remaining validation - validations(false, "__secondary_validation__"); + // Prepare object that needed + prepare_instance_objects(); + // Routing related + if (!routing_config.empty() && !routing_config_model.empty() && + !m_routing_config.empty()) { + // Prepare routing issue that need to be solved + nlohmann::json routings = prepare_routing_json(); + // Solve the routing issue + solve_routing_json(routings, routing_config_model); + } // Finalize the attribute for configuration set_config_attributes(); - // Print warning - for (auto& instance : m_instances) { - validate_instance(instance, true); - if (!instance["__validation__"]) { - POST_WARN_MSG(0, "Generated IO bitstream is invalid"); - break; - } - } // Output write_json(output); } @@ -175,18 +172,20 @@ ModelConfig_IO::~ModelConfig_IO() { delete m_messages.back(); m_messages.pop_back(); } - if (m_resource != nullptr) { - delete m_resource; - m_resource = nullptr; - } } /* Call config mapping initialization if it was defined */ -void ModelConfig_IO::python_file(bool is_unittest) { - CFG_ASSERT(m_config_mapping.contains("__file__")); - CFG_ASSERT(m_python != nullptr); +void ModelConfig_IO::initialize_python(bool is_unittest, + const std::string& routing_config) { + CFG_ASSERT(m_config_mapping.contains("__init_file__")); + CFG_ASSERT(m_config_mapping["__init_file__"].is_object()); + CFG_ASSERT(m_config_mapping["__init_file__"].contains("__args__")); + CFG_ASSERT(m_config_mapping["__init_file__"]["__args__"].is_array()); + CFG_ASSERT(m_config_mapping["__init_file__"].contains("__file__")); + CFG_ASSERT(m_config_mapping["__init_file__"]["__file__"].is_array()); + CFG_ASSERT(m_python == nullptr); std::filesystem::path fullpath = std::filesystem::absolute("config.py"); std::string filename = fullpath.filename().string(); std::string standard_fullpath = @@ -196,54 +195,39 @@ void ModelConfig_IO::python_file(bool is_unittest) { } else { POST_DEBUG_MSG(0, "Preparing Python file: %s", standard_fullpath.c_str()); } + std::vector arguments; + for (auto& str : m_config_mapping["__init_file__"]["__args__"]) { + CFG_ASSERT(str.is_string()); + arguments.push_back(str); + } std::ofstream output(standard_fullpath.c_str()); - for (auto& str : m_config_mapping["__file__"]) { + for (auto& str : m_config_mapping["__init_file__"]["__file__"]) { CFG_ASSERT(str.is_string()); output << ((std::string)(str)).c_str() << "\n"; } output.close(); - CFG_ASSERT(m_python->set_file(standard_fullpath) == "config"); -} - -/* - Read resources from config mapping -*/ -void ModelConfig_IO::read_resources() { - POST_INFO_MSG(0, "Read resources"); - CFG_ASSERT(m_resource == nullptr); - CFG_ASSERT(m_config_mapping.contains("__resources__")); - nlohmann::json& resources = m_config_mapping["__resources__"]; - CFG_ASSERT(resources.is_object()); - m_resource = new ModelConfig_IO_RESOURCE(); - for (auto& iter : resources.items()) { - CFG_ASSERT(((nlohmann::json)(iter.key())).is_string()); - std::string resource = std::string(iter.key()); - nlohmann::json& items = iter.value(); - CFG_ASSERT(items.is_array()); - for (auto& item : items) { - CFG_ASSERT(item.is_object()); - CFG_ASSERT(item.size() == 5); - CFG_ASSERT(item.contains("name")); - CFG_ASSERT(item.contains("ric_name")); - CFG_ASSERT(item.contains("type")); - CFG_ASSERT(item.contains("subtype")); - CFG_ASSERT(item.contains("bank")); - nlohmann::json& name = item["name"]; - nlohmann::json& ric_name = item["ric_name"]; - nlohmann::json& type = item["type"]; - nlohmann::json& subtype = item["subtype"]; - nlohmann::json& bank = item["bank"]; - CFG_ASSERT(name.is_string()); - CFG_ASSERT(ric_name.is_string()); - CFG_ASSERT(type.is_string()); - CFG_ASSERT(subtype.is_string()); - CFG_ASSERT(bank.is_number()); - m_resource->add_resource(resource, std::string(name), - std::string(ric_name), std::string(type), - std::string(subtype), uint32_t(bank)); - } - } - m_global_args["__resources_string__"] = resources.dump(); + m_python = new CFG_Python_MGR(standard_fullpath, arguments); + CFG_ASSERT(m_python->get_main_module() == "config"); + CFG_ASSERT_MSG( + m_python->results().size() == arguments.size(), + "Expected python.set_file() results size() == %ld, but found %ld", + arguments.size(), m_python->results().size()); + for (auto arg : arguments) { + m_global_args[arg] = m_python->result_str(arg); + } + if (routing_config.size()) { + CFG_ASSERT(routing_config.size() > 3 && + (routing_config.rfind(".py") == (routing_config.size() - 3))); + std::filesystem::path rfullpath = std::filesystem::absolute(routing_config); + std::string standard_rfullpath = + CFG_change_directory_to_linux_format(rfullpath.string()); + m_routing_config = rfullpath.filename().string(); + m_routing_config = m_routing_config.substr(0, m_routing_config.size() - 3); + CFG_ASSERT(m_routing_config.size()); + CFG_ASSERT(m_python->set_file(standard_rfullpath) == m_routing_config); + } else { + m_routing_config = ""; + } } /* @@ -251,11 +235,14 @@ void ModelConfig_IO::read_resources() { Store the instances as m_instances */ void ModelConfig_IO::validate_instances(nlohmann::json& instances) { - POST_INFO_MSG(0, "Validate Instances"); + POST_INFO_MSG(0, "Validate netlist instances"); CFG_ASSERT(instances.is_object()); + CFG_ASSERT(instances.contains("status")); + CFG_ASSERT(instances["status"].is_boolean()); CFG_ASSERT(instances.contains("instances")); CFG_ASSERT(instances["instances"].is_array()); CFG_ASSERT(m_instances.is_null()); + m_status = bool(instances["status"]); m_instances = instances["instances"]; for (auto& instance : m_instances) { validate_instance(instance); @@ -284,6 +271,7 @@ void ModelConfig_IO::validate_instance(const nlohmann::json& instance, CFG_ASSERT(instance.contains("errors")); if (is_final) { CFG_ASSERT(instance.contains("route_clock_result")); + CFG_ASSERT(instance.contains("config_attributes")); } // Check type CFG_ASSERT(instance["module"].is_string()); @@ -304,6 +292,14 @@ void ModelConfig_IO::validate_instance(const nlohmann::json& instance, CFG_ASSERT(instance["errors"].is_array()); if (is_final) { CFG_ASSERT(instance["route_clock_result"].is_object()); + CFG_ASSERT(instance["config_attributes"].is_array()); + for (auto& cfg_attr : instance["config_attributes"]) { + CFG_ASSERT(cfg_attr.is_object()); + for (auto& iter2 : cfg_attr.items()) { + CFG_ASSERT(((nlohmann::json)(iter2.key())).is_string()); + CFG_ASSERT(((nlohmann::json)(iter2.value())).is_string()); + } + } } // Check linked object CFG_ASSERT(instance["linked_objects"].size()); @@ -316,8 +312,6 @@ void ModelConfig_IO::validate_instance(const nlohmann::json& instance, CFG_ASSERT(object.contains("properties")); if (is_final) { CFG_ASSERT(object.contains("config_attributes")); - } else { - CFG_ASSERT(!object.contains("config_attributes")); } // Check type CFG_ASSERT(object["location"].is_string()); @@ -385,6 +379,81 @@ void ModelConfig_IO::validate_instance(const nlohmann::json& instance, } } +/* + Validate JSON format of routing +*/ +void ModelConfig_IO::validate_routing(const nlohmann::json& routing, + bool is_final) { + CFG_ASSERT(routing.is_object()); + // Check existence + CFG_ASSERT(routing.contains("feature")); + CFG_ASSERT(routing.contains("comments")); + CFG_ASSERT(routing.contains("source")); + CFG_ASSERT(routing.contains("destinations")); + CFG_ASSERT(routing.contains("filters")); + CFG_ASSERT(routing.contains("flags")); + if (is_final) { + CFG_ASSERT(routing.contains("msgs")); + CFG_ASSERT(routing.contains("potential paths")); + CFG_ASSERT(routing.contains("config mux")); + CFG_ASSERT(routing.contains("status")); + } + // Check type + CFG_ASSERT(routing["feature"].is_string()); + CFG_ASSERT(routing["comments"].is_array()); + for (auto& r : routing["comments"]) { + CFG_ASSERT(r.is_string()); + } + CFG_ASSERT(routing["source"].is_string()); + CFG_ASSERT(routing["destinations"].is_array()); + for (auto& r : routing["destinations"]) { + CFG_ASSERT(r.is_string()); + } + CFG_ASSERT(routing["filters"].is_array()); + for (auto& r : routing["filters"]) { + CFG_ASSERT(r.is_string()); + } + CFG_ASSERT(routing["flags"].is_array()); + for (auto& r : routing["flags"]) { + CFG_ASSERT(r.is_string()); + } + if (is_final) { + CFG_ASSERT(routing["msgs"].is_array()); + for (auto& r : routing["msgs"]) { + CFG_ASSERT(r.is_string()); + } + CFG_ASSERT(routing["potential paths"].is_array()); + for (auto& r : routing["potential paths"]) { + CFG_ASSERT(r.is_array()); + for (auto& p : r) { + CFG_ASSERT(p.is_string()); + } + } + CFG_ASSERT(routing["config mux"].is_array()); + for (auto& r : routing["config mux"]) { + if (r.is_object()) { + CFG_ASSERT(r.size() == 1); + for (auto& iter0 : r.items()) { + CFG_ASSERT(((nlohmann::json)(iter0.key())).is_string()); + std::string key0 = (std::string)(iter0.key()); + CFG_ASSERT(key0.size()); + CFG_ASSERT(iter0.value().is_object()); + CFG_ASSERT(iter0.value().size()); + for (auto& iter1 : iter0.value().items()) { + CFG_ASSERT(((nlohmann::json)(iter1.key())).is_string()); + std::string key1 = (std::string)(iter1.key()); + CFG_ASSERT(key1.size()); + CFG_ASSERT(iter1.value().is_string()); + } + } + } else { + CFG_ASSERT(r.is_null()); + } + } + CFG_ASSERT(routing["status"].is_boolean()); + } +} + /* Entry function to merge the property json into instances */ @@ -481,8 +550,7 @@ void ModelConfig_IO::initialization() { Entry function to perform validation based on mapping */ void ModelConfig_IO::validations(bool init, const std::string& key) { - POST_INFO_MSG(0, "Validation using '%s' rule", key.c_str()); - MODEL_RESOURCES resource_instances; + POST_INFO_MSG(0, "Validate instances using '%s' rule", key.c_str()); for (auto& instance : m_instances) { // This is the most basic validation which will be run first // Hence it is impossible there is any object key @@ -498,23 +566,17 @@ void ModelConfig_IO::validations(bool init, const std::string& key) { } if (g_enable_python) { if (init || instance["__validation__"]) { - validation(instance, resource_instances, key); + validation(instance, key); } } else { instance["__validation__"] = false; instance["__validation_msg__"] = "Skip because Python is ignored"; - } - } - for (auto iter : resource_instances) { - while (iter.second.size()) { - delete iter.second.back(); - iter.second.pop_back(); + m_status = false; } } } void ModelConfig_IO::validation(nlohmann::json& instance, - MODEL_RESOURCES& resource_instances, const std::string& key) { CFG_ASSERT(m_python != nullptr); validate_instance(instance); @@ -577,7 +639,6 @@ void ModelConfig_IO::validation(nlohmann::json& instance, is_siblings_match(validation_info, (std::string)(instance["pre_primitive"]), instance["post_primitives"])) { - bool is_resource = false; if (validation_info.contains("__connectivity__")) { CFG_ASSERT(validation_info["__connectivity__"].is_array()); uint32_t connectivity_count = 0; @@ -626,65 +687,13 @@ void ModelConfig_IO::validation(nlohmann::json& instance, } std::vector equations = get_json_string_list(__equation__, args); - if (validation_info.contains("__resource__")) { - CFG_ASSERT(validation_info["__resource__"].is_boolean()); - is_resource = (bool)(validation_info["__resource__"]); - } - if (is_resource) { - m_python->run(equations, {"__resource_name__", "__location__", - "__resource__", "__total_resource__"}); - } else { - m_python->run(equations, {"pin_result"}); - } - if (is_resource) { - CFG_ASSERT(m_python->results().size() == 4); - std::string name = m_python->result_str("__resource_name__"); - std::string location = m_python->result_str("__location__"); - uint32_t resource = m_python->result_u32("__resource__"); - uint32_t total = m_python->result_u32("__total_resource__"); - if (resource_instances.find(name) == resource_instances.end()) { - resource_instances[name] = - std::vector({}); - } - MODEL_RESOURCE_INSTANCE* new_instance = - new MODEL_RESOURCE_INSTANCE( - location, resource, total, - (uint32_t)(resource_instances[name].size())); - status = allocate_resource(resource_instances[name], new_instance, - false); - if (status && validation_info.contains("__if_resource_pass__")) { - std::string updated_resource = "__updated_resource__ = {"; - size_t i = 0; - for (auto& r : resource_instances[name]) { - if (i) { - updated_resource += ","; - } - updated_resource = - CFG_print("%s '%s' : %d", updated_resource.c_str(), - r->location.c_str(), r->decision); - } - updated_resource += " }"; - std::vector equations = get_json_string_list( - validation_info["__if_resource_pass__"], args); - equations.insert(equations.begin(), updated_resource); - m_python->run(equations, {}); - } - if (!status && validation_info.contains("__if_resource_fail__")) { - std::vector equations = get_json_string_list( - validation_info["__if_resource_fail__"], args); - m_python->run(equations, {}); - } - set_validation_msg(status, msg, module, name, locations, - seq_name); - } else { - CFG_ASSERT_MSG( - m_python->results().size() == 1, - "Expected python.run() results size() == 1, but found %ld", - m_python->results().size()); - status = m_python->result_bool("pin_result"); - set_validation_msg(status, msg, module, name, locations, - seq_name); - } + m_python->run(equations, {"validation_result"}); + CFG_ASSERT_MSG( + m_python->results().size() == 1, + "Expected python.run() results size() == 1, but found %ld", + m_python->results().size()); + status = m_python->result_bool("validation_result"); + set_validation_msg(status, msg, module, name, locations, seq_name); // If you hit one module, no need to check the rest break; } @@ -711,7 +720,7 @@ void ModelConfig_IO::validation(nlohmann::json& instance, Entry function to perform internal error validation */ void ModelConfig_IO::internal_error_validations() { - POST_INFO_MSG(0, "Internal error validations"); + POST_INFO_MSG(0, "Validate error from netlist"); for (auto& instance : m_instances) { // This is the most basic validation which will be run first // Hence it is impossible there is any object key @@ -777,6 +786,7 @@ void ModelConfig_IO::invalidate_chain(const std::string& linked_object) { instance["__validation__"] = false; instance["__validation_msg__"] = "Invalidated because other instance in the chain is invalid"; + m_status = false; } } } @@ -796,14 +806,14 @@ void ModelConfig_IO::assign_no_location_instance() { CFG_ASSERT(instance["__validation_msg__"].is_string()); if (instance["__validation__"] && (instance["module"] == "BOOT_CLOCK" || instance["module"] == "FCLK_BUF")) { - POST_INFO_MSG(1, "Instance: %s", - ((std::string)(instance["name"])).c_str()); + POST_DEBUG_MSG(1, "Instance: %s", + ((std::string)(instance["name"])).c_str()); CFG_ASSERT(((std::string)(instance["location"])).size() == 0); instance["location"] = CFG_print("__SKIP_LOCATION_CHECK__:%s", ((std::string)(instance["location_object"])).c_str()); for (auto iter : instance["linked_objects"].items()) { - POST_INFO_MSG(2, "Object: %s", ((std::string)(iter.key())).c_str()); + POST_DEBUG_MSG(2, "Object: %s", ((std::string)(iter.key())).c_str()); nlohmann::json& object = iter.value(); CFG_ASSERT(((std::string)(object["location"])).size() == 0); object["location"] = CFG_print("__SKIP_LOCATION_CHECK__:%s", @@ -819,7 +829,7 @@ void ModelConfig_IO::assign_no_location_instance() { */ void ModelConfig_IO::assign_no_location_instance_child_location( const std::string& linked_object) { - POST_INFO_MSG(3, "Assign location for child from instance-without-location"); + POST_DEBUG_MSG(3, "Assign location for child from instance-without-location"); for (auto& instance : m_instances) { validate_instance(instance); // basic validate_locations should have been called @@ -846,245 +856,45 @@ void ModelConfig_IO::assign_no_location_instance_child_location( } /* - Determine the FCLK resource ultilization + Prepare empty object for all instance */ -void ModelConfig_IO::allocate_fclk_routing() { - POST_INFO_MSG(0, "Allocate FCLK routing resource"); +void ModelConfig_IO::prepare_instance_objects() { for (auto& instance : m_instances) { validate_instance(instance); - // basic validate_locations should have been called - // Object key must be there - CFG_ASSERT(instance.contains("__validation__")); - CFG_ASSERT(instance.contains("__validation_msg__")); - CFG_ASSERT(instance["__validation__"].is_boolean()); - CFG_ASSERT(instance["__validation_msg__"].is_string()); CFG_ASSERT(!instance.contains("route_clock_result")); instance["route_clock_result"] = nlohmann::json::object(); - if (instance["__validation__"]) { - if (instance["module"] == "CLK_BUF") { - m_resource->backup(); - allocate_clkbuf_fclk_routing(instance, "O"); - if (!instance["__validation__"]) { - m_resource->restore(); - } - } else if (instance["module"] == "PLL") { - std::vector port_sequence = { -#if 1 - "CLK_OUT_DIV4", - "CLK_OUT_DIV3", - "CLK_OUT_DIV2", - "CLK_OUT", - "FAST_CLK" - }; -#else - "FAST_CLK", - "CLK_OUT", - "CLK_OUT_DIV2", - "CLK_OUT_DIV3", - "CLK_OUT_DIV4" - }; -#endif - m_resource->backup(); - for (auto port : port_sequence) { - if (instance["route_clock_to"].contains(port)) { - allocate_pll_fclk_routing(instance, port); - if (!instance["__validation__"]) { - m_resource->restore(); - break; - } - } - } - } - } - } -} - -/* - Determine the FCLK resource ultilization by CLKBUF - Unittest: All negative tests included -*/ -void ModelConfig_IO::allocate_clkbuf_fclk_routing(nlohmann::json& instance, - const std::string& port) { - validate_instance(instance); - CFG_ASSERT(instance["__validation__"]); - CFG_ASSERT(instance.contains("route_clock_result")); - std::string name = instance["name"]; - std::string src_location = get_location(name); - PIN_INFO src_pin_info = get_pin_info(src_location); - std::string src_type = src_pin_info.type; - CFG_string_tolower(src_type); - nlohmann::json dest_instances = nlohmann::json::array(); - nlohmann::json& result = instance["route_clock_result"]; - CFG_ASSERT(result.is_object()); - if (instance["route_clock_to"].contains(port)) { - dest_instances = instance["route_clock_to"][port]; - result[port] = nlohmann::json::array(); - } - POST_DEBUG_MSG(1, "CLKBUF %s (location:%s)", name.c_str(), - src_location.c_str()); - for (auto& dinstance : dest_instances) { - std::string dest_instance = (std::string)(dinstance); - std::string dest_module = ""; - std::string dest_location = get_location(dest_instance, &dest_module); - std::string err_msg = ""; - POST_DEBUG_MSG(2, "Route to gearbox module %s (location:%s)", - dest_instance.c_str(), dest_location.c_str()); - if (dest_location.size()) { - PIN_INFO dest_pin_info = get_pin_info(dest_location); - // Pin only can route to same within same type and same bank - if (src_pin_info.type == dest_pin_info.type && - src_pin_info.bank == dest_pin_info.bank) { - std::string type = dest_pin_info.type; - CFG_string_tolower(type); - char ab = char('A') + char(dest_pin_info.ab_io); - std::string fclk_name = - CFG_print("%s_fclk_%d_%c", type.c_str(), dest_pin_info.bank, ab); - if (m_resource->use_resource("fclk", src_location, fclk_name, "")) { - result[port].push_back(m_resource->m_msg); - POST_DEBUG_MSG(3, m_resource->m_msg.c_str()); - } else { - err_msg = clkbuf_routing_failure_msg( - name, src_location, dest_instance, dest_module, dest_location); - err_msg = CFG_print("%s. Reason: %s", err_msg.c_str(), - m_resource->m_msg.c_str()); - } - } else { - err_msg = clkbuf_routing_failure_msg(name, src_location, dest_instance, - dest_module, dest_location); - err_msg = CFG_print("%s. Reason: They are not in same physical bank", - err_msg.c_str()); - } - } else { - err_msg = - clkbuf_routing_failure_msg(name, src_location, dest_instance, "", ""); - err_msg = - CFG_print("%s. Reason: Module usage is invalid in the first place", - err_msg.c_str()); - } - if (err_msg.size()) { - instance["__validation__"] = false; - instance["__validation_msg__"] = "Fail to route the clock"; - result[port].push_back(err_msg); - POST_WARN_MSG(3, err_msg.c_str()); + CFG_ASSERT(!instance.contains("config_attributes")); + instance["config_attributes"] = nlohmann::json::array(); + for (auto& object_iter : instance["linked_objects"].items()) { + nlohmann::json& object = object_iter.value(); + CFG_ASSERT(!object.contains("config_attributes")); + object["config_attributes"] = nlohmann::json::array(); } } } /* - Determine the FCLK resource ultilization by PLL - Unittest: All negative tests included + Create empty routing object */ -void ModelConfig_IO::allocate_pll_fclk_routing(nlohmann::json& instance, - const std::string& port) { - validate_instance(instance); - CFG_ASSERT(instance["__validation__"]); - CFG_ASSERT(instance["route_clock_to"].contains(port)); - CFG_ASSERT(instance.contains("route_clock_result")); - std::string name = instance["name"]; - std::string src_location = get_location(name); - PIN_INFO src_pin_info = get_pin_info(src_location); - nlohmann::json dest_instances = instance["route_clock_to"][port]; - nlohmann::json& result = instance["route_clock_result"]; - CFG_ASSERT(result.is_object()); - result[port] = nlohmann::json::array(); - POST_DEBUG_MSG(1, "PLL %s Port %s (location:%s)", name.c_str(), port.c_str(), - src_location.c_str()); - if (port == "FAST_CLK" || port == "CLK_OUT") { - for (auto& dinstance : dest_instances) { - std::string dest_instance = (std::string)(dinstance); - std::string dest_module = ""; - std::string dest_location = get_location(dest_instance, &dest_module); - std::string err_msg = ""; - POST_DEBUG_MSG(2, "Route to gearbox module %s (location:%s)", - dest_instance.c_str(), dest_location.c_str()); - if (dest_location.size()) { - PIN_INFO dest_pin_info = get_pin_info(dest_location); - // Pin only can route to same within same type and same bank - if ((src_pin_info.type == "HVR" && dest_pin_info.type == "HVL") || - (src_pin_info.type == "HVL" && dest_pin_info.type == "HVR")) { - std::string pll = (src_pin_info.type == "HVL") ? "PLL #0" : "PLL #1"; - err_msg = - pll_routing_failure_msg(name, port, src_location, dest_instance, - dest_module, dest_location); - err_msg = - CFG_print("%s. Reason: %s (needed by %s) cannot route to %s", - err_msg.c_str(), pll.c_str(), src_pin_info.type.c_str(), - dest_pin_info.type.c_str()); - } else { - std::string type = dest_pin_info.type; - uint32_t fclk = (dest_pin_info.index < 20) ? 0 : 1; - char ab = char('A') + char(fclk); - std::string fclk_name = - CFG_print("%s_fclk_%d_%c", CFG_string_tolower(type).c_str(), - dest_pin_info.bank, ab); - std::string fclk_src = CFG_print("PLL:%s", src_location.c_str()); - if (m_resource->use_resource( - "fclk", fclk_src, fclk_name, - port == "FAST_CLK" ? "VCO" : "NOT_VCO")) { - std::vector fclks = - m_resource->get_used_resource("fclk", fclk_src); - uint32_t requested_pll_resource = 0; - for (auto& fclk : fclks) { - uint32_t requested_pll = fclk_use_pll_resource(fclk->m_name); - requested_pll_resource |= (1 << requested_pll); - } - if (requested_pll_resource == 3) { - err_msg = - clkbuf_routing_failure_msg(name, src_location, dest_instance, - dest_module, dest_location); - err_msg = CFG_print( - "%s. Reason: A single PLL instance cannot route from both " - "PLL #0 and PLL#1. You need to explicitely instantiate two " - "PLLs", - err_msg.c_str()); - } else { - result[port].push_back(m_resource->m_msg); - POST_DEBUG_MSG(3, m_resource->m_msg.c_str()); - } - } else { - err_msg = clkbuf_routing_failure_msg( - name, src_location, dest_instance, dest_module, dest_location); - err_msg = CFG_print("%s. Reason: %s", err_msg.c_str(), - m_resource->m_msg.c_str()); - } - } - } else { - err_msg = pll_routing_failure_msg(name, port, src_location, - dest_instance, "", ""); - err_msg = - CFG_print("%s. Reason: Module usage is invalid in the first place", - err_msg.c_str()); - } - if (err_msg.size()) { - instance["__validation__"] = false; - instance["__validation_msg__"] = "Fail to route the clock"; - result[port].push_back(err_msg); - POST_WARN_MSG(3, err_msg.c_str()); - } - } - } else { - for (auto& dinstance : dest_instances) { - std::string dest_instance = (std::string)(dinstance); - std::string err_msg = pll_routing_failure_msg(name, port, src_location, - dest_instance, "", ""); - err_msg = CFG_print( - "%s. Reason: Only PLL output port 'CLK_OUT' can use FCLK resource", - err_msg.c_str()); - result[port].push_back(err_msg); - POST_WARN_MSG(2, err_msg.c_str()); - } - instance["__validation__"] = false; - instance["__validation_msg__"] = "Fail to route the clock"; - } +nlohmann::json ModelConfig_IO::create_routing_object() { + nlohmann::json routing = nlohmann::json::object(); + routing["feature"] = ""; + routing["comments"] = nlohmann::json::array(); + routing["source"] = ""; + routing["destinations"] = nlohmann::json::array(); + routing["filters"] = nlohmann::json::array(); + routing["flags"] = nlohmann::json::array(); + routing["parameters"] = nlohmann::json::object(); + return routing; } /* - Determine the Root Bank CLKMUX resource ultilization + Prepare routing issue that need to be solved */ -void ModelConfig_IO::allocate_and_set_root_bank_routing() { - POST_INFO_MSG( - 0, - "Allocate ROOT BANK routing resource (and set configuration attributes)"); +nlohmann::json ModelConfig_IO::prepare_routing_json() { + nlohmann::json routings = nlohmann::json::array(); + POST_INFO_MSG(0, "Prepare routing resource info for fast clock"); + uint32_t instance_index = 0; for (auto& instance : m_instances) { validate_instance(instance); // basic validate_locations should have been called @@ -1093,56 +903,88 @@ void ModelConfig_IO::allocate_and_set_root_bank_routing() { CFG_ASSERT(instance.contains("__validation_msg__")); CFG_ASSERT(instance["__validation__"].is_boolean()); CFG_ASSERT(instance["__validation_msg__"].is_string()); - CFG_ASSERT(instance.contains("route_clock_result")); - // Two conditions we will need to use Root Bank - // 1. When RX IO (CLK_BUF) need to route to fabric - // 2. When CLK_OUT (I_SERDES) generated by clk_gen need to route to fabric - std::string module = instance["module"]; - if (instance["__validation__"] && - (CFG_find_string_in_vector({"CLK_BUF", "I_SERDES"}, module) >= 0) && - instance["parameters"].contains("ROUTE_TO_FABRIC_CLK")) { - m_resource->backup(); - std::string name = instance["name"]; - POST_DEBUG_MSG(2, "%s %s", module.c_str(), name.c_str()); - std::string src_location = get_location(name); - PIN_INFO src_pin_info = get_pin_info(src_location); - std::string sub_resource = "CORE"; - if (module == "I_SERDES" && instance["parameters"].contains("DPA_MODE")) { - if (instance["parameters"]["DPA_MODE"] == "DPA" || - instance["parameters"]["DPA_MODE"] == "CDR") { - sub_resource = "CDR"; + if (instance["__validation__"]) { + std::string src_module = instance["module"]; + nlohmann::json routes = instance["route_clock_to"]; + if ((src_module == "CLK_BUF" || src_module == "PLL") && + (routes.size() > 0)) { + // Only this two primitives can route clock to fast_clk + std::string src_name = instance["name"]; + std::string src_location = get_location(src_name); + PIN_INFO src_pin_info = get_pin_info(src_location); + CFG_ASSERT(CFG_find_string_in_vector({"BOOT_CLOCK", "HP", "HVL", "HVR"}, + src_pin_info.type) >= 0); + uint32_t fast_clock_index = 0; + for (auto& iter : routes.items()) { + CFG_ASSERT(fast_clock_index <= 0xFF); + CFG_ASSERT(instance_index <= 0xFFFF); + std::string port = iter.key(); + nlohmann::json gearboxes = iter.value(); + for (std::string dest_name : gearboxes) { + uint32_t routing_index = (instance_index << 16) | fast_clock_index; + CFG_ASSERT(m_routing_instance_tracker.find(routing_index) == + m_routing_instance_tracker.end()); + std::string dest_module = ""; + uint8_t dest_status = 0; + std::string dest_location = + get_location(dest_name, &dest_module, &dest_status); + CFG_ASSERT(dest_status & 1); + if (dest_status & 2) { + PIN_INFO dest_pin_info = get_pin_info(dest_location); + CFG_ASSERT(CFG_find_string_in_vector({"HP", "HVL", "HVR"}, + dest_pin_info.type) >= 0); + std::string feature = CFG_print( + "Fast Clock: module %s %s port %s (location: %s) -> module " + "%s %s " + "(location: %s)", + src_module.c_str(), src_name.c_str(), port.c_str(), + src_location.c_str(), dest_module.c_str(), dest_name.c_str(), + dest_location.c_str()); + nlohmann::json routing = create_routing_object(); + routing["feature"] = feature; + routing["comments"].push_back((std::string)(instance["name"])); + routing["comments"].push_back(port); + routing["comments"].push_back(dest_name); + routing["parameters"][src_module] = instance["parameters"]; + if (src_pin_info.type == "BOOT_CLOCK") { + routing["source"] = + CFG_print("%s->osc", src_pin_info.model_name.c_str()); + } else { + routing["source"] = src_location; + } + if (src_module == "PLL") { + routing["destinations"].push_back( + CFG_print("RE:%s->%s", PLL_RE.c_str(), + get_pll_port_name(port).c_str())); + routing["parameters"][src_module]["__pll_enable__"] = + m_pll_workaround.size() ? m_pll_workaround : "1"; + } else { + routing["filters"].push_back("partial:pll_refmux"); + } + routing["destinations"].push_back( + CFG_print("%s->fast_clk", dest_pin_info.model_name.c_str())); + if (dest_module == "O_SERDES_CLK") { + routing["destinations"].push_back( + CFG_print("%s->tx_clk", dest_pin_info.model_name.c_str())); + } + m_routing_instance_tracker[routing_index] = int(routings.size()); + routings.push_back(routing); + } else { + m_routing_instance_tracker[routing_index] = -1; + m_status = false; + } + fast_clock_index++; + } } - } - std::pair status = m_resource->use_root_bank_clkmux( - name, src_location, sub_resource, src_pin_info); - if (status.first) { - POST_DEBUG_MSG(3, "Resource: %s", status.second.c_str()); - // Set ROOT_BANK_CLKMUX - instance["__AB__"] = src_pin_info.ab_name; - instance["__ROOT_BANK_MUX__"] = - std::to_string(src_pin_info.root_bank_mux_core_input_index); - instance["__ROOT_BANK_MUX_LOCATION__"] = - src_pin_info.root_bank_mux_location; - // Set ROOT_MUX - instance["__ROOT_MUX__"] = - std::to_string(src_pin_info.root_mux_input_index); } else { - std::string err_msg = CFG_print("Fail to route the clock. Reason: %s", - status.second.c_str()); - instance["__validation__"] = false; - instance["__validation_msg__"] = err_msg; - POST_WARN_MSG(3, err_msg.c_str()); - m_resource->restore(); + // The rest of the primitives should have empty "route_clock_to" + CFG_ASSERT(routes.size() == 0); } } + instance_index++; } -} - -/* - Entry function to determine the configuration attributes of CLKBUF -*/ -void ModelConfig_IO::set_clkbuf_config_attributes() { - POST_INFO_MSG(0, "Set CLKBUF remaining configuration attributes (FCLK)"); + POST_INFO_MSG(0, "Prepare routing resource info for core clock"); + instance_index = 0; for (auto& instance : m_instances) { validate_instance(instance); // basic validate_locations should have been called @@ -1151,241 +993,349 @@ void ModelConfig_IO::set_clkbuf_config_attributes() { CFG_ASSERT(instance.contains("__validation_msg__")); CFG_ASSERT(instance["__validation__"].is_boolean()); CFG_ASSERT(instance["__validation_msg__"].is_string()); - if (instance["__validation__"] && instance["module"] == "CLK_BUF") { - if (instance["parameters"].contains("ROUTE_TO_FABRIC_CLK")) { - set_clkbuf_config_attribute(instance); + if (instance["__validation__"]) { + std::string src_module = instance["module"]; + if (CFG_find_string_in_vector( + {"CLK_BUF", "BOOT_CLOCK", "FCLK_BUF", "PLL", "I_SERDES"}, + src_module) >= 0) { + bool is_pll = src_module == "PLL"; + for (uint32_t core_clock_index = 0; core_clock_index < (is_pll ? 4 : 1); + core_clock_index++) { + CFG_ASSERT(instance_index <= 0xFFFF); + uint32_t routing_index = + (instance_index << 16) | 0x0100 | core_clock_index; + CFG_ASSERT(m_routing_instance_tracker.find(routing_index) == + m_routing_instance_tracker.end()); + std::string parameter_name = + is_pll ? CFG_print("OUT%d_ROUTE_TO_FABRIC_CLK", core_clock_index) + : "ROUTE_TO_FABRIC_CLK"; + if (instance["parameters"].contains(parameter_name)) { + std::string src_name = instance["name"]; + std::string src_location = + src_module == "FCLK_BUF" + ? std::string(instance["location_object"]) + : get_location(src_name); + PIN_INFO src_pin_info = get_pin_info(src_location); + std::string fabric_slot = instance["parameters"][parameter_name]; + std::string port = "O"; + if (src_module == "I_SERDES") { + port = "CLK_OUT"; + } else if (src_module == "PLL") { + port = (core_clock_index == 0 + ? "CLK_OUT" + : CFG_print("CLK_OUT_DIV%d", core_clock_index + 1)); + } + std::string feature = CFG_print( + "Core Clock: module %s %s port %s (location: %s) -> core " + "clock " + "slot[%s]", + src_module.c_str(), src_name.c_str(), port.c_str(), + src_location.c_str(), fabric_slot.c_str()); + nlohmann::json routing = create_routing_object(); + routing["feature"] = feature; + routing["parameters"][src_module] = instance["parameters"]; + if (src_pin_info.type == "BOOT_CLOCK") { + routing["source"] = + CFG_print("%s->osc", src_pin_info.model_name.c_str()); + } else if (src_pin_info.type == "FABRIC_CLKBUF") { + CFG_ASSERT( + instance["parameters"].contains("ROUTE_FROM_FABRIC_CLK")); + std::string fclk_buf_source = + instance["parameters"]["ROUTE_FROM_FABRIC_CLK"]; + routing["source"] = + CFG_print("%s[%s]", src_pin_info.model_name.c_str(), + fclk_buf_source.c_str()); + } else if (src_module == "I_SERDES") { + routing["source"] = + CFG_print("%s->fast_clk", src_pin_info.model_name.c_str()); + } else { + routing["source"] = src_location; + } + routing["filters"].push_back("partial:_fclk_mux_"); + if (src_module == "PLL") { + routing["destinations"].push_back( + CFG_print("RE:%s->%s", PLL_RE.c_str(), + get_pll_port_name(port).c_str())); + routing["parameters"][src_module]["__pll_enable__"] = + m_pll_workaround.size() ? m_pll_workaround : "1"; + } else { + if (src_module == "I_SERDES") { + routing["destinations"].push_back( + CFG_print("partial:root_bank_clkmux->%s_clk", + get_iserdes_clk_mode(instance).c_str())); + } + routing["filters"].push_back("partial:pll_refmux"); + } + routing["destinations"].push_back( + CFG_print("fabric_clk[%s]", fabric_slot.c_str())); + m_routing_instance_tracker[routing_index] = int(routings.size()); + routings.push_back(routing); + } + } } } + instance_index++; } + return routings; } /* - Real function to determine the configuration attributes of CLKBUF + Solve routing issue */ -void ModelConfig_IO::set_clkbuf_config_attribute(nlohmann::json& instance) { - // Set FCLK - set_fclk_config_attribute(instance); -} - -/* - Entry function to determine the configuration attributes of PLL -*/ -void ModelConfig_IO::set_pll_config_attributes() { - POST_INFO_MSG(0, "Set PLL remaining configuration attributes (FCLK)"); - for (auto& instance : m_instances) { - validate_instance(instance); - // basic validate_locations should have been called - // Object key must be there - CFG_ASSERT(instance.contains("__validation__")); - CFG_ASSERT(instance.contains("__validation_msg__")); - CFG_ASSERT(instance["__validation__"].is_boolean()); - CFG_ASSERT(instance["__validation_msg__"].is_string()); - if (instance["__validation__"] && instance["module"] == "PLL") { - set_pll_config_attribute(instance); +void ModelConfig_IO::solve_routing_json(nlohmann::json& routings, + const std::string& route_model) { + POST_INFO_MSG(0, "Solve routing"); + CFG_ASSERT(routings.is_array()); + if (routings.size()) { + // Write it to file + std::filesystem::path fullpath = + std::filesystem::absolute("io_routing.json"); + std::string json_fullpath = + CFG_change_directory_to_linux_format(fullpath.string()); + std::ofstream io_routing_json(json_fullpath); + CFG_ASSERT(io_routing_json.is_open()); + io_routing_json << std::setw(2) << routings << std::endl; + io_routing_json.close(); + // Solve it + std::vector results = m_python->run_file( + m_routing_config, "cpp_entry", + std::vector( + {CFG_Python_OBJ((std::string)(route_model.c_str())), + CFG_Python_OBJ(json_fullpath)})); + CFG_ASSERT(results.size() == 1); + CFG_ASSERT(results[0].type == CFG_Python_OBJ::TYPE::BOOL); + CFG_ASSERT(results[0].get_bool()); + // Retrieve it + std::ifstream input(json_fullpath.c_str()); + CFG_ASSERT(input.is_open() && input.good()); + nlohmann::json solved_routings = nlohmann::json::parse(input); + input.close(); + // Real work + CFG_ASSERT(solved_routings.is_array()); + CFG_ASSERT(routings.size() == solved_routings.size()); + std::map> routing_results; + for (auto& routing : solved_routings) { + POST_DEBUG_MSG(1, "Feature: %s", + ((std::string)(routing["feature"])).c_str()); + POST_DEBUG_MSG(2, "Status: %s", + ((bool)(routing["status"]) ? "True" : "False")); + for (std::string msg : routing["msgs"]) { + POST_DEBUG_MSG(2, "Msg: %s", msg.c_str()); + } + std::map> rresults; + validate_routings_result(routing, rresults); + validate_routings_result(routing, routing_results); + for (auto iter0 : rresults) { + POST_DEBUG_MSG(3, "TCL Block: %s", iter0.first.c_str()); + for (auto iter1 : iter0.second) { + POST_DEBUG_MSG(4, "%s: %s", iter1.first.c_str(), + iter1.second.c_str()); + } + } + } + // + for (auto iter : m_routing_instance_tracker) { + uint32_t instance_index = iter.first >> 16; + uint8_t type = (iter.first >> 8) & 0xFF; + uint32_t clk_index = iter.first & 0xFF; + CFG_ASSERT(instance_index < uint32_t(m_instances.size())); + CFG_ASSERT(type == 0 || type == 1); + nlohmann::json& instance = m_instances[instance_index]; + CFG_ASSERT((bool)(instance["__validation__"])); + if (iter.second >= 0) { + CFG_ASSERT(iter.second < int(solved_routings.size())); + } + if (type == 0) { + CFG_ASSERT(iter.second == -1 || iter.second >= 0); + nlohmann::json routes = instance["route_clock_to"]; + CFG_ASSERT(routes.size()); + uint32_t fast_clock_index = 0; + bool found = false; + for (auto& riter : routes.items()) { + std::string port = riter.key(); + if (!instance["route_clock_result"].contains(port)) { + instance["route_clock_result"][port] = nlohmann::json::array(); + } + nlohmann::json gearboxes = riter.value(); + for (std::string dest_name : gearboxes) { + if (fast_clock_index == clk_index) { + // Found, double check everything match updated + if (iter.second == -1) { + instance["route_clock_result"][port].push_back( + "Error: Destination gearbox is invalid"); + } else { + nlohmann::json& routing = solved_routings[iter.second]; + CFG_ASSERT((std::string)(routing["comments"][0]) == + (std::string)(instance["name"])); + CFG_ASSERT((std::string)(routing["comments"][1]) == port); + CFG_ASSERT((std::string)(routing["comments"][2]) == dest_name); + std::string msgs; + for (std::string m : routing["msgs"]) { + if (msgs.size()) { + msgs = CFG_print("%s; %s", msgs.c_str(), m.c_str()); + } else { + msgs = m; + } + } + if ((bool)(routing["status"])) { + instance["route_clock_result"][port].push_back( + CFG_print("Pass: %s", msgs.c_str())); + } else { + instance["route_clock_result"][port].push_back( + CFG_print("Error: %s", msgs.c_str())); + } + get_routing_result(instance, routing, false); + } + found = true; + break; + } + fast_clock_index++; + } + if (found) { + break; + } + } + CFG_ASSERT(found); + } else { + CFG_ASSERT(iter.second >= 0); + nlohmann::json& routing = solved_routings[iter.second]; + get_routing_result(instance, routing, true); + } } } } /* - Real function to determine the configuration attributes of PLL + Determine the PLL model port name from primitive port name */ -void ModelConfig_IO::set_pll_config_attribute(nlohmann::json& instance) { - // FCLK - set_fclk_config_attribute(instance); +std::string ModelConfig_IO::get_pll_port_name( + std::string& pritimive_port_name) { + std::string name = ""; + if (pritimive_port_name == "FAST_CLK") { + name = "foutvco"; + } else if (pritimive_port_name == "CLK_OUT") { + name = "fout[0]"; + } else if (pritimive_port_name == "CLK_OUT_DIV2") { + name = "fout[1]"; + } else if (pritimive_port_name == "CLK_OUT_DIV3") { + name = "fout[2]"; + } else if (pritimive_port_name == "CLK_OUT_DIV4") { + name = "fout[3]"; + } + CFG_ASSERT_MSG(name.size(), "Unknown PLL primitive port name %s", + pritimive_port_name.c_str()); + return name; } -void ModelConfig_IO::set_fclk_config_attribute(nlohmann::json& instance) { - POST_DEBUG_MSG(1, "Set FCLK configuration attributes"); +/* + Determine the I_SERDES clock mode +*/ +std::string ModelConfig_IO::get_iserdes_clk_mode(nlohmann::json& instance) { validate_instance(instance); CFG_ASSERT(instance["__validation__"]); - std::string name = instance["name"]; - std::string src_location = get_location(name); - PIN_INFO src_pin_info = get_pin_info(src_location); - CFG_ASSERT(instance["module"] == "CLK_BUF" || instance["module"] == "PLL"); - bool is_pll = instance["module"] == "PLL"; - // Set the FCLK MUX - nlohmann::json config = nlohmann::json::array(); - std::string query_name = src_location; - if (is_pll) { - query_name = CFG_print("PLL:%s", src_location.c_str()); - } - std::vector resources = - m_resource->get_used_resource("fclk", query_name); - if (resources.size() == 0) { - POST_DEBUG_MSG(2, "Skip for %s", query_name.c_str()); - } - for (auto resource : resources) { - POST_DEBUG_MSG(2, "%s %s (location:%s) use %s", is_pll ? "PLL" : "CLKBUF", - name.c_str(), src_location.c_str(), - resource->m_name.c_str()); - char ab = resource->m_name.back(); - std::string location = resource->m_ric_name; - std::map fclk_data = { - {"cfg_rxclk_phase_sel", (is_pll ? 0 : 1)}, - {"cfg_rx_fclkio_sel", (is_pll ? 0 : src_pin_info.ab_io)}, - {"cfg_vco_clk_sel", (resource->m_sub_resource == "NOT_VCO" ? 1 : 0)}}; - for (auto& iter : fclk_data) { - nlohmann::json attribute = nlohmann::json::object(); - attribute["__location__"] = location; - attribute[CFG_print("%s_%c_%d", iter.first.c_str(), ab, - resource->m_bank)] = std::to_string(iter.second); - config.push_back(attribute); - } - } - instance["CPP_CONFIG_ATTRIBUTES"] = config; + std::string mode = "core"; + if (instance["parameters"].contains("DPA_MODE") && + CFG_find_string_in_vector({"DPA", "CDR"}, + instance["parameters"]["DPA_MODE"]) >= 0) { + mode = "cdr"; + } + return mode; } /* - Entry function to determine the PLL resource + Vaidate the routings result */ -void ModelConfig_IO::allocate_pll() { - POST_INFO_MSG( - 0, "Allocate PLL resource (and set PLLREF configuration attributes)"); - CFG_ASSERT(m_resource->get_resource_availability_index("pll") == - (uint64_t)((1 << m_resource->get_resource_count("pll")) - 1)); - for (auto& instance : m_instances) { - validate_instance(instance); - CFG_ASSERT(!instance.contains("__pll_resource__")); - } - uint32_t init_undecided_pll_count = 0; - while ((init_undecided_pll_count = undecided_pll())) { - allocate_pll(false); - uint32_t undecided_pll_count = undecided_pll(); - if (init_undecided_pll_count == undecided_pll_count) { - allocate_pll(true); +void ModelConfig_IO::validate_routings_result( + nlohmann::json& routing, + std::map>& results) { + validate_routing(routing, true); + if ((bool)(routing["status"])) { + CFG_ASSERT(routing["config mux"].size()); + bool solved = false; + for (auto& r : routing["config mux"]) { + if (r.is_object()) { + CFG_ASSERT(r.size() == 1); + for (auto& iter0 : r.items()) { + CFG_ASSERT(((nlohmann::json)(iter0.key())).is_string()); + std::string key0 = (std::string)(iter0.key()); + if (results.find(key0) == results.end()) { + results[key0] = std::map({}); + } + for (auto& iter1 : iter0.value().items()) { + std::string key1 = (std::string)(iter1.key()); + std::string value = std::string(iter1.value()); + if (results[key0].find(key1) == results[key0].end()) { + results[key0][key1] = value; + } else { + CFG_ASSERT(results[key0][key1] == value); + } + solved = true; + } + } + } else { + CFG_ASSERT(r.is_null()); + } } + CFG_ASSERT(solved); } } /* - Real function to determine the PLL resource - Unittest: All negative tests included + Retrieve result from routing to instance */ -void ModelConfig_IO::allocate_pll(bool force) { - for (auto& instance : m_instances) { - validate_instance(instance); - // basic validate_locations should have been called - // Object key must be there - CFG_ASSERT(instance.contains("__validation__")); - CFG_ASSERT(instance.contains("__validation_msg__")); - CFG_ASSERT(instance["__validation__"].is_boolean()); - CFG_ASSERT(instance["__validation_msg__"].is_string()); - if (instance["module"] == "PLL" && instance["__validation__"] && - !instance.contains("__pll_resource__")) { - std::string name = instance["name"]; - std::string src_location = get_location(name); - PIN_INFO src_pin_info = get_pin_info(src_location); - // Check if FCLK decided which PLL to use - std::vector fclks = - m_resource->get_used_resource( - "fclk", CFG_print("PLL:%s", src_location.c_str())); - std::string fclk_names = ""; - for (auto& fclk : fclks) { - if (fclk_names.size()) { - fclk_names = - CFG_print("%s, %s", fclk_names.c_str(), fclk->m_name.c_str()); - } else { - fclk_names = fclk->m_name; +void ModelConfig_IO::get_routing_result(nlohmann::json& instance, + nlohmann::json& routing, + bool update_error) { + validate_instance(instance); + validate_routing(routing, true); + if ((bool)(routing["status"])) { + CFG_ASSERT(routing["config mux"].size()); + std::map> results; + validate_routings_result(routing, results); + CFG_ASSERT(results.size()); + std::vector locations; + for (auto& iter0 : results) { + bool configured = false; + for (auto& config : instance["config_attributes"]) { + if (config["__location__"] == iter0.first) { + configured = true; + break; } } - POST_DEBUG_MSG(1, "PLL %s (location:%s) uses FCLK '%s'", name.c_str(), - src_location.c_str(), fclk_names.c_str()); - uint64_t requested_pll_resource = 0; - for (auto& fclk : fclks) { - uint32_t request_bank = fclk_use_pll_resource(fclk->m_name); - requested_pll_resource |= ((uint64_t)(1) << request_bank); - } - uint64_t pin_resource = - src_pin_info.type == "HVL" ? 1 : (src_pin_info.type == "HVR" ? 2 : 3); - uint64_t pll_availability = - m_resource->get_resource_availability_index("pll"); - POST_DEBUG_MSG(2, - "Pin resource: %d, PLL FCLK requested resource: %d, PLL " - "availability: %ld", - pin_resource, requested_pll_resource, pll_availability); - std::string msg = ""; - if (requested_pll_resource == 0) { - msg = - "PLL request resource is 0 - does not need to route PLL output to " - "FCLK. Only need to configure PLLREF configuration attributes"; - POST_WARN_MSG(3, msg.c_str()); - } - uint32_t final_resource = pin_resource & pll_availability; - uint32_t one_count = 0; - uint32_t pll_index = 0; - if (requested_pll_resource) { - final_resource &= requested_pll_resource; - } - for (size_t i = 0; i < m_resource->get_resource_count("pll"); i++) { - if (final_resource & ((uint64_t)(1) << i)) { - one_count++; - pll_index = i; - if (force) { - POST_DEBUG_MSG(3, "Force to use first found resource"); - force = false; - break; - } + if (!configured) { + nlohmann::json attributes = nlohmann::json::object(); + attributes["__location__"] = iter0.first; + instance["config_attributes"].push_back(attributes); + if (std::find(locations.begin(), locations.end(), iter0.first) == + locations.end()) { + locations.push_back(iter0.first); } } - if (one_count == 0) { - msg = CFG_print("Cannot fit in any Pin/FCLK/PLL resource"); - instance["__validation__"] = false; - instance["__validation_msg__"] = msg; - POST_WARN_MSG(3, msg.c_str()); - } else if (one_count == 1) { - instance["__pll_resource__"] = std::to_string(pll_index); - instance["__pll_enable__"] = - m_pll_workaround.size() ? m_pll_workaround : "1"; - std::string pll_resource_name = CFG_print("pll_%d", pll_index); - CFG_ASSERT(m_resource->use_resource("pll", src_location, - pll_resource_name, "")); - POST_DEBUG_MSG(3, m_resource->m_msg.c_str()); - POST_DEBUG_MSG(4, "Set PLLREF configuration attributes"); - uint32_t rx_io = src_pin_info.ab_io == 0 ? 0 : 3; - uint32_t divide_by_2 = 0; - if (instance["parameters"].contains("DIVIDE_CLK_IN_BY_2")) { - std::string temp = instance["parameters"]["DIVIDE_CLK_IN_BY_2"]; - if (CFG_find_string_in_vector({"TRUE", "ON", "1"}, temp) >= 0) { - divide_by_2 = 1; + configured = false; + for (auto& config : instance["config_attributes"]) { + if (config["__location__"] == iter0.first) { + for (auto& iter1 : iter0.second) { + if (!config.contains(iter1.first)) { + config[iter1.first] = iter1.second; + } else { + CFG_ASSERT(config[iter1.first] == iter1.second); + } } + configured = true; + break; } - instance["__SRC__"] = src_pin_info.type; - if (src_pin_info.type == "BOOT_CLOCK") { - instance["__PIN__"] = "UNKNOWN"; - instance["__BANK__"] = "UNKNOWN"; - } else if (src_pin_info.type == "HP") { - instance["__PIN__"] = std::to_string(rx_io); - instance["__BANK__"] = std::to_string(src_pin_info.bank); - } else { - instance["__SRC__"] = "HV"; - instance["__PIN__"] = std::to_string(rx_io & 1); - instance["__BANK__"] = std::to_string(src_pin_info.bank); - } - instance["__DIV__"] = std::to_string(divide_by_2); - } else { - msg = - CFG_print("It is flexible to use more than one PLL. Decide later"); - POST_DEBUG_MSG(3, msg.c_str()); } + CFG_ASSERT(configured); } - } -} - -/* - Determine the FCLK resource ultilization by PLL -*/ -uint32_t ModelConfig_IO::undecided_pll() { - uint32_t count = 0; - for (auto& instance : m_instances) { - validate_instance(instance); - CFG_ASSERT(instance.contains("__validation__")); - CFG_ASSERT(instance["__validation__"].is_boolean()); - if (instance["module"] == "PLL" && instance["__validation__"] && - !instance.contains("__pll_resource__")) { - count++; + } else { + if (update_error) { + for (std::string m : routing["msgs"]) { + instance["errors"].push_back( + CFG_print("ModelConfigError: %s", m.c_str())); + } } + m_status = false; } - return count; } /********************************** @@ -1399,68 +1349,54 @@ uint32_t ModelConfig_IO::undecided_pll() { void ModelConfig_IO::set_config_attributes() { POST_INFO_MSG(0, "Set configuration attributes"); for (auto& instance : m_instances) { - validate_instance(instance); - std::string module = std::string(instance["module"]); - CFG_ASSERT(instance.contains("__validation__")); - CFG_ASSERT(instance.contains("__validation_msg__")); - CFG_ASSERT(instance["__validation__"].is_boolean()); - if (!instance["__validation__"]) { - CFG_ASSERT(!instance.contains("config_attributes")); + validate_instance(instance, true); + if ((bool)(instance["__validation__"])) { + std::string module = std::string(instance["module"]); + std::map instance_args = m_global_args; + retrieve_instance_args(instance, instance_args); + POST_DEBUG_MSG(1, "Module: %s (%s)", + ((std::string)(instance["module"])).c_str(), + ((std::string)(instance["name"])).c_str()); for (auto& object_iter : instance["linked_objects"].items()) { + std::string object_name = std::string(object_iter.key()); + POST_DEBUG_MSG(2, "Object: %s", object_name.c_str()); nlohmann::json& object = object_iter.value(); + nlohmann::json parameters = nlohmann::json::object(); + nlohmann::json properties = nlohmann::json::object(); + nlohmann::json define = nlohmann::json::object(); object["config_attributes"] = nlohmann::json::array(); + std::string location = std::string(object["location"]); + if (instance.contains("parameters")) { + parameters = instance["parameters"]; + CFG_ASSERT(parameters.is_object()); + } + if (object.contains("properties")) { + properties = object["properties"]; + CFG_ASSERT(properties.is_object()); + } + if (m_config_mapping.contains("__define__")) { + define = m_config_mapping["__define__"]; + CFG_ASSERT(define.is_object()); + } + std::map args = instance_args; + parameters["__location__"] = location; + properties["__location__"] = location; + args["__location__"] = location; + POST_DEBUG_MSG(3, "Parameter"); + set_config_attribute(object["config_attributes"], module, + (std::string)(instance["pre_primitive"]), + instance["post_primitives"], parameters, + m_config_mapping["parameters"], + instance["connectivity"], args, define); + args = instance_args; + args["__location__"] = location; + POST_DEBUG_MSG(3, "Property"); + set_config_attribute(object["config_attributes"], module, + (std::string)(instance["pre_primitive"]), + instance["post_primitives"], properties, + m_config_mapping["properties"], + instance["connectivity"], args, define); } - continue; - } - std::map instance_args = m_global_args; - retrieve_instance_args(instance, instance_args); - m_current_instance = &instance; - POST_DEBUG_MSG(1, "Module: %s (%s)", - ((std::string)(instance["module"])).c_str(), - ((std::string)(instance["name"])).c_str()); - for (auto& object_iter : instance["linked_objects"].items()) { - std::string object_name = std::string(object_iter.key()); - POST_DEBUG_MSG(2, "Object: %s", object_name.c_str()); - nlohmann::json& object = object_iter.value(); - nlohmann::json parameters = nlohmann::json::object(); - nlohmann::json properties = nlohmann::json::object(); - nlohmann::json define = nlohmann::json::object(); - object["config_attributes"] = nlohmann::json::array(); - // If there is CPP_CONFIG_ATTRIBUTES - if (instance.contains("CPP_CONFIG_ATTRIBUTES")) { - object["config_attributes"] = instance["CPP_CONFIG_ATTRIBUTES"]; - } - std::string location = std::string(object["location"]); - if (instance.contains("parameters")) { - parameters = instance["parameters"]; - CFG_ASSERT(parameters.is_object()); - } - if (object.contains("properties")) { - properties = object["properties"]; - CFG_ASSERT(properties.is_object()); - } - if (m_config_mapping.contains("__define__")) { - define = m_config_mapping["__define__"]; - CFG_ASSERT(define.is_object()); - } - std::map args = instance_args; - parameters["__location__"] = location; - properties["__location__"] = location; - args["__location__"] = location; - POST_DEBUG_MSG(3, "Parameter"); - set_config_attribute(object["config_attributes"], module, - (std::string)(instance["pre_primitive"]), - instance["post_primitives"], parameters, - m_config_mapping["parameters"], - instance["connectivity"], args, define); - args = instance_args; - args["__location__"] = location; - POST_DEBUG_MSG(3, "Property"); - set_config_attribute(object["config_attributes"], module, - (std::string)(instance["pre_primitive"]), - instance["post_primitives"], properties, - m_config_mapping["properties"], - instance["connectivity"], args, define); } } } @@ -1497,12 +1433,13 @@ void ModelConfig_IO::set_config_attribute( } if (ready) { CFG_ASSERT(rules.contains("rules")); - nlohmann::json results = get_combined_results(rules, "results", key); - nlohmann::json neg_results = - get_combined_results(rules, "neg_results", key); + CFG_ASSERT(rules.contains("results")); + nlohmann::json neg_results = rules.contains("neg_results") + ? rules["neg_results"] + : nlohmann::json::array(); set_config_attribute_by_rules(config_attributes, inputs, connectivity, - rules["rules"], results, neg_results, - args, define); + rules["rules"], rules["results"], + neg_results, args, define); } } } @@ -1539,7 +1476,8 @@ void ModelConfig_IO::set_config_attribute_by_rules( } /* - To set configuration attributes for instance after evaluate if the rule match + To set configuration attributes for instance after evaluate if the rule + match */ void ModelConfig_IO::set_config_attribute_by_rule( nlohmann::json& config_attributes, nlohmann::json& results, @@ -1696,7 +1634,10 @@ void ModelConfig_IO::assign_json_object(nlohmann::json& object, Base on given module name, figure the first location */ std::string ModelConfig_IO::get_location(const std::string& name, - std::string* module) { + std::string* module, uint8_t* status) { + if (status != nullptr) { + *status = 0; + } std::string location = ""; for (auto& instance : m_instances) { validate_instance(instance); @@ -1704,8 +1645,11 @@ std::string ModelConfig_IO::get_location(const std::string& name, CFG_ASSERT(instance.contains("__validation_msg__")); CFG_ASSERT(instance["__validation__"].is_boolean()); CFG_ASSERT(instance["__validation_msg__"].is_string()); - if ((bool)(instance["__validation__"])) { - if (instance["name"] == name) { + if (instance["name"] == name) { + if (status != nullptr) { + *status = 1; + } + if ((bool)(instance["__validation__"])) { location = (std::string)(instance["location"]); if (location.find("__SKIP_LOCATION_CHECK__") == 0) { location = location.substr(23); @@ -1716,8 +1660,12 @@ std::string ModelConfig_IO::get_location(const std::string& name, if (module != nullptr) { (*module) = (std::string)(instance["module"]); } - break; + if (status != nullptr) { + *status |= 2; + } + } else { } + break; } } return location; @@ -1745,10 +1693,21 @@ void ModelConfig_IO::set_validation_msg(bool status, std::string& msg, } else { msg = CFG_print("Fail:%s", seq_name.c_str()); } - CFG_POST_WARNING( +#if 0 + POST_ERROR_MSG( + 1, "Skip module:%s name:%s location(s):\"%s\" because it failed in %s " "validation", module.c_str(), name.c_str(), location.c_str(), seq_name.c_str()); +#else + std::string msg = CFG_print( + "Error: Skip module:%s name:%s location(s):\"%s\" because it failed " + "in " + "%s validation", + module.c_str(), name.c_str(), location.c_str(), seq_name.c_str()); + m_messages.push_back(new ModelConfig_IO_MSG(1, msg)); +#endif + m_status = false; } } @@ -1868,56 +1827,6 @@ void ModelConfig_IO::post_msg(MCIO_MSG_TYPE type, uint32_t space, } } -/* - Generate standard failure message for not able to route CLKBUF to gearbox -*/ -std::string ModelConfig_IO::clkbuf_routing_failure_msg( - const std::string& clkbuf, const std::string& clkbuf_location, - const std::string& gearbox, const std::string& gearbox_module, - const std::string& gearbox_location) { - std::string msg = ""; - if (gearbox_module.size()) { - CFG_ASSERT(gearbox_location.size()); - msg = CFG_print( - "Not able to route clock-capable pin %s (location:%s) to gearbox " - "module %s clock (module:%s) (location:%s)", - clkbuf.c_str(), clkbuf_location.c_str(), gearbox.c_str(), - gearbox_module.c_str(), gearbox_location.c_str()); - } else { - CFG_ASSERT(gearbox_location.size() == 0); - msg = CFG_print( - "Not able to route clock-capable pin %s (location:%s) to gearbox " - "module %s clock", - clkbuf.c_str(), clkbuf_location.c_str(), gearbox.c_str()); - } - return msg; -} - -/* - Generate standard failure message for not able to route PLL to gearbox -*/ -std::string ModelConfig_IO::pll_routing_failure_msg( - const std::string& pll, const std::string& pll_port, - const std::string& pll_location, const std::string& gearbox, - const std::string& gearbox_module, const std::string& gearbox_location) { - std::string msg = ""; - if (gearbox_module.size()) { - CFG_ASSERT(gearbox_location.size()); - msg = CFG_print( - "Not able to route PLL %s Port %s (location:%s) to gearbox module %s " - "clock (module:%s) (location:%s)", - pll.c_str(), pll_port.c_str(), pll_location.c_str(), gearbox.c_str(), - gearbox_module.c_str(), gearbox_location.c_str()); - } else { - CFG_ASSERT(gearbox_location.size() == 0); - msg = CFG_print( - "Not able to route PLL %s Port %s (location:%s) to gearbox module %s " - "clock", - pll.c_str(), pll_port.c_str(), pll_location.c_str(), gearbox.c_str()); - } - return msg; -} - /* Getting pin information from Python */ @@ -1926,10 +1835,10 @@ PIN_INFO ModelConfig_IO::get_pin_info(const std::string& name) { std::vector results = m_python->run_file("config", "get_pin_info", std::vector({CFG_Python_OBJ(name)})); - CFG_ASSERT_MSG(results.size() == 11, - "Expect Python get_pin_info() function return 10 arguments, " + CFG_ASSERT_MSG(results.size() == 8, + "Expect Python get_pin_info(%s) function return 8 arguments, " "but found %ld", - results.size()); + name.c_str(), results.size()); CFG_ASSERT(results[0].type == CFG_Python_OBJ::TYPE::STR); CFG_ASSERT(results[1].type == CFG_Python_OBJ::TYPE::INT); CFG_ASSERT(results[2].type == CFG_Python_OBJ::TYPE::BOOL); @@ -1938,62 +1847,11 @@ PIN_INFO ModelConfig_IO::get_pin_info(const std::string& name) { CFG_ASSERT(results[5].type == CFG_Python_OBJ::TYPE::INT); CFG_ASSERT(results[6].type == CFG_Python_OBJ::TYPE::STR); CFG_ASSERT(results[7].type == CFG_Python_OBJ::TYPE::STR); - CFG_ASSERT(results[8].type == CFG_Python_OBJ::TYPE::STR); - CFG_ASSERT(results[9].type == CFG_Python_OBJ::TYPE::INT); - CFG_ASSERT(results[10].type == CFG_Python_OBJ::TYPE::INT); - return PIN_INFO( - results[0].get_str(), results[1].get_u32(), results[2].get_bool(), - results[3].get_u32(), results[4].get_u32(), results[5].get_u32(), - results[6].get_str(), results[7].get_str(), results[8].get_str(), - results[9].get_u32(), results[10].get_u32()); -} - -/* - Getting FCLK PLL resource from Python -*/ -uint32_t ModelConfig_IO::fclk_use_pll_resource(const std::string& name) { - CFG_ASSERT(m_python != nullptr); - std::vector results = - m_python->run_file("config", "fclk_use_pll_resource", - std::vector({CFG_Python_OBJ(name)})); - CFG_ASSERT(results.size() == 1); - CFG_ASSERT(results[0].type == CFG_Python_OBJ::TYPE::INT); - return results[0].get_u32(); -} - -/* - Combine CPP generated result and JSON rule result -*/ -nlohmann::json ModelConfig_IO::get_combined_results( - nlohmann::json& rules, std::string targeted_result, - const std::string& instance_key) { - CFG_ASSERT(m_current_instance != nullptr); - CFG_ASSERT(rules.is_object()); - nlohmann::json results = nlohmann::json::array(); - std::string cpp_key = targeted_result; - cpp_key = CFG_print("CPP_%s_%s", instance_key.c_str(), - CFG_string_toupper(cpp_key).c_str()); - if (m_current_instance->contains(cpp_key)) { - nlohmann::json cpp_results = (*m_current_instance)[cpp_key]; - CFG_ASSERT(cpp_results.is_array()); - for (auto& cpp : cpp_results) { - CFG_ASSERT(cpp.is_object()); - results.push_back(cpp); - } - } - if (rules.contains(targeted_result)) { - nlohmann::json rule_results = rules[targeted_result]; - if (rule_results.is_array()) { - for (auto& rule : rule_results) { - CFG_ASSERT(rule.is_object()); - results.push_back(rule); - } - } else { - CFG_ASSERT(rule_results.is_object()); - results.push_back(rule_results); - } - } - return results; + ; + return PIN_INFO(results[0].get_str(), results[1].get_u32(), + results[2].get_bool(), results[3].get_u32(), + results[4].get_u32(), results[5].get_u32(), + results[6].get_str(), results[7].get_str()); } /********************************** @@ -2109,18 +1967,35 @@ bool ModelConfig_IO::is_siblings_match(nlohmann::json& primitive, Entry function to write instances (message) into JSON */ void ModelConfig_IO::write_json(const std::string& file) { + nlohmann::json messages = nlohmann::json::array(); + for (auto& msg : m_messages) { + std::string message = msg->msg; + for (uint32_t i = 0; i < msg->offset; i++) { + message = " " + message; + } + messages.push_back(message); + } + write_json(file, m_status, "IO", messages, m_instances); +} + +void ModelConfig_IO::write_json(const std::string& file, bool status, + const std::string& feature, + nlohmann::json& messages, + nlohmann::json& instances) { + CFG_ASSERT(messages.is_array()); std::ofstream json(file.c_str()); size_t index = 0; - json << "{\n \"messages\" : [\n"; - for (auto& msg : m_messages) { + json << "{\n"; + json << " \"status\": " << (status ? "true" : "false") << ",\n"; + json << " \"feature\": \"" << feature.c_str() << "\",\n"; + json << " \"messages\": [\n"; + for (auto& msg : messages) { + CFG_ASSERT(msg.is_string()); if (index) { json << ",\n"; } json << " \""; - for (uint32_t i = 0; i < msg->offset; i++) { - json << " "; - } - write_json_data(msg->msg, json); + write_json_data(msg, json); json << "\""; json.flush(); index++; @@ -2129,9 +2004,9 @@ void ModelConfig_IO::write_json(const std::string& file) { json << "\n"; } json << " ],\n"; - json << " \"instances\" : [\n"; + json << " \"instances\": [\n"; index = 0; - for (auto& instance : m_instances) { + for (auto& instance : instances) { if (index) { json << ",\n"; } @@ -2168,7 +2043,7 @@ void ModelConfig_IO::write_json_instance(nlohmann::json& instance, CFG_split_string(std::string(instance["linked_object"]), "+", 0, false); nlohmann::json& objects = instance["linked_objects"]; CFG_ASSERT(obj_seq.size() == objects.size()); - json << " \"linked_objects\" : {\n"; + json << " \"linked_objects\": {\n"; size_t index = 0; for (auto& obj : obj_seq) { if (index) { @@ -2176,13 +2051,13 @@ void ModelConfig_IO::write_json_instance(nlohmann::json& instance, } CFG_ASSERT(objects.contains(obj)); nlohmann::json object = objects[obj]; - json << " \"" << obj.c_str() << "\" : {\n"; + json << " \"" << obj.c_str() << "\": {\n"; write_json_object("location", std::string(object["location"]), json, 5); json << ",\n"; - json << " \"properties\" : {\n"; + json << " \"properties\": {\n"; write_json_map(object["properties"], json, 6); json << " },\n"; - json << " \"config_attributes\" : [\n"; + json << " \"config_attributes\": [\n"; size_t attr_index = 0; for (auto& cfg_attr : object["config_attributes"]) { CFG_ASSERT(cfg_attr.is_object()); @@ -2203,31 +2078,31 @@ void ModelConfig_IO::write_json_instance(nlohmann::json& instance, } json << "\n"; json << " },\n"; - json << " \"connectivity\" : {\n"; + json << " \"connectivity\": {\n"; write_json_map(instance["connectivity"], json); json << " },\n"; - json << " \"parameters\" : {\n"; + json << " \"parameters\": {\n"; write_json_map(instance["parameters"], json); json << " },\n"; - json << " \"flags\" : [\n"; + json << " \"flags\": [\n"; write_json_array(get_json_string_list(instance["flags"], args), json); json << " ],\n"; write_json_object("pre_primitive", (std::string)(instance["pre_primitive"]), json); json << ",\n"; - json << " \"post_primitives\" : [\n", + json << " \"post_primitives\": [\n", write_json_array(get_json_string_list(instance["post_primitives"], args), json); json << " ],\n"; for (auto key : std::vector({"route_clock_to", "route_clock_result"})) { index = 0; - json << " \"" << key.c_str() << "\" : {\n"; + json << " \"" << key.c_str() << "\": {\n"; for (auto iter : instance[key].items()) { if (index) { json << ",\n"; } - json << " \"" << std::string(iter.key()).c_str() << "\" : [\n"; + json << " \"" << std::string(iter.key()).c_str() << "\": [\n"; write_json_array(get_json_string_list(iter.value(), args), json, 5); json << " ]"; index++; @@ -2237,7 +2112,7 @@ void ModelConfig_IO::write_json_instance(nlohmann::json& instance, } json << " },\n"; } - json << " \"errors\" : [\n"; + json << " \"errors\": [\n"; write_json_array(get_json_string_list(instance["errors"], args), json, 4); json << " ],\n"; for (auto& iter : instance.items()) { @@ -2252,18 +2127,36 @@ void ModelConfig_IO::write_json_instance(nlohmann::json& instance, } } } - write_json_object("__validation__", - (bool)(instance["__validation__"]) ? "TRUE" : "FALSE", - json); - json << ",\n"; + if ((bool)(instance["__validation__"])) { + json << " \"__validation__\": true,\n"; + } else { + json << " \"__validation__\": false,\n"; + } write_json_object("__validation_msg__", std::string(instance["__validation_msg__"]), json); + json << ",\n"; + json << " \"config_attributes\": [\n"; + size_t attr_index = 0; + for (auto& cfg_attr : instance["config_attributes"]) { + CFG_ASSERT(cfg_attr.is_object()); + if (attr_index) { + json << ",\n"; + } + json << " {\n"; + write_json_map(cfg_attr, json, 5); + json << " }"; + attr_index++; + } + if (attr_index) { + json << "\n"; + } + json << " ]"; json << "\n }"; } /* To write object into JSON - "string" : "string" + "string": "string" */ void ModelConfig_IO::write_json_object(const std::string& key, const std::string& value, @@ -2275,7 +2168,7 @@ void ModelConfig_IO::write_json_object(const std::string& key, json << "\""; write_json_data(key, json); json << "\""; - json << " : "; + json << ": "; json << "\""; write_json_data(value, json); json << "\""; @@ -2283,8 +2176,8 @@ void ModelConfig_IO::write_json_object(const std::string& key, /* To write object into JSON - "string" : "string", - "string" : "string", + "string": "string", + "string": "string", .... */ void ModelConfig_IO::write_json_map(nlohmann::json& map, std::ofstream& json, @@ -2344,155 +2237,4 @@ void ModelConfig_IO::write_json_data(const std::string& str, } } -/********************************** - * - * Static function - * - **********************************/ -/* - Entry function to allocate resource -*/ -bool ModelConfig_IO::allocate_resource( - std::vector& instances, - MODEL_RESOURCE_INSTANCE*& new_instance, bool print_msg) { - bool status = false; - // Sanity check, all must have been decided except last one - // All total must be same - uint32_t total = new_instance->total; - for (size_t i = 0; i < (instances.size() + 1); i++) { - MODEL_RESOURCE_INSTANCE* inst = - i < instances.size() ? instances[i] : new_instance; - CFG_ASSERT(total == inst->total); - } - for (auto& inst : instances) { - inst->backup(); - } - uint32_t allocated_resource_track = 0; - uint32_t decided_instance_track = 0; - std::vector new_instances; - bool stop = false; - while (!stop) { - // Very time figure out which instances has least chance (least fortunate) - uint32_t least_possible = (uint32_t)(-1); - size_t least_fortunate_instance = (size_t)(-1); - bool use_shift_method = false; - for (size_t i = 0; i < (instances.size() + 1); i++) { - // Only search for instance which has not been decided - if ((decided_instance_track & (1 << i)) == 0) { - MODEL_RESOURCE_INSTANCE*& inst = - i < instances.size() ? instances[i] : new_instance; - uint32_t possible_count = 0; - for (uint32_t j = 0; j < inst->total; j++) { - if (((inst->possible & (1 << j)) != 0) && - ((allocated_resource_track & (1 << j)) == 0)) { - possible_count++; - } - } - if (possible_count == 0) { - // We cannot find any resource that this instance can useful - // We try if we can shift around other instances - for (uint32_t j = 0; j < inst->total; j++) { - if (inst->possible & (1 << j)) { - if (shift_instance_resource(j, allocated_resource_track, - new_instances, print_msg)) { - // shift_instance_resource had updated the decisions of - // existing instances and allocated_resource_track - inst->decision = j; - new_instances.push_back(inst); - decided_instance_track |= (1 << i); - use_shift_method = true; - if (print_msg) { - printf( - " Decided instance %d to use resource %d (after " - "other " - "shift)\n", - inst->index, inst->decision); - } - break; - } - } - } - stop = !use_shift_method; - if (print_msg && stop) { - printf(" Cannot find resource for instance %d\n", inst->index); - } - break; - } else { - if (possible_count < least_possible) { - least_possible = possible_count; - least_fortunate_instance = i; - } - } - } - } - if (!stop && !use_shift_method) { - CFG_ASSERT(least_fortunate_instance <= instances.size()); - MODEL_RESOURCE_INSTANCE*& inst = - least_fortunate_instance < instances.size() - ? instances[least_fortunate_instance] - : new_instance; - for (uint32_t j = 0; j < inst->total; j++) { - if (((inst->possible & (1 << j)) != 0) && - ((allocated_resource_track & (1 << j)) == 0)) { - allocated_resource_track |= (1 << j); - decided_instance_track |= (1 << least_fortunate_instance); - inst->decision = j; - new_instances.push_back(inst); - if (print_msg) { - printf(" Decided instance %d to use resource %d\n", inst->index, - inst->decision); - } - break; - } - } - } - if (!stop) { - if ((instances.size() + 1) == new_instances.size()) { - stop = true; - status = true; - instances.push_back(new_instance); - } - } - } - if (!status) { - delete new_instance; - new_instance = nullptr; - for (auto& inst : instances) { - inst->restore(); - } - } - return status; -} - -/* - Move the resource if it is flexible and give opportunity to those that less - flexible -*/ -bool ModelConfig_IO::shift_instance_resource( - uint32_t try_resource, uint32_t& allocated_resource_track, - std::vector& instances, bool print_msg) { - bool shifted = false; - for (auto& inst : instances) { - if (inst->decision == try_resource) { - for (uint32_t j = 0; j < inst->total; j++) { - if (j != try_resource && ((inst->possible & (1 << j)) != 0) && - ((allocated_resource_track & (1 << j)) == 0)) { - if (print_msg) { - printf(" Shift instance %d from resource %d to resource %d\n", - inst->index, inst->decision, j); - } - inst->decision = j; // new decision made - allocated_resource_track |= (1 << j); - shifted = true; - break; - } - } - if (shifted) { - break; - } - } - } - return shifted; -} - } // namespace FOEDAG diff --git a/src/Configuration/ModelConfig/ModelConfig_IO.h b/src/Configuration/ModelConfig/ModelConfig_IO.h index 7ad606c83..3e13116cf 100644 --- a/src/Configuration/ModelConfig/ModelConfig_IO.h +++ b/src/Configuration/ModelConfig/ModelConfig_IO.h @@ -28,7 +28,6 @@ along with this program. If not, see . #include #include -#include "ModelConfig_IO_resource.h" #include "nlohmann_json/json.hpp" struct ModelConfig_IO_MSG; @@ -73,6 +72,32 @@ struct MODEL_RESOURCE_INSTANCE { typedef std::map> MODEL_RESOURCES; +struct PIN_INFO { + PIN_INFO(const std::string& in0, uint32_t in1, bool in2, uint32_t in3, + uint32_t in4, uint32_t in5, const std::string& in6, + const std::string& in7) + : type(in0), + bank(in1), + is_clock(in2), + index(in3), + pair_index(in4), + ab_io(in5), + ab_name(in6), + model_name(in7) { + CFG_ASSERT(((type == "BOOT_CLOCK" || type == "FABRIC_CLKBUF") && + ab_name.size() == 0) || + ab_name.size() == 1); + } + const std::string type = ""; + const uint32_t bank = 0; + const bool is_clock = false; + const uint32_t index = 0; + const uint32_t pair_index = 0; + const uint32_t ab_io = 0; + const std::string ab_name = ""; + const std::string model_name = ""; +}; + namespace FOEDAG { class ModelConfig_IO { @@ -81,12 +106,16 @@ class ModelConfig_IO { const std::map& options, const std::string& output); ~ModelConfig_IO(); + static void write_json(const std::string& file, bool status, + const std::string& feature, nlohmann::json& messages, + nlohmann::json& instances); private: - void python_file(bool is_unittest); - void read_resources(); + void initialize_python(bool is_unittest, const std::string& routing_config); void validate_instances(nlohmann::json& instances); - void validate_instance(const nlohmann::json& instance, bool is_final = false); + static void validate_instance(const nlohmann::json& instance, + bool is_final = false); + void validate_routing(const nlohmann::json& routing, bool is_final); void merge_property_instances(nlohmann::json property_instances); void merge_property_instance(nlohmann::json& netlist_instance, nlohmann::json property_instances); @@ -94,28 +123,26 @@ class ModelConfig_IO { void locate_instance(nlohmann::json& instance); void initialization(); void validations(bool init, const std::string& key); - void validation(nlohmann::json& instance, MODEL_RESOURCES& resources, - const std::string& key); + void validation(nlohmann::json& instance, const std::string& key); void internal_error_validations(); void invalidate_childs(); void invalidate_chain(const std::string& linked_object); void assign_no_location_instance(); void assign_no_location_instance_child_location( const std::string& linked_object); - void allocate_fclk_routing(); - void allocate_clkbuf_fclk_routing(nlohmann::json& instance, - const std::string& port); - void allocate_pll_fclk_routing(nlohmann::json& instance, - const std::string& port); - void allocate_and_set_root_bank_routing(); - void set_clkbuf_config_attributes(); - void set_clkbuf_config_attribute(nlohmann::json& instance); - void allocate_pll(); - void allocate_pll(bool force); - void set_pll_config_attributes(); - void set_pll_config_attribute(nlohmann::json& instance); - void set_fclk_config_attribute(nlohmann::json& instance); - uint32_t undecided_pll(); + void prepare_instance_objects(); + nlohmann::json create_routing_object(); + nlohmann::json prepare_routing_json(); + void solve_routing_json(nlohmann::json& routings, + const std::string& route_model); + std::string get_pll_port_name(std::string& pritimive_port_name); + std::string get_iserdes_clk_mode(nlohmann::json& instance); + void validate_routings_result( + nlohmann::json& routing, + std::map>& results); + void get_routing_result(nlohmann::json& instance, nlohmann::json& routing, + bool update_error); + /* Functions to set configuration attributes */ @@ -153,13 +180,13 @@ class ModelConfig_IO { const std::string& value, const std::string& name, const std::string& feature); std::string get_location(const std::string& name, - std::string* module = nullptr); - + std::string* module = nullptr, + uint8_t* status = nullptr); void set_validation_msg(bool status, std::string& msg, const std::string& module, const std::string& name, const std::string& location, const std::string& seq_name, bool skip = false); - std::vector get_json_string_list( + static std::vector get_json_string_list( const nlohmann::json& strings, std::map& args); void retrieve_instance_args(nlohmann::json& instance, std::map& args); @@ -168,22 +195,8 @@ class ModelConfig_IO { ARG_PROPERTY get_arg_info(std::string str, std::string& name, std::string& value); void post_msg(MCIO_MSG_TYPE type, uint32_t space, const std::string& msg); - std::string clkbuf_routing_failure_msg(const std::string& clkbuf, - const std::string& clkbuf_location, - const std::string& gearbox, - const std::string& gearbox_module, - const std::string& gearbox_location); - std::string pll_routing_failure_msg(const std::string& pll, - const std::string& pll_port, - const std::string& pll_location, - const std::string& gearbox, - const std::string& gearbox_module, - const std::string& gearbox_location); PIN_INFO get_pin_info(const std::string& name); - uint32_t fclk_use_pll_resource(const std::string& name); - nlohmann::json get_combined_results(nlohmann::json& rules, - std::string targeted_result, - const std::string& instance_key); + /* Functions to check sibling rules */ @@ -198,37 +211,27 @@ class ModelConfig_IO { Helper to write JSON */ void write_json(const std::string& file); - void write_json_instance(nlohmann::json& instance, std::ofstream& json); - void write_json_object(const std::string& key, const std::string& value, - std::ofstream& json, uint32_t space = 3); - void write_json_map(nlohmann::json& map, std::ofstream& json, - uint32_t space = 4); - void write_json_array(std::vector array, std::ofstream& json, - uint32_t space = 4); - void write_json_data(const std::string& str, std::ofstream& json); - - /* - Static - */ - public: - static bool allocate_resource( - std::vector& instances, - MODEL_RESOURCE_INSTANCE*& new_instance, bool print_msg); - - private: - static bool shift_instance_resource( - uint32_t try_resource, uint32_t& allocated_resource_track, - std::vector& instances, bool print_msg); + static void write_json_instance(nlohmann::json& instance, + std::ofstream& json); + static void write_json_object(const std::string& key, + const std::string& value, std::ofstream& json, + uint32_t space = 3); + static void write_json_map(nlohmann::json& map, std::ofstream& json, + uint32_t space = 4); + static void write_json_array(std::vector array, + std::ofstream& json, uint32_t space = 4); + static void write_json_data(const std::string& str, std::ofstream& json); protected: + bool m_status = true; CFG_Python_MGR* m_python = nullptr; std::string m_pll_workaround = ""; nlohmann::json m_instances; nlohmann::json m_config_mapping; std::map m_global_args; - ModelConfig_IO_RESOURCE* m_resource = nullptr; std::vector m_messages; - const nlohmann::json* m_current_instance = nullptr; + std::string m_routing_config = ""; + std::map m_routing_instance_tracker; }; } // namespace FOEDAG diff --git a/src/Configuration/ModelConfig/ModelConfig_IO_resource.cpp b/src/Configuration/ModelConfig/ModelConfig_IO_resource.cpp deleted file mode 100644 index 3a281141e..000000000 --- a/src/Configuration/ModelConfig/ModelConfig_IO_resource.cpp +++ /dev/null @@ -1,255 +0,0 @@ -/* -Copyright 2023 The Foedag team - -GPL License - -Copyright (c) 2023 The Open-Source FPGA Foundation - -This program is free software: you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation, either version 3 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program. If not, see . -*/ - -#include "ModelConfig_IO_resource.h" - -namespace FOEDAG { - -ModelConfig_IO_MODEL::ModelConfig_IO_MODEL(const std::string& name, - const std::string& ric_name, - const std::string& type, - const std::string& subtype, - uint32_t bank) - : m_name(name), - m_ric_name(ric_name), - m_type(type), - m_subtype(subtype), - m_bank(bank) {} - -void ModelConfig_IO_MODEL::assign(const std::string* const_ptr, - const std::string& value) const { - std::string* ptr = const_cast(const_ptr); - (*ptr) = value; -} - -void ModelConfig_IO_MODEL::backup() const { - assign(&m_backup_instantiator, m_instantiator); -} - -void ModelConfig_IO_MODEL::restore() const { - assign(&m_instantiator, m_backup_instantiator); -} - -void ModelConfig_IO_MODEL::set_instantiator( - const std::string& instantiator, const std::string& sub_resource) const { - assign(&m_instantiator, instantiator); - assign(&m_sub_resource, sub_resource); -} - -void ModelConfig_IO_MODEL::set_sub_resource( - const std::string& sub_resource) const { - CFG_ASSERT(m_sub_resource.size() == 0); - assign(&m_sub_resource, sub_resource); -} - -ModelConfig_IO_RESOURCE::ModelConfig_IO_RESOURCE() {} - -ModelConfig_IO_RESOURCE::~ModelConfig_IO_RESOURCE() { - for (auto& iter : m_resources) { - while (iter.second->size()) { - delete iter.second->back(); - iter.second->pop_back(); - } - delete iter.second; - } -} - -/* - Add resource, retrieving from the config map -*/ -void ModelConfig_IO_RESOURCE::add_resource(const std::string& resource, - const std::string& name, - const std::string& ric_name, - const std::string& type, - const std::string& subtype, - uint32_t bank) { - if (m_resources.find(resource) == m_resources.end()) { - m_resources[resource] = new std::vector; - } - m_resources[resource]->push_back( - new ModelConfig_IO_MODEL(name, ric_name, type, subtype, bank)); -} - -/* - Get resource count -*/ -size_t ModelConfig_IO_RESOURCE::get_resource_count( - const std::string& resource) { - CFG_ASSERT(m_resources.find(resource) != m_resources.end()); - return m_resources[resource]->size(); -} - -/* - Get index of resource availability -*/ -uint64_t ModelConfig_IO_RESOURCE::get_resource_availability_index( - const std::string& resource) { - CFG_ASSERT(m_resources.find(resource) != m_resources.end()); - uint64_t availability = 0; - uint64_t index = 0; - for (auto& r : *m_resources[resource]) { - if (r->m_instantiator.size() == 0) { - availability |= ((uint64_t)(1) << index); - } - index++; - } - return availability; -} - -/* - Get the resource list that being used by instantiator -*/ -std::vector -ModelConfig_IO_RESOURCE::get_used_resource( - std::vector* models, - const std::string& instantiator) { - CFG_ASSERT(instantiator.size()); - std::vector resources; - for (auto& model : *models) { - if (model->m_instantiator == instantiator || - (model->m_instantiator.size() > 0 && instantiator == "__ALL__")) { - resources.push_back(model); - } - } - return resources; -} - -/* - Entry function to get the resource list that being used by instantiator -*/ -std::vector -ModelConfig_IO_RESOURCE::get_used_resource(const std::string& resource, - const std::string& instantiator) { - CFG_ASSERT(m_resources.find(resource) != m_resources.end()); - return get_used_resource(m_resources[resource], instantiator); -} - -/* - Try to use the resource -*/ -bool ModelConfig_IO_RESOURCE::use_resource( - std::vector* models, - const std::string& instantiator, const std::string& name, - const std::string& type, const std::string& sub_resource) { - CFG_ASSERT(instantiator.size()); - CFG_ASSERT(name.size()); - m_msg = ""; - bool status = false; - for (auto& model : *models) { - if (model->m_name == name) { - if (model->m_instantiator.size()) { - if (model->m_instantiator == instantiator) { - if (model->m_sub_resource.size() == 0 || sub_resource.size() == 0 || - model->m_sub_resource == sub_resource) { - m_msg = - CFG_print("Use %s: %s", type.c_str(), model->m_name.c_str()); - if (model->m_sub_resource.size() == 0 && sub_resource.size() > 0) { - model->set_sub_resource(sub_resource); - } - status = true; - } else { - m_msg = CFG_print( - "Attemp to use %s: %s which conflict with exist sub-resource " - "%s (attempted sub-resource: %s)", - type.c_str(), model->m_name.c_str(), - model->m_sub_resource.c_str(), sub_resource.c_str()); - } - } else { - m_msg = CFG_print("Attemp to use %s: %s, but it had been used by %s", - type.c_str(), model->m_name.c_str(), - model->m_instantiator.c_str()); - } - } else { - model->set_instantiator(instantiator, sub_resource); - m_msg = CFG_print("Use %s: %s (sub-resource: %s)", type.c_str(), - model->m_name.c_str(), sub_resource.c_str()); - status = true; - } - break; - } - } - if (!status && m_msg.size() == 0) { - m_msg = - CFG_print("Cannot find %s resource: %s", type.c_str(), name.c_str()); - } - return status; -} - -/* - Entry function to try to use the resource -*/ -bool ModelConfig_IO_RESOURCE::use_resource(const std::string& resource, - const std::string& instantiator, - const std::string& name, - const std::string& sub_resource) { - CFG_ASSERT(m_resources.find(resource) != m_resources.end()); - std::string r = resource; - return use_resource(m_resources[resource], instantiator, name, - CFG_string_toupper(r), sub_resource); -} - -/* - Entry function to try to use the resource -*/ -std::pair ModelConfig_IO_RESOURCE::use_root_bank_clkmux( - const std::string& module, const std::string& location, - const std::string& sub_resource, PIN_INFO& pin_info) { - CFG_ASSERT(sub_resource == "CORE" || sub_resource == "CDR"); - std::string resource = CFG_print( - "%s(%s)", pin_info.root_bank_mux_resource.c_str(), sub_resource.c_str()); - std::pair status; - if (m_root_bank_clkmuxes.find(resource) != m_root_bank_clkmuxes.end()) { - status = std::make_pair( - false, CFG_print("%s is already used by %s", resource.c_str(), - m_root_bank_clkmuxes.at(resource).c_str())); - } else { - m_root_bank_clkmuxes[resource] = - CFG_print("module %s (location: %s)", module.c_str(), location.c_str()); - status = std::make_pair(true, resource); - } - return status; -} - -/* - Fail-safe mechanism -*/ -void ModelConfig_IO_RESOURCE::backup() { - for (auto& iter : m_resources) { - for (auto& item : *(iter.second)) { - item->backup(); - } - } - m_backup_root_bank_clkmuxes = m_root_bank_clkmuxes; -} - -/* - Fail-safe mechanism -*/ -void ModelConfig_IO_RESOURCE::restore() { - for (auto& iter : m_resources) { - for (auto& item : *(iter.second)) { - item->restore(); - } - } - m_root_bank_clkmuxes = m_backup_root_bank_clkmuxes; -} - -} // namespace FOEDAG diff --git a/src/Configuration/ModelConfig/ModelConfig_IO_resource.h b/src/Configuration/ModelConfig/ModelConfig_IO_resource.h deleted file mode 100644 index c946190a8..000000000 --- a/src/Configuration/ModelConfig/ModelConfig_IO_resource.h +++ /dev/null @@ -1,117 +0,0 @@ -/* -Copyright 2023 The Foedag team - -GPL License - -Copyright (c) 2023 The Open-Source FPGA Foundation - -This program is free software: you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation, either version 3 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program. If not, see . - */ - -#ifndef MODEL_CONFIG_IO_RESOURCE_H -#define MODEL_CONFIG_IO_RESOURCE_H - -#include - -namespace FOEDAG { - -struct PIN_INFO { - PIN_INFO(const std::string& in0, uint32_t in1, bool in2, uint32_t in3, - uint32_t in4, uint32_t in5, const std::string& in6, - const std::string& in7, const std::string& in8, uint32_t in9, - uint32_t in10) - : type(in0), - bank(in1), - is_clock(in2), - index(in3), - pair_index(in4), - ab_io(in5), - ab_name(in6), - root_bank_mux_location(in7), - root_bank_mux_resource(in8), - root_bank_mux_core_input_index(in9), - root_mux_input_index(in10) { - CFG_ASSERT((type == "BOOT_CLOCK" && ab_name.size() == 0) || - ab_name.size() == 1); - } - const std::string type = ""; - const uint32_t bank = 0; - const bool is_clock = false; - const uint32_t index = 0; - const uint32_t pair_index = 0; - const uint32_t ab_io = 0; - const std::string ab_name = ""; - const std::string root_bank_mux_location = ""; - const std::string root_bank_mux_resource = ""; - const uint32_t root_bank_mux_core_input_index = 0; - const uint32_t root_mux_input_index = 0; -}; - -struct ModelConfig_IO_MODEL { - ModelConfig_IO_MODEL(const std::string& name, const std::string& ric_name, - const std::string& type, const std::string& subtype, - uint32_t bank); - void assign(const std::string* const_ptr, const std::string& value) const; - void backup() const; - void restore() const; - void set_instantiator(const std::string& instantiator, - const std::string& sub_resource) const; - void set_sub_resource(const std::string& sub_resource) const; - const std::string m_name = ""; - const std::string m_ric_name = ""; - const std::string m_type = ""; - const std::string m_subtype = ""; - const uint32_t m_bank = 0; - std::string m_instantiator = ""; - std::string m_backup_instantiator = ""; - std::string m_sub_resource = ""; -}; - -struct ModelConfig_IO_RESOURCE { - ModelConfig_IO_RESOURCE(); - ~ModelConfig_IO_RESOURCE(); - // Initialize the resource - void add_resource(const std::string& resource, const std::string& name, - const std::string& ric_name, const std::string& type, - const std::string& subtype, uint32_t bank); - // Query - size_t get_resource_count(const std::string& resource); - uint64_t get_resource_availability_index(const std::string& resource); - std::vector get_used_resource( - std::vector* models, - const std::string& instantiator); - std::vector get_used_resource( - const std::string& resource, const std::string& instantiator); - // Try to use the resource - bool use_resource(std::vector* models, - const std::string& instantiator, const std::string& name, - const std::string& type, const std::string& sub_resource); - bool use_resource(const std::string& resource, - const std::string& instantiator, const std::string& name, - const std::string& sub_resource); - std::pair use_root_bank_clkmux( - const std::string& module, const std::string& location, - const std::string& sub_resource, PIN_INFO& pin_info); - // Fail-safe mechanism - void backup(); - void restore(); - std::map*> m_resources; - std::map m_root_bank_clkmuxes; - std::map m_backup_root_bank_clkmuxes; - std::string m_msg = ""; -}; - -} // namespace FOEDAG - -#endif diff --git a/tests/unittest/CFGCommon/CFGCommon_test.cpp b/tests/unittest/CFGCommon/CFGCommon_test.cpp index f4089f917..69037c645 100644 --- a/tests/unittest/CFGCommon/CFGCommon_test.cpp +++ b/tests/unittest/CFGCommon/CFGCommon_test.cpp @@ -359,7 +359,12 @@ TEST(CFGCommon, test_python_mgr) { EXPECT_EQ(mgr.result_str("str"), "xyz"); EXPECT_EQ(mgr.result_bool("bool0"), false); EXPECT_EQ(mgr.result_bool("bool1"), true); - mgr.set_file(CFG_print("%s/python_file_test.py", current_dir.c_str())); + EXPECT_EQ( + mgr.set_file(CFG_print("%s/python_file_test.py", current_dir.c_str()), + std::vector({"abc", "xyz"})), + "python_file_test"); + EXPECT_EQ(mgr.results().size(), 1); + EXPECT_EQ(mgr.result_u32("abc"), 101); std::vector results = mgr.run_file( "python_file_test", "func1", std::vector( diff --git a/tests/unittest/CFGCommon/python_file_test.py b/tests/unittest/CFGCommon/python_file_test.py index 1d7608886..bc37dfee6 100644 --- a/tests/unittest/CFGCommon/python_file_test.py +++ b/tests/unittest/CFGCommon/python_file_test.py @@ -27,4 +27,6 @@ def func1(arg0, arg1, arg2, arg3, arg4, arg5) : return [not arg0, arg1 - 10, arg2.upper(), bytearray([a + 10 for a in arg3]), arg4 + [-5, 5], [a.lower() for a in arg5], None] def func2() : - print_something("Start of func2") \ No newline at end of file + print_something("Start of func2") + +abc = 101 \ No newline at end of file diff --git a/tests/unittest/ModelConfig/ModelConfig_IO_test.cpp b/tests/unittest/ModelConfig/ModelConfig_IO_test.cpp index 0562a6c7e..4476c92ca 100644 --- a/tests/unittest/ModelConfig/ModelConfig_IO_test.cpp +++ b/tests/unittest/ModelConfig/ModelConfig_IO_test.cpp @@ -56,57 +56,6 @@ class ModelConfig_IO : public ::testing::Test { void TearDown() override { std::filesystem::current_path("../.."); } }; -TEST_F(ModelConfig_IO, allocate_resources) { - std::vector> TEST_CASES = { - {0, 2, 3}, {1, 3}, {1, 2}, {1, 2}, {0}}; - std::vector instances; - uint32_t i = 0; - for (auto test : TEST_CASES) { - printf("Testing Case %d\n", i); - uint32_t possible = 0; - for (auto p : test) { - possible |= (1 << p); - } - MODEL_RESOURCE_INSTANCE* new_resource = - new MODEL_RESOURCE_INSTANCE("a", possible, 5, i); - bool status = FOEDAG::ModelConfig_IO::allocate_resource(instances, - new_resource, true); - if (i < 4) { - EXPECT_EQ(status, true); - EXPECT_EQ((uint32_t)(instances.size()), i + 1); - EXPECT_NE(new_resource, nullptr); - if (i == 0) { - EXPECT_EQ(instances[0]->decision, 0); - } else if (i == 1) { - EXPECT_EQ(instances[0]->decision, 0); - EXPECT_EQ(instances[1]->decision, 1); - } else if (i == 2) { - EXPECT_EQ(instances[0]->decision, 0); - EXPECT_EQ(instances[1]->decision, 1); - EXPECT_EQ(instances[2]->decision, 2); - } else { - EXPECT_EQ(instances[0]->decision, 0); - EXPECT_EQ(instances[1]->decision, 3); - EXPECT_EQ(instances[2]->decision, 2); - EXPECT_EQ(instances[3]->decision, 1); - } - } else { - EXPECT_EQ(status, false); - EXPECT_EQ((uint32_t)(instances.size()), 4); - EXPECT_EQ(new_resource, nullptr); - EXPECT_EQ(instances[0]->decision, 0); - EXPECT_EQ(instances[1]->decision, 3); - EXPECT_EQ(instances[2]->decision, 2); - EXPECT_EQ(instances[3]->decision, 1); - } - i++; - } - while (instances.size()) { - delete instances.back(); - instances.pop_back(); - } -} - TEST_F(ModelConfig_IO, set_property) { compiler_tcl_common_run("clear_property"); compiler_tcl_common_run( @@ -129,11 +78,15 @@ TEST_F(ModelConfig_IO, gen_ppdb) { std::string cmd = CFG_print( "model_config gen_ppdb -netlist_ppdb %s/model_config_netlist.ppdb.json " "-config_mapping %s/apis/config_attributes.mapping.json " + "-routing_config %s/apis/routing_configurator.py " + "-routing_config_model %s/apis/1vg28_routing.py " "-property_json model_config.property.json " "-is_unittest -pll_workaround 0 " "model_config.ppdb.json", - current_dir.c_str(), current_dir.c_str()); + current_dir.c_str(), current_dir.c_str(), current_dir.c_str(), + current_dir.c_str()); compiler_tcl_common_run(cmd); + compiler_tcl_common_run("exec mv io_routing.json positive_io_routing.json"); } TEST_F(ModelConfig_IO, gen_ppdb_negative) { @@ -142,10 +95,14 @@ TEST_F(ModelConfig_IO, gen_ppdb_negative) { "model_config gen_ppdb -netlist_ppdb " "%s/model_config_netlist.negative.ppdb.json " "-config_mapping %s/apis/config_attributes.mapping.json " + "-routing_config %s/apis/routing_configurator.py " + "-routing_config_model %s/apis/1vg28_routing.py " "-is_unittest " "model_config.negative.ppdb.json", - current_dir.c_str(), current_dir.c_str()); + current_dir.c_str(), current_dir.c_str(), current_dir.c_str(), + current_dir.c_str()); compiler_tcl_common_run(cmd); + compiler_tcl_common_run("exec mv io_routing.json negative_io_routing.json"); } TEST_F(ModelConfig_IO, gen_bitstream_source) { source_model(); } @@ -189,10 +146,14 @@ TEST_F(ModelConfig_IO, compare_result) { golden_dir); compare_unittest_file(false, "model_config.simplified.property.json", "ModelConfig", golden_dir); + compare_unittest_file(false, "positive_io_routing.json", "ModelConfig", + golden_dir); compare_unittest_file(false, "model_config.ppdb.json", "ModelConfig", golden_dir); compare_unittest_file(false, "model_config_io_bitstream.detail.bit", "ModelConfig", golden_dir); + compare_unittest_file(false, "negative_io_routing.json", "ModelConfig", + golden_dir); compare_unittest_file(false, "model_config.negative.ppdb.json", "ModelConfig", golden_dir); compare_unittest_file(false, "model_config_io_bitstream.negative.detail.bit", diff --git a/tests/unittest/ModelConfig/apis/1vg28_routing.py b/tests/unittest/ModelConfig/apis/1vg28_routing.py new file mode 100644 index 000000000..cfe8add12 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/1vg28_routing.py @@ -0,0 +1,110 @@ +from routing_library import function_library +load_model("routing_library/gbox_hp_40x2.py") +load_model("routing_library/gbox_hv_40x2.py") + +# Block +create_block(name="Virgo", top=True) + +# Ports +for type_bank in [["P", 1], ["P", 2], ["R", 1], ["R", 2], ["R", 3], ["R", 5]] : + for i in range(40) : + location = function_library.get_location(type_bank[0], type_bank[1], i) + add_port(name=location, dir=DIR_IN) +add_port(name="fabric_clk", dir=DIR_OUT, bit=16) +add_port(name="fclk_buf", dir=DIR_IN, bit=8) + +# Instances +add_instance(name="hp_40x2", block="gbox_hp_40x2") +add_instance(name="hvl_40x2", block="gbox_hv_40x2") +add_instance(name="hvr_40x2", block="gbox_hv_40x2") + +# Connections +# pin --> hp/hvl/hvr pin +for type_bank in [["P", 1, 0], ["P", 2, 1], ["R", 1, 0], ["R", 2, 1], ["R", 3, 0], ["R", 5, 1]] : + instance = "hp" if type_bank[0] == "P" else ("hvl" if type_bank[1] in [1, 2] else "hvr") + instance = "%s_40x2" % instance + bank = type_bank[2] + bank_pin_name = "bank%d_rx_in" % bank + for i in range(40) : + top_location = function_library.get_location(type_bank[0], type_bank[1], i) + add_connection(source=top_location, destinations=["%s->%s[%d]" % (instance, bank_pin_name, i)]) +# hvl/hvr clk pin --> hp clk pin +for bank in range(2) : + for pin in range(2) : + source_pin = "bank%d_rx_io_clk[%d]" % (bank, pin) + add_connection(source="hvl_40x2->%s" % (source_pin), destinations=["hp_40x2->hvl_bank%d_rx_io_clk[%d]" % (bank, pin)]) + add_connection(source="hvr_40x2->%s" % (source_pin), destinations=["hp_40x2->hvr_bank%d_rx_io_clk[%d]" % (bank, pin)]) +# hp pll --> hvl pll +add_connection(source="hp_40x2->pll_foutvco[0]", destinations=["hvl_40x2->pll_foutvco"]) +add_connection(source="hp_40x2->pll_fout[0]", destinations=["hvl_40x2->pll_fout"]) +# hp pll --> hvr pll +add_connection(source="hp_40x2->pll_foutvco[1]", destinations=["hvr_40x2->pll_foutvco"]) +add_connection(source="hp_40x2->pll_fout[1]", destinations=["hvr_40x2->pll_fout"]) +# hvl core clk + cdr clk --> HP core clk + cdr clk +add_connection(source="hvl_40x2->bank0_root_core_clk[0]", destinations=["hp_40x2->hvl_bank0_root_core_clk[0]"]) +add_connection(source="hvl_40x2->bank0_root_core_clk[1]", destinations=["hp_40x2->hvl_bank0_root_core_clk[1]"]) +add_connection(source="hvl_40x2->bank0_root_cdr_clk[0]", destinations=["hp_40x2->hvl_bank0_root_cdr_clk[0]"]) +add_connection(source="hvl_40x2->bank0_root_cdr_clk[1]", destinations=["hp_40x2->hvl_bank0_root_cdr_clk[1]"]) +add_connection(source="hvl_40x2->bank1_root_core_clk[0]", destinations=["hp_40x2->hvl_bank1_root_core_clk[0]"]) +add_connection(source="hvl_40x2->bank1_root_core_clk[1]", destinations=["hp_40x2->hvl_bank1_root_core_clk[1]"]) +add_connection(source="hvl_40x2->bank1_root_cdr_clk[0]", destinations=["hp_40x2->hvl_bank1_root_cdr_clk[0]"]) +add_connection(source="hvl_40x2->bank1_root_cdr_clk[1]", destinations=["hp_40x2->hvl_bank1_root_cdr_clk[1]"]) +# hvr core clk + cdr clk --> HP core clk + cdr clk +add_connection(source="hvr_40x2->bank0_root_core_clk[0]", destinations=["hp_40x2->hvr_bank0_root_core_clk[0]"]) +add_connection(source="hvr_40x2->bank0_root_core_clk[1]", destinations=["hp_40x2->hvr_bank0_root_core_clk[1]"]) +add_connection(source="hvr_40x2->bank0_root_cdr_clk[0]", destinations=["hp_40x2->hvr_bank0_root_cdr_clk[0]"]) +add_connection(source="hvr_40x2->bank0_root_cdr_clk[1]", destinations=["hp_40x2->hvr_bank0_root_cdr_clk[1]"]) +add_connection(source="hvr_40x2->bank1_root_core_clk[0]", destinations=["hp_40x2->hvr_bank1_root_core_clk[0]"]) +add_connection(source="hvr_40x2->bank1_root_core_clk[1]", destinations=["hp_40x2->hvr_bank1_root_core_clk[1]"]) +add_connection(source="hvr_40x2->bank1_root_cdr_clk[0]", destinations=["hp_40x2->hvr_bank1_root_cdr_clk[0]"]) +add_connection(source="hvr_40x2->bank1_root_cdr_clk[1]", destinations=["hp_40x2->hvr_bank1_root_cdr_clk[1]"]) +# hp instance fabric clk --> fabric clk +for i in range(16) : + add_connection(source="hp_40x2->fabric_clk[%d]" % i, destinations=["fabric_clk[%d]" % i]) +# fclk buf --> instance fclk buf +for i in range(8) : + add_connection(source="fclk_buf[%d]" % i, destinations=["hp_40x2->fclk_buf[%d]" % i]) + +# Mapping to TCL model +for type_bank in [["P", 1, 0], ["P", 2, 1], ["R", 1, 0], ["R", 2, 1], ["R", 3, 0], ["R", 5, 1]] : + # Pin location + instance = "hp" if type_bank[0] == "P" else ("hvl" if type_bank[1] in [1, 2] else "hvr") + instance = "%s_40x2" % instance + bank = type_bank[2] + for i in range(40) : + # Gearbox mapping - hp_40x2.bank0_hpio.gearbox_P[0] ==> u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_18 or HP_1_0_0P + python_name = "%s.bank%d_hpio.%s" % (instance, bank, function_library.get_gbox_top_name(i)) + tcl_name = function_library.get_location(type_bank[0], type_bank[1], i) + add_tcl_map(python_name, tcl_name) +for type_bank in [["p", "P", ""], ["vl", "V", "_VL"], ["vr", "V", "_VR"]] : + # Top Level Type + add_tcl_map("h%s_40x2" % type_bank[0], "u_GBOX_H%s_40X2%s" % (type_bank[1], type_bank[2])) +for type_bank in [[0, "A"], [0, "B"], [1, "A"], [1, "B"]] : + # FCLK + for bit in ["vco_clk_sel", "rx_fclkio_sel", "rxclk_phase_sel"]: + python_name = "bank%d_fclk_mux_%s->%s" % (type_bank[0], type_bank[1], bit) + tcl_name = "u_gbox_fclk_mux_all->cfg_%s_%s_%d" % (bit, type_bank[1], type_bank[0]) + add_tcl_map(python_name, tcl_name) +for bank in [0, 1] : + # Root Bank + add_tcl_map("bank%d_root_bank_clkmux" % bank, "u_gbox_root_bank_clkmux_%d" % bank) +# PLL REFMUX +add_tcl_map("pll_refmux[0]", "u_gbox_pll_refmux_0") +add_tcl_map("pll_refmux[1]", "u_gbox_pll_refmux_1") +# PLL +add_tcl_map("pll[0]", "u_gbox_PLLTS16FFCFRACF_0") +add_tcl_map("pll[1]", "u_gbox_PLLTS16FFCFRACF_1") +for slot in range(16): + python_name = "->root_mux_sel[%d]" % slot + tcl_name = ".u_gbox_clkmux_52x1_left_%d->ROOT_MUX_SEL" % slot + add_tcl_map(python_name, tcl_name) + +# Diagram mapping +for type_bank in [["P", 1, 0], ["P", 2, 1], ["R", 1, 0], ["R", 2, 1], ["R", 3, 0], ["R", 5, 1]] : + instance = "hp" if type_bank[0] == "P" else ("hvl" if type_bank[1] in [1, 2] else "hvr") + # The graphviz module that we use to draw diagram have difficulty supporting ":" + # Suppose we have to display [39:0] + mapped_name = "%s_bank%s_pin[39:0]" % (instance, type_bank[2]) + for i in range(40) : + location = function_library.get_location(type_bank[0], type_bank[1], i) + add_diagram_map(name=location, mapped_name=mapped_name) \ No newline at end of file diff --git a/tests/unittest/ModelConfig/apis/config_attributes.mapping.json b/tests/unittest/ModelConfig/apis/config_attributes.mapping.json index d93f5b96f..4b9b7616d 100644 --- a/tests/unittest/ModelConfig/apis/config_attributes.mapping.json +++ b/tests/unittest/ModelConfig/apis/config_attributes.mapping.json @@ -110,25 +110,6 @@ "I_SERDES" : "DPA_MODE==NONE" } }, - "I_SERDES.ROOT_BANK_CLKMUX" : { - "rules" : { - "ROUTE_TO_FABRIC_CLK" : "__arg0__", - "DPA_MODE" : "__arg1__" - }, - "results" : { - "__location__" : "__ROOT_BANK_MUX_LOCATION__", - "I_SERDES" : "ROOT_BANK_SRC==__AB__&DPA_MODE==__arg1__ --#MUX=__ROOT_BANK_MUX__" - } - }, - "I_SERDES.ROOT_MUX" : { - "rules" : { - "ROUTE_TO_FABRIC_CLK" : "__arg0__" - }, - "results" : { - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__", - "ROOT_MUX_SEL" : "__ROOT_MUX__" - } - }, "O_SERDES.BYPASS" : { "rules" : { "WIDTH" : "__arg0__" @@ -154,13 +135,6 @@ "O_SERDES" : "DDR_MODE==SDR" } }, - "O_SERDES_CLK.IO" : { - "rules" : { - }, - "results" : { - "TX_CLOCK_IO" : "TX_clock_IO" - } - }, "O_SERDES_CLK.CLK_PHASE" : { "rules" : { "CLOCK_PHASE" : "__argCLOCK_PHASE__" @@ -180,101 +154,6 @@ "neg_results" : { "O_SERDES_CLK" : "DDR_MODE==SDR" } - }, - "BOOT_CLOCK" : { - "rules" : { - "ROUTE_TO_FABRIC_CLK" : "__arg0__" - }, - "results" : [ - { - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__", - "ROOT_MUX_SEL" : "48" - } - ] - }, - "PLL.PLLREF_MUX" : { - "rules" : { - }, - "results" : { - "__location__" : "u_GBOX_HP_40X2.u_gbox_pll_refmux___pll_resource__", - "PLL" : "PLLREF_SRC==__SRC__ --#PIN=__PIN__ --#BANK=__BANK__ --#DIV=__DIV__" - } - }, - "PLL.PLL" : { - "rules" : { - "PLL_DIV" : "__argDIV__", - "PLL_MULT" : "__argMULT__", - "PLL_POST_DIV" : "__argPOST_DIV__" - }, - "results" : { - "__define__" : "parse_pll_parameter", - "__location__" : "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF___pll_resource__", - "PLL" : "PLL_SRC==DEFAULT", - "pll_REFDIV" : "__refdiv__", - "pll_FBDIV" : "__fbdiv__", - "pll_POSTDIV1" : "__postdiv1__", - "pll_POSTDIV2" : "__postdiv2__", - "pll_PLLEN" : "__pll_enable__" - } - }, - "PLL.ROOT_MUX0" : { - "rules" : { - "__connectivity__" : "CLK_OUT", - "__index__" : "__argIndex{default:0}__", - "OUT0_ROUTE_TO_FABRIC_CLK" : "__arg0__" - }, - "results" : { - "__define__" : "parse_pll_root_mux", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__", - "ROOT_MUX_SEL" : "__pll_root_mux_sel__" - } - }, - "PLL.ROOT_MUX1" : { - "rules" : { - "__connectivity__" : "CLK_OUT_DIV2", - "__index__" : "__argIndex{default:1}__", - "OUT1_ROUTE_TO_FABRIC_CLK" : "__arg0__" - }, - "results" : { - "__define__" : "parse_pll_root_mux", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__", - "ROOT_MUX_SEL" : "__pll_root_mux_sel__" - } - }, - "PLL.ROOT_MUX2" : { - "rules" : { - "__connectivity__" : "CLK_OUT_DIV3", - "__index__" : "__argIndex{default:2}__", - "OUT2_ROUTE_TO_FABRIC_CLK" : "__arg0__" - }, - "results" : { - "__define__" : "parse_pll_root_mux", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__", - "ROOT_MUX_SEL" : "__pll_root_mux_sel__" - } - }, - "PLL.ROOT_MUX3" : { - "rules" : { - "__connectivity__" : "CLK_OUT_DIV4", - "__index__" : "__argIndex{default:3}__", - "OUT3_ROUTE_TO_FABRIC_CLK" : "__arg0__" - }, - "results" : { - "__define__" : "parse_pll_root_mux", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__", - "ROOT_MUX_SEL" : "__pll_root_mux_sel__" - } - }, - "FCLK_BUF" : { - "rules" : { - "ROUTE_TO_FABRIC_CLK" : "__arg0__", - "ROUTE_FROM_FABRIC_CLK" : "__arg1__" - }, - "results" : { - "__define__" : "parse_fabric_clock_buffer_root_mux", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__", - "ROOT_MUX_SEL" : "__fclk_buf_root_mux_sel__" - } } }, "properties" : { @@ -350,118 +229,75 @@ "results" : { "CLK_BUF" : "GBOX_TOP_SRC==DEFAULT" } - }, - "CLK_BUF.ROOT_BANK_CLKMUX" : { - "rules" : { - "ROUTE_TO_FABRIC_CLK" : "__arg0__" - }, - "results" : { - "__location__" : "__ROOT_BANK_MUX_LOCATION__", - "CLK_BUF" : "ROOT_BANK_SRC==__AB__ --#MUX=__ROOT_BANK_MUX__" - } - }, - "CLK_BUF.ROOT_MUX" : { - "rules" : { - "ROUTE_TO_FABRIC_CLK" : "__arg0__" - }, - "results" : { - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left___arg0__", - "ROOT_MUX_SEL" : "__ROOT_MUX__" - } } }, - "__file__" : [ - "import re", - "def get_pin_info(name) :", - " bank = 0", - " is_clock = False", - " index = 0", - " pair_index = 0", - " ab_io = 0", - " ab_name = ''", - " root_bank_mux_location = ''", - " root_bank_mux_resource = ''", - " root_bank_mux_core_input_index = 0", - " root_mux_input_index = 0", - " if name.find('BOOT_CLOCK#') == 0:", - " type = 'BOOT_CLOCK'", - " index = int(name[11:])", - " else :", - " m = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', name)", - " assert m != None", - " assert len(m.groups()) == 6", - " type = 'HP' if m.group(1) == 'P' else ('HVL' if m.group(2) in ['1', '2'] else 'HVR')", - " bank = 0 if m.group(2) in ['1', '3'] else 1", - " is_clock = m.group(2) == '_CC'", - " index = int(m.group(4))", - " pair_index = int(m.group(5))", - " ab_io = 0 if (pair_index < 10) else 1", - " ab_name = '%c' % (ord('A') + ab_io)", - " root_name = 'u_GBOX_HP_40X2' if type == 'HP' else ('u_GBOX_HV_40X2_VL' if type == 'HVL' else 'u_GBOX_HV_40X2_VR')", - " root_bank_mux_location = '%s.u_gbox_root_bank_clkmux_%d' % (root_name, bank)", - " root_bank_mux_resource = '%s (Bank %s)' % (root_bank_mux_location, ab_name)", - " root_bank_mux_core_input_index = index - (20 * ab_io)", - " root_mux_input_index = 0 if type == 'HP' else (8 if type == 'HVL' else 16)", - " root_mux_input_index += ((2 * bank) + ab_io)", - " return [type, bank, is_clock, index, pair_index, ab_io, ab_name, root_bank_mux_location, root_bank_mux_resource, root_bank_mux_core_input_index, root_mux_input_index]", - "def fclk_use_pll_resource(fclk) :", - " pll_resource = 0", - " if fclk.find('hvl_fclk_') == 0 :", - " pll_resource = 0", - " elif fclk.find('hvr_fclk_') == 0 :", - " pll_resource = 1", - " elif fclk.find('hp_fclk_0') == 0 :", - " pll_resource = 0", - " elif fclk.find('hp_fclk_1') == 0 :", - " pll_resource = 1", - " else :", - " raise Exception('Unknown FCLK %s' % fclk)", - " return [pll_resource]" - ], - "__resources__" : { - "pll" : [ - { "name" : "pll_0", "ric_name" : "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", "type" : "HP", "subtype" : "hp", "bank" : 0 }, - { "name" : "pll_1", "ric_name" : "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1", "type" : "HP", "subtype" : "hp", "bank" : 1 } - ], - "fclk" : [ - { "name" : "hp_fclk_0_A", "ric_name" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", "type" : "HP", "subtype" : "hp", "bank" : 0 }, - { "name" : "hp_fclk_0_B", "ric_name" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", "type" : "HP", "subtype" : "hp", "bank" : 0 }, - { "name" : "hp_fclk_1_A", "ric_name" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", "type" : "HP", "subtype" : "hp", "bank" : 1 }, - { "name" : "hp_fclk_1_B", "ric_name" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", "type" : "HP", "subtype" : "hp", "bank" : 1 }, - { "name" : "hvl_fclk_0_A", "ric_name" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", "type" : "HV", "subtype" : "hvl", "bank" : 0 }, - { "name" : "hvl_fclk_0_B", "ric_name" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", "type" : "HV", "subtype" : "hvl", "bank" : 0 }, - { "name" : "hvl_fclk_1_A", "ric_name" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", "type" : "HV", "subtype" : "hvl", "bank" : 1 }, - { "name" : "hvl_fclk_1_B", "ric_name" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", "type" : "HV", "subtype" : "hvl", "bank" : 1 }, - { "name" : "hvr_fclk_0_A", "ric_name" : "u_GBOX_HV_40X2_VR.u_gbox_fclk_mux_all", "type" : "HV", "subtype" : "hvr", "bank" : 0 }, - { "name" : "hvr_fclk_0_B", "ric_name" : "u_GBOX_HV_40X2_VR.u_gbox_fclk_mux_all", "type" : "HV", "subtype" : "hvr", "bank" : 0 }, - { "name" : "hvr_fclk_1_A", "ric_name" : "u_GBOX_HV_40X2_VR.u_gbox_fclk_mux_all", "type" : "HV", "subtype" : "hvr", "bank" : 1 }, - { "name" : "hvr_fclk_1_B", "ric_name" : "u_GBOX_HV_40X2_VR.u_gbox_fclk_mux_all", "type" : "HV", "subtype" : "hvr", "bank" : 1 } - ] - }, - "__init__" : { + "__init_file__" : { "__args__" : [], - "__equation__" : [ - "import json", - "G_RESOURCES = json.loads('__resources_string__')", - "assert 'pll' in G_RESOURCES", - "assert 'fclk' in G_RESOURCES", + "__file__" : [ + "import re", "MAX_BOOT_CLOCK_RESOURCE = 1", - "MAX_FABRIC_CLOCK_RESOURCE = 16", - "MAX_PLL_RESOURCE = len(G_RESOURCES['pll'])", "hp_banks = ['HP_%d' % i for i in [1, 2]]", "hr_banks = ['HR_%d' % i for i in [1, 2, 3, 5]]", "all_banks = hp_banks + hr_banks", - "pin_list = ['%d_%d%c' % (i, i//2, 'N' if i%2 else 'P') for i in range(40)]", - "cc_pin_list = ['%d_%d%c' % (i, i//2, 'N' if i%2 else 'P') for i in [18, 19, 38, 39]]", - "cc_p_pin_list = [pin for pin in cc_pin_list if pin[-1] == 'P']", - "g_all_pins = ['%s_%s%s' % (i, 'CC_' if j in cc_pin_list else '', j) for i in all_banks for j in pin_list]", - "g_all_clock_pins = ['%s_CC_%s' % (i, j) for i in all_banks for j in cc_p_pin_list]", + "bank_pin_count = 40", + "CC_index = [18, 19, 38, 39]", + "exclude_index = []", + "pin_list = ['%s%d_%d%c' % ('CC_' if i in CC_index else '', i, i//2, 'N' if i%2 else 'P') for i in range(bank_pin_count) if i not in exclude_index]", + "cc_p_pin_list = [pin for pin in pin_list if (pin.find('CC_') == 0 and pin[-1] == 'P')]", + "g_all_pins = ['%s_%s' % (i, j) for i in all_banks for j in pin_list]", + "g_all_clock_pins = ['%s_%s' % (i, j) for i in all_banks for j in cc_p_pin_list]", "g_all_pll_clock_pins = [pin for pin in g_all_clock_pins]", "g_boot_clock_resources = 0", "g_pin_resources = {}", - "g_fabric_clock_resources = 0", - "g_pll_resources = []", - "g_gearbox_width = {}" + "g_input_gearbox_width = {}", + "g_output_gearbox_width = {}", + "def parse_pin_location(location):", + " assert location in g_all_pins", + " m = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', location)", + " assert m != None", + " assert len(m.groups()) == 6", + " type = 'HP' if m.group(1) == 'P' else ('HVL' if m.group(2) in ['1', '2'] else 'HVR')", + " bank = 0 if m.group(2) in ['1', '3'] else 1", + " is_clock = m.group(3) == '_CC'", + " index = int(m.group(4))", + " pair_index = int(m.group(5))", + " assert pair_index == (index//2)", + " ab_io = 0 if (pair_index < 10) else 1", + " ab_name = '%c' % (ord('A') + ab_io)", + " return [m, type, bank, is_clock, index, pair_index, ab_io, ab_name]", + "def get_peer_location(location):", + " (m, type, bank, is_clock, index, pair_index, ab_io, ab_name) = parse_pin_location(location)", + " pn = 'P' if m.group(6) == 'N' else 'N'", + " index = int(m.group(4)) & ~1", + " index += (1 if pn == 'N' else 0)", + " peer_location = 'H%s_%s%s_%d_%s%s' % (m.group(1), m.group(2), m.group(3), index, m.group(5), pn)", + " return [m.group(6), peer_location]", + "def validate_data_width_parameter(location, width, gearboxes):", + " (self_pn, peer_location) = get_peer_location(location)", + " result = width >= 3 and width <= (10 if self_pn == 'P' else 5)", + " result = result and ((peer_location not in gearboxes) or (gearboxes[peer_location] <= 5 and width <=5))", + " gearboxes[location if result else ''] = width", + " gearboxes.pop('', None)", + " return result", + "def get_pin_info(name):", + " bank = 0", + " is_clock = False", + " index = 0", + " pair_index = 0", + " ab_io = 0", + " ab_name = ''", + " if name.find('BOOT_CLOCK#') == 0:", + " type = 'BOOT_CLOCK'", + " index = int(name[11:])", + " model_name = 'hp_40x2.rc_osc_50mhz'", + " elif name.find('FABRIC_CLKBUF#') == 0:", + " type = 'FABRIC_CLKBUF'", + " index = int(name[14:])", + " model_name = 'fclk_buf'", + " else :", + " (m, type, bank, is_clock, index, pair_index, ab_io, ab_name) = parse_pin_location(name)", + " model_name = '%s_40x2.bank%d_hpio.gearbox_%s[%d]' % (type.lower(), bank, m.group(6), pair_index)", + " return [type, bank, is_clock, index, pair_index, ab_io, ab_name, model_name]" ] }, "__primary_validation__" : { @@ -473,12 +309,18 @@ "__check_ds_pin_resource__", "__clock_pin_is_valid__", "__check_boot_clock_resource__", - "__pll_clock_pin_is_valid__" + "__pll_clock_pin_is_valid__", + "__check_input_data_width_parameter__", + "__check_output_data_width_parameter__", + "__check_data_rate_parameter__", + "__check_dpa_mode_parameter__", + "__check_clock_phase_parameter__", + "__check_pll_parameter__" ], "__pin_is_valid__" : { "__module__" : ["I_BUF", "O_BUF", "O_BUFT"], "__equation__" : [ - "pin_result = '__location0__' in g_all_pins" + "validation_result = '__location0__' in g_all_pins" ] }, "__check_pin_resource__" : { @@ -487,47 +329,47 @@ "temp = '__primitive_flags__'.split(',')", "bidir = 'INOUT' in temp", "value = 1 if 'I_BUF' in temp else 2", - "pin_result = '__location0__' not in g_pin_resources or ((g_pin_resources['__location0__'] & value) == 0)", + "validation_result = '__location0__' not in g_pin_resources or ((g_pin_resources['__location0__'] & value) == 0)", "exist = 0 if '__location0__' not in g_pin_resources else g_pin_resources['__location0__']", - "g_pin_resources['__location0__' if pin_result else ''] = exist | (value if bidir else 3)", + "g_pin_resources['__location0__' if validation_result else ''] = exist | (value if bidir else 3)", "g_pin_resources.pop('', None)" ] }, "__ds_pin_is_valid__" : { "__module__" : ["I_BUF_DS", "O_BUF_DS", "O_BUFT_DS"], "__equation__" : [ - "pin_result = '__location0__' in g_all_pins", - "pin_result = pin_result and '__location1__' in g_all_pins" + "validation_result = '__location0__' in g_all_pins", + "validation_result = validation_result and '__location1__' in g_all_pins" ] }, "__pin_is_differential__" : { "__module__" : ["I_BUF_DS", "O_BUF_DS", "O_BUFT_DS"], "__equation__" : [ "import re", - "pin_result = '__location0__' in g_all_pins", - "pin_result = pin_result and '__location1__' in g_all_pins", + "validation_result = '__location0__' in g_all_pins", + "validation_result = validation_result and '__location1__' in g_all_pins", "m0 = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', '__location0__')", "m1 = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', '__location1__')", - "pin_result = pin_result and m0 != None", - "pin_result = pin_result and m1 != None", - "pin_result = pin_result and len(m0.groups()) == 6", - "pin_result = pin_result and len(m1.groups()) == 6", - "pin_result = pin_result and m0.group(1) == m1.group(1)", - "pin_result = pin_result and m0.group(2) == m1.group(2)", - "pin_result = pin_result and m0.group(3) == m1.group(3)", - "pin_result = pin_result and m0.group(4) != m1.group(4)", - "pin_result = pin_result and m0.group(5) == m1.group(5)", - "pin_result = pin_result and m0.group(6) != m1.group(6)" + "validation_result = validation_result and m0 != None", + "validation_result = validation_result and m1 != None", + "validation_result = validation_result and len(m0.groups()) == 6", + "validation_result = validation_result and len(m1.groups()) == 6", + "validation_result = validation_result and m0.group(1) == m1.group(1)", + "validation_result = validation_result and m0.group(2) == m1.group(2)", + "validation_result = validation_result and m0.group(3) == m1.group(3)", + "validation_result = validation_result and m0.group(4) != m1.group(4)", + "validation_result = validation_result and m0.group(5) == m1.group(5)", + "validation_result = validation_result and m0.group(6) != m1.group(6)" ] }, "__check_ds_pin_resource__" : { "__module__" : ["I_BUF_DS", "O_BUF_DS", "O_BUFT_DS"], "__equation__" : [ - "pin_result = '__location0__' not in g_pin_resources", - "pin_result = pin_result and '__location1__' not in g_pin_resources", - "g_pin_resources['__location0__' if pin_result else ''] = 3", + "validation_result = '__location0__' not in g_pin_resources", + "validation_result = validation_result and '__location1__' not in g_pin_resources", + "g_pin_resources['__location0__' if validation_result else ''] = 3", "g_pin_resources.pop('', None)", - "g_pin_resources['__location1__' if pin_result else ''] = 3", + "g_pin_resources['__location1__' if validation_result else ''] = 3", "g_pin_resources.pop('', None)" ] }, @@ -535,79 +377,56 @@ "__module__" : ["CLK_BUF"], "__equation__" : [ "temp = '__primitive_flags__'.split(',')", - "pin_result = '__location0__' in g_all_clock_pins or 'PIN_CLOCK_CORE_ONLY' in temp" + "validation_result = '__location0__' in g_all_clock_pins or 'PIN_CLOCK_CORE_ONLY' in temp" ] }, "__check_boot_clock_resource__" : { "__module__" : ["BOOT_CLOCK"], "__equation__" : [ - "pin_result = g_boot_clock_resources < MAX_BOOT_CLOCK_RESOURCE", - "g_boot_clock_resources += (1 if pin_result else 0)" + "validation_result = g_boot_clock_resources < MAX_BOOT_CLOCK_RESOURCE", + "g_boot_clock_resources += (1 if validation_result else 0)" ] }, "__pll_clock_pin_is_valid__" : { "__module__" : ["PLL"], "pre_primitive" : "CLK_BUF", "__equation__" : [ - "pin_result = '__location0__' in g_all_pll_clock_pins" + "validation_result = '__location0__' in g_all_pll_clock_pins" ] - } - }, - "__secondary_validation__" : { - "__seqeunce__" : [ - "__check_fabric_clock_resource__", - "__check_data_width_parameter__", - "__check_data_rate_parameter__", - "__check_dpa_mode_parameter__", - "__check_clock_phase_parameter__", - "__check_pll_parameter__", - "__update_fabric_clock_resource__" - ], - "__check_fabric_clock_resource__" : { - "__module__" : ["CLK_BUF", "PLL"], - "__connectivity__" : ["O", "CLK_OUT", "CLK_OUT_DIV2", "CLK_OUT_DIV3", "CLK_OUT_DIV4"], + }, + "__check_input_data_width_parameter__" : { + "__module__" : ["I_SERDES"], + "__parameter__" : ["WIDTH"], "__equation__" : [ - "pin_result = (__connectivity_count__ + g_fabric_clock_resources) <= MAX_FABRIC_CLOCK_RESOURCE" + "validation_result = validate_data_width_parameter('__location__', int('WIDTH'), g_input_gearbox_width)" ] }, - "__check_data_width_parameter__" : { - "__module__" : ["I_SERDES", "O_SERDES"], + "__check_output_data_width_parameter__" : { + "__module__" : ["O_SERDES"], "__parameter__" : ["WIDTH"], "__equation__" : [ - "import re", - "assert '__location__' in g_all_pins", - "m = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', '__location__')", - "assert m != None", - "pn = 'P' if m.group(6) == 'N' else 'N'", - "index = int(m.group(4)) & ~1", - "index += (1 if pn == 'N' else 0)", - "peer_location = 'H%s_%s%s_%d_%s%s' % (m.group(1), m.group(2), m.group(3), index, m.group(5), pn)", - "width = int('WIDTH')", - "pin_result = width >= 3 and width <= (10 if m.group(6) == 'P' else 5)", - "pin_result = pin_result and ((peer_location not in g_gearbox_width) or (g_gearbox_width[peer_location] <= 5 and width <=5))", - "g_gearbox_width['__location__' if pin_result else ''] = width", - "g_gearbox_width.pop('', None)" + "validation_result = validate_data_width_parameter('__location__', int('WIDTH'), g_output_gearbox_width)" ] }, "__check_data_rate_parameter__" : { "__module__" : ["I_SERDES", "O_SERDES", "O_SERDES_CLK"], "__parameter__" : ["DATA_RATE"], "__equation__" : [ - "pin_result = 'DATA_RATE' in ['SDR', 'DDR']" + "validation_result = 'DATA_RATE' in ['SDR', 'DDR']" ] }, "__check_dpa_mode_parameter__" : { "__module__" : ["I_SERDES"], "__parameter__" : ["DPA_MODE"], "__equation__" : [ - "pin_result = 'DPA_MODE' in ['NONE', 'DPA', 'CDR']" + "validation_result = 'DPA_MODE' in ['NONE', 'DPA', 'CDR']" ] }, "__check_clock_phase_parameter__" : { "__module__" : ["O_SERDES_CLK"], "__parameter__" : ["CLOCK_PHASE"], "__equation__" : [ - "pin_result = 'CLOCK_PHASE' in ['0', '90', '180', '270']" + "validation_result = 'CLOCK_PHASE' in ['0', '90', '180', '270']" ] }, "__check_pll_parameter__" : { @@ -619,72 +438,21 @@ "post_div = int('PLL_POST_DIV', 0)", "post_div1 = post_div >> 4", "post_div2 = post_div & 0xF", - "pin_result = (div >= 1 and div <= 63)", - "pin_result = pin_result and (mult >= 16 and mult <= 640)", - "pin_result = pin_result and (post_div1 >= 1 and post_div1 <= 7)", - "pin_result = pin_result and (post_div2 >= 1 and post_div2 <= 7)", - "pin_result = pin_result and (post_div1 >= post_div2)" - ] - }, - "__check_pll_clock_pin_resource__" : { - "__module__" : ["PLL"], - "__equation__" : [ - "pin_result = '__location0__' not in g_pll_resources", - "pin_result = pin_result and len(g_pll_resources) < MAX_PLL_RESOURCE", - "g_pll_resources.append('__location0__' if pin_result else '')", - "g_pll_resources = [pin for pin in g_pll_resources if pin != '']" - ] - }, - "__update_fabric_clock_resource__" : { - "__module__" : ["CLK_BUF", "PLL"], - "__connectivity__" : ["O", "CLK_OUT", "CLK_OUT_DIV2", "CLK_OUT_DIV3", "CLK_OUT_DIV4"], - "__equation__" : [ - "assert ((__connectivity_count__ + g_fabric_clock_resources) <= MAX_FABRIC_CLOCK_RESOURCE)", - "g_fabric_clock_resources += __connectivity_count__" + "validation_result = (div >= 1 and div <= 63)", + "validation_result = validation_result and (mult >= 16 and mult <= 640)", + "validation_result = validation_result and (post_div1 >= 1 and post_div1 <= 7)", + "validation_result = validation_result and (post_div2 >= 1 and post_div2 <= 7)", + "validation_result = validation_result and (post_div1 >= post_div2)" ] } }, "__define__" : { - "parse_location" : { - "__args__" : ["__type__", "__bank__"], - "__equation__" : [ - "import re", - "assert '__location__' in g_all_pins", - "m = re.search(r'H(P|R?)_(\\d?)(|_CC?)_(\\d+?)_(\\d\\d?)(P|N?)', '__location__')", - "__type__ = 'HP' if m.group(1) == 'P' else 'HV'", - "__bank__ = '0' if m.group(2) in ['1', '3'] else '1'" - ] - }, "parse_o_serdes_clk_phase_parameter" : { "__args__" : ["__clock_phase__"], "__equation__" : [ "__clock_phase__ = 'TX_phase_%d' % __argCLOCK_PHASE__" ] }, - "parse_pll_parameter" : { - "__args__" : ["__refdiv__", "__fbdiv__", "__postdiv1__", "__postdiv2__"], - "__equation__" : [ - "__refdiv__ = str(int('__argDIV__', 0))", - "__fbdiv__ = str(int('__argMULT__', 0))", - "__postdiv1__ = str((int('__argPOST_DIV__', 0) >> 4) & 0x7)", - "__postdiv2__ = str((int('__argPOST_DIV__', 0)) & 0x7)" - ] - }, - "parse_pll_root_mux" : { - "__args__" : ["__pll_root_mux_sel__"], - "__equation__" : [ - "__pll_root_mux_sel__ = 32 + (int('__pll_resource__') * 4) + __argIndex__", - "__pll_root_mux_sel__ = '%d' % __pll_root_mux_sel__" - ] - }, - "parse_fabric_clock_buffer_root_mux" : { - "__args__" : ["__fclk_buf_root_mux_sel__"], - "__equation__" : [ - "fabric_clock_buffer_slot = int('__arg1__')", - "__fclk_buf_root_mux_sel__ = (40 + fabric_clock_buffer_slot - 4) if (fabric_clock_buffer_slot >= 4) else (44 + fabric_clock_buffer_slot)", - "__fclk_buf_root_mux_sel__ = '%d' % __fclk_buf_root_mux_sel__" - ] - }, "parse_serdes_width" : { "__args__" : ["__peer_is_on__"], "__equation__" : [ diff --git a/tests/unittest/ModelConfig/apis/routing_configurator.py b/tests/unittest/ModelConfig/apis/routing_configurator.py new file mode 100644 index 000000000..6352357c7 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_configurator.py @@ -0,0 +1,1692 @@ +import argparse +import os +import shlex +import sys +import copy +import re +import json +import threading +import ast +import time + +DIR_IN = 0 +DIR_OUT = 1 +MAX_THREAD = 4 + +def match_string(keyword, strings): + + match = -1 + if keyword.find("partial:") == 0: + keyword = keyword[8:] + assert len(keyword) + for i, s in enumerate(strings): + if s.find(keyword) != -1: + match = i + break + elif keyword.find("RE:") == 0: + keyword = keyword[3:] + keyword = keyword.replace("[", "\[") + keyword = keyword.replace("]", "\]") + expected_match_count = 0 + for replacement in ["(*s*)", "(*d*)"]: + index = keyword.find(replacement) + while index != -1: + expected_match_count += 1 + index = keyword.find(replacement, index + len(replacement)) + if replacement == "(*s*)": + keyword = keyword.replace(replacement, "([-+]?[a-zA-Z0-9_.\[\]]+)") + else: + keyword = keyword.replace(replacement, "([-+]?[0-9]+)") + assert len(keyword) + for i, s in enumerate(strings): + m = re.search(r"%s\n" % keyword, "%s\n" % s) + if m != None and len(m.groups()) == expected_match_count: + match = i + break + else: + if keyword in strings: + match = strings.index(keyword) + else: + match = -1 + return match + +class PORT: + + def __init__(self, bit): + + self.bit = bit + +class CONFIG_BIT: + + def __init__(self, bit): + + self.bit = bit + +class CONFIG_RESULT: + + def __init__(self, feature, instance, bit_name, bit_value): + + self.feature = feature + self.instance = instance + self.bit_name = bit_name + self.bit_value = bit_value + +class DIAGRAM: + + def __init__(self, block_name, instance_name, type, instance): + + self.block_name = block_name + self.instance_name = instance_name + self.type = type + self.instance = instance + self.mapped_edge = {} + assert self.type in ["IN_PORTS", "OUT_PORTS", "BLOCK", "MUX", "NODE"] + self.iport_names = "" + self.oport_names = "" + self.mux_names = "" + if type == "NODE": + self.mapped_edge[instance_name] = instance_name + + def add_ports(self, dir, ports, format): + + assert dir in [DIR_IN, DIR_OUT] + if dir == DIR_IN: + assert self.iport_names == "" + else: + assert self.oport_names == "" + + def update_mapped_edge(edge, bit, name): + + for i in range(bit): + if self.type == "BLOCK": + original_name = "%s->%s%s" % ( + self.instance_name, + name, + "" if bit == 1 else ("[%d]" % i), + ) + else: + original_name = "%s%s" % (name, "" if bit == 1 else ("[%d]" % i)) + assert original_name not in self.mapped_edge + self.mapped_edge[original_name] = edge + + # Create port name + names = ["**INPUT Ports**" if dir == DIR_IN else "**OUTPUT Ports**"] + mapped_names = [] + for name, p in ports.items(): + edge = "edge%d" % len(self.mapped_edge) + if (format & 2) == 0 and name in self.instance.diagram_map: + if self.instance.diagram_map[name] not in mapped_names: + mapped_names.append(self.instance.diagram_map[name]) + names.append("<%s>%s" % (edge, self.instance.diagram_map[name])) + update_mapped_edge(edge, p.bit, name) + else: + if p.bit == 1: + names.append("<%s>%s" % (edge, name)) + else: + names.append("<%s>%s[%d:%d]" % (edge, name, p.bit - 1, 0)) + update_mapped_edge(edge, p.bit, name) + + # Serialize + if dir == DIR_IN: + self.iport_names = "|".join(names) + else: + self.oport_names = "|".join(names) + + def add_mux_input(self, inputs, values, bits): + + assert len(inputs) + assert len(inputs) == len(values) + assert self.iport_names == "" + assert self.mux_names == "" + total_size = 0 + bit_infos = [self.block_name] + msize = 0 + for (b, size) in bits: + total_size += size + bit_infos.append("%s - %dbit(s)" % (b, size)) + assert total_size + dsize = len(str((1 << total_size) - 1)) + names = ["**INPUT Ports**"] + for i, v in zip(inputs, values): + edge = "edge%d" % len(self.mapped_edge) + names.append( + "<%s>%s\\n0b%0*d (%*d)" + % (edge, i, total_size, int(bin(v)[2:]), dsize, v) + ) + names[-1] = names[-1].replace("->", "\\n") + assert i not in self.mapped_edge + self.mapped_edge[i] = edge + self.iport_names = "|".join(names) + self.mux_names = "|".join(bit_infos) + + def add_mux_output(self, output): + + assert len(output) + assert self.oport_names == "" + names = ["**OUTPUT Ports**"] + edge = "edge%d" % len(self.mapped_edge) + names.append("<%s>%s" % (edge, output)) + names[-1] = names[-1].replace("->", "\\n") + assert output not in self.mapped_edge + self.mapped_edge[output] = edge + self.oport_names = "|".join(names) + + def get_node_label(self): + + if self.type == "IN_PORTS": + return "{%s}" % (self.iport_names) + elif self.type == "OUT_PORTS": + return "{%s}" % (self.oport_names) + elif self.type == "BLOCK": + return "{%s} | {%s|%s} | {%s}" % ( + self.iport_names, + self.block_name, + self.instance_name, + self.oport_names, + ) + elif self.type == "MUX": + return "{%s} | {%s} | {%s}" % ( + self.iport_names, + self.mux_names, + self.oport_names, + ) + else: + assert self.type == "NODE" + return self.instance_name + +class BLOCK: + + def __init__(self, name, top): + + self.name = name + self.top = top + self.instantiated = False + self.instance_name = None + self.parent = None + self.id = None + self.in_ports = {} + self.out_ports = {} + self.nodes = [] + self.instances = {} + self.drives = {} + self.sinks = {} + self.mux_drives = {} + self.mux_sinks = {} + self.mux_values = {} + self.mux_bits = {} + self.config_bits = {} + self.mux_drive_selection = {} + self.parameter_primitive_name = None + self.parameter_script = None + self.diagram_map = {} + + def fullname(self, do_not_include_if_not_exist=False): + + if self.parent == None: + assert self.top + if do_not_include_if_not_exist: + return "" + else: + return self.instance_name + else: + assert not self.top + parent_name = self.parent.fullname(do_not_include_if_not_exist) + if len(parent_name): + return "%s.%s" % (parent_name, self.instance_name) + else: + return self.instance_name + + def update_child(self, instances, ignore=False): + + for name, instance in self.instances.items(): + assert instance.instance_name == None or ignore + assert instance.parent == None or ignore + assert instance.id == None or ignore + instance.instance_name = name + instance.parent = self + instance.id = len(instances) + instances.append(instance) + instance.update_child(instances, ignore) + + def check_naming(self, name, support_indexing, feature): + + m = re.search(r"([-+]?[a-zA-Z0-9_]+)", name) + if m != None and len(m.groups()) == 1 and m.group(1) == name: + pass + elif support_indexing: + # Retry + valid = False + index = name.find("[") + if index != -1 and name[-1] == "]": + regular_name = name[:index] + if len(regular_name): + m = re.search(r"([-+]?[a-zA-Z0-9_]+)", regular_name) + if ( + m != None + and len(m.groups()) == 1 + and m.group(1) == regular_name + ): + sub_name = name[index + 1 : -1] + if len(sub_name): + m = re.search(r"([-+]?[0-9]+)", sub_name) + if ( + m != None + and len(m.groups()) == 1 + and m.group(1) == sub_name + ): + valid = True + name = regular_name + if not valid: + raise Exception( + "Invalid %s name %s which should consist character in re format {a-zA-Z0-9_} or {a-zA-Z0-9_}[{0-9}]" + % (feature, name) + ) + else: + raise Exception( + "Invalid %s name %s which should consist character in re format {a-zA-Z0-9_}" + % (feature, name) + ) + return name + + def add_port(self, name, dir, bit): + + assert dir in [DIR_IN, DIR_OUT] + assert bit > 0 + self.check_naming(name, False, "port") + assert name not in self.in_ports, ( + "Port %s had been defined as input port" % name + ) + assert name not in self.out_ports, ( + "Port %s had been defined as ouput port" % name + ) + for n in self.nodes: + n = self.check_naming(n, True, "node") + assert name != n, "Port %s had been defined as node" % name + if dir == DIR_IN: + self.in_ports[name] = PORT(bit) + else: + self.out_ports[name] = PORT(bit) + + def add_node(self, name): + + no_index_name = self.check_naming(name, True, "node") + assert name not in self.in_ports, ( + "Node %s had been defined as input port" % name + ) + assert name not in self.out_ports, ( + "Node %s had been defined as output port" % name + ) + assert name not in self.nodes, "Node %s had been defined as node" % name + assert no_index_name not in self.in_ports, ( + "Node %s had been defined as input port" % no_index_name + ) + assert no_index_name not in self.out_ports, ( + "Node %s had been defined as output port" % no_index_name + ) + assert no_index_name not in self.nodes, ( + "Node %s had been defined as node" % no_index_name + ) + self.nodes.append(name) + + def add_instance(self, name, block): + + self.check_naming(name, True, "instance") + assert name not in self.instances, "Block %s already has instance named %s" % ( + self.name, + name, + ) + assert isinstance(block, BLOCK) + self.instances[name] = block + + def check_connection_bit(self, is_input, connection): + + if connection in self.nodes: + return connection + else: + assert is_input in [None, False, True] + m = re.search(r"([-+]?[a-zA-Z0-9_]+)\[([-+]?[0-9]+)\]", connection) + if m != None: + assert len(m.groups()) == 2 + name = m.group(1) + bit = int(m.group(2)) + else: + name = connection + bit = None + if is_input == None: + assert ( + name in self.in_ports or name in self.out_ports + ), "Block %s does not have input/output port named %s" % ( + self.name, + name, + ) + if name in self.in_ports: + bits = self.in_ports[name] + else: + bits = self.out_ports[name] + elif is_input == True: + assert ( + name in self.in_ports + ), "Block %s does not have input port named %s" % (self.name, name) + bits = self.in_ports[name] + else: + assert is_input == False + assert ( + name in self.out_ports + ), "Block %s does not have output port named %s" % (self.name, name) + bits = self.out_ports[name] + assert (bit == None and bits.bit == 1) or ( + bit != None and bit < bits.bit + ), ( + "Block %s port %s is %d bit(s), connection should be made bit by bit or within valid bit range" + % (self.name, name, bits.bit) + ) + if bits.bit == 1: + # Always return no [] + return name + else: + return connection + + def get_connection_info(self, connection): + + instance = None + port = None + assert isinstance(connection, str) + cons = connection.split("->") + assert len(cons) in [1, 2] + if len(cons) == 1: + # This is a pin + port = cons[0] + instance = self + else: + # This is instance + if cons[0] == self.fullname(): + instance = self + elif cons[0] in self.instances: + instance = self.instances[cons[0]] + elif self.parent != None and cons[0] == self.parent.fullname(): + instance = self.parent + else: + for inst in self.instances: + if self.instances[inst].fullname() == cons[0]: + instance = self.instances[inst] + break + if instance == None and self.parent != None: + for inst in self.parent.instances: + if self.parent.instances[inst].fullname() == cons[0]: + instance = self.parent.instances[inst] + break + assert ( + instance != None + ), "Block %s (%s) does not have instance named %s" % ( + self.name, + self.fullname(), + cons[0], + ) + port = cons[1] + assert isinstance(instance, BLOCK) + port = instance.check_connection_bit(None, port) + return [instance, port] + + def check_connection(self, connection, is_drive): + + assert isinstance(connection, str) + cons = connection.split("->") + assert len(cons) in [1, 2] + if len(cons) == 1: + # This is a pin + return self.check_connection_bit(is_drive, cons[0]) + else: + # This is instance + # Node is not accessible by instance + assert cons[0] in self.instances, ( + "Instance %s does not exist to make connection" % cons[0] + ) + instance = self.instances[cons[0]] + assert ( + cons[1] not in instance.nodes + ), "Block %s (any block) should not access instance %s node %s" % ( + self.name, + cons[0], + cons[1], + ) + return "%s->%s" % ( + cons[0], + instance.check_connection_bit(not is_drive, cons[1]), + ) + + def add_connection(self, source, destinations): + + # Pin [input] -> Instance [input] + # Instance [output] -> Instance [input] + # Instance [output] -> Pin [output] + # Pin [input] -> Pin [output] + for i in range(len(destinations)): + assert ( + destinations[i] not in self.nodes + ), "Block %s (any block) does not support add connection to a node %s" % ( + self.name, + destinations[i], + ) + destinations[i] = self.check_connection(destinations[i], False) + assert ( + source not in self.nodes + ), "Block %s (any block) does not support add connection from a node %s" % ( + self.name, + source, + ) + source = self.check_connection(source, True) + # assert source not in self.drives, "Block %s driving source %s connection had been made" % (self.name, source) + if source in self.drives: + for dest in destinations: + assert ( + dest not in self.drives[source] + ), "Block %s driving source %s already drive %s" % ( + self.name, + source, + dest, + ) + self.drives[source].append(dest) + else: + self.drives[source] = destinations + for dest in destinations: + dest = self.check_connection(dest, False) + assert ( + dest not in self.sinks + ), "Block %s sink destination %s connection had been made" % ( + self.name, + dest, + ) + self.sinks[dest] = source + + def add_config_mux(self, out, selection, bits): + + out = self.check_connection(out, False) + assert ( + out not in self.mux_sinks + ), "Block %s mux sink destination %s connection had been made" % ( + self.name, + out, + ) + assert out not in self.mux_values, "Block %s mux value %s had been defined" % ( + self.name, + out, + ) + assert out not in self.mux_bits, "Block %s mux bits %s had been defined" % ( + self.name, + out, + ) + self.mux_sinks[out] = [] + self.mux_values[out] = [] + self.mux_bits[out] = [] + total_bits = 0 + bit_names = [] + for bit in bits: + for b, size in bit.items(): + self.check_naming(b, True, "mux-bit") + assert ( + b not in bit_names + ), "Block %s configuration bits %s had been defined" % (self.name, b) + if b in self.config_bits: + assert self.config_bits[b].bit == size, ( + "Block %s configuration bits %s has conflict bit size definition (%d defined vs %d defining)" + % (self.name, b, self.config_bits[b].bit, size) + ) + else: + self.config_bits[b] = CONFIG_BIT(size) + bit_names.append(b) + total_bits += size + for value, drive in selection.items(): + drive = self.check_connection(drive, True) + assert value < (1 << total_bits), ( + "Block %s configuration mux %s selection value 0x%X (%d) (drive: %s) is out of range (bit-size=%d)" + % (self.name, out, value, value, drive, total_bits) + ) + if drive not in self.mux_drives: + self.mux_drives[drive] = [] + assert out not in self.mux_drives[drive] + self.mux_drives[drive].append(out) + self.mux_sinks[out].append(drive) + self.mux_values[out].append(value) + # bits + values = {} + index = 0 + for bit in bits: + for b, size in bit.items(): + v = (value >> index) & ((1 << size) - 1) + index += size + values[b] = str(v) + drive_path = "%s | %s" % (drive, out) + assert drive_path not in self.mux_drive_selection + self.mux_drive_selection[drive_path] = values + for bit in bits: + for b, size in bit.items(): + self.mux_bits[out].append([b, size]) + + def add_parameter(self, primitive_name, script): + + assert self.parameter_primitive_name == None + assert self.parameter_script == None + self.parameter_primitive_name = primitive_name + self.parameter_script = script + + def add_diagram_map(self, name, mapped_name): + + assert name not in self.diagram_map + assert name in self.in_ports or name in self.out_ports + self.diagram_map[name] = mapped_name + + def recursive_query( + self, + start_node, + paths, + configs, + end_node=None, + filters=None, + path=[], + config=[None], + ): + + instance_node = "%s->%s" % (self.instance_name, start_node) + full_instance_node = "%s->%s" % (self.fullname(), start_node) + path = list(path) + path.append(full_instance_node) + if filters != None: + assert isinstance(filters, list) + for f in filters: + assert isinstance(f, str) and len(f) > 0 + if match_string(f, [full_instance_node]) != -1: + return + if end_node != None and match_string(end_node, [full_instance_node]) != -1: + paths.append(path) + configs.append(config) + return + found = False + if start_node in self.drives: + for dest in self.drives[start_node]: + (instance, port) = self.get_connection_info(dest) + instance.recursive_query( + port, paths, configs, end_node, filters, path, config + [None] + ) + found = True + if self.parent != None and instance_node in self.parent.drives: + for dest in self.parent.drives[instance_node]: + (instance, port) = self.parent.get_connection_info(dest) + instance.recursive_query( + port, paths, configs, end_node, filters, path, config + [None] + ) + found = True + if start_node in self.mux_drives: + for dest in self.mux_drives[start_node]: + (instance, port) = self.get_connection_info(dest) + c = "%s | %s" % (start_node, dest) + assert c in self.mux_drive_selection + c = self.mux_drive_selection[c] + instance.recursive_query( + port, + paths, + configs, + end_node, + filters, + path, + config + [{self.fullname(True): c}], + ) + found = True + if self.parent != None and instance_node in self.parent.mux_drives: + for dest in self.parent.mux_drives[instance_node]: + (instance, port) = self.parent.get_connection_info(dest) + c = "%s | %s" % (instance_node, dest) + assert c in self.parent.mux_drive_selection + c = self.parent.mux_drive_selection[c] + instance.recursive_query( + port, + paths, + configs, + end_node, + filters, + path, + config + [{self.parent.fullname(True): c}], + ) + found = True + if not found: + paths.append(path) + configs.append(config) + + def query(self, start_node, end_node=None, filters=None): + + assert end_node == None or (isinstance(end_node, str) and len(end_node) > 0) + assert filters == None or (isinstance(filters, list)) + potential_paths = [] + potential_configs = [] + paths = [] + configs = [] + start_node = self.check_connection(start_node, True) + self.recursive_query( + start_node, potential_paths, potential_configs, end_node, filters + ) + assert isinstance(potential_paths, list) + assert isinstance(potential_configs, list) + assert len(potential_paths) == len(potential_configs) + for p, c in zip(potential_paths, potential_configs): + assert isinstance(p, list) + assert isinstance(c, list) + assert len(p) + assert len(p) == len(c) + if end_node != None: + if match_string(end_node, [p[-1]]) != -1: + paths.append(p) + configs.append(c) + else: + paths.append(p) + configs.append(c) + return [paths, configs] + + def graph_diagram(self, graph, format): + def get_edge(diagrams, is_self_connection, instance_name, connection, is_mux): + + if is_self_connection: + name = connection + else: + name = "%s->%s" % (instance_name, connection) + edge = "" + for diagram in diagrams: + if ( + is_mux + and diagram.type == "MUX" + and diagram.instance_name == instance_name + ) or (not is_mux and diagram.type != "MUX"): + if name in diagram.mapped_edge: + if diagram.type == "NODE": + edge = "%s" % (diagram.instance_name) + else: + edge = "%s:%s" % ( + diagram.instance_name, + diagram.mapped_edge[name], + ) + break + return edge + + def make_mux_connection( + connections, connection_pairs, diagrams, mux_name, connection, m2b + ): + + mux_edge = get_edge(diagrams, True, mux_name, connection, True) + assert len(mux_edge) + inst, connection = self.get_connection_info(connection) + edge = get_edge( + diagrams, inst == self, inst.instance_name, connection, False + ) + if len(edge): + if m2b: + connection_name = "%s + %s" % (mux_edge, edge) + else: + connection_name = "%s + %s" % (edge, mux_edge) + if connection_name not in connections: + connection_pairs.append( + [mux_edge, edge] if m2b else [edge, mux_edge] + ) + connections.append(connection_name) + + graph.rankdir = "LR" + diagrams = [] + # We must have input ports + assert len(self.in_ports) + diagrams.append(DIAGRAM(self.name, "@in", "IN_PORTS", self)) + diagrams[-1].add_ports(DIR_IN, self.in_ports, format) + + # Add instance as "BLOCK" + for inst_name, instance in self.instances.items(): + diagrams.append(DIAGRAM(instance.name, inst_name, "BLOCK", instance)) + diagrams[-1].add_ports(DIR_IN, instance.in_ports, format) + diagrams[-1].add_ports(DIR_OUT, instance.out_ports, format) + + mux_names = {} + for out, selections in self.mux_sinks.items(): + assert len(selections) == len(self.mux_values[out]) + name = "@mux%d" % len(mux_names) + mux_names[out] = name + diagrams.append(DIAGRAM("MUX", name, "MUX", self)) + diagrams[-1].add_mux_input( + selections, self.mux_values[out], self.mux_bits[out] + ) + diagrams[-1].add_mux_output(out) + + for node in self.nodes: + diagrams.append(DIAGRAM("NODE", node, "NODE", self)) + + # Not neccessary for output ports + diagrams.append(DIAGRAM(self.name, "@out", "OUT_PORTS", self)) + diagrams[-1].add_ports(DIR_OUT, self.out_ports, format) + + for diagram in diagrams: + graph.node( + diagram.instance_name, + label=diagram.get_node_label(), + shape=("circle" if diagram.type == "NODE" else "record"), + ) + + connections = [] + connection_pairs = [] + for src, destinations in self.drives.items(): + inst, connection = self.get_connection_info(src) + src_edge = get_edge( + diagrams, inst == self, inst.instance_name, connection, False + ) + if len(src_edge): + for destination in destinations: + inst, connection = self.get_connection_info(destination) + dest_edge = get_edge( + diagrams, inst == self, inst.instance_name, connection, False + ) + if len(dest_edge): + connection_name = "%s + %s" % (src_edge, dest_edge) + if connection_name not in connections: + connection_pairs.append([src_edge, dest_edge]) + connections.append(connection_name) + + for out, selections in self.mux_sinks.items(): + make_mux_connection( + connections, connection_pairs, diagrams, mux_names[out], out, True + ) + if len(selections) <= 10 or (format & 4) != 0: + for s in selections: + make_mux_connection( + connections, + connection_pairs, + diagrams, + mux_names[out], + s, + False, + ) + + # RGB + if len(connection_pairs): + color_groups = (len(connection_pairs) + 7) // 8 + color_step = int(((255 + color_groups - 1) / color_groups) * 0.8) + lcolor = 0 + ccolor = color_step + for i, pair in enumerate(connection_pairs): + rcolor = ccolor if (i & 1) else lcolor + gcolor = ccolor if (i & 2) else lcolor + bcolor = ccolor if (i & 4) else lcolor + color = "#%02X%02X%02X" % (rcolor, gcolor, bcolor) + graph.edge(pair[0], pair[1], color=color) + if (i % 8) == 7: + lcolor += color_step // 2 + ccolor += color_step + +class PathFinderThread(threading.Thread): + + def __init__(self, configurator, routing): + + threading.Thread.__init__(self) + self.configurator = configurator + self.routing = routing + self.paths = None + self.configs = None + self.status = False + self.error_msg = "" + self.parameters = {} + self.defined_parameters = {} + + def run(self): + + assert "feature" in self.routing + assert "source" in self.routing + assert "destinations" in self.routing + assert "flags" in self.routing + assert "filters" in self.routing + assert "parameters" in self.routing + feature = self.routing["feature"] + src = self.routing["source"] + dests = self.routing["destinations"] + flags = self.routing["flags"] + filters = self.routing["filters"] + parameters = self.routing["parameters"] + assert self.configurator.top_block != None + assert isinstance(src, str) and len(src) + assert isinstance(dests, list) + assert isinstance(flags, list) + assert isinstance(filters, list) + (src, self.error_msg) = self.configurator.validate_node(src, True) + if len(self.error_msg) == 0: + self.routing["source"] = src + for i, dest in enumerate(dests): + assert isinstance(dest, str) and len(dest) + (dests[i], self.error_msg) = self.configurator.validate_node( + dests[i], False + ) + if len(self.error_msg): + break + if len(self.error_msg) == 0: + self.routing["destinations"] = dests + for flag in flags: + assert isinstance(flag, str) and len(flag) + for filter in filters: + assert isinstance(filter, str) and len(filter) + assert src not in dests + (self.paths, self.configs) = self.configurator.query( + src, None if len(dests) == 0 else dests[-1], filters + ) + self.apply_parameters(parameters) + self.configurator.validate_paths_and_configs(self.paths, self.configs) + ( + self.paths, + self.configs, + ) = self.configurator.confirm_intermediate_path( + self.paths, self.configs, dests[:-1] + ) + (self.paths, self.configs) = self.configurator.apply_flag( + self.paths, self.configs, flags + ) + self.status = True + + def filter(self, update_routing): + + assert self.paths != None and self.configs != None + (self.paths, self.configs) = self.configurator.filter_used_path( + self.routing["feature"], self.paths, self.configs, self.routing["msgs"] + ) + if update_routing: + self.routing["potential paths"] = self.paths + + def apply_parameters(self, parameters): + + assert isinstance(parameters, dict) + if len(parameters): + for path, config in zip(self.paths, self.configs): + applied_block = [] + for i in range(len(path)): + ps = path[i].split("->") + assert len(ps) == 2 + for inst in self.configurator.instances: + if ( + inst.fullname() == ps[0] + and inst.parameter_primitive_name != None + and inst.parameter_script != None + and inst.parameter_primitive_name in parameters + and inst.name not in applied_block + ): + self.parameters = parameters[inst.parameter_primitive_name] + self.defined_parameters = {} + exec(inst.parameter_script) + if config[i] == None: + config[i] = {} + inst_name = inst.fullname(True) + if inst_name not in config[i]: + config[i][inst_name] = {} + for p, v in self.defined_parameters.items(): + assert isinstance(p, (str, int)) and len(p) + assert isinstance(v, (str, int)) + if isinstance(v, int): + v = str(v) + assert len(v) + if p not in config[i][inst_name]: + config[i][inst_name][p] = v + else: + assert config[i][inst_name][p] == v + applied_block.append(inst.name) + break + +class CONFIGURATOR: + + def __init__(self, top_model_file, enable_tcl_map, debug_level, is_external): + + self.top_model_file = top_model_file + assert os.path.exists(self.top_model_file), ( + "Model file %s must exist" % self.top_model_file + ) + self.enable_tcl_map = enable_tcl_map + self.debug_level = debug_level + self.is_external = is_external + self.top_directory = os.path.dirname(os.path.abspath(self.top_model_file)) + if self.top_directory not in sys.path: + sys.path.insert(0, self.top_directory) + self.sub_directories = [] + self.top_model_file_md5 = None + self.models_md5 = [] + self.current_model_md5 = None + self.current_block = None + self.top_block = None + self.blocks = [] + self.instances = [] + self.config_results = {} + self.tcl_map = {} + self.print_info(1, 0, "Top model file: %s" % self.top_model_file) + self.load_model_file(self.top_model_file) + + def reset_config_results(self): + + self.config_results = {} + + def print_info(self, level, space, msg): + + if level <= self.debug_level: + + assert space >= 0 + spacing = "" + while space != 0: + spacing += " " + space -= 1 + print("INFO : %s%s" % (spacing, msg)) + + def print_warning(self, msg): + + if self.is_external: + print("WARNING: %s" % msg) + + def load_model_file(self, file): + + def load_model(file): + self.load_model_file(file) + + def create_block(name, top=False): + self.create_block(name, top) + + def add_port(name, dir, bit=1, parent=None): + self.add_port(name, dir, bit, parent) + + def add_node(name, parent=None): + self.add_node(name, parent) + + def add_instance(name, block, parent=None): + self.add_instance(name, block, parent) + + def add_connection(source, destinations, parent=None): + self.add_connection(source, destinations, parent) + + def add_config_mux(out, selection, bits, parent=None): + self.add_config_mux(out, selection, bits, parent) + + def add_parameter(primitive_name, script, parent=None): + self.add_parameter(primitive_name, script, parent) + + def add_tcl_map(name, tcl_name): + self.add_tcl_map(name, tcl_name) + + def add_diagram_map(name, mapped_name, parent=None): + self.add_diagram_map(name, mapped_name, parent) + + assert isinstance(file, str) and len(file) + if os.path.exists(file): + pass + else: + found = False + tested_file = [file] + search_directories = [self.top_directory] + self.sub_directories + for directory in search_directories: + relative_file = "%s/%s" % (directory, file) + relative_file = relative_file.replace("\\", "/") + while relative_file.find("//") != -1: + relative_file = relative_file.replace("//", "/") + if os.path.exists(relative_file): + file = relative_file + found = True + break + elif relative_file not in tested_file: + tested_file.append(relative_file) + if not found: + raise Exception("Model file(s) (%s) does not exist" % (tested_file)) + current_dir = os.path.dirname(os.path.abspath(file)) + if current_dir != self.top_directory and current_dir not in self.sub_directories: + self.sub_directories.append(current_dir) + self.print_info(1, 1, "Load model file: %s" % file) + # Original intention is to use md5 but it does not work for msys2 + # Fullpath will work too + # hashlib.sha256(open(file, "rb").read()).hexdigest() + md5 = os.path.abspath(file) + if self.top_model_file_md5 == None: + assert len(self.models_md5) == 0 + assert self.current_model_md5 == None + self.top_model_file_md5 = md5 + self.current_model_md5 = md5 + exec(open(file).read()) + self.set_top() + elif self.current_model_md5 == md5: + raise Exception("Illegal to self-load model file %s" % file) + elif md5 in self.models_md5: + self.print_warning("Model file %s had been loaded. Skip" % file) + else: + assert md5 != self.top_model_file_md5, ( + "Illegal to load top model file %s more than once" % file + ) + self.models_md5.append(md5) + backup_md5 = self.current_model_md5 + self.current_model_md5 = md5 + exec(open(file).read()) + self.current_model_md5 = backup_md5 + + def create_block(self, name, top): + + assert isinstance(name, str) and len(name) + assert isinstance(top, bool) + self.print_info(1, 2, "Create block %s (Top:%r)" % (name, top)) + assert len(name) + self.curret_block = None + for block in self.blocks: + if block.name == name: + raise Exception("Block %s had already been created" % name) + else: + assert not top or not block.top, ( + "Block %s already has been set as top module, cannot set block %s as top module" + % (block.name, name) + ) + if self.curret_block == None: + self.current_block = BLOCK(name, top) + self.blocks.append(self.current_block) + + def get_current_block(self, parent): + + assert self.current_block != None, "No block is created" + if parent != None: + self.current_block = None + for block in self.blocks: + if block.name == parent: + self.current_block = block + break + assert self.current_block == None, ( + "Specified parent %s does not exist" % parent + ) + self.print_info( + 2, 1, "Switch the current block to %s" % self.current_block.name + ) + + def set_top(self): + + assert self.top_block == None + assert len(self.instances) == 0 + for b in self.blocks: + if b.top: + assert self.top_block == None + assert not b.instantiated + self.top_block = b + assert self.top_block != None, "Not top block is set" + assert self.top_block.instance_name == None + assert self.top_block.id == None + self.top_block.instance_name = self.top_block.name + self.top_block.id = len(self.instances) + self.instances.append(self.top_block) + self.top_block.update_child(self.instances) + assert self.top_block.parent == None + assert self.top_block.fullname(True) == "" + assert self.top_block.fullname() == self.top_block.instance_name + + def copy_block(self, name): + + block = None + for b in self.blocks: + if b.name == name: + b.instantiated = True + block = copy.deepcopy(b) + break + assert block != None, "Could not find block %s" % (name) + return block + + def add_port(self, name, dir, bit, parent): + + assert isinstance(name, str) and len(name) + assert isinstance(bit, int) and bit > 0 + assert dir in [DIR_IN, DIR_OUT] + assert parent == None or (isinstance(parent, str) and len(parent)) + self.get_current_block(parent) + self.print_info(2, 3, "Add port %s" % name) + assert not self.current_block.instantiated, ( + "Block %s had instantiated, it is illegal to add more port" + % self.current_block.name + ) + self.current_block.add_port(name, dir, bit) + + def add_node(self, name, parent): + + assert isinstance(name, str) and len(name) + assert parent == None or (isinstance(parent, str) and len(parent)) + self.get_current_block(parent) + self.print_info(2, 3, "Add node %s" % name) + assert not self.current_block.instantiated, ( + "Block %s had instantiated, it is illegal to add more node" + % self.current_block.name + ) + self.current_block.add_node(name) + + def add_instance(self, name, block, parent): + + assert isinstance(name, str) and len(name) + assert isinstance(block, str) and len(block) + assert parent == None or (isinstance(parent, str) and len(parent)) + self.get_current_block(parent) + self.print_info(2, 3, "Add block %s as instance %s" % (block, name)) + assert not self.current_block.instantiated, ( + "Block %s had instantiated, it is illegal to add more instance" + % self.current_block.name + ) + block = self.copy_block(block) + assert isinstance(block, BLOCK) + self.current_block.add_instance(name, block) + + def add_connection(self, source, destinations, parent): + + assert isinstance(source, str) + assert isinstance(destinations, list) and len(destinations) > 0 + for dest in destinations: + assert isinstance(dest, str) + assert parent == None or (isinstance(parent, str) and len(parent)) + self.get_current_block(parent) + self.print_info( + 3, 2, "Add connection: source=%s, destinations=%s" % (source, destinations) + ) + self.current_block.add_connection(source, destinations) + + def add_config_mux(self, out, selection, bits, parent): + + assert isinstance(out, str) and len(out) + assert isinstance(selection, dict) and len(selection) + for value, drive in selection.items(): + assert isinstance(value, int) + assert isinstance(drive, str) + assert isinstance(bits, list) and len(bits) + for bit in bits: + assert isinstance(bit, dict) and len(bit) == 1 + for b, size in bit.items(): + assert isinstance(b, str) + assert isinstance(size, int) and size > 0 + assert parent == None or (isinstance(parent, str) and len(parent)) + self.get_current_block(parent) + self.print_info(2, 3, "Add configuration mux for %s" % (out)) + self.current_block.add_config_mux(out, selection, bits) + + def add_parameter(self, primitive_name, script, parent): + + assert isinstance(primitive_name, str) and len(primitive_name) + assert isinstance(script, str) and len(script) + assert parent == None or (isinstance(parent, str) and len(parent)) + self.get_current_block(parent) + self.print_info(2, 3, "Add parameter") + self.current_block.add_parameter(primitive_name, script) + + def add_tcl_map(self, name, tcl_name): + + assert isinstance(name, str) and len(name) + assert isinstance(tcl_name, str) and len(tcl_name) + assert name not in self.tcl_map, "Duplicated tcl map: %s" % name + self.tcl_map[name] = tcl_name + + def add_diagram_map(self, name, mapped_name, parent): + + assert isinstance(name, str) and len(name) + assert isinstance(mapped_name, str) and len(mapped_name) + assert parent == None or (isinstance(parent, str) and len(parent)) + self.get_current_block(parent) + self.current_block.add_diagram_map(name, mapped_name) + + def get_instance_and_node(self, node): + + block = None + cons = node.split("->") + if len(cons) == 1: + # No instance name, so it is top + block = self.top_block + else: + assert len(cons) == 2 + # There is instance + for instance in self.instances: + if cons[0] == instance.fullname() or cons[0] == instance.fullname(True): + block = instance + break + assert block != None, "Instance name %s does not exist" % cons[0] + node = cons[1] + return [block, node] + + def validate_node(self, node, is_source): + + assert not is_source or (node.find("partial:") != 0 and node.find("RE:") != 0) + if node.find("partial:") == 0 or node.find("RE:") == 0: + pass + else: + try: + cons = node.split("->") + assert len(cons) in [1, 2] + if len(cons) == 1: + node = "%s->%s" % ( + self.top_block.name, + self.top_block.check_connection_bit( + True if is_source else None, cons[0] + ), + ) + elif len(cons) == 2: + status = False + for instance in self.instances: + if cons[0] == instance.fullname() or cons[ + 0 + ] == instance.fullname(True): + status = True + node = "%s->%s" % (instance.fullname(), cons[1]) + break + if not status: + count = 0 + fullname = "" + for instance in self.instances: + if cons[0] == instance.instance_name: + count += 1 + fullname = instance.fullname() + if count == 1: + node = "%s->%s" % (fullname, cons[1]) + elif count == 0: + raise Exception("Instance name %s is invalid" % cons[0]) + else: + raise Exception( + "There are more than one instance with name %s, please use more detail name" + % cons[0] + ) + except AssertionError as msg: + msg = str(msg) + assert len(msg) + return [node, msg] + except Exception as error: + return [node, "Exception: %s: %s" % (type(error).__name__, str(error))] + return [node, ""] + + def query(self, node, dest, filters): + + assert self.top_block != None + assert isinstance(node, str) + assert dest == None or isinstance(dest, str) + (block, node) = self.get_instance_and_node(node) + (paths, configs) = block.query(node, dest, filters) + return [paths, configs] + + def validate_paths_and_configs(self, paths, configs): + + assert isinstance(paths, list) + assert isinstance(configs, list) + for p, c in zip(paths, configs): + assert isinstance(p, list) + assert isinstance(c, list) + assert len(p) == len(c) + + def finalize_path(self, paths, configs, routing): + + assert isinstance(paths, list) + assert isinstance(configs, list) + assert len(paths) + assert len(paths) == len(configs) + for config in configs: + if config != None: + assert isinstance(config, dict), config + assert len(config) == 1 + for instance, muxes in config.items(): + for mux, value in muxes.items(): + imux = "%s->%s" % (instance, mux) + if imux in self.config_results: + assert self.config_results[imux].bit_value == value + else: + self.config_results[imux] = CONFIG_RESULT( + routing["feature"], instance, mux, value + ) + + def confirm_intermediate_path( + self, potential_paths, potential_configs, intermediate_paths + ): + + self.validate_paths_and_configs(potential_paths, potential_configs) + assert isinstance(intermediate_paths, list) + paths = [] + configs = [] + for path, config in zip(potential_paths, potential_configs): + count = 0 + for ip in intermediate_paths: + if match_string(ip, path) != -1: + count += 1 + if count == len(intermediate_paths): + paths.append(path) + configs.append(config) + return [paths, configs] + + def apply_flag(self, potential_paths, potential_configs, flags): + + self.validate_paths_and_configs(potential_paths, potential_configs) + if len(potential_paths) > 0 and "shortest path" in flags: + for flag in flags: + if flag == "shortest path": + shortest_path = len(potential_paths[0]) + paths = [] + configs = [] + for path, config in zip(potential_paths, potential_configs): + if len(path) < shortest_path: + shortest_path = len(path) + for path, config in zip(potential_paths, potential_configs): + if len(path) == shortest_path: + paths.append(path) + configs.append(config) + # Update for next flag if we need to support more + potential_paths = paths + patontial_configs = configs + else: + paths = potential_paths + configs = potential_configs + return [paths, configs] + + def filter_used_path(self, feature, potential_paths, potential_configs, msgs): + + self.validate_paths_and_configs(potential_paths, potential_configs) + paths = [] + configs = [] + for path, config in zip(potential_paths, potential_configs): + conflict = False + for c in config: + if c != None: + assert isinstance(c, dict) + assert len(c) == 1 + for instance, muxes in c.items(): + for mux, value in muxes.items(): + imux = "%s->%s" % (instance, mux) + if imux in self.config_results: + if self.config_results[imux].bit_value != value: + msgs.append( + "'%s' had conflict to set config mux %s to value %s, had been set with value %s by '%s'" + % ( + feature, + imux, + value, + self.config_results[imux].bit_value, + self.config_results[imux].feature, + ) + ) + conflict = True + break + if conflict: + break + if conflict: + break + if not conflict: + paths.append(path) + configs.append(config) + return [paths, configs] + + def find_path(self, routing): + + thread = PathFinderThread(self, routing) + thread.start() + thread.join() + # thread.filter(True) + return [thread.status, thread.error_msg, thread.paths, thread.configs] + + def finalize_config_mux(self, config_mux): + + assert isinstance(config_mux, list) + assert len(config_mux) + if self.enable_tcl_map: + tcl_config_mux = [] + muxed = False + for config in config_mux: + if config != None: + tcl_config = {} + assert isinstance(config, dict) + assert len(config) + for module, bits in config.items(): + assert isinstance(bits, dict) + for bit, value in bits.items(): + assert module.find("->") == -1 + assert bit.find("->") == -1 + name = "%s->%s" % (module, bit) + for p, t in self.tcl_map.items(): + name = name.replace(p, t) + names = name.split("->") + assert len(names) == 2 + if names[0] not in tcl_config: + tcl_config[names[0]] = {} + tcl_config[names[0]][names[1]] = value + muxed = True + tcl_config_mux.append(tcl_config) + else: + tcl_config_mux.append(None) + assert muxed + return tcl_config_mux + else: + return config_mux + + def solve_routings(self, path_file, clean): + + assert os.path.exists(path_file), "Routing JSON %s does not exist" % path_file + file = open(path_file) + routings = json.load(file) + file.close() + assert isinstance(routings, list) and len(routings) + # Reset + restart_routings = [] + for routing in routings: + assert isinstance(routing, dict) + temp = {} + for key in [ + "feature", + "comments", + "source", + "destinations", + "filters", + "flags", + "parameters", + ]: + if key in routing: + temp[key] = routing[key] + elif key in ["feature"]: + temp[key] = "NOT-provided" + elif key in ["comments", "filters", "flags"]: + temp[key] = [] + elif key in ["parameters"]: + temp[key] = {} + restart_routings.append(temp) + routings = restart_routings + if clean == None or clean == False: + threads = [] + running_threads = [] + for routing in routings: + assert isinstance(routing, dict) + assert "feature" in routing + assert "source" in routing + assert "destinations" in routing + assert "filters" in routing + assert "flags" in routing + routing["msgs"] = [] + thread = PathFinderThread(self, routing) + thread.start() + running_threads.append(thread) + if len(running_threads) == MAX_THREAD: + running_threads[0].join() + threads.append(running_threads[0]) + running_threads.pop(0) + while len(running_threads): + running_threads[0].join() + threads.append(running_threads[0]) + running_threads.pop(0) + assert len(routings) == len(threads) + for force in [False, True]: + for thread in threads: + if "status" not in thread.routing: + if thread.status: + thread.filter(not force) + if len(thread.paths) == 0: + thread.routing["msgs"].append( + "Fail to find any paths %s round" + % ("first" if force == False else "second") + ) + thread.routing["config mux"] = [] + thread.routing["status"] = False + elif len(thread.paths) == 1: + self.validate_paths_and_configs( + thread.paths, thread.configs + ) + self.finalize_path( + thread.paths[0], thread.configs[0], thread.routing + ) + thread.routing["config mux"] = self.finalize_config_mux( + thread.configs[0] + ) + thread.routing["status"] = True + elif force: + assert "potential paths" in thread.routing + assert len(thread.routing["potential paths"]) + index = -1 + for i, paths in enumerate( + thread.routing["potential paths"] + ): + if len(paths) == len(thread.paths[0]): + found = True + for p0, p1 in zip(paths, thread.paths[0]): + if p0 != p1: + found = False + break + if found: + index = i + break + assert index != -1 + thread.routing["msgs"].append( + "Force to use first valid path at index #%d" % index + ) + self.finalize_path( + thread.paths[0], thread.configs[0], thread.routing + ) + thread.routing["config mux"] = self.finalize_config_mux( + thread.configs[0] + ) + thread.routing["status"] = True + else: + # There is an error + if len(thread.error_msg): + thread.routing["msgs"].append(thread.error_msg) + else: + thread.routing["msgs"].append("Unknown error in finding path") + thread.routing["potential paths"] = [] + thread.routing["config mux"] = [] + thread.routing["status"] = False + file = open(path_file, "w") + json.dump(routings, file, indent=2) + file.close() + + def solve_routing(self, commands): + + assert isinstance(commands, list) and len(commands) + query_parser = argparse.ArgumentParser( + prog="Configuration Modeler Query", + description="Query Configuration Modeler", + ) + query_parser.add_argument( + "--source", type=str, required=True, help="Source node" + ) + query_parser.add_argument( + "--destinations", type=str, help="Destination nodes seperated by comma" + ) + query_parser.add_argument( + "--filters", type=str, help="Filters seperated by comma" + ) + query_parser.add_argument( + "--parameters", type=str, help="Parameters dictionary text" + ) + query_parser.add_argument("--flags", type=str, help="Flags seperated by comma") + args = query_parser.parse_args(commands) + self.reset_config_results() + routing = {"feature": "Query", "source": args.source} + if args.destinations != None: + routing["destinations"] = args.destinations.split(",") + else: + routing["destinations"] = [] + if args.filters != None: + routing["filters"] = args.filters.split(",") + else: + routing["filters"] = [] + if args.flags != None: + routing["flags"] = args.flags.split(",") + else: + routing["flags"] = [] + if args.parameters != None: + routing["parameters"] = ast.literal_eval(args.parameters) + assert isinstance(routing["parameters"], dict) + else: + routing["parameters"] = {} + routing["msgs"] = [] + (status, error_msg, paths, configs) = self.find_path(routing) + if status: + self.validate_paths_and_configs(paths, configs) + self.print_info(0, 0, "Messages:") + for i, msg in enumerate(routing["msgs"]): + self.print_info(0, 1, "%d) %s" % (i, msg)) + self.print_info(0, 0, "Potential Paths:") + for i, (path, config) in enumerate(zip(paths, configs)): + max = 0 + for p in path: + if len(p) > max: + max = len(p) + for j, (p, c) in enumerate(zip(path, config)): + i_str = str(i) + c_str = str(c) + if c != None: + assert isinstance(c, dict) + assert len(c) == 1 + for k, v in c.items(): + c_str = "%s: %s" % (k, str(v)) + if j == 0: + self.print_info(0, 1, "%s) %-*s (%s)" % (i_str, max, p, c_str)) + else: + self.print_info( + 0, 1, "%s %-*s (%s)" % (" " * len(i_str), max, p, c_str) + ) + elif len(error_msg): + self.print_info(0, 0, "ErrorMessages: %s" % error_msg) + else: + self.print_info(0, 0, "ErrorMessages: Unknown error in finding path") + + def diagram(self, format): + + import graphviz + + for block in self.blocks: + block.top = False + for block in self.blocks: + graph = graphviz.Digraph("%s" % block.name) + graph.attr("node", shape="record") + graph.attr(layout="dot", splines="spline") + graph.attr(nodesep="1", ranksep="2") + block.top = True + block.update_child([], True) + block.graph_diagram(graph, format) + block.top = False + graph.render() + +def main(external): + + start = time.time() + parser = argparse.ArgumentParser( + prog="Configuration Modeler", description="Generate configuration via modeling" + ) + parser.add_argument( + "-m", "--model", type=str, required=True, help="Top model input file" + ) + parser.add_argument("-s", "--solve", type=str, help="Routing JSON to solve") + parser.add_argument( + "-q", + "--query", + type=str, + help='Query. Format "--source=??? --destinations=???,??? --filters=???,??? --flags=???,???"', + ) + parser.add_argument("-t", "--tcl_map", action="store_true", help=argparse.SUPPRESS) + parser.add_argument("-v", "--debug", type=int, default=0, help="Debug level") + parser.add_argument("-c", "--clean", action="store_true", help=argparse.SUPPRESS) + parser.add_argument("-d", "--diagram", type=int, default=0, help=argparse.SUPPRESS) + args = parser.parse_args() + configurator = CONFIGURATOR(args.model, args.tcl_map == True, args.debug, external) + if args.solve != None: + configurator.solve_routings(args.solve, args.clean) + if args.query != None: + configurator.solve_routing(shlex.split(args.query)) + if args.diagram > 0: + configurator.diagram(args.diagram) + end = time.time() + if external: print("Elapsed time: %f" % (end - start)) + +def cpp_entry(top_file, json_file): + + assert isinstance(top_file, str) + assert isinstance(json_file, str) + sys.argv = ["config_model.py", "--model", top_file, "--solve", json_file, "--tcl_map"] + main(False) + return [True] + +if __name__ == "__main__": + main(True) \ No newline at end of file diff --git a/tests/unittest/ModelConfig/apis/routing_library/__init__.py b/tests/unittest/ModelConfig/apis/routing_library/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/tests/unittest/ModelConfig/apis/routing_library/function_library.py b/tests/unittest/ModelConfig/apis/routing_library/function_library.py new file mode 100644 index 000000000..2a4e7ad04 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/function_library.py @@ -0,0 +1,18 @@ +import os +import sys +current_dir = os.path.dirname(os.path.abspath(__file__)) +if current_dir not in sys.path: + sys.path.insert(0, current_dir) + +def get_gbox_top_name(index) : + + pn = "P" if (index % 2) == 0 else "N" + return "gearbox_%s[%d]" % (pn, index//2) + +def get_location(type, bank, index) : + + pn = "P" if (index % 2) == 0 else "N" + if index in [18, 19, 38, 39] : + return "H%s_%d_CC_%d_%d%s" % (type, bank, index, index//2, pn) + else : + return "H%s_%d_%d_%d%s" % (type, bank, index, index//2, pn) diff --git a/tests/unittest/ModelConfig/apis/routing_library/gbox_fclk_mux.py b/tests/unittest/ModelConfig/apis/routing_library/gbox_fclk_mux.py new file mode 100644 index 000000000..9cdd1b323 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/gbox_fclk_mux.py @@ -0,0 +1,17 @@ +# Block +create_block(name="gbox_fclk_mux") + +# Ports +add_port(name="vco_clk", dir=DIR_IN, bit=2) +add_port(name="rx_io_clk", dir=DIR_IN, bit=2) +add_port(name="fast_clk", dir=DIR_OUT, bit=1) + +# Config +add_config_mux(out="fast_clk", + selection={0b000 : "vco_clk[0]", + 0b001 : "vco_clk[1]", + 0b100 : "rx_io_clk[0]", + 0b110 : "rx_io_clk[1]"}, + bits=[{"vco_clk_sel" : 1}, + {"rx_fclkio_sel" : 1}, + {"rxclk_phase_sel":1}]) diff --git a/tests/unittest/ModelConfig/apis/routing_library/gbox_hp_40x2.py b/tests/unittest/ModelConfig/apis/routing_library/gbox_hp_40x2.py new file mode 100644 index 000000000..628af5892 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/gbox_hp_40x2.py @@ -0,0 +1,148 @@ +import function_library +load_model("gbox_osc.py") +load_model("gbox_pll_refmux.py") +load_model("gbox_pll.py") +load_model("gbox_fclk_mux.py") +load_model("gbox_hpio.py") +load_model("gbox_top.py") +load_model("gbox_root_bank_clkmux.py") + +# Block +create_block(name="gbox_hp_40x2") + +# Ports +add_port(name="bank0_rx_in", dir=DIR_IN, bit=40) +add_port(name="bank1_rx_in", dir=DIR_IN, bit=40) +add_port(name="hvl_bank0_rx_io_clk", dir=DIR_IN, bit=2) +add_port(name="hvl_bank1_rx_io_clk", dir=DIR_IN, bit=2) +add_port(name="hvr_bank0_rx_io_clk", dir=DIR_IN, bit=2) +add_port(name="hvr_bank1_rx_io_clk", dir=DIR_IN, bit=2) +add_port(name="hvl_bank0_root_core_clk", dir=DIR_IN, bit=2) +add_port(name="hvl_bank0_root_cdr_clk", dir=DIR_IN, bit=2) +add_port(name="hvl_bank1_root_core_clk", dir=DIR_IN, bit=2) +add_port(name="hvl_bank1_root_cdr_clk", dir=DIR_IN, bit=2) +add_port(name="hvr_bank0_root_core_clk", dir=DIR_IN, bit=2) +add_port(name="hvr_bank0_root_cdr_clk", dir=DIR_IN, bit=2) +add_port(name="hvr_bank1_root_core_clk", dir=DIR_IN, bit=2) +add_port(name="hvr_bank1_root_cdr_clk", dir=DIR_IN, bit=2) +add_port(name="fclk_buf", dir=DIR_IN, bit=8) +add_port(name="pll_foutvco", dir=DIR_OUT, bit=2) +add_port(name="pll_fout", dir=DIR_OUT, bit=2) +add_port(name="fabric_clk", dir=DIR_OUT, bit=16) + +# Instances +add_instance(name="rc_osc_50mhz", block="rc_osc_50mhz") +add_instance(name="pll_refmux[0]", block="gbox_pll_refmux") +add_instance(name="pll_refmux[1]", block="gbox_pll_refmux") +add_instance(name="pll[0]", block="PLL") +add_instance(name="pll[1]", block="PLL") +add_instance(name="bank0_fclk_mux_A", block="gbox_fclk_mux") +add_instance(name="bank1_fclk_mux_A", block="gbox_fclk_mux") +add_instance(name="bank0_fclk_mux_B", block="gbox_fclk_mux") +add_instance(name="bank1_fclk_mux_B", block="gbox_fclk_mux") +add_instance(name="bank0_hpio", block="gbox_hpio") +add_instance(name="bank1_hpio", block="gbox_hpio") +add_instance(name="bank0_root_bank_clkmux", block="gbox_root_bank_clkmux") +add_instance(name="bank1_root_bank_clkmux", block="gbox_root_bank_clkmux") + +# Connections +# osc + pin --> refmux +add_connection(source="rc_osc_50mhz->o_osc", destinations=["pll_refmux[0]->rosc_clk", "pll_refmux[1]->rosc_clk"]) +add_connection(source="bank0_hpio->rx_io_clk[0]", destinations=["pll_refmux[0]->bank0_hp_rx_io_clk[0]", "pll_refmux[1]->bank0_hp_rx_io_clk[0]"]) +add_connection(source="bank0_hpio->rx_io_clk[1]", destinations=["pll_refmux[0]->bank0_hp_rx_io_clk[1]", "pll_refmux[1]->bank0_hp_rx_io_clk[1]"]) +add_connection(source="bank1_hpio->rx_io_clk[0]", destinations=["pll_refmux[0]->bank1_hp_rx_io_clk[0]", "pll_refmux[1]->bank1_hp_rx_io_clk[0]"]) +add_connection(source="bank1_hpio->rx_io_clk[1]", destinations=["pll_refmux[0]->bank1_hp_rx_io_clk[1]", "pll_refmux[1]->bank1_hp_rx_io_clk[1]"]) +add_connection(source="hvl_bank0_rx_io_clk[0]", destinations=["pll_refmux[0]->bank0_hv_rx_io_clk[0]"]) +add_connection(source="hvl_bank0_rx_io_clk[1]", destinations=["pll_refmux[0]->bank0_hv_rx_io_clk[1]"]) +add_connection(source="hvl_bank1_rx_io_clk[0]", destinations=["pll_refmux[0]->bank1_hv_rx_io_clk[0]"]) +add_connection(source="hvl_bank1_rx_io_clk[1]", destinations=["pll_refmux[0]->bank1_hv_rx_io_clk[1]"]) +add_connection(source="hvr_bank0_rx_io_clk[0]", destinations=["pll_refmux[1]->bank0_hv_rx_io_clk[0]"]) +add_connection(source="hvr_bank0_rx_io_clk[1]", destinations=["pll_refmux[1]->bank0_hv_rx_io_clk[1]"]) +add_connection(source="hvr_bank1_rx_io_clk[0]", destinations=["pll_refmux[1]->bank1_hv_rx_io_clk[0]"]) +add_connection(source="hvr_bank1_rx_io_clk[1]", destinations=["pll_refmux[1]->bank1_hv_rx_io_clk[1]"]) +# refmux --> pll +add_connection(source="pll_refmux[0]->out", destinations=["pll[0]->fref"]) +add_connection(source="pll_refmux[1]->out", destinations=["pll[1]->fref"]) +# pll + pin --> fclk mux +add_connection(source="pll[0]->foutvco", destinations=["bank0_fclk_mux_A->vco_clk[0]", "pll_foutvco[0]"]) +add_connection(source="pll[0]->fout[0]", destinations=["bank0_fclk_mux_A->vco_clk[1]", "pll_fout[0]"]) +add_connection(source="bank0_hpio->rx_io_clk[0]", destinations=["bank0_fclk_mux_A->rx_io_clk[0]"]) +add_connection(source="bank0_hpio->rx_io_clk[1]", destinations=["bank0_fclk_mux_A->rx_io_clk[1]"]) +add_connection(source="pll[1]->foutvco", destinations=["bank1_fclk_mux_A->vco_clk[0]", "pll_foutvco[1]"]) +add_connection(source="pll[1]->fout[0]", destinations=["bank1_fclk_mux_A->vco_clk[1]", "pll_fout[1]"]) +add_connection(source="bank1_hpio->rx_io_clk[0]", destinations=["bank1_fclk_mux_A->rx_io_clk[0]"]) +add_connection(source="bank1_hpio->rx_io_clk[1]", destinations=["bank1_fclk_mux_A->rx_io_clk[1]"]) +add_connection(source="pll[0]->foutvco", destinations=["bank0_fclk_mux_B->vco_clk[0]"]) +add_connection(source="pll[0]->fout[0]", destinations=["bank0_fclk_mux_B->vco_clk[1]"]) +add_connection(source="bank0_hpio->rx_io_clk[0]", destinations=["bank0_fclk_mux_B->rx_io_clk[0]"]) +add_connection(source="bank0_hpio->rx_io_clk[1]", destinations=["bank0_fclk_mux_B->rx_io_clk[1]"]) +add_connection(source="pll[1]->foutvco", destinations=["bank1_fclk_mux_B->vco_clk[0]"]) +add_connection(source="pll[1]->fout[0]", destinations=["bank1_fclk_mux_B->vco_clk[1]"]) +add_connection(source="bank1_hpio->rx_io_clk[0]", destinations=["bank1_fclk_mux_B->rx_io_clk[0]"]) +add_connection(source="bank1_hpio->rx_io_clk[1]", destinations=["bank1_fclk_mux_B->rx_io_clk[1]"]) +# fclk mux --> gearbox fast clk +add_connection(source="bank0_fclk_mux_A->fast_clk", destinations=["bank0_hpio->fast_clk_A"]) +add_connection(source="bank0_fclk_mux_B->fast_clk", destinations=["bank0_hpio->fast_clk_B"]) +add_connection(source="bank1_fclk_mux_A->fast_clk", destinations=["bank1_hpio->fast_clk_A"]) +add_connection(source="bank1_fclk_mux_B->fast_clk", destinations=["bank1_hpio->fast_clk_B"]) +# pin --> gearbox pin +# gearbox core clk + cdr clk --> root bank core clk + cdr clk +for bank in range(2) : + gbox_hpio_name = "bank%d_hpio" % bank + gbox_root_bank_clkmux_name = "bank%d_root_bank_clkmux" % bank + for i in range(40) : + gbox_pin = "bank%d_rx_in[%d]" % (bank, i) + add_connection(source=gbox_pin, destinations=["%s->rx_in[%d]" % (gbox_hpio_name, i)]) + add_connection(source="%s->core_clk[%d]" % (gbox_hpio_name, i), destinations=["%s->core_clk_in[%d]" % (gbox_root_bank_clkmux_name, i)]) + add_connection(source="%s->cdr_clk[%d]" % (gbox_hpio_name, i), destinations=["%s->cdr_clk_in[%d]" % (gbox_root_bank_clkmux_name, i)]) + +# Config +# Root selection for fabric_clk +root_mux_selection = { + 0 : "bank0_root_bank_clkmux->core_clk[0]", + 1 : "bank0_root_bank_clkmux->core_clk[1]", + 2 : "bank1_root_bank_clkmux->core_clk[0]", + 3 : "bank1_root_bank_clkmux->core_clk[1]", + 4 : "bank0_root_bank_clkmux->cdr_clk[0]", + 5 : "bank0_root_bank_clkmux->cdr_clk[1]", + 6 : "bank1_root_bank_clkmux->cdr_clk[0]", + 7 : "bank1_root_bank_clkmux->cdr_clk[1]", + 8 : "hvl_bank0_root_core_clk[0]", + 9 : "hvl_bank0_root_core_clk[1]", + 10 : "hvl_bank1_root_core_clk[0]", + 11 : "hvl_bank1_root_core_clk[1]", + 12 : "hvl_bank0_root_cdr_clk[0]", + 13 : "hvl_bank0_root_cdr_clk[1]", + 14 : "hvl_bank1_root_cdr_clk[0]", + 15 : "hvl_bank1_root_cdr_clk[1]", + 16 : "hvr_bank0_root_core_clk[0]", + 17 : "hvr_bank0_root_core_clk[1]", + 18 : "hvr_bank1_root_core_clk[0]", + 19 : "hvr_bank1_root_core_clk[1]", + 20 : "hvr_bank0_root_cdr_clk[0]", + 21 : "hvr_bank0_root_cdr_clk[1]", + 22 : "hvr_bank1_root_cdr_clk[0]", + 24 : "hvr_bank1_root_cdr_clk[1]", + 32 : "pll[0]->fout[0]", + 33 : "pll[0]->fout[1]", + 34 : "pll[0]->fout[2]", + 35 : "pll[0]->fout[3]", + 36 : "pll[1]->fout[0]", + 37 : "pll[1]->fout[1]", + 38 : "pll[1]->fout[2]", + 39 : "pll[1]->fout[3]", + 40 : "fclk_buf[4]", + 41 : "fclk_buf[5]", + 42 : "fclk_buf[6]", + 43 : "fclk_buf[7]", + 44 : "fclk_buf[0]", + 45 : "fclk_buf[1]", + 46 : "fclk_buf[2]", + 47 : "fclk_buf[3]", + 48 : "rc_osc_50mhz->o_osc" +} +for i in range(16) : + add_config_mux(out="fabric_clk[%d]" % i, + selection=root_mux_selection, + bits=[{"root_mux_sel[%d]" % i : 6}]) + \ No newline at end of file diff --git a/tests/unittest/ModelConfig/apis/routing_library/gbox_hpio.py b/tests/unittest/ModelConfig/apis/routing_library/gbox_hpio.py new file mode 100644 index 000000000..de2ddce0f --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/gbox_hpio.py @@ -0,0 +1,33 @@ +import function_library +load_model("gbox_top.py") + +# Block +create_block(name="gbox_hpio") + +# Ports +add_port(name="fast_clk_A", dir=DIR_IN) +add_port(name="fast_clk_B", dir=DIR_IN) +add_port(name="rx_in", dir=DIR_IN, bit=40) +add_port(name="rx_io_clk", dir=DIR_OUT, bit=2) +add_port(name="core_clk", dir=DIR_OUT, bit=40) +add_port(name="cdr_clk", dir=DIR_OUT, bit=40) +add_port(name="tx_clk", dir=DIR_OUT, bit=40) + +# Instances +for i in range(40) : + instance_name = function_library.get_gbox_top_name(i) + add_instance(name=instance_name, block="gbox_top") + +# Connections +for i in range(40) : + instance_name = function_library.get_gbox_top_name(i) + if i < 20 : + add_connection(source="fast_clk_A", destinations=["%s->fast_clk" % instance_name]) + else : + add_connection(source="fast_clk_B", destinations=["%s->fast_clk" % instance_name]) + add_connection(source="rx_in[%d]" % i, destinations=["%s->rx_in" % instance_name]) + add_connection(source="%s->core_clk" % instance_name, destinations=["core_clk[%d]" % i]) + add_connection(source="%s->cdr_clk" % instance_name, destinations=["cdr_clk[%d]" % i]) + add_connection(source="%s->tx_clk" % instance_name, destinations=["tx_clk[%d]" % i]) +add_connection(source="rx_in[18]", destinations=["rx_io_clk[0]"]) +add_connection(source="rx_in[38]", destinations=["rx_io_clk[1]"]) diff --git a/tests/unittest/ModelConfig/apis/routing_library/gbox_hv_40x2.py b/tests/unittest/ModelConfig/apis/routing_library/gbox_hv_40x2.py new file mode 100644 index 000000000..f47e59689 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/gbox_hv_40x2.py @@ -0,0 +1,74 @@ +import function_library +load_model("gbox_hpio.py") + +# Block +create_block(name="gbox_hv_40x2") + +# Ports +add_port(name="bank0_rx_in", dir=DIR_IN, bit=40) +add_port(name="bank1_rx_in", dir=DIR_IN, bit=40) +add_port(name="pll_fout", dir=DIR_IN, bit=1) +add_port(name="pll_foutvco", dir=DIR_IN, bit=1) +add_port(name="bank0_rx_io_clk", dir=DIR_OUT, bit=2) +add_port(name="bank1_rx_io_clk", dir=DIR_OUT, bit=2) +add_port(name="bank0_root_core_clk", dir=DIR_OUT, bit=2) +add_port(name="bank1_root_core_clk", dir=DIR_OUT, bit=2) +add_port(name="bank0_root_cdr_clk", dir=DIR_OUT, bit=2) +add_port(name="bank1_root_cdr_clk", dir=DIR_OUT, bit=2) + +# Instances +add_instance(name="bank0_fclk_mux_A", block="gbox_fclk_mux") +add_instance(name="bank1_fclk_mux_A", block="gbox_fclk_mux") +add_instance(name="bank0_fclk_mux_B", block="gbox_fclk_mux") +add_instance(name="bank1_fclk_mux_B", block="gbox_fclk_mux") +add_instance(name="bank0_hpio", block="gbox_hpio") +add_instance(name="bank1_hpio", block="gbox_hpio") +add_instance(name="bank0_root_bank_clkmux", block="gbox_root_bank_clkmux") +add_instance(name="bank1_root_bank_clkmux", block="gbox_root_bank_clkmux") + +# Connections +# pll + pin --> fclk mux +add_connection(source="pll_foutvco", destinations=["bank0_fclk_mux_A->vco_clk[0]"]) +add_connection(source="pll_fout", destinations=["bank0_fclk_mux_A->vco_clk[1]"]) +add_connection(source="bank0_hpio->rx_io_clk[0]", destinations=["bank0_fclk_mux_A->rx_io_clk[0]"]) +add_connection(source="bank0_hpio->rx_io_clk[1]", destinations=["bank0_fclk_mux_A->rx_io_clk[1]"]) +add_connection(source="pll_foutvco", destinations=["bank1_fclk_mux_A->vco_clk[0]"]) +add_connection(source="pll_fout", destinations=["bank1_fclk_mux_A->vco_clk[1]"]) +add_connection(source="bank1_hpio->rx_io_clk[0]", destinations=["bank1_fclk_mux_A->rx_io_clk[0]"]) +add_connection(source="bank1_hpio->rx_io_clk[1]", destinations=["bank1_fclk_mux_A->rx_io_clk[1]"]) +add_connection(source="pll_foutvco", destinations=["bank0_fclk_mux_B->vco_clk[0]"]) +add_connection(source="pll_fout", destinations=["bank0_fclk_mux_B->vco_clk[1]"]) +add_connection(source="bank0_hpio->rx_io_clk[0]", destinations=["bank0_fclk_mux_B->rx_io_clk[0]"]) +add_connection(source="bank0_hpio->rx_io_clk[1]", destinations=["bank0_fclk_mux_B->rx_io_clk[1]"]) +add_connection(source="pll_foutvco", destinations=["bank1_fclk_mux_B->vco_clk[0]"]) +add_connection(source="pll_fout", destinations=["bank1_fclk_mux_B->vco_clk[1]"]) +add_connection(source="bank1_hpio->rx_io_clk[0]", destinations=["bank1_fclk_mux_B->rx_io_clk[0]"]) +add_connection(source="bank1_hpio->rx_io_clk[1]", destinations=["bank1_fclk_mux_B->rx_io_clk[1]"]) +# fclk mux --> gearbox fast clk +add_connection(source="bank0_fclk_mux_A->fast_clk", destinations=["bank0_hpio->fast_clk_A"]) +add_connection(source="bank0_fclk_mux_B->fast_clk", destinations=["bank0_hpio->fast_clk_B"]) +add_connection(source="bank1_fclk_mux_A->fast_clk", destinations=["bank1_hpio->fast_clk_A"]) +add_connection(source="bank1_fclk_mux_B->fast_clk", destinations=["bank1_hpio->fast_clk_B"]) +# pin --> gearbox pin +# gearbox core clk + cdr clk --> root bank core clk + cdr clk +for bank in range(2) : + gbox_hpio_name = "bank%d_hpio" % bank + gbox_root_bank_clkmux_name = "bank%d_root_bank_clkmux" % bank + for i in range(40) : + source = "bank%d_rx_in[%d]" % (bank, i) + add_connection(source=source, destinations=["%s->rx_in[%d]" % (gbox_hpio_name, i)]) + source = "%s->core_clk[%d]" % (gbox_hpio_name, i) + add_connection(source=source, destinations=["%s->core_clk_in[%d]" % (gbox_root_bank_clkmux_name, i)]) + source = "%s->cdr_clk[%d]" % (gbox_hpio_name, i) + add_connection(source=source, destinations=["%s->cdr_clk_in[%d]" % (gbox_root_bank_clkmux_name, i)]) + for i in range(2) : + add_connection(source="bank%s_hpio->rx_io_clk[%d]" % (bank, i), destinations=["bank%d_rx_io_clk[%d]" % (bank, i)]) +# root bank core clk + cdr clk --> pin core clk + cdr clk +add_connection(source="bank0_root_bank_clkmux->core_clk[0]", destinations=["bank0_root_core_clk[0]"]) +add_connection(source="bank0_root_bank_clkmux->core_clk[1]", destinations=["bank0_root_core_clk[1]"]) +add_connection(source="bank1_root_bank_clkmux->core_clk[0]", destinations=["bank1_root_core_clk[0]"]) +add_connection(source="bank1_root_bank_clkmux->core_clk[1]", destinations=["bank1_root_core_clk[1]"]) +add_connection(source="bank0_root_bank_clkmux->cdr_clk[0]", destinations=["bank0_root_cdr_clk[0]"]) +add_connection(source="bank0_root_bank_clkmux->cdr_clk[1]", destinations=["bank0_root_cdr_clk[1]"]) +add_connection(source="bank1_root_bank_clkmux->cdr_clk[0]", destinations=["bank1_root_cdr_clk[0]"]) +add_connection(source="bank1_root_bank_clkmux->cdr_clk[1]", destinations=["bank1_root_cdr_clk[1]"]) diff --git a/tests/unittest/ModelConfig/apis/routing_library/gbox_osc.py b/tests/unittest/ModelConfig/apis/routing_library/gbox_osc.py new file mode 100644 index 000000000..18ff792e6 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/gbox_osc.py @@ -0,0 +1,9 @@ +# Block +create_block(name="rc_osc_50mhz") + +# Ports +add_port(name="osc", dir=DIR_IN) +add_port(name="o_osc", dir=DIR_OUT) + +# Connections +add_connection(source="osc", destinations=["o_osc"]) diff --git a/tests/unittest/ModelConfig/apis/routing_library/gbox_pll.py b/tests/unittest/ModelConfig/apis/routing_library/gbox_pll.py new file mode 100644 index 000000000..152acf2c6 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/gbox_pll.py @@ -0,0 +1,30 @@ +# PLL +create_block(name="PLL") + +# Ports +add_port(name="fref", dir=DIR_IN) +add_port(name="fout", dir=DIR_OUT, bit=4) +add_port(name="foutvco", dir=DIR_OUT, bit=1) + +# Connections +add_connection(source="fref", destinations=["fout[0]", "fout[1]", "fout[2]", "fout[3]", "foutvco"]) + +# Add parameters +parameter_script = """ +if 'PLL_DIV' in self.parameters and 'PLL_MULT' in self.parameters and 'PLL_POST_DIV' in self.parameters and '__pll_enable__' in self.parameters: + post_div = int(self.parameters['PLL_POST_DIV'], 0) + self.defined_parameters['pll_DSKEWCALBYP'] = 'DSKEWCALBYP_0' + self.defined_parameters['pll_DSKEWCALIN'] = 0 + self.defined_parameters['pll_DSKEWCALCNT'] = 2 + self.defined_parameters['pll_DSKEWFASTCAL'] = 'DSKEWFASTCAL_0' + self.defined_parameters['pll_DSKEWCALEN'] = 'DSKEWCALEN_0' + self.defined_parameters['pll_FRAC'] = 0 + self.defined_parameters['pll_FBDIV'] = int(self.parameters['PLL_MULT'], 0) + self.defined_parameters['pll_REFDIV'] = int(self.parameters['PLL_DIV'], 0) + self.defined_parameters['pll_PLLEN'] = int(self.parameters['__pll_enable__'], 0) + self.defined_parameters['pll_POSTDIV1'] = (post_div >> 4) & 7 + self.defined_parameters['pll_POSTDIV2'] = post_div & 7 + self.defined_parameters['pll_DSMEN'] = 'DSMEN_0' + self.defined_parameters['pll_DACEN'] = 'DACEN_0' +""" +add_parameter("PLL", parameter_script) diff --git a/tests/unittest/ModelConfig/apis/routing_library/gbox_pll_refmux.py b/tests/unittest/ModelConfig/apis/routing_library/gbox_pll_refmux.py new file mode 100644 index 000000000..07630b190 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/gbox_pll_refmux.py @@ -0,0 +1,56 @@ +# Block +create_block(name="gbox_pll_refmux") + +# Ports +add_port(name="rosc_clk", dir=DIR_IN) +add_port(name="bank0_hp_rx_io_clk", dir=DIR_IN, bit=2) +add_port(name="bank1_hp_rx_io_clk", dir=DIR_IN, bit=2) +add_port(name="bank0_hv_rx_io_clk", dir=DIR_IN, bit=2) +add_port(name="bank1_hv_rx_io_clk", dir=DIR_IN, bit=2) +add_port(name="out", dir=DIR_OUT) + +# Config +''' + selection | use_rosc use_hv hp_bank_rx_io_sel hp_rx_io_sel hv_bank_rx_io_sel hv_rx_io_sel + --------- | -------- ------ ----------------- ------------ ----------------- ------------ + rosc_clk | 1 x x xx xx x + bank0_hp_rx_io_clk[0] | 0 0 0 x0 xx x + bank0_hp_rx_io_clk[1] | 0 0 0 x1 xx x + bank1_hp_rx_io_clk[0] | 0 0 1 0x xx x + bank1_hp_rx_io_clk[1] | 0 0 1 1x xx x + bank0_hv_rx_io_clk[0] | 0 1 x xx 00 0 + bank0_hv_rx_io_clk[1] | 0 1 x xx 00 1 + bank1_hv_rx_io_clk[0] | 0 1 x xx 01 0 + bank1_hv_rx_io_clk[1] | 0 1 x xx 01 1 +''' +selection = { + 0b10000000 : "rosc_clk", + 0b00000000 : "bank0_hp_rx_io_clk[0]", + 0b00001000 : "bank0_hp_rx_io_clk[1]", + 0b00100000 : "bank1_hp_rx_io_clk[0]", + 0b00110000 : "bank1_hp_rx_io_clk[1]", + 0b01000000 : "bank0_hv_rx_io_clk[0]", + 0b01000001 : "bank0_hv_rx_io_clk[1]", + 0b01000010 : "bank1_hv_rx_io_clk[0]", + 0b01000011 : "bank1_hv_rx_io_clk[1]" +} +bits = [ + {"cfg_pllref_hv_rx_io_sel" : 1}, + {"cfg_pllref_hv_bank_rx_io_sel" : 2}, + {"cfg_pllref_hp_rx_io_sel" : 2}, + {"cfg_pllref_hp_bank_rx_io_sel" : 1}, + {"cfg_pllref_use_hv" : 1}, + {"cfg_pllref_use_rosc" : 1} +] +add_config_mux(out="out", + selection=selection, + bits=bits) + +# Add parameters +parameter_script = """ +if 'DIVIDE_CLK_IN_BY_2' in self.parameters and self.parameters['DIVIDE_CLK_IN_BY_2'] in ['TRUE', 'ON', '1']: + self.defined_parameters['cfg_pllref_use_div'] = 1 +else: + self.defined_parameters['cfg_pllref_use_div'] = 0 +""" +add_parameter("PLL", parameter_script) \ No newline at end of file diff --git a/tests/unittest/ModelConfig/apis/routing_library/gbox_root_bank_clkmux.py b/tests/unittest/ModelConfig/apis/routing_library/gbox_root_bank_clkmux.py new file mode 100644 index 000000000..3fc49fb95 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/gbox_root_bank_clkmux.py @@ -0,0 +1,31 @@ +# Block +create_block(name="gbox_root_bank_clkmux") + +# Ports +add_port(name="core_clk_in", dir=DIR_IN, bit=40) +add_port(name="cdr_clk_in", dir=DIR_IN, bit=40) +add_port(name="core_clk", dir=DIR_OUT, bit=2) +add_port(name="cdr_clk", dir=DIR_OUT, bit=2) + +# Config +core_clk_selection_A = {} +core_clk_selection_B = {} +cdr_clk_selection_A = {} +cdr_clk_selection_B = {} +for i in range(20) : + core_clk_selection_A[i] = "core_clk_in[%d]" % i + core_clk_selection_B[i] = "core_clk_in[%d]" % (20 + i) + cdr_clk_selection_A[i] = "cdr_clk_in[%d]" % i + cdr_clk_selection_B[i] = "cdr_clk_in[%d]" % (20 + i) +add_config_mux(out="core_clk[0]", + selection=core_clk_selection_A, + bits=[{"CORE_CLK_ROOT_SEL_A" : 5}]) +add_config_mux(out="core_clk[1]", + selection=core_clk_selection_B, + bits=[{"CORE_CLK_ROOT_SEL_B" : 5}]) +add_config_mux(out="cdr_clk[0]", + selection=cdr_clk_selection_A, + bits=[{"CDR_CLK_ROOT_SEL_A" : 5}]) +add_config_mux(out="cdr_clk[1]", + selection=cdr_clk_selection_B, + bits=[{"CDR_CLK_ROOT_SEL_B" : 5}]) \ No newline at end of file diff --git a/tests/unittest/ModelConfig/apis/routing_library/gbox_top.py b/tests/unittest/ModelConfig/apis/routing_library/gbox_top.py new file mode 100644 index 000000000..7d00a56a6 --- /dev/null +++ b/tests/unittest/ModelConfig/apis/routing_library/gbox_top.py @@ -0,0 +1,25 @@ +# Block +create_block(name="gbox_top") + +# Ports +add_port(name="fast_clk", dir=DIR_IN) +add_port(name="rx_in", dir=DIR_IN) +add_port(name="core_clk", dir=DIR_OUT) +add_port(name="cdr_clk", dir=DIR_OUT) +add_port(name="tx_clk", dir=DIR_OUT) + +# Connections +add_connection(source="fast_clk", destinations=["cdr_clk"]) + +# Config +add_config_mux(out="core_clk", + selection={ + 0 : "fast_clk", + 1 : "rx_in" + }, + bits=[{"RX_CLOCK_IO" : 1}]) +add_config_mux(out="tx_clk", + selection={ + 1 : "fast_clk" + }, + bits=[{"TX_CLOCK_IO" : 1}]) diff --git a/tests/unittest/ModelConfig/design_edit.sdc b/tests/unittest/ModelConfig/design_edit.sdc index f6cf0ea0f..6749e5437 100644 --- a/tests/unittest/ModelConfig/design_edit.sdc +++ b/tests/unittest/ModelConfig/design_edit.sdc @@ -42,136 +42,136 @@ set_clock_out -device_clock clk[0] -design_clock clk0_div # Each pin mode and location assignment # ############# -# Clock data from object clk0 port O is not routed to fabric -# Pin clk0 :: I_BUF |-> CLK_BUF - -# Object clk1 is primitive \PLL but data signal is not defined -# Pin clk1 :: I_BUF |-> CLK_BUF |-> PLL - -# Clock data from object clk2 port O is not routed to fabric -# Pin clk2 :: I_BUF |-> CLK_BUF - -# Pin din :: I_BUF |-> I_DELAY -# set_mode MODE_BP_DIR_A_RX HP_1_20_10P -# set_io din HP_1_20_10P --> (original) -set_io din_delay HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A - -# Pin din_clk2 :: I_BUF -# set_mode MODE_BP_DIR_A_RX HR_5_0_0P -# set_io din_clk2 HR_5_0_0P --> (original) -set_io $ibuf_din_clk2 HR_5_0_0P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A - -# Pin din_serdes :: I_BUF |-> I_SERDES -# set_mode MODE_RATE_8_A_RX HR_2_0_0P -# set_io din_serdes HR_2_0_0P --> (original) -set_io serdes_data[0] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[0]_A -set_io serdes_data[1] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[1]_A -set_io serdes_data[2] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[2]_A -set_io serdes_data[3] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[3]_A -set_io serdes_data[4] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[4]_A -set_io serdes_data[5] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[5]_A -set_io serdes_data[6] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[6]_A -set_io serdes_data[7] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[7]_A - -# Pin din_serdes_clk_out :: I_BUF -# set_mode MODE_BP_DIR_A_RX HR_2_6_3P -# set_io din_serdes_clk_out HR_2_6_3P --> (original) -set_io $ibuf_din_serdes_clk_out HR_2_6_3P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A +# Skip reason: Clock data from object clk0 port O does not need to route to fabric +# Pin clk0 :: I_BUF |-> CLK_BUF + +# Skip reason: Object clk1 is primitive \PLL but data signal is not defined +# Pin clk1 :: I_BUF |-> CLK_BUF |-> PLL + +# Skip reason: Clock data from object clk2 port O does not need to route to fabric +# Pin clk2 :: I_BUF |-> CLK_BUF + +# Pin din :: I_BUF |-> I_DELAY +# set_mode MODE_BP_DIR_A_RX HP_1_20_10P +# set_io din HP_1_20_10P --> (original) +set_io din_delay HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Pin din_clk2 :: I_BUF +# set_mode MODE_BP_DIR_A_RX HR_5_0_0P +# set_io din_clk2 HR_5_0_0P --> (original) +set_io $ibuf_din_clk2 HR_5_0_0P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Pin din_serdes :: I_BUF |-> I_SERDES +# set_mode MODE_RATE_8_A_RX HR_2_0_0P +# set_io din_serdes HR_2_0_0P --> (original) +set_io serdes_data[0] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[0]_A +set_io serdes_data[1] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[1]_A +set_io serdes_data[2] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[2]_A +set_io serdes_data[3] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[3]_A +set_io serdes_data[4] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[4]_A +set_io serdes_data[5] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[5]_A +set_io serdes_data[6] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[6]_A +set_io serdes_data[7] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[7]_A + +# Pin din_serdes_clk_out :: I_BUF +# set_mode MODE_BP_DIR_A_RX HR_2_6_3P +# set_io din_serdes_clk_out HR_2_6_3P --> (original) +set_io $ibuf_din_serdes_clk_out HR_2_6_3P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A # Pin location is not assigned -# Pin enable :: I_BUF - -# Pin reset :: I_BUF -# set_mode MODE_BP_DIR_A_RX HP_1_0_0P -# set_io reset HP_1_0_0P --> (original) -set_io $ibuf_reset HP_1_0_0P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A - -# Object clk_out is primitive \O_SERDES_CLK but data signal is not defined -# Pin clk_out :: O_SERDES_CLK |-> O_BUFT - -# Pin delay_tap[0] :: O_BUFT -# set_mode MODE_BP_DIR_A_TX HR_2_20_10P -# set_io delay_tap[0] HR_2_20_10P --> (original) -set_io $obuf_delay_tap[0] HR_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A - -# Pin delay_tap[1] :: O_BUFT -# set_mode MODE_BP_DIR_A_TX HR_2_22_11P -# set_io delay_tap[1] HR_2_22_11P --> (original) -set_io $obuf_delay_tap[1] HR_2_22_11P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A - -# Pin delay_tap[2] :: O_BUFT -# set_mode MODE_BP_DIR_A_TX HR_2_24_12P -# set_io delay_tap[2] HR_2_24_12P --> (original) -set_io $obuf_delay_tap[2] HR_2_24_12P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A - -# Pin delay_tap[3] :: O_BUFT -# set_mode MODE_BP_DIR_A_TX HR_2_26_13P -# set_io delay_tap[3] HR_2_26_13P --> (original) -set_io $obuf_delay_tap[3] HR_2_26_13P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A - -# Pin delay_tap[4] :: O_BUFT -# set_mode MODE_BP_DIR_A_TX HR_2_28_14P -# set_io delay_tap[4] HR_2_28_14P --> (original) -set_io $obuf_delay_tap[4] HR_2_28_14P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A - -# Pin delay_tap[5] :: O_BUFT -# set_mode MODE_BP_DIR_A_TX HR_2_30_15P -# set_io delay_tap[5] HR_2_30_15P --> (original) -set_io $obuf_delay_tap[5] HR_2_30_15P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A - -# Pin dout :: O_DELAY |-> O_BUFT -# set_mode MODE_BP_DIR_A_TX HP_2_20_10P -# set_io dout HP_2_20_10P --> (original) -set_io dout_pre_delay HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A - -# Pin dout_clk2 :: O_BUFT -# set_mode MODE_BP_DIR_B_TX HR_5_1_0N -# set_io dout_clk2 HR_5_1_0N --> (original) -set_io $obuf_dout_clk2 HR_5_0_0P -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_out[5]_A - -# Pin dout_serdes :: O_SERDES |-> O_BUFT -# set_mode MODE_RATE_8_A_TX HR_2_2_1P -# set_io dout_serdes HR_2_2_1P --> (original) -set_io $auto_540 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[0]_A -set_io $auto_541 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[1]_A -set_io $auto_542 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[2]_A -set_io $auto_543 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[3]_A -set_io $auto_544 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[4]_A -set_io $auto_545 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[5]_A -set_io $auto_546 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[6]_A -set_io $auto_547 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[7]_A - -# Pin dout_serdes_clk_out :: O_BUFT -# set_mode MODE_BP_DIR_B_TX HR_2_7_3N -# set_io dout_serdes_clk_out HR_2_7_3N --> (original) -set_io $obuf_dout_serdes_clk_out HR_2_6_3P -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_out[5]_A +# Pin enable :: I_BUF + +# Pin reset :: I_BUF +# set_mode MODE_BP_DIR_A_RX HP_1_0_0P +# set_io reset HP_1_0_0P --> (original) +set_io $ibuf_reset HP_1_0_0P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Skip reason: Object clk_out is primitive \O_SERDES_CLK but data signal is not defined +# Pin clk_out :: O_SERDES_CLK |-> O_BUFT + +# Pin delay_tap[0] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_20_10P +# set_io delay_tap[0] HR_2_20_10P --> (original) +set_io $f2g_tx_out_$obuf_delay_tap[0] HR_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[1] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_22_11P +# set_io delay_tap[1] HR_2_22_11P --> (original) +set_io $f2g_tx_out_$obuf_delay_tap[1] HR_2_22_11P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[2] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_24_12P +# set_io delay_tap[2] HR_2_24_12P --> (original) +set_io $f2g_tx_out_$obuf_delay_tap[2] HR_2_24_12P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[3] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_26_13P +# set_io delay_tap[3] HR_2_26_13P --> (original) +set_io $f2g_tx_out_$obuf_delay_tap[3] HR_2_26_13P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[4] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_28_14P +# set_io delay_tap[4] HR_2_28_14P --> (original) +set_io $f2g_tx_out_$obuf_delay_tap[4] HR_2_28_14P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[5] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_30_15P +# set_io delay_tap[5] HR_2_30_15P --> (original) +set_io $f2g_tx_out_$obuf_delay_tap[5] HR_2_30_15P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin dout :: O_DELAY |-> O_BUFT +# set_mode MODE_BP_DIR_A_TX HP_2_20_10P +# set_io dout HP_2_20_10P --> (original) +set_io $f2g_tx_out_dout_pre_delay HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin dout_clk2 :: O_BUFT +# set_mode MODE_BP_DIR_B_TX HR_5_1_0N +# set_io dout_clk2 HR_5_1_0N --> (original) +set_io $f2g_tx_out_$obuf_dout_clk2 HR_5_0_0P -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_out[5]_A + +# Pin dout_serdes :: O_SERDES |-> O_BUFT +# set_mode MODE_RATE_8_A_TX HR_2_2_1P +# set_io dout_serdes HR_2_2_1P --> (original) +set_io $f2g_tx_out_serdes_data[0] HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[0]_A +set_io $f2g_tx_out_serdes_data[1] HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[1]_A +set_io $f2g_tx_out_serdes_data[2] HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[2]_A +set_io $f2g_tx_out_serdes_data[3] HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[3]_A +set_io $f2g_tx_out_serdes_data[4] HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[4]_A +set_io $f2g_tx_out_serdes_data[5] HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[5]_A +set_io $f2g_tx_out_serdes_data[6] HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[6]_A +set_io $f2g_tx_out_serdes_data[7] HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_out[7]_A + +# Pin dout_serdes_clk_out :: O_BUFT +# set_mode MODE_BP_DIR_B_TX HR_2_7_3N +# set_io dout_serdes_clk_out HR_2_7_3N --> (original) +set_io $f2g_tx_out_$obuf_dout_serdes_clk_out HR_2_6_3P -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_out[5]_A # Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid' -# Pin din_n :: I_BUF_DS |-> I_DDR +# Pin din_n :: I_BUF_DS |-> I_DDR -# Pin din_p :: I_BUF_DS |-> I_DDR -# set_mode MODE_BP_DDR_A_RX HP_1_4_2P -# set_io din_p HP_1_4_2P --> (original) -set_io o_ddr_d[0] HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin g2f_rx_in[0]_A -set_io o_ddr_d[1] HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin g2f_rx_in[1]_A +# Pin din_p :: I_BUF_DS |-> I_DDR +# set_mode MODE_BP_DDR_A_RX HP_1_4_2P +# set_io din_p HP_1_4_2P --> (original) +set_io o_ddr_d[0] HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin g2f_rx_in[0]_A +set_io o_ddr_d[1] HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin g2f_rx_in[1]_A # Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid' -# Pin dout_n :: O_DDR |-> O_BUF_DS +# Pin dout_n :: O_DDR |-> O_BUFT_DS -# Pin dout_p :: O_DDR |-> O_BUF_DS -# set_mode MODE_BP_DDR_A_TX HP_1_8_4P -# set_io dout_p HP_1_8_4P --> (original) -set_io $auto_536 HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[0]_A -set_io $auto_537 HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[1]_A +# Pin dout_p :: O_DDR |-> O_BUFT_DS +# set_mode MODE_BP_DDR_A_TX HP_1_8_4P +# set_io dout_p HP_1_8_4P --> (original) +set_io $f2g_tx_out_o_ddr_d[0] HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[0]_A +set_io $f2g_tx_out_o_ddr_d[1] HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[1]_A # Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid' -# Pin dout_osc_n :: O_DDR |-> O_BUF_DS +# Pin dout_osc_n :: O_DDR |-> O_BUFT_DS -# Pin dout_osc_p :: O_DDR |-> O_BUF_DS -# set_mode MODE_BP_DDR_A_TX HP_2_22_11P -# set_io dout_osc_p HP_2_22_11P --> (original) -set_io $auto_538 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[0]_A -set_io $auto_539 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[1]_A +# Pin dout_osc_p :: O_DDR |-> O_BUFT_DS +# set_mode MODE_BP_DDR_A_TX HP_2_22_11P +# set_io dout_osc_p HP_2_22_11P --> (original) +set_io $f2g_tx_out_o_ddr_d[0]_2 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[0]_A +set_io $f2g_tx_out_o_ddr_d[1]_2 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[1]_A ############# # @@ -183,14 +183,14 @@ set_io $auto_539 HP_2_22_11P -mode # Location: HR_1_CC_18_9P # Port: EN # Signal: in:f2g_in_en_{A|B} -set_io $auto_500 HR_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A +set_io $auto_500 HR_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A # Module: I_BUF # LinkedObject: clk1 # Location: HP_1_CC_18_9P # Port: EN # Signal: in:f2g_in_en_{A|B} -set_io $auto_501 HP_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A +set_io $auto_501 HP_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A # Module: PLL # LinkedObject: clk1 @@ -205,21 +205,21 @@ set_io $auto_501 HP_1_CC_18_9P -mode MODE_BP_DIR_A_RX # Port: PLL_EN # Signal: in:TO_BE_DETERMINED # Skip reason: TO_BE_DETERMINED -# set_io $auto_534 HP_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin TO_BE_DETERMINED +# set_io $auto_536 HP_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin TO_BE_DETERMINED # Module: I_BUF # LinkedObject: clk2 # Location: HR_5_CC_38_19P # Port: EN # Signal: in:f2g_in_en_{A|B} -set_io $auto_502 HR_5_CC_38_19P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A +set_io $auto_502 HR_5_CC_38_19P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A # Module: I_BUF # LinkedObject: din # Location: HP_1_20_10P # Port: EN # Signal: in:f2g_in_en_{A|B} -set_io $auto_503 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A +set_io $auto_503 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A # Module: I_DELAY # LinkedObject: din @@ -227,7 +227,7 @@ set_io $auto_503 HP_1_20_10P -mode MODE_BP_DIR_A_RX # Port: DLY_ADJ # Signal: in:rule=half-first:f2g_trx_dly_adj # Remap location from HP_1_20_10P to HP_1_20_10P -set_io $auto_521 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_trx_dly_adj +set_io $auto_521 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_trx_dly_adj # Module: I_DELAY # LinkedObject: din @@ -235,7 +235,7 @@ set_io $auto_521 HP_1_20_10P -mode MODE_BP_DIR_A_RX # Port: DLY_INCDEC # Signal: in:rule=half-first:f2g_trx_dly_inc # Remap location from HP_1_20_10P to HP_1_20_10P -set_io $auto_522 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_trx_dly_inc +set_io $auto_522 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_trx_dly_inc # Module: I_DELAY # LinkedObject: din @@ -243,7 +243,7 @@ set_io $auto_522 HP_1_20_10P -mode MODE_BP_DIR_A_RX # Port: DLY_LOAD # Signal: in:rule=half-first:f2g_trx_dly_ld # Remap location from HP_1_20_10P to HP_1_20_10P -set_io $auto_523 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_trx_dly_ld +set_io $auto_523 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_trx_dly_ld # Module: I_DELAY # LinkedObject: din @@ -251,26 +251,26 @@ set_io $auto_523 HP_1_20_10P -mode MODE_BP_DIR_A_RX # Port: DLY_TAP_VALUE # Signal: out:rule=half-first:g2f_trx_dly_tap # Remap location from HP_1_20_10P to HP_1_20_10P -set_io $ifab_$obuf_delay_tap[0] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[0] -set_io $ifab_$obuf_delay_tap[1] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[1] -set_io $ifab_$obuf_delay_tap[2] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[2] -set_io $ifab_$obuf_delay_tap[3] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[3] -set_io $ifab_$obuf_delay_tap[4] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[4] -set_io $ifab_$obuf_delay_tap[5] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[5] +set_io $ifab_$obuf_delay_tap[0] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[0] +set_io $ifab_$obuf_delay_tap[1] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[1] +set_io $ifab_$obuf_delay_tap[2] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[2] +set_io $ifab_$obuf_delay_tap[3] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[3] +set_io $ifab_$obuf_delay_tap[4] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[4] +set_io $ifab_$obuf_delay_tap[5] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[5] # Module: I_BUF # LinkedObject: din_clk2 # Location: HR_5_0_0P # Port: EN # Signal: in:f2g_in_en_{A|B} -set_io $auto_504 HR_5_0_0P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A +set_io $auto_504 HR_5_0_0P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A # Module: I_BUF # LinkedObject: din_serdes # Location: HR_2_0_0P # Port: EN # Signal: in:f2g_in_en_{A|B} -set_io $auto_505 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin f2g_in_en_A +set_io $auto_505 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin f2g_in_en_A # Module: I_SERDES # LinkedObject: din_serdes @@ -278,7 +278,7 @@ set_io $auto_505 HR_2_0_0P -mode MODE_RATE_8_A_RX # Port: BITSLIP_ADJ # Signal: in:rule=half-first:f2g_rx_bitslip_adj # Remap location from HR_2_0_0P to HR_2_0_0P -set_io $auto_524 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin f2g_rx_bitslip_adj +set_io $auto_524 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin f2g_rx_bitslip_adj # Module: I_SERDES # LinkedObject: din_serdes @@ -307,21 +307,21 @@ set_io $auto_524 HR_2_0_0P -mode MODE_RATE_8_A_RX # Port: EN # Signal: in:TO_BE_DETERMINED # Skip reason: TO_BE_DETERMINED -# set_io $auto_525 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin TO_BE_DETERMINED +# set_io $auto_525 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin TO_BE_DETERMINED # Module: I_SERDES # LinkedObject: din_serdes # Location: HR_2_0_0P # Port: RST # Signal: in:f2g_trx_reset_n_{A|B} -set_io $auto_526 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin f2g_trx_reset_n_A +set_io $auto_526 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin f2g_trx_reset_n_A # Module: I_BUF # LinkedObject: din_serdes_clk_out # Location: HR_2_6_3P # Port: EN # Signal: in:f2g_in_en_{A|B} -set_io $auto_506 HR_2_6_3P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A +set_io $auto_506 HR_2_6_3P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A # Module: I_BUF # LinkedObject: enable @@ -335,70 +335,70 @@ set_io $auto_506 HR_2_6_3P -mode MODE_BP_DIR_A_RX # Location: HP_1_0_0P # Port: EN # Signal: in:f2g_in_en_{A|B} -set_io $auto_508 HP_1_0_0P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A +set_io $auto_508 HP_1_0_0P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A # Module: O_BUFT # LinkedObject: clk_out # Location: HR_2_4_2P # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_509 HR_2_4_2P -mode MODE_BP_SDR_A_TX -internal_pin f2g_tx_oe_A +set_io $auto_509 HR_2_4_2P -mode MODE_BP_SDR_A_TX -internal_pin f2g_tx_oe_A # Module: O_SERDES_CLK # LinkedObject: clk_out # Location: HR_2_4_2P # Port: CLK_EN # Signal: in:f2g_tx_clk_en_{A|B} -set_io $auto_533 HR_2_4_2P -mode MODE_BP_SDR_A_TX -internal_pin f2g_tx_clk_en_A +set_io $auto_535 HR_2_4_2P -mode MODE_BP_SDR_A_TX -internal_pin f2g_tx_clk_en_A # Module: O_BUFT # LinkedObject: delay_tap[0] # Location: HR_2_20_10P # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_510 HR_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A +set_io $auto_510 HR_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A # Module: O_BUFT # LinkedObject: delay_tap[1] # Location: HR_2_22_11P # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_511 HR_2_22_11P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A +set_io $auto_511 HR_2_22_11P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A # Module: O_BUFT # LinkedObject: delay_tap[2] # Location: HR_2_24_12P # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_512 HR_2_24_12P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A +set_io $auto_512 HR_2_24_12P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A # Module: O_BUFT # LinkedObject: delay_tap[3] # Location: HR_2_26_13P # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_513 HR_2_26_13P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A +set_io $auto_513 HR_2_26_13P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A # Module: O_BUFT # LinkedObject: delay_tap[4] # Location: HR_2_28_14P # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_514 HR_2_28_14P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A +set_io $auto_514 HR_2_28_14P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A # Module: O_BUFT # LinkedObject: delay_tap[5] # Location: HR_2_30_15P # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_515 HR_2_30_15P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A +set_io $auto_515 HR_2_30_15P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A # Module: O_BUFT # LinkedObject: dout # Location: HP_2_20_10P # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_516 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A +set_io $auto_516 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A # Module: O_DELAY # LinkedObject: dout @@ -406,7 +406,7 @@ set_io $auto_516 HP_2_20_10P -mode MODE_BP_DIR_A_TX # Port: DLY_ADJ # Signal: in:rule=half-first:f2g_trx_dly_adj # Remap location from HP_2_20_10P to HP_2_20_10P -set_io $auto_527 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_trx_dly_adj +set_io $auto_529 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_trx_dly_adj # Module: O_DELAY # LinkedObject: dout @@ -414,7 +414,7 @@ set_io $auto_527 HP_2_20_10P -mode MODE_BP_DIR_A_TX # Port: DLY_INCDEC # Signal: in:rule=half-first:f2g_trx_dly_inc # Remap location from HP_2_20_10P to HP_2_20_10P -set_io $auto_528 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_trx_dly_inc +set_io $auto_530 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_trx_dly_inc # Module: O_DELAY # LinkedObject: dout @@ -422,7 +422,7 @@ set_io $auto_528 HP_2_20_10P -mode MODE_BP_DIR_A_TX # Port: DLY_LOAD # Signal: in:rule=half-first:f2g_trx_dly_ld # Remap location from HP_2_20_10P to HP_2_20_10P -set_io $auto_529 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_trx_dly_ld +set_io $auto_531 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_trx_dly_ld # Module: O_DELAY # LinkedObject: dout @@ -436,14 +436,14 @@ set_io $auto_529 HP_2_20_10P -mode MODE_BP_DIR_A_TX # Location: HR_5_1_0N # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_517 HR_5_1_0N -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_oe_B +set_io $auto_517 HR_5_1_0N -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_oe_B # Module: O_BUFT # LinkedObject: dout_serdes # Location: HR_2_2_1P # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_518 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_oe_A +set_io $auto_518 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_oe_A # Module: O_SERDES # LinkedObject: dout_serdes @@ -464,7 +464,7 @@ set_io $auto_518 HR_2_2_1P -mode MODE_RATE_8_A_TX # Location: HR_2_2_1P # Port: DATA_VALID # Signal: in:f2g_tx_dvalid_{A|B} -set_io $auto_530 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_dvalid_A +set_io $auto_532 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_tx_dvalid_A # Module: O_SERDES # LinkedObject: dout_serdes @@ -472,7 +472,7 @@ set_io $auto_530 HR_2_2_1P -mode MODE_RATE_8_A_TX # Port: OE_IN # Signal: in:TO_BE_DETERMINED # Skip reason: TO_BE_DETERMINED -# set_io $auto_531 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin TO_BE_DETERMINED +# set_io $auto_533 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin TO_BE_DETERMINED # Module: O_SERDES # LinkedObject: dout_serdes @@ -493,14 +493,14 @@ set_io $auto_530 HR_2_2_1P -mode MODE_RATE_8_A_TX # Location: HR_2_2_1P # Port: RST # Signal: in:f2g_trx_reset_n_{A|B} -set_io $auto_532 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_trx_reset_n_A +set_io $auto_534 HR_2_2_1P -mode MODE_RATE_8_A_TX -internal_pin f2g_trx_reset_n_A # Module: O_BUFT # LinkedObject: dout_serdes_clk_out # Location: HR_2_7_3N # Port: T # Signal: in:f2g_tx_oe_{A|B} -set_io $auto_519 HR_2_7_3N -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_oe_B +set_io $auto_519 HR_2_7_3N -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_oe_B # Module: PLL # LinkedObject: BOOT_CLOCK#0 @@ -521,7 +521,7 @@ set_io $auto_519 HR_2_7_3N -mode MODE_BP_DIR_B_TX # Location: HP_1_4_2P # Port: EN # Signal: in:f2g_in_en_{A|B} -set_io $auto_520 HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin f2g_in_en_A +set_io $auto_520 HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin f2g_in_en_A # Module: I_DDR # LinkedObject: din_n+din_p @@ -529,7 +529,7 @@ set_io $auto_520 HP_1_4_2P -mode MODE_BP_DDR_A_RX # Port: E # Signal: in:TO_BE_DETERMINED # Skip reason: TO_BE_DETERMINED -# set_io $ofab_$ibuf_enable_4 HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin TO_BE_DETERMINED +# set_io $ofab_$ibuf_enable_4 HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin TO_BE_DETERMINED # Module: I_DDR # LinkedObject: din_n+din_p @@ -537,7 +537,14 @@ set_io $auto_520 HP_1_4_2P -mode MODE_BP_DDR_A_RX # Port: R # Signal: in:TO_BE_DETERMINED # Skip reason: TO_BE_DETERMINED -# set_io $f2g_trx_reset_n_A_$ibuf_reset_4 HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin TO_BE_DETERMINED +# set_io $f2g_trx_reset_n_$ibuf_reset_4 HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin TO_BE_DETERMINED + +# Module: O_BUFT_DS +# LinkedObject: dout_n+dout_p +# Location: HP_1_8_4P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_527 HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_oe_A # Module: O_DDR # LinkedObject: dout_n+dout_p @@ -545,7 +552,7 @@ set_io $auto_520 HP_1_4_2P -mode MODE_BP_DDR_A_RX # Port: E # Signal: in:TO_BE_DETERMINED # Skip reason: TO_BE_DETERMINED -# set_io $ofab_$ibuf_enable HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin TO_BE_DETERMINED +# set_io $ofab_$ibuf_enable HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin TO_BE_DETERMINED # Module: O_DDR # LinkedObject: dout_n+dout_p @@ -553,7 +560,14 @@ set_io $auto_520 HP_1_4_2P -mode MODE_BP_DDR_A_RX # Port: R # Signal: in:TO_BE_DETERMINED # Skip reason: TO_BE_DETERMINED -# set_io $f2g_trx_reset_n_A_$ibuf_reset HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin TO_BE_DETERMINED +# set_io $f2g_trx_reset_n_$ibuf_reset HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin TO_BE_DETERMINED + +# Module: O_BUFT_DS +# LinkedObject: dout_osc_n+dout_osc_p +# Location: HP_2_22_11P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_528 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_oe_A # Module: O_DDR # LinkedObject: dout_osc_n+dout_osc_p @@ -561,7 +575,7 @@ set_io $auto_520 HP_1_4_2P -mode MODE_BP_DDR_A_RX # Port: E # Signal: in:TO_BE_DETERMINED # Skip reason: TO_BE_DETERMINED -# set_io $ofab_$ibuf_enable_2 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin TO_BE_DETERMINED +# set_io $ofab_$ibuf_enable_2 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin TO_BE_DETERMINED # Module: O_DDR # LinkedObject: dout_osc_n+dout_osc_p @@ -569,7 +583,7 @@ set_io $auto_520 HP_1_4_2P -mode MODE_BP_DDR_A_RX # Port: R # Signal: in:TO_BE_DETERMINED # Skip reason: TO_BE_DETERMINED -# set_io $f2g_trx_reset_n_A_$ibuf_reset_2 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin TO_BE_DETERMINED +# set_io $f2g_trx_reset_n_$ibuf_reset_2 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin TO_BE_DETERMINED ############# # diff --git a/tests/unittest/ModelConfig/golden/config.py b/tests/unittest/ModelConfig/golden/config.py index e90561d8b..3d8ab15f8 100644 --- a/tests/unittest/ModelConfig/golden/config.py +++ b/tests/unittest/ModelConfig/golden/config.py @@ -1,46 +1,64 @@ import re -def get_pin_info(name) : +MAX_BOOT_CLOCK_RESOURCE = 1 +hp_banks = ['HP_%d' % i for i in [1, 2]] +hr_banks = ['HR_%d' % i for i in [1, 2, 3, 5]] +all_banks = hp_banks + hr_banks +bank_pin_count = 40 +CC_index = [18, 19, 38, 39] +exclude_index = [] +pin_list = ['%s%d_%d%c' % ('CC_' if i in CC_index else '', i, i//2, 'N' if i%2 else 'P') for i in range(bank_pin_count) if i not in exclude_index] +cc_p_pin_list = [pin for pin in pin_list if (pin.find('CC_') == 0 and pin[-1] == 'P')] +g_all_pins = ['%s_%s' % (i, j) for i in all_banks for j in pin_list] +g_all_clock_pins = ['%s_%s' % (i, j) for i in all_banks for j in cc_p_pin_list] +g_all_pll_clock_pins = [pin for pin in g_all_clock_pins] +g_boot_clock_resources = 0 +g_pin_resources = {} +g_input_gearbox_width = {} +g_output_gearbox_width = {} +def parse_pin_location(location): + assert location in g_all_pins + m = re.search(r'H(P|R?)_(\d?)(|_CC?)_(\d+?)_(\d\d?)(P|N?)', location) + assert m != None + assert len(m.groups()) == 6 + type = 'HP' if m.group(1) == 'P' else ('HVL' if m.group(2) in ['1', '2'] else 'HVR') + bank = 0 if m.group(2) in ['1', '3'] else 1 + is_clock = m.group(3) == '_CC' + index = int(m.group(4)) + pair_index = int(m.group(5)) + assert pair_index == (index//2) + ab_io = 0 if (pair_index < 10) else 1 + ab_name = '%c' % (ord('A') + ab_io) + return [m, type, bank, is_clock, index, pair_index, ab_io, ab_name] +def get_peer_location(location): + (m, type, bank, is_clock, index, pair_index, ab_io, ab_name) = parse_pin_location(location) + pn = 'P' if m.group(6) == 'N' else 'N' + index = int(m.group(4)) & ~1 + index += (1 if pn == 'N' else 0) + peer_location = 'H%s_%s%s_%d_%s%s' % (m.group(1), m.group(2), m.group(3), index, m.group(5), pn) + return [m.group(6), peer_location] +def validate_data_width_parameter(location, width, gearboxes): + (self_pn, peer_location) = get_peer_location(location) + result = width >= 3 and width <= (10 if self_pn == 'P' else 5) + result = result and ((peer_location not in gearboxes) or (gearboxes[peer_location] <= 5 and width <=5)) + gearboxes[location if result else ''] = width + gearboxes.pop('', None) + return result +def get_pin_info(name): bank = 0 is_clock = False index = 0 pair_index = 0 ab_io = 0 ab_name = '' - root_bank_mux_location = '' - root_bank_mux_resource = '' - root_bank_mux_core_input_index = 0 - root_mux_input_index = 0 if name.find('BOOT_CLOCK#') == 0: type = 'BOOT_CLOCK' index = int(name[11:]) + model_name = 'hp_40x2.rc_osc_50mhz' + elif name.find('FABRIC_CLKBUF#') == 0: + type = 'FABRIC_CLKBUF' + index = int(name[14:]) + model_name = 'fclk_buf' else : - m = re.search(r'H(P|R?)_(\d?)(|_CC?)_(\d+?)_(\d\d?)(P|N?)', name) - assert m != None - assert len(m.groups()) == 6 - type = 'HP' if m.group(1) == 'P' else ('HVL' if m.group(2) in ['1', '2'] else 'HVR') - bank = 0 if m.group(2) in ['1', '3'] else 1 - is_clock = m.group(2) == '_CC' - index = int(m.group(4)) - pair_index = int(m.group(5)) - ab_io = 0 if (pair_index < 10) else 1 - ab_name = '%c' % (ord('A') + ab_io) - root_name = 'u_GBOX_HP_40X2' if type == 'HP' else ('u_GBOX_HV_40X2_VL' if type == 'HVL' else 'u_GBOX_HV_40X2_VR') - root_bank_mux_location = '%s.u_gbox_root_bank_clkmux_%d' % (root_name, bank) - root_bank_mux_resource = '%s (Bank %s)' % (root_bank_mux_location, ab_name) - root_bank_mux_core_input_index = index - (20 * ab_io) - root_mux_input_index = 0 if type == 'HP' else (8 if type == 'HVL' else 16) - root_mux_input_index += ((2 * bank) + ab_io) - return [type, bank, is_clock, index, pair_index, ab_io, ab_name, root_bank_mux_location, root_bank_mux_resource, root_bank_mux_core_input_index, root_mux_input_index] -def fclk_use_pll_resource(fclk) : - pll_resource = 0 - if fclk.find('hvl_fclk_') == 0 : - pll_resource = 0 - elif fclk.find('hvr_fclk_') == 0 : - pll_resource = 1 - elif fclk.find('hp_fclk_0') == 0 : - pll_resource = 0 - elif fclk.find('hp_fclk_1') == 0 : - pll_resource = 1 - else : - raise Exception('Unknown FCLK %s' % fclk) - return [pll_resource] + (m, type, bank, is_clock, index, pair_index, ab_io, ab_name) = parse_pin_location(name) + model_name = '%s_40x2.bank%d_hpio.gearbox_%s[%d]' % (type.lower(), bank, m.group(6), pair_index) + return [type, bank, is_clock, index, pair_index, ab_io, ab_name, model_name] diff --git a/tests/unittest/ModelConfig/golden/model_config.negative.ppdb.json b/tests/unittest/ModelConfig/golden/model_config.negative.ppdb.json index 955a63979..f37f36c93 100644 --- a/tests/unittest/ModelConfig/golden/model_config.negative.ppdb.json +++ b/tests/unittest/ModelConfig/golden/model_config.negative.ppdb.json @@ -1,77 +1,258 @@ { - "messages" : [ + "status": false, + "feature": "IO", + "messages": [ "Preparing Python file: config.py", - "Read resources", - "Validate Instances", + "Validate netlist instances", "Merge properties into instances", "Re-location instances", - "Configure Mapping file initialization", - "Validation using '__primary_validation__' rule", - "Internal error validations", + "Validate instances using '__primary_validation__' rule", + " Error: Skip module:I_BUF name:$ibuf$top.$ibuf_din10 location(s):\"\" because it failed in __pin_is_valid__ validation", + " Error: Skip module:I_BUF name:$ibuf$top.$ibuf_din20 location(s):\"\" because it failed in __pin_is_valid__ validation", + " Error: Skip module:I_BUF name:$ibuf$top.$ibuf_dinosc2 location(s):\"\" because it failed in __pin_is_valid__ validation", + " Error: Skip module:O_BUFT name:$obuf$top.$obuf_dout10 location(s):\"\" because it failed in __pin_is_valid__ validation", + " Error: Skip module:O_BUFT name:$obuf$top.$obuf_dout20 location(s):\"\" because it failed in __pin_is_valid__ validation", + " Error: Skip module:O_BUFT_DS name:o_buf_ds location(s):\"HR_2_7_3N,HR_2_4_2P\" because it failed in __pin_is_differential__ validation", + "Validate error from netlist", + " Error: Skip module:O_SERDES_CLK name:o_serdes_clk_osc location(s):\"\" because it failed in internal_error validation", "Assign instance-without-location", " Instance: boot_clock", " Object: BOOT_CLOCK#0", " Assign location for child from instance-without-location", - "Allocate FCLK routing resource", - " CLKBUF clk_buf00 (location:HP_1_CC_18_9P)", - " Route to gearbox module i_ddr00 (location:HP_1_20_10P)", - " Use FCLK: hp_fclk_0_B (sub-resource: )", - " PLL pll00 Port CLK_OUT (location:HP_1_CC_18_9P)", - " Route to gearbox module i_ddr01 (location:HR_1_20_10P)", - " Use FCLK: hvl_fclk_0_B (sub-resource: NOT_VCO)", - " CLKBUF clk_buf10 (location:HR_1_CC_18_9P)", - " Route to gearbox module i_ddr10 (location:)", - " Warning: Not able to route clock-capable pin clk_buf10 (location:HR_1_CC_18_9P) to gearbox module i_ddr10 clock. Reason: Module usage is invalid in the first place", - " Route to gearbox module i_ddr11 (location:HR_5_2_1P)", - " Warning: Not able to route clock-capable pin clk_buf10 (location:HR_1_CC_18_9P) to gearbox module i_ddr11 clock (module:I_DDR) (location:HR_5_2_1P). Reason: They are not in same physical bank", - " Route to gearbox module i_ddr12 (location:HR_1_24_12P)", - " Warning: Not able to route clock-capable pin clk_buf10 (location:HR_1_CC_18_9P) to gearbox module i_ddr12 clock (module:I_DDR) (location:HR_1_24_12P). Reason: Attemp to use FCLK: hvl_fclk_0_B, but it had been used by PLL:HP_1_CC_18_9P", - " CLKBUF $clkbuf$top.$ibuf_clk20 (location:HP_1_CC_38_19P)", - " PLL pllosc0 Port CLK_OUT (location:BOOT_CLOCK#0)", - " Route to gearbox module i_ddr_osc0 (location:HR_2_20_10P)", - " Use FCLK: hvl_fclk_1_B (sub-resource: NOT_VCO)", - " Route to gearbox module i_ddr_osc1 (location:HR_5_20_10P)", - " Warning: Not able to route clock-capable pin pllosc0 (location:BOOT_CLOCK#0) to gearbox module i_ddr_osc1 clock (module:I_DDR) (location:HR_5_20_10P). Reason: A single PLL instance cannot route from both PLL #0 and PLL#1. You need to explicitely instantiate two PLLs", - " Route to gearbox module i_ddr_osc2 (location:)", - " Warning: Not able to route PLL pllosc0 Port CLK_OUT (location:BOOT_CLOCK#0) to gearbox module i_ddr_osc2 clock. Reason: Module usage is invalid in the first place", - " PLL pllosc1 Port CLK_OUT_DIV2 (location:BOOT_CLOCK#0)", - " Warning: Not able to route PLL pllosc1 Port CLK_OUT_DIV2 (location:BOOT_CLOCK#0) to gearbox module i_ddr_osc3 clock. Reason: Only PLL output port 'CLK_OUT' can use FCLK resource", - " PLL pllosc2 Port CLK_OUT (location:BOOT_CLOCK#0)", - " Route to gearbox module i_ddr_osc4 (location:HR_1_30_15P)", - " Warning: Not able to route clock-capable pin pllosc2 (location:BOOT_CLOCK#0) to gearbox module i_ddr_osc4 clock (module:I_DDR) (location:HR_1_30_15P). Reason: Attemp to use FCLK: hvl_fclk_0_B, but it had been used by PLL:HP_1_CC_18_9P", - " CLKBUF clk_buf30 (location:HR_1_CC_38_19P)", - " PLL pll30 Port CLK_OUT (location:HR_1_CC_38_19P)", - " Route to gearbox module i_ddr30 (location:HR_2_0_0P)", - " Use FCLK: hvl_fclk_1_A (sub-resource: NOT_VCO)", - " CLKBUF clk_buf31 (location:HR_3_CC_38_19P)", - " PLL pll31 Port CLK_OUT (location:HR_3_CC_38_19P)", - " Route to gearbox module i_ddr31 (location:HR_2_2_1P)", - " Warning: Not able to route PLL pll31 Port CLK_OUT (location:HR_3_CC_38_19P) to gearbox module i_ddr31 clock (module:I_DDR) (location:HR_2_2_1P). Reason: PLL #1 (needed by HVR) cannot route to HVL", - " CLKBUF clk_buf40 (location:HR_2_CC_38_19P)", - " Route to gearbox module o_serdes_clk (location:HR_2_8_4P)", - " Warning: Not able to route clock-capable pin clk_buf40 (location:HR_2_CC_38_19P) to gearbox module o_serdes_clk clock (module:O_SERDES_CLK) (location:HR_2_8_4P). Reason: Attemp to use FCLK: hvl_fclk_1_A, but it had been used by PLL:HR_1_CC_38_19P", - "Allocate ROOT BANK routing resource (and set configuration attributes)", - " CLK_BUF clk_buf00", - " Resource: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 (Bank A)(CORE)", - " CLK_BUF $clkbuf$top.$ibuf_clk20", - " Resource: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 (Bank B)(CORE)", - "Set CLKBUF remaining configuration attributes (FCLK)", - " Set FCLK configuration attributes", - " CLKBUF clk_buf00 (location:HP_1_CC_18_9P) use hp_fclk_0_B", - " Set FCLK configuration attributes", - " Skip for HP_1_CC_38_19P", - "Allocate PLL resource (and set PLLREF configuration attributes)", - " PLL pll00 (location:HP_1_CC_18_9P) uses FCLK 'hvl_fclk_0_B'", - " Pin resource: 3, PLL FCLK requested resource: 1, PLL availability: 3", - " Use PLL: pll_0 (sub-resource: )", - " Set PLLREF configuration attributes", - " PLL pll30 (location:HR_1_CC_38_19P) uses FCLK 'hvl_fclk_1_A'", - " Pin resource: 1, PLL FCLK requested resource: 1, PLL availability: 2", - " Warning: Cannot fit in any Pin/FCLK/PLL resource", - "Set PLL remaining configuration attributes (FCLK)", - " Set FCLK configuration attributes", - " PLL pll00 (location:HP_1_CC_18_9P) use hvl_fclk_0_B", - "Validation using '__secondary_validation__' rule", + "Prepare routing resource info for fast clock", + "Prepare routing resource info for core clock", + "Solve routing", + " Feature: Fast Clock: module CLK_BUF clk_buf00 port O (location: HP_1_CC_18_9P) -> module I_DDR i_ddr00 (location: HP_1_20_10P)", + " Status: True", + " TCL Block: u_GBOX_HP_40X2.u_gbox_fclk_mux_all", + " cfg_rx_fclkio_sel_B_0: 0", + " cfg_rxclk_phase_sel_B_0: 1", + " cfg_vco_clk_sel_B_0: 0", + " Feature: Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)", + " Status: True", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 1", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " TCL Block: u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + " cfg_rx_fclkio_sel_B_0: 0", + " cfg_rxclk_phase_sel_B_0: 0", + " cfg_vco_clk_sel_B_0: 1", + " Feature: Fast Clock: module CLK_BUF clk_buf10 port O (location: HR_1_CC_18_9P) -> module I_DDR i_ddr11 (location: HR_5_2_1P)", + " Status: False", + " Msg: Fail to find any paths first round", + " Feature: Fast Clock: module CLK_BUF clk_buf10 port O (location: HR_1_CC_18_9P) -> module I_DDR i_ddr12 (location: HR_1_24_12P)", + " Status: False", + " Msg: 'Fast Clock: module CLK_BUF clk_buf10 port O (location: HR_1_CC_18_9P) -> module I_DDR i_ddr12 (location: HR_1_24_12P)' had conflict to set config mux hvl_40x2.bank0_fclk_mux_B->vco_clk_sel to value 0, had been set with value 1 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'", + " Msg: Fail to find any paths first round", + " Feature: Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc0 (location: HR_2_20_10P)", + " Status: False", + " Msg: 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc0 (location: HR_2_20_10P)' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_use_rosc to value 1, had been set with value 0 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'", + " Msg: Fail to find any paths first round", + " Feature: Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)", + " Status: True", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 1", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_1", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 1", + " TCL Block: u_GBOX_HV_40X2_VR.u_gbox_fclk_mux_all", + " cfg_rx_fclkio_sel_B_1: 0", + " cfg_rxclk_phase_sel_B_1: 0", + " cfg_vco_clk_sel_B_1: 1", + " Feature: Fast Clock: module PLL pllosc1 port CLK_OUT_DIV2 (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc3 (location: HR_5_22_11P)", + " Status: False", + " Msg: Fail to find any paths first round", + " Feature: Fast Clock: module PLL pllosc2 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc4 (location: HR_1_30_15P)", + " Status: False", + " Msg: 'Fast Clock: module PLL pllosc2 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc4 (location: HR_1_30_15P)' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_use_rosc to value 1, had been set with value 0 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'", + " Msg: Fail to find any paths first round", + " Feature: Fast Clock: module PLL pll30 port FAST_CLK (location: HR_1_CC_38_19P) -> module I_DDR i_ddr30 (location: HR_2_0_0P)", + " Status: False", + " Msg: 'Fast Clock: module PLL pll30 port FAST_CLK (location: HR_1_CC_38_19P) -> module I_DDR i_ddr30 (location: HR_2_0_0P)' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_hv_rx_io_sel to value 1, had been set with value 0 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'", + " Msg: Fail to find any paths first round", + " Feature: Fast Clock: module PLL pll31 port CLK_OUT (location: HR_3_CC_38_19P) -> module I_DDR i_ddr31 (location: HR_2_2_1P)", + " Status: False", + " Msg: Fail to find any paths first round", + " Feature: Fast Clock: module CLK_BUF clk_buf40 port O (location: HR_2_CC_38_19P) -> module O_SERDES_CLK o_serdes_clk (location: HR_2_8_4P)", + " Status: True", + " TCL Block: HR_2_8_4P", + " TX_CLOCK_IO: 1", + " TCL Block: u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + " cfg_rx_fclkio_sel_A_1: 1", + " cfg_rxclk_phase_sel_A_1: 1", + " cfg_vco_clk_sel_A_1: 0", + " Feature: Core Clock: module CLK_BUF clk_buf00 port O (location: HP_1_CC_18_9P) -> core clock slot[0]", + " Status: True", + " TCL Block: HP_1_CC_18_9P", + " RX_CLOCK_IO: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0", + " ROOT_MUX_SEL: 0", + " TCL Block: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0", + " CORE_CLK_ROOT_SEL_A: 18", + " Feature: Core Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> core clock slot[1]", + " Status: True", + " Msg: 'Core Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> core clock slot[1]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_rosc to value 0, had been set with value 1 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 1", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1", + " ROOT_MUX_SEL: 32", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " Feature: Core Clock: module PLL pll00 port CLK_OUT_DIV2 (location: HP_1_CC_18_9P) -> core clock slot[2]", + " Status: True", + " Msg: 'Core Clock: module PLL pll00 port CLK_OUT_DIV2 (location: HP_1_CC_18_9P) -> core clock slot[2]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_rosc to value 0, had been set with value 1 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 1", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2", + " ROOT_MUX_SEL: 33", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " Feature: Core Clock: module PLL pll00 port CLK_OUT_DIV3 (location: HP_1_CC_18_9P) -> core clock slot[3]", + " Status: True", + " Msg: 'Core Clock: module PLL pll00 port CLK_OUT_DIV3 (location: HP_1_CC_18_9P) -> core clock slot[3]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_rosc to value 0, had been set with value 1 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 1", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3", + " ROOT_MUX_SEL: 34", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " Feature: Core Clock: module PLL pll00 port CLK_OUT_DIV4 (location: HP_1_CC_18_9P) -> core clock slot[4]", + " Status: True", + " Msg: 'Core Clock: module PLL pll00 port CLK_OUT_DIV4 (location: HP_1_CC_18_9P) -> core clock slot[4]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_rosc to value 0, had been set with value 1 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 1", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4", + " ROOT_MUX_SEL: 35", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " Feature: Core Clock: module CLK_BUF clk_buf10 port O (location: HR_1_CC_18_9P) -> core clock slot[5]", + " Status: True", + " TCL Block: HR_1_CC_18_9P", + " RX_CLOCK_IO: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5", + " ROOT_MUX_SEL: 8", + " TCL Block: u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0", + " CORE_CLK_ROOT_SEL_A: 18", + " Feature: Core Clock: module CLK_BUF $clkbuf$top.$ibuf_clk20 port O (location: HP_1_CC_38_19P) -> core clock slot[6]", + " Status: True", + " TCL Block: HP_1_CC_38_19P", + " RX_CLOCK_IO: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6", + " ROOT_MUX_SEL: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0", + " CORE_CLK_ROOT_SEL_B: 18", + " Feature: Core Clock: module PLL pll31 port CLK_OUT (location: HR_3_CC_38_19P) -> core clock slot[7]", + " Status: False", + " Msg: 'Core Clock: module PLL pll31 port CLK_OUT (location: HR_3_CC_38_19P) -> core clock slot[7]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_hv_rx_io_sel to value 1, had been set with value 0 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'", + " Msg: Fail to find any paths first round", "Set configuration attributes", " Module: I_BUF ($ibuf$top.$ibuf_clk00)", " Object: clk00", @@ -87,30 +268,9 @@ " Property", " Rule CLK_BUF.GBOX_TOP", " Match", - " Rule CLK_BUF.ROOT_BANK_CLKMUX", - " Match", - " Rule CLK_BUF.ROOT_MUX", - " Match", " Module: PLL (pll00)", " Object: clk00", " Parameter", - " Rule PLL.PLL", - " Match", - " Defined function: parse_pll_parameter", - " Rule PLL.PLLREF_MUX", - " Match", - " Rule PLL.ROOT_MUX0", - " Match", - " Defined function: parse_pll_root_mux", - " Rule PLL.ROOT_MUX1", - " Match", - " Defined function: parse_pll_root_mux", - " Rule PLL.ROOT_MUX2", - " Match", - " Defined function: parse_pll_root_mux", - " Rule PLL.ROOT_MUX3", - " Match", - " Defined function: parse_pll_root_mux", " Property", " Module: I_BUF ($ibuf$top.$ibuf_clk10)", " Object: clk10", @@ -120,6 +280,12 @@ " Property", " Rule I_BUF.IOSTANDARD", " Mismatch", + " Module: CLK_BUF (clk_buf10)", + " Object: clk10", + " Parameter", + " Property", + " Rule CLK_BUF.GBOX_TOP", + " Match", " Module: I_BUF ($ibuf$top.$ibuf_clk20)", " Object: clk20", " Parameter", @@ -134,10 +300,6 @@ " Property", " Rule CLK_BUF.GBOX_TOP", " Match", - " Rule CLK_BUF.ROOT_BANK_CLKMUX", - " Match", - " Rule CLK_BUF.ROOT_MUX", - " Match", " Module: I_BUF ($ibuf$top.$ibuf_din00)", " Object: din00", " Parameter", @@ -264,8 +426,6 @@ " Defined function: parse_o_serdes_clk_phase_parameter", " Rule O_SERDES_CLK.DDR_MODE", " Match", - " Rule O_SERDES_CLK.IO", - " Match", " Property", " Module: O_BUFT ($obuf$top.$obuf_dinoutosc)", " Object: dinoutosc", @@ -324,8 +484,18 @@ " Module: BOOT_CLOCK (boot_clock)", " Object: BOOT_CLOCK#0", " Parameter", - " Rule BOOT_CLOCK", - " Mismatch", + " Property", + " Module: PLL (pllosc0)", + " Object: BOOT_CLOCK#0", + " Parameter", + " Property", + " Module: PLL (pllosc1)", + " Object: BOOT_CLOCK#0", + " Parameter", + " Property", + " Module: PLL (pllosc2)", + " Object: BOOT_CLOCK#0", + " Parameter", " Property", " Module: I_BUF (i_buf30)", " Object: clk30", @@ -341,10 +511,10 @@ " Property", " Rule CLK_BUF.GBOX_TOP", " Match", - " Rule CLK_BUF.ROOT_BANK_CLKMUX", - " Mismatch", - " Rule CLK_BUF.ROOT_MUX", - " Mismatch", + " Module: PLL (pll30)", + " Object: clk30", + " Parameter", + " Property", " Module: I_BUF (i_buf31)", " Object: clk31", " Parameter", @@ -359,10 +529,10 @@ " Property", " Rule CLK_BUF.GBOX_TOP", " Match", - " Rule CLK_BUF.ROOT_BANK_CLKMUX", - " Mismatch", - " Rule CLK_BUF.ROOT_MUX", - " Mismatch", + " Module: PLL (pll31)", + " Object: clk31", + " Parameter", + " Property", " Module: I_BUF (i_buf40)", " Object: clk40", " Parameter", @@ -371,6 +541,12 @@ " Property", " Rule I_BUF.IOSTANDARD", " Mismatch", + " Module: CLK_BUF (clk_buf40)", + " Object: clk40", + " Parameter", + " Property", + " Rule CLK_BUF.GBOX_TOP", + " Match", " Module: I_BUF_DS (i_buf_ds30)", " Object: din30_n", " Parameter", @@ -423,2740 +599,2997 @@ " Rule I_DDR", " Match", " Property", - "Warning: Generated IO bitstream is invalid" + "Info: Model bitstream generation: model_config.negative.ppdb.json", + "Warning: Skip $ibuf$top.$ibuf_clk00 [I_BUF] because the config attribute is empty", + "Warning: Skip pll00 [PLL] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_clk10 [I_BUF] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_clk20 [I_BUF] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_din00 [I_BUF] because the config attribute is empty", + "Warning: Skip i_ddr00 [I_DDR] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_din01 [I_BUF] because the config attribute is empty", + "Warning: Skip i_ddr01 [I_DDR] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_din10 [I_BUF] because the location is not set", + "Warning: Skip $ibuf$top.$ibuf_din10 [I_BUF] because the location is not set", + "Warning: Skip i_ddr10 [I_DDR] because the location is not set", + "Warning: Skip i_ddr10 [I_DDR] because the location is not set", + "Warning: Skip $ibuf$top.$ibuf_din11 [I_BUF] because the config attribute is empty", + "Warning: Skip i_ddr11 [I_DDR] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_din12 [I_BUF] because the config attribute is empty", + "Warning: Skip i_ddr12 [I_DDR] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_din20 [I_BUF] because the location is not set", + "Warning: Skip $ibuf$top.$ibuf_din20 [I_BUF] because the location is not set", + "Warning: Skip $ibuf$top.$ibuf_dinosc0 [I_BUF] because the config attribute is empty", + "Warning: Skip i_ddr_osc0 [I_DDR] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_dinosc1 [I_BUF] because the config attribute is empty", + "Warning: Skip i_ddr_osc1 [I_DDR] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_dinosc2 [I_BUF] because the location is not set", + "Warning: Skip $ibuf$top.$ibuf_dinosc2 [I_BUF] because the location is not set", + "Warning: Skip i_ddr_osc2 [I_DDR] because the location is not set", + "Warning: Skip i_ddr_osc2 [I_DDR] because the location is not set", + "Warning: Skip $ibuf$top.$ibuf_dinosc3 [I_BUF] because the config attribute is empty", + "Warning: Skip i_ddr_osc3 [I_DDR] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_dinosc4 [I_BUF] because the config attribute is empty", + "Warning: Skip i_ddr_osc4 [I_DDR] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_clk_out [O_BUFT] because the config attribute is empty", + "Warning: Skip o_serdes_clk [O_SERDES_CLK] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_clk_out_osc [O_BUFT] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_clk_out_osc [O_BUFT] because the config attribute is empty", + "Warning: Skip o_serdes_clk_osc [O_SERDES_CLK] because the config attribute is empty", + "Warning: Skip o_serdes_clk_osc [O_SERDES_CLK] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dinoutosc [O_BUFT] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dout00 [O_BUFT] because the config attribute is empty", + "Warning: Skip o_ddr00 [O_DDR] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dout01 [O_BUFT] because the config attribute is empty", + "Warning: Skip o_ddr01 [O_DDR] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dout10 [O_BUFT] because the location is not set", + "Warning: Skip $obuf$top.$obuf_dout10 [O_BUFT] because the location is not set", + "Warning: Skip o_ddr10 [O_DDR] because the location is not set", + "Warning: Skip o_ddr10 [O_DDR] because the location is not set", + "Warning: Skip $obuf$top.$obuf_dout11 [O_BUFT] because the config attribute is empty", + "Warning: Skip o_ddr11 [O_DDR] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dout12 [O_BUFT] because the config attribute is empty", + "Warning: Skip o_ddr12 [O_DDR] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dout20 [O_BUFT] because the location is not set", + "Warning: Skip $obuf$top.$obuf_dout20 [O_BUFT] because the location is not set", + "Warning: Skip boot_clock [BOOT_CLOCK] because the config attribute is empty", + "Warning: Skip boot_clock [BOOT_CLOCK] because the config attribute is empty", + "Warning: Skip pllosc0 [PLL] because the config attribute is empty", + "Warning: Skip pllosc1 [PLL] because the config attribute is empty", + "Warning: Skip pllosc1 [PLL] because the config attribute is empty", + "Warning: Skip pllosc2 [PLL] because the config attribute is empty", + "Warning: Skip pllosc2 [PLL] because the config attribute is empty", + "Warning: Skip i_buf30 [I_BUF] because the config attribute is empty", + "Warning: Skip clk_buf30 [CLK_BUF] because the config attribute is empty", + "Warning: Skip pll30 [PLL] because the config attribute is empty", + "Warning: Skip pll30 [PLL] because the config attribute is empty", + "Warning: Skip i_buf31 [I_BUF] because the config attribute is empty", + "Warning: Skip clk_buf31 [CLK_BUF] because the config attribute is empty", + "Warning: Skip pll31 [PLL] because the config attribute is empty", + "Warning: Skip pll31 [PLL] because the config attribute is empty", + "Warning: Skip i_buf40 [I_BUF] because the config attribute is empty", + "Warning: Skip i_buf_ds30 [I_BUF_DS] because the config attribute is empty", + "Warning: Skip i_ddr30 [I_DDR] because the config attribute is empty", + "Warning: Skip i_buf_ds31 [I_BUF_DS] because the config attribute is empty", + "Warning: Skip i_ddr31 [I_DDR] because the config attribute is empty", + "Warning: Skip o_buf_ds [O_BUFT_DS] because the config attribute is empty", + "Warning: Skip o_buf_ds [O_BUFT_DS] because the config attribute is empty", + "Warning: Skip o_buf_ds [O_BUFT_DS] because the config attribute is empty", + "Warning: Skip o_ddr3x [O_DDR] because the config attribute is empty", + "Warning: Skip o_ddr3x [O_DDR] because the config attribute is empty", + "Warning: Skip o_ddr3x [O_DDR] because the config attribute is empty", + "Warning: Generated IO bitstream is invalid" ], - "instances" : [ + "instances": [ { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk00", - "location_object" : "clk00", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk00", - "linked_objects" : { - "clk00" : { - "location" : "HP_1_CC_18_9P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk00", + "location_object": "clk00", + "location": "HP_1_CC_18_9P", + "linked_object": "clk00", + "linked_objects": { + "clk00": { + "location": "HP_1_CC_18_9P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "clk00", - "O" : "$ibuf_clk00" + "connectivity": { + "I": "clk00", + "O": "$ibuf_clk00" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf00", - "location_object" : "clk00", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk00", - "linked_objects" : { - "clk00" : { - "location" : "HP_1_CC_18_9P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "0" - }, - "config_attributes" : [ - { - "__location__" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", - "cfg_rx_fclkio_sel_B_0" : "0" - }, - { - "__location__" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", - "cfg_rxclk_phase_sel_B_0" : "1" - }, - { - "__location__" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", - "cfg_vco_clk_sel_B_0" : "0" - }, - { - "CLK_BUF" : "GBOX_TOP_SRC==DEFAULT" - }, - { - "CLK_BUF" : "ROOT_BANK_SRC==A --#MUX=18", - "__location__" : "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0" - }, - { - "ROOT_MUX_SEL" : "0", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0" + "module": "CLK_BUF", + "name": "clk_buf00", + "location_object": "clk00", + "location": "HP_1_CC_18_9P", + "linked_object": "clk00", + "linked_objects": { + "clk00": { + "location": "HP_1_CC_18_9P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "0" + }, + "config_attributes": [ + { + "CLK_BUF": "GBOX_TOP_SRC==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$ibuf_clk00", - "O" : "clkbuf00" + "connectivity": { + "I": "$ibuf_clk00", + "O": "clkbuf00" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "0" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "0" }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ "PLL" ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "i_ddr00" ] }, - "route_clock_result" : { - "O" : [ - "Use FCLK: hp_fclk_0_B (sub-resource: )" + "route_clock_result": { + "O": [ + "Pass: " ] }, - "errors" : [ + "errors": [ ], - "__AB__" : "A", - "__ROOT_BANK_MUX_LOCATION__" : "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0", - "__ROOT_BANK_MUX__" : "18", - "__ROOT_MUX__" : "0", - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__clock_pin_is_valid__,__check_fabric_clock_resource__,__update_fabric_clock_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__clock_pin_is_valid__", + "config_attributes": [ + { + "__location__": "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", + "cfg_rx_fclkio_sel_B_0": "0", + "cfg_rxclk_phase_sel_B_0": "1", + "cfg_vco_clk_sel_B_0": "0" + }, + { + "RX_CLOCK_IO": "1", + "__location__": "HP_1_CC_18_9P" + }, + { + "ROOT_MUX_SEL": "0", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0" + }, + { + "CORE_CLK_ROOT_SEL_A": "18", + "__location__": "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0" + } + ] }, { - "module" : "PLL", - "name" : "pll00", - "location_object" : "clk00", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk00", - "linked_objects" : { - "clk00" : { - "location" : "HP_1_CC_18_9P", - "properties" : { - "OUT0_ROUTE_TO_FABRIC_CLK" : "1", - "OUT1_ROUTE_TO_FABRIC_CLK" : "2", - "OUT2_ROUTE_TO_FABRIC_CLK" : "3", - "OUT3_ROUTE_TO_FABRIC_CLK" : "4" - }, - "config_attributes" : [ - { - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", - "cfg_rx_fclkio_sel_B_0" : "0" - }, - { - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", - "cfg_rxclk_phase_sel_B_0" : "0" - }, - { - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", - "cfg_vco_clk_sel_B_0" : "1" - }, - { - "PLL" : "PLL_SRC==DEFAULT", - "__location__" : "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", - "pll_FBDIV" : "16", - "pll_PLLEN" : "1", - "pll_POSTDIV1" : "2", - "pll_POSTDIV2" : "2", - "pll_REFDIV" : "1" - }, - { - "PLL" : "PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0", - "__location__" : "u_GBOX_HP_40X2.u_gbox_pll_refmux_0" - }, - { - "ROOT_MUX_SEL" : "32", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1" - }, - { - "ROOT_MUX_SEL" : "33", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2" - }, - { - "ROOT_MUX_SEL" : "34", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3" - }, - { - "ROOT_MUX_SEL" : "35", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4" - } + "module": "PLL", + "name": "pll00", + "location_object": "clk00", + "location": "HP_1_CC_18_9P", + "linked_object": "clk00", + "linked_objects": { + "clk00": { + "location": "HP_1_CC_18_9P", + "properties": { + "OUT0_ROUTE_TO_FABRIC_CLK": "1", + "OUT1_ROUTE_TO_FABRIC_CLK": "2", + "OUT2_ROUTE_TO_FABRIC_CLK": "3", + "OUT3_ROUTE_TO_FABRIC_CLK": "4" + }, + "config_attributes": [ ] } }, - "connectivity" : { - "CLK_IN" : "clkbuf00", - "CLK_OUT" : "pll00_clk1", - "CLK_OUT_DIV2" : "pll00_clk2", - "CLK_OUT_DIV3" : "pll00_clk3", - "CLK_OUT_DIV4" : "pll00_clk4" - }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "OUT0_ROUTE_TO_FABRIC_CLK" : "1", - "OUT1_ROUTE_TO_FABRIC_CLK" : "2", - "OUT2_ROUTE_TO_FABRIC_CLK" : "3", - "OUT3_ROUTE_TO_FABRIC_CLK" : "4", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" - }, - "flags" : [ + "connectivity": { + "CLK_IN": "clkbuf00", + "CLK_OUT": "pll00_clk1", + "CLK_OUT_DIV2": "pll00_clk2", + "CLK_OUT_DIV3": "pll00_clk3", + "CLK_OUT_DIV4": "pll00_clk4" + }, + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "1", + "OUT1_ROUTE_TO_FABRIC_CLK": "2", + "OUT2_ROUTE_TO_FABRIC_CLK": "3", + "OUT3_ROUTE_TO_FABRIC_CLK": "4", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" + }, + "flags": [ "PLL" ], - "pre_primitive" : "CLK_BUF", - "post_primitives" : [ + "pre_primitive": "CLK_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_ddr01" ] }, - "route_clock_result" : { - "CLK_OUT" : [ - "Use FCLK: hvl_fclk_0_B (sub-resource: NOT_VCO)" + "route_clock_result": { + "CLK_OUT": [ + "Pass: " ] }, - "errors" : [ - ], - "__BANK__" : "0", - "__DIV__" : "0", - "__PIN__" : "0", - "__SRC__" : "HP", - "__pll_enable__" : "1", - "__pll_resource__" : "0", - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pll_clock_pin_is_valid__,__check_fabric_clock_resource__,__check_pll_parameter__,__update_fabric_clock_resource__" + "errors": [ + ], + "__validation__": true, + "__validation_msg__": "Pass:__pll_clock_pin_is_valid__,__check_pll_parameter__", + "config_attributes": [ + { + "__location__": "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + "pll_DACEN": "DACEN_0", + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSMEN": "DSMEN_0", + "pll_FBDIV": "16", + "pll_FRAC": "0", + "pll_PLLEN": "1", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_REFDIV": "1" + }, + { + "__location__": "u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_use_div": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + }, + { + "__location__": "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + "cfg_rx_fclkio_sel_B_0": "0", + "cfg_rxclk_phase_sel_B_0": "0", + "cfg_vco_clk_sel_B_0": "1" + }, + { + "ROOT_MUX_SEL": "32", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1" + }, + { + "ROOT_MUX_SEL": "33", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2" + }, + { + "ROOT_MUX_SEL": "34", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3" + }, + { + "ROOT_MUX_SEL": "35", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4" + } + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk10", - "location_object" : "clk10", - "location" : "HR_1_CC_18_9P", - "linked_object" : "clk10", - "linked_objects" : { - "clk10" : { - "location" : "HR_1_CC_18_9P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk10", + "location_object": "clk10", + "location": "HR_1_CC_18_9P", + "linked_object": "clk10", + "linked_objects": { + "clk10": { + "location": "HR_1_CC_18_9P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "clk10", - "O" : "$ibuf_clk10" + "connectivity": { + "I": "clk10", + "O": "$ibuf_clk10" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf10", - "location_object" : "clk10", - "location" : "HR_1_CC_18_9P", - "linked_object" : "clk10", - "linked_objects" : { - "clk10" : { - "location" : "HR_1_CC_18_9P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "5" - }, - "config_attributes" : [ + "module": "CLK_BUF", + "name": "clk_buf10", + "location_object": "clk10", + "location": "HR_1_CC_18_9P", + "linked_object": "clk10", + "linked_objects": { + "clk10": { + "location": "HR_1_CC_18_9P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "5" + }, + "config_attributes": [ + { + "CLK_BUF": "GBOX_TOP_SRC==DEFAULT" + } ] } }, - "connectivity" : { - "I" : "$ibuf_clk10", - "O" : "clkbuf10" + "connectivity": { + "I": "$ibuf_clk10", + "O": "clkbuf10" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "5" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "5" }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "i_ddr10", "i_ddr11", "i_ddr12" ] }, - "route_clock_result" : { - "O" : [ - "Not able to route clock-capable pin clk_buf10 (location:HR_1_CC_18_9P) to gearbox module i_ddr10 clock. Reason: Module usage is invalid in the first place", - "Not able to route clock-capable pin clk_buf10 (location:HR_1_CC_18_9P) to gearbox module i_ddr11 clock (module:I_DDR) (location:HR_5_2_1P). Reason: They are not in same physical bank", - "Not able to route clock-capable pin clk_buf10 (location:HR_1_CC_18_9P) to gearbox module i_ddr12 clock (module:I_DDR) (location:HR_1_24_12P). Reason: Attemp to use FCLK: hvl_fclk_0_B, but it had been used by PLL:HP_1_CC_18_9P" + "route_clock_result": { + "O": [ + "Error: Destination gearbox is invalid", + "Error: Fail to find any paths first round", + "Error: 'Fast Clock: module CLK_BUF clk_buf10 port O (location: HR_1_CC_18_9P) -> module I_DDR i_ddr12 (location: HR_1_24_12P)' had conflict to set config mux hvl_40x2.bank0_fclk_mux_B->vco_clk_sel to value 0, had been set with value 1 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'; Fail to find any paths first round" ] }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail to route the clock" + "__validation__": true, + "__validation_msg__": "Pass:__clock_pin_is_valid__", + "config_attributes": [ + { + "RX_CLOCK_IO": "1", + "__location__": "HR_1_CC_18_9P" + }, + { + "ROOT_MUX_SEL": "8", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5" + }, + { + "CORE_CLK_ROOT_SEL_A": "18", + "__location__": "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0" + } + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk20", - "location_object" : "clk20", - "location" : "HP_1_CC_38_19P", - "linked_object" : "clk20", - "linked_objects" : { - "clk20" : { - "location" : "HP_1_CC_38_19P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk20", + "location_object": "clk20", + "location": "HP_1_CC_38_19P", + "linked_object": "clk20", + "linked_objects": { + "clk20": { + "location": "HP_1_CC_38_19P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "clk20", - "O" : "$ibuf_clk20" + "connectivity": { + "I": "clk20", + "O": "$ibuf_clk20" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "CLK_BUF", - "name" : "$clkbuf$top.$ibuf_clk20", - "location_object" : "clk20", - "location" : "HP_1_CC_38_19P", - "linked_object" : "clk20", - "linked_objects" : { - "clk20" : { - "location" : "HP_1_CC_38_19P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "6" - }, - "config_attributes" : [ - { - "CLK_BUF" : "GBOX_TOP_SRC==DEFAULT" - }, - { - "CLK_BUF" : "ROOT_BANK_SRC==B --#MUX=18", - "__location__" : "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0" - }, - { - "ROOT_MUX_SEL" : "1", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6" + "module": "CLK_BUF", + "name": "$clkbuf$top.$ibuf_clk20", + "location_object": "clk20", + "location": "HP_1_CC_38_19P", + "linked_object": "clk20", + "linked_objects": { + "clk20": { + "location": "HP_1_CC_38_19P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "6" + }, + "config_attributes": [ + { + "CLK_BUF": "GBOX_TOP_SRC==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$ibuf_clk20", - "O" : "$clk_buf_$ibuf_clk20" + "connectivity": { + "I": "$ibuf_clk20", + "O": "$clk_buf_$ibuf_clk20" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "6" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "6" }, - "flags" : [ + "flags": [ "CLK_BUF", "PIN_CLOCK_CORE_ONLY" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__AB__" : "B", - "__ROOT_BANK_MUX_LOCATION__" : "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0", - "__ROOT_BANK_MUX__" : "18", - "__ROOT_MUX__" : "1", - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__clock_pin_is_valid__,__check_fabric_clock_resource__,__update_fabric_clock_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__clock_pin_is_valid__", + "config_attributes": [ + { + "RX_CLOCK_IO": "1", + "__location__": "HP_1_CC_38_19P" + }, + { + "ROOT_MUX_SEL": "1", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6" + }, + { + "CORE_CLK_ROOT_SEL_B": "18", + "__location__": "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0" + } + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din00", - "location_object" : "din00", - "location" : "HP_1_20_10P", - "linked_object" : "din00", - "linked_objects" : { - "din00" : { - "location" : "HP_1_20_10P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din00", + "location_object": "din00", + "location": "HP_1_20_10P", + "linked_object": "din00", + "linked_objects": { + "din00": { + "location": "HP_1_20_10P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "din00", - "O" : "$ibuf_din00" + "connectivity": { + "I": "din00", + "O": "$ibuf_din00" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr00", - "location_object" : "din00", - "location" : "HP_1_20_10P", - "linked_object" : "din00", - "linked_objects" : { - "din00" : { - "location" : "HP_1_20_10P", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr00", + "location_object": "din00", + "location": "HP_1_20_10P", + "linked_object": "din00", + "linked_objects": { + "din00": { + "location": "HP_1_20_10P", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "clkbuf00", - "D" : "$ibuf_din00" + "connectivity": { + "C": "clkbuf00", + "D": "$ibuf_din00" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din01", - "location_object" : "din01", - "location" : "HR_1_20_10P", - "linked_object" : "din01", - "linked_objects" : { - "din01" : { - "location" : "HR_1_20_10P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din01", + "location_object": "din01", + "location": "HR_1_20_10P", + "linked_object": "din01", + "linked_objects": { + "din01": { + "location": "HR_1_20_10P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "din01", - "O" : "$ibuf_din01" + "connectivity": { + "I": "din01", + "O": "$ibuf_din01" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr01", - "location_object" : "din01", - "location" : "HR_1_20_10P", - "linked_object" : "din01", - "linked_objects" : { - "din01" : { - "location" : "HR_1_20_10P", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr01", + "location_object": "din01", + "location": "HR_1_20_10P", + "linked_object": "din01", + "linked_objects": { + "din01": { + "location": "HR_1_20_10P", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pll00_clk1", - "D" : "$ibuf_din01" + "connectivity": { + "C": "pll00_clk1", + "D": "$ibuf_din01" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din10", - "location_object" : "din10", - "location" : "", - "linked_object" : "din10", - "linked_objects" : { - "din10" : { - "location" : "", - "properties" : { - }, - "config_attributes" : [ + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din10", + "location_object": "din10", + "location": "", + "linked_object": "din10", + "linked_objects": { + "din10": { + "location": "", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "I" : "din10", - "O" : "$ibuf_din10" + "connectivity": { + "I": "din10", + "O": "$ibuf_din10" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail:__pin_is_valid__" + "__validation__": false, + "__validation_msg__": "Fail:__pin_is_valid__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr10", - "location_object" : "din10", - "location" : "", - "linked_object" : "din10", - "linked_objects" : { - "din10" : { - "location" : "", - "properties" : { - }, - "config_attributes" : [ + "module": "I_DDR", + "name": "i_ddr10", + "location_object": "din10", + "location": "", + "linked_object": "din10", + "linked_objects": { + "din10": { + "location": "", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "C" : "clkbuf10", - "D" : "$ibuf_din10" + "connectivity": { + "C": "clkbuf10", + "D": "$ibuf_din10" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Invalidated because other instance in the chain is invalid" + "__validation__": false, + "__validation_msg__": "Invalidated because other instance in the chain is invalid", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din11", - "location_object" : "din11", - "location" : "HR_5_2_1P", - "linked_object" : "din11", - "linked_objects" : { - "din11" : { - "location" : "HR_5_2_1P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din11", + "location_object": "din11", + "location": "HR_5_2_1P", + "linked_object": "din11", + "linked_objects": { + "din11": { + "location": "HR_5_2_1P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "din11", - "O" : "$ibuf_din11" + "connectivity": { + "I": "din11", + "O": "$ibuf_din11" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr11", - "location_object" : "din11", - "location" : "HR_5_2_1P", - "linked_object" : "din11", - "linked_objects" : { - "din11" : { - "location" : "HR_5_2_1P", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr11", + "location_object": "din11", + "location": "HR_5_2_1P", + "linked_object": "din11", + "linked_objects": { + "din11": { + "location": "HR_5_2_1P", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "clkbuf10", - "D" : "$ibuf_din11" + "connectivity": { + "C": "clkbuf10", + "D": "$ibuf_din11" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din12", - "location_object" : "din12", - "location" : "HR_1_24_12P", - "linked_object" : "din12", - "linked_objects" : { - "din12" : { - "location" : "HR_1_24_12P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din12", + "location_object": "din12", + "location": "HR_1_24_12P", + "linked_object": "din12", + "linked_objects": { + "din12": { + "location": "HR_1_24_12P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "din12", - "O" : "$ibuf_din12" + "connectivity": { + "I": "din12", + "O": "$ibuf_din12" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr12", - "location_object" : "din12", - "location" : "HR_1_24_12P", - "linked_object" : "din12", - "linked_objects" : { - "din12" : { - "location" : "HR_1_24_12P", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr12", + "location_object": "din12", + "location": "HR_1_24_12P", + "linked_object": "din12", + "linked_objects": { + "din12": { + "location": "HR_1_24_12P", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "clkbuf10", - "D" : "$ibuf_din12" + "connectivity": { + "C": "clkbuf10", + "D": "$ibuf_din12" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din20", - "location_object" : "din20", - "location" : "", - "linked_object" : "din20", - "linked_objects" : { - "din20" : { - "location" : "", - "properties" : { - }, - "config_attributes" : [ + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din20", + "location_object": "din20", + "location": "", + "linked_object": "din20", + "linked_objects": { + "din20": { + "location": "", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "I" : "din20", - "O" : "$ibuf_din20" + "connectivity": { + "I": "din20", + "O": "$ibuf_din20" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail:__pin_is_valid__" + "__validation__": false, + "__validation_msg__": "Fail:__pin_is_valid__", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc0", - "location_object" : "dinosc0", - "location" : "HR_2_20_10P", - "linked_object" : "dinosc0", - "linked_objects" : { - "dinosc0" : { - "location" : "HR_2_20_10P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc0", + "location_object": "dinosc0", + "location": "HR_2_20_10P", + "linked_object": "dinosc0", + "linked_objects": { + "dinosc0": { + "location": "HR_2_20_10P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "dinosc0", - "O" : "$ibuf_dinosc0" + "connectivity": { + "I": "dinosc0", + "O": "$ibuf_dinosc0" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc0", - "location_object" : "dinosc0", - "location" : "HR_2_20_10P", - "linked_object" : "dinosc0", - "linked_objects" : { - "dinosc0" : { - "location" : "HR_2_20_10P", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr_osc0", + "location_object": "dinosc0", + "location": "HR_2_20_10P", + "linked_object": "dinosc0", + "linked_objects": { + "dinosc0": { + "location": "HR_2_20_10P", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pllosc0_clk0", - "D" : "$ibuf_dinosc0" + "connectivity": { + "C": "pllosc0_clk0", + "D": "$ibuf_dinosc0" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc1", - "location_object" : "dinosc1", - "location" : "HR_5_20_10P", - "linked_object" : "dinosc1", - "linked_objects" : { - "dinosc1" : { - "location" : "HR_5_20_10P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc1", + "location_object": "dinosc1", + "location": "HR_5_20_10P", + "linked_object": "dinosc1", + "linked_objects": { + "dinosc1": { + "location": "HR_5_20_10P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "dinosc1", - "O" : "$ibuf_dinosc1" + "connectivity": { + "I": "dinosc1", + "O": "$ibuf_dinosc1" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc1", - "location_object" : "dinosc1", - "location" : "HR_5_20_10P", - "linked_object" : "dinosc1", - "linked_objects" : { - "dinosc1" : { - "location" : "HR_5_20_10P", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr_osc1", + "location_object": "dinosc1", + "location": "HR_5_20_10P", + "linked_object": "dinosc1", + "linked_objects": { + "dinosc1": { + "location": "HR_5_20_10P", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pllosc0_clk0", - "D" : "$ibuf_dinosc1" + "connectivity": { + "C": "pllosc0_clk0", + "D": "$ibuf_dinosc1" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc2", - "location_object" : "dinosc2", - "location" : "", - "linked_object" : "dinosc2", - "linked_objects" : { - "dinosc2" : { - "location" : "", - "properties" : { - }, - "config_attributes" : [ + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc2", + "location_object": "dinosc2", + "location": "", + "linked_object": "dinosc2", + "linked_objects": { + "dinosc2": { + "location": "", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "I" : "dinosc2", - "O" : "$ibuf_dinosc2" + "connectivity": { + "I": "dinosc2", + "O": "$ibuf_dinosc2" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail:__pin_is_valid__" + "__validation__": false, + "__validation_msg__": "Fail:__pin_is_valid__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc2", - "location_object" : "dinosc2", - "location" : "", - "linked_object" : "dinosc2", - "linked_objects" : { - "dinosc2" : { - "location" : "", - "properties" : { - }, - "config_attributes" : [ + "module": "I_DDR", + "name": "i_ddr_osc2", + "location_object": "dinosc2", + "location": "", + "linked_object": "dinosc2", + "linked_objects": { + "dinosc2": { + "location": "", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "C" : "pllosc0_clk0", - "D" : "$ibuf_dinosc2" + "connectivity": { + "C": "pllosc0_clk0", + "D": "$ibuf_dinosc2" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Invalidated because other instance in the chain is invalid" + "__validation__": false, + "__validation_msg__": "Invalidated because other instance in the chain is invalid", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc3", - "location_object" : "dinosc3", - "location" : "HR_5_22_11P", - "linked_object" : "dinosc3", - "linked_objects" : { - "dinosc3" : { - "location" : "HR_5_22_11P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc3", + "location_object": "dinosc3", + "location": "HR_5_22_11P", + "linked_object": "dinosc3", + "linked_objects": { + "dinosc3": { + "location": "HR_5_22_11P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "dinosc3", - "O" : "$ibuf_dinosc3" + "connectivity": { + "I": "dinosc3", + "O": "$ibuf_dinosc3" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc3", - "location_object" : "dinosc3", - "location" : "HR_5_22_11P", - "linked_object" : "dinosc3", - "linked_objects" : { - "dinosc3" : { - "location" : "HR_5_22_11P", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr_osc3", + "location_object": "dinosc3", + "location": "HR_5_22_11P", + "linked_object": "dinosc3", + "linked_objects": { + "dinosc3": { + "location": "HR_5_22_11P", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pllosc1_clk1", - "D" : "$ibuf_dinosc3" + "connectivity": { + "C": "pllosc1_clk1", + "D": "$ibuf_dinosc3" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc4", - "location_object" : "dinosc4", - "location" : "HR_1_30_15P", - "linked_object" : "dinosc4", - "linked_objects" : { - "dinosc4" : { - "location" : "HR_1_30_15P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==NONE" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc4", + "location_object": "dinosc4", + "location": "HR_1_30_15P", + "linked_object": "dinosc4", + "linked_objects": { + "dinosc4": { + "location": "HR_1_30_15P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "dinosc4", - "O" : "$ibuf_dinosc4" + "connectivity": { + "I": "dinosc4", + "O": "$ibuf_dinosc4" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc4", - "location_object" : "dinosc4", - "location" : "HR_1_30_15P", - "linked_object" : "dinosc4", - "linked_objects" : { - "dinosc4" : { - "location" : "HR_1_30_15P", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr_osc4", + "location_object": "dinosc4", + "location": "HR_1_30_15P", + "linked_object": "dinosc4", + "linked_objects": { + "dinosc4": { + "location": "HR_1_30_15P", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pllosc2_clk0", - "D" : "$ibuf_dinosc4" + "connectivity": { + "C": "pllosc2_clk0", + "D": "$ibuf_dinosc4" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_clk_out", - "location_object" : "clk_out", - "location" : "HR_2_8_4P", - "linked_object" : "clk_out", - "linked_objects" : { - "clk_out" : { - "location" : "HR_2_8_4P", - "properties" : { - }, - "config_attributes" : [ - { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "module": "O_BUFT", + "name": "$obuf$top.$obuf_clk_out", + "location_object": "clk_out", + "location": "HR_2_8_4P", + "linked_object": "clk_out", + "linked_objects": { + "clk_out": { + "location": "HR_2_8_4P", + "properties": { + }, + "config_attributes": [ + { + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_clk_out", - "O" : "clk_out" + "connectivity": { + "I": "$obuf_clk_out", + "O": "clk_out" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_SERDES_CLK" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_SERDES_CLK", - "name" : "o_serdes_clk", - "location_object" : "clk_out", - "location" : "HR_2_8_4P", - "linked_object" : "clk_out", - "linked_objects" : { - "clk_out" : { - "location" : "HR_2_8_4P", - "properties" : { - }, - "config_attributes" : [ - { - "TX_CLK_PHASE" : "TX_phase_270" - }, - { - "O_SERDES_CLK" : "DDR_MODE==SDR" + "module": "O_SERDES_CLK", + "name": "o_serdes_clk", + "location_object": "clk_out", + "location": "HR_2_8_4P", + "linked_object": "clk_out", + "linked_objects": { + "clk_out": { + "location": "HR_2_8_4P", + "properties": { + }, + "config_attributes": [ + { + "TX_CLK_PHASE": "TX_phase_270" }, { - "TX_CLOCK_IO" : "TX_clock_IO" + "O_SERDES_CLK": "DDR_MODE==SDR" } ] } }, - "connectivity" : { - "OUTPUT_CLK" : "$obuf_clk_out", - "PLL_CLK" : "clkbuf40" + "connectivity": { + "OUTPUT_CLK": "$obuf_clk_out", + "PLL_CLK": "clkbuf40" }, - "parameters" : { - "CLOCK_PHASE" : "270", - "DATA_RATE" : "SDR" + "parameters": { + "CLOCK_PHASE": "270", + "DATA_RATE": "SDR" }, - "flags" : [ + "flags": [ "O_SERDES_CLK" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__check_data_rate_parameter__,__check_clock_phase_parameter__" + "__validation__": true, + "__validation_msg__": "Pass:__check_data_rate_parameter__,__check_clock_phase_parameter__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_clk_out_osc", - "location_object" : "clk_out_osc", - "location" : "HR_2_9_4N", - "linked_object" : "clk_out_osc", - "linked_objects" : { - "clk_out_osc" : { - "location" : "HR_2_9_4N", - "properties" : { - }, - "config_attributes" : [ + "module": "O_BUFT", + "name": "$obuf$top.$obuf_clk_out_osc", + "location_object": "clk_out_osc", + "location": "HR_2_9_4N", + "linked_object": "clk_out_osc", + "linked_objects": { + "clk_out_osc": { + "location": "HR_2_9_4N", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "I" : "$obuf_clk_out_osc", - "O" : "clk_out_osc" + "connectivity": { + "I": "$obuf_clk_out_osc", + "O": "clk_out_osc" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_SERDES_CLK" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Invalidated because other instance in the chain is invalid" + "__validation__": false, + "__validation_msg__": "Invalidated because other instance in the chain is invalid", + "config_attributes": [ + ] }, { - "module" : "O_SERDES_CLK", - "name" : "o_serdes_clk_osc", - "location_object" : "clk_out_osc", - "location" : "HR_2_9_4N", - "linked_object" : "clk_out_osc", - "linked_objects" : { - "clk_out_osc" : { - "location" : "HR_2_9_4N", - "properties" : { - }, - "config_attributes" : [ + "module": "O_SERDES_CLK", + "name": "o_serdes_clk_osc", + "location_object": "clk_out_osc", + "location": "HR_2_9_4N", + "linked_object": "clk_out_osc", + "linked_objects": { + "clk_out_osc": { + "location": "HR_2_9_4N", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "OUTPUT_CLK" : "$obuf_clk_out_osc", - "PLL_CLK" : "osc" + "connectivity": { + "OUTPUT_CLK": "$obuf_clk_out_osc", + "PLL_CLK": "osc" }, - "parameters" : { - "CLOCK_PHASE" : "180", - "DATA_RATE" : "DDR" + "parameters": { + "CLOCK_PHASE": "180", + "DATA_RATE": "DDR" }, - "flags" : [ + "flags": [ "O_SERDES_CLK" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ "\\O_SERDES_CLK \\o_serdes_clk_osc fast clock port \\PLL_CLK (net: \\osc) is not routable" ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail:internal_error" + "__validation__": false, + "__validation_msg__": "Pass:__check_data_rate_parameter__,__check_clock_phase_parameter__;Fail:internal_error", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dinoutosc", - "location_object" : "dinoutosc", - "location" : "HR_2_22_11P", - "linked_object" : "dinoutosc", - "linked_objects" : { - "dinoutosc" : { - "location" : "HR_2_22_11P", - "properties" : { - }, - "config_attributes" : [ - { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dinoutosc", + "location_object": "dinoutosc", + "location": "HR_2_22_11P", + "linked_object": "dinoutosc", + "linked_objects": { + "dinoutosc": { + "location": "HR_2_22_11P", + "properties": { + }, + "config_attributes": [ + { + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_dinoutosc", - "O" : "dinoutosc" + "connectivity": { + "I": "$f2g_tx_out_$obuf_dinoutosc", + "O": "dinoutosc" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout00", - "location_object" : "dout00", - "location" : "HP_1_22_11P", - "linked_object" : "dout00", - "linked_objects" : { - "dout00" : { - "location" : "HP_1_22_11P", - "properties" : { - }, - "config_attributes" : [ - { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout00", + "location_object": "dout00", + "location": "HP_1_22_11P", + "linked_object": "dout00", + "linked_objects": { + "dout00": { + "location": "HP_1_22_11P", + "properties": { + }, + "config_attributes": [ + { + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_dout00", - "O" : "dout00" + "connectivity": { + "I": "$obuf_dout00", + "O": "dout00" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_DDR", - "name" : "o_ddr00", - "location_object" : "dout00", - "location" : "HP_1_22_11P", - "linked_object" : "dout00", - "linked_objects" : { - "dout00" : { - "location" : "HP_1_22_11P", - "properties" : { - }, - "config_attributes" : [ - { - "O_DDR" : "MODE==DDR" + "module": "O_DDR", + "name": "o_ddr00", + "location_object": "dout00", + "location": "HP_1_22_11P", + "linked_object": "dout00", + "linked_objects": { + "dout00": { + "location": "HP_1_22_11P", + "properties": { + }, + "config_attributes": [ + { + "O_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "clkbuf00", - "Q" : "$obuf_dout00" + "connectivity": { + "C": "clkbuf00", + "Q": "$obuf_dout00" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout01", - "location_object" : "dout01", - "location" : "HR_1_22_11P", - "linked_object" : "dout01", - "linked_objects" : { - "dout01" : { - "location" : "HR_1_22_11P", - "properties" : { - }, - "config_attributes" : [ - { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout01", + "location_object": "dout01", + "location": "HR_1_22_11P", + "linked_object": "dout01", + "linked_objects": { + "dout01": { + "location": "HR_1_22_11P", + "properties": { + }, + "config_attributes": [ + { + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_dout01", - "O" : "dout01" + "connectivity": { + "I": "$obuf_dout01", + "O": "dout01" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_DDR", - "name" : "o_ddr01", - "location_object" : "dout01", - "location" : "HR_1_22_11P", - "linked_object" : "dout01", - "linked_objects" : { - "dout01" : { - "location" : "HR_1_22_11P", - "properties" : { - }, - "config_attributes" : [ - { - "O_DDR" : "MODE==DDR" + "module": "O_DDR", + "name": "o_ddr01", + "location_object": "dout01", + "location": "HR_1_22_11P", + "linked_object": "dout01", + "linked_objects": { + "dout01": { + "location": "HR_1_22_11P", + "properties": { + }, + "config_attributes": [ + { + "O_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pll00_clk1", - "Q" : "$obuf_dout01" + "connectivity": { + "C": "pll00_clk1", + "Q": "$obuf_dout01" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout10", - "location_object" : "dout10", - "location" : "", - "linked_object" : "dout10", - "linked_objects" : { - "dout10" : { - "location" : "", - "properties" : { - }, - "config_attributes" : [ + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout10", + "location_object": "dout10", + "location": "", + "linked_object": "dout10", + "linked_objects": { + "dout10": { + "location": "", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "I" : "$obuf_dout10", - "O" : "dout10" + "connectivity": { + "I": "$obuf_dout10", + "O": "dout10" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail:__pin_is_valid__" + "__validation__": false, + "__validation_msg__": "Fail:__pin_is_valid__", + "config_attributes": [ + ] }, { - "module" : "O_DDR", - "name" : "o_ddr10", - "location_object" : "dout10", - "location" : "", - "linked_object" : "dout10", - "linked_objects" : { - "dout10" : { - "location" : "", - "properties" : { - }, - "config_attributes" : [ + "module": "O_DDR", + "name": "o_ddr10", + "location_object": "dout10", + "location": "", + "linked_object": "dout10", + "linked_objects": { + "dout10": { + "location": "", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "C" : "clkbuf10", - "Q" : "$obuf_dout10" + "connectivity": { + "C": "clkbuf10", + "Q": "$obuf_dout10" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Invalidated because other instance in the chain is invalid" + "__validation__": false, + "__validation_msg__": "Invalidated because other instance in the chain is invalid", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout11", - "location_object" : "dout11", - "location" : "HR_5_4_2P", - "linked_object" : "dout11", - "linked_objects" : { - "dout11" : { - "location" : "HR_5_4_2P", - "properties" : { - }, - "config_attributes" : [ - { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout11", + "location_object": "dout11", + "location": "HR_5_4_2P", + "linked_object": "dout11", + "linked_objects": { + "dout11": { + "location": "HR_5_4_2P", + "properties": { + }, + "config_attributes": [ + { + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_dout11", - "O" : "dout11" + "connectivity": { + "I": "$obuf_dout11", + "O": "dout11" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_DDR", - "name" : "o_ddr11", - "location_object" : "dout11", - "location" : "HR_5_4_2P", - "linked_object" : "dout11", - "linked_objects" : { - "dout11" : { - "location" : "HR_5_4_2P", - "properties" : { - }, - "config_attributes" : [ - { - "O_DDR" : "MODE==DDR" + "module": "O_DDR", + "name": "o_ddr11", + "location_object": "dout11", + "location": "HR_5_4_2P", + "linked_object": "dout11", + "linked_objects": { + "dout11": { + "location": "HR_5_4_2P", + "properties": { + }, + "config_attributes": [ + { + "O_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "clkbuf10", - "Q" : "$obuf_dout11" + "connectivity": { + "C": "clkbuf10", + "Q": "$obuf_dout11" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout12", - "location_object" : "dout12", - "location" : "HR_1_26_13P", - "linked_object" : "dout12", - "linked_objects" : { - "dout12" : { - "location" : "HR_1_26_13P", - "properties" : { - }, - "config_attributes" : [ - { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout12", + "location_object": "dout12", + "location": "HR_1_26_13P", + "linked_object": "dout12", + "linked_objects": { + "dout12": { + "location": "HR_1_26_13P", + "properties": { + }, + "config_attributes": [ + { + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_dout12", - "O" : "dout12" + "connectivity": { + "I": "$obuf_dout12", + "O": "dout12" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_DDR", - "name" : "o_ddr12", - "location_object" : "dout12", - "location" : "HR_1_26_13P", - "linked_object" : "dout12", - "linked_objects" : { - "dout12" : { - "location" : "HR_1_26_13P", - "properties" : { - }, - "config_attributes" : [ - { - "O_DDR" : "MODE==DDR" + "module": "O_DDR", + "name": "o_ddr12", + "location_object": "dout12", + "location": "HR_1_26_13P", + "linked_object": "dout12", + "linked_objects": { + "dout12": { + "location": "HR_1_26_13P", + "properties": { + }, + "config_attributes": [ + { + "O_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "clkbuf10", - "Q" : "$obuf_dout12" + "connectivity": { + "C": "clkbuf10", + "Q": "$obuf_dout12" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout20", - "location_object" : "dout20", - "location" : "", - "linked_object" : "dout20", - "linked_objects" : { - "dout20" : { - "location" : "", - "properties" : { - }, - "config_attributes" : [ + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout20", + "location_object": "dout20", + "location": "", + "linked_object": "dout20", + "linked_objects": { + "dout20": { + "location": "", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "I" : "$obuf_dout20", - "O" : "dout20" + "connectivity": { + "I": "$f2g_tx_out_$obuf_dout20", + "O": "dout20" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail:__pin_is_valid__" + "__validation__": false, + "__validation_msg__": "Fail:__pin_is_valid__", + "config_attributes": [ + ] }, { - "module" : "BOOT_CLOCK", - "name" : "boot_clock", - "location_object" : "BOOT_CLOCK#0", - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "properties" : { - }, - "config_attributes" : [ + "module": "BOOT_CLOCK", + "name": "boot_clock", + "location_object": "BOOT_CLOCK#0", + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "O" : "osc" + "connectivity": { + "O": "osc" }, - "parameters" : { - "PERIOD" : "25" + "parameters": { + "PERIOD": "25" }, - "flags" : [ + "flags": [ "BOOT_CLOCK" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "PLL", "PLL", "PLL" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__check_boot_clock_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__check_boot_clock_resource__", + "config_attributes": [ + ] }, { - "module" : "PLL", - "name" : "pllosc0", - "location_object" : "BOOT_CLOCK#0", - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "properties" : { - }, - "config_attributes" : [ + "module": "PLL", + "name": "pllosc0", + "location_object": "BOOT_CLOCK#0", + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "CLK_IN" : "osc", - "CLK_OUT" : "pllosc0_clk0" + "connectivity": { + "CLK_IN": "osc", + "CLK_OUT": "pllosc0_clk0" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "BOOT_CLOCK", - "post_primitives" : [ + "pre_primitive": "BOOT_CLOCK", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_ddr_osc0", "i_ddr_osc1", "i_ddr_osc2" ] }, - "route_clock_result" : { - "CLK_OUT" : [ - "Use FCLK: hvl_fclk_1_B (sub-resource: NOT_VCO)", - "Not able to route clock-capable pin pllosc0 (location:BOOT_CLOCK#0) to gearbox module i_ddr_osc1 clock (module:I_DDR) (location:HR_5_20_10P). Reason: A single PLL instance cannot route from both PLL #0 and PLL#1. You need to explicitely instantiate two PLLs", - "Not able to route PLL pllosc0 Port CLK_OUT (location:BOOT_CLOCK#0) to gearbox module i_ddr_osc2 clock. Reason: Module usage is invalid in the first place" + "route_clock_result": { + "CLK_OUT": [ + "Error: 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc0 (location: HR_2_20_10P)' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_use_rosc to value 1, had been set with value 0 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'; Fail to find any paths first round", + "Pass: ", + "Error: Destination gearbox is invalid" ] }, - "errors" : [ - ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail to route the clock" + "errors": [ + ], + "__validation__": true, + "__validation_msg__": "Pass:__check_pll_parameter__", + "config_attributes": [ + { + "__location__": "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1", + "pll_DACEN": "DACEN_0", + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSMEN": "DSMEN_0", + "pll_FBDIV": "16", + "pll_FRAC": "0", + "pll_PLLEN": "1", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_REFDIV": "1" + }, + { + "__location__": "u_GBOX_HP_40X2.u_gbox_pll_refmux_1", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_use_div": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "1" + }, + { + "__location__": "u_GBOX_HV_40X2_VR.u_gbox_fclk_mux_all", + "cfg_rx_fclkio_sel_B_1": "0", + "cfg_rxclk_phase_sel_B_1": "0", + "cfg_vco_clk_sel_B_1": "1" + } + ] }, { - "module" : "PLL", - "name" : "pllosc1", - "location_object" : "BOOT_CLOCK#0", - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "properties" : { - }, - "config_attributes" : [ + "module": "PLL", + "name": "pllosc1", + "location_object": "BOOT_CLOCK#0", + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "CLK_IN" : "osc", - "CLK_OUT_DIV2" : "pllosc1_clk1" + "connectivity": { + "CLK_IN": "osc", + "CLK_OUT_DIV2": "pllosc1_clk1" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "BOOT_CLOCK", - "post_primitives" : [ + "pre_primitive": "BOOT_CLOCK", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT_DIV2" : [ + "route_clock_to": { + "CLK_OUT_DIV2": [ "i_ddr_osc3" ] }, - "route_clock_result" : { - "CLK_OUT_DIV2" : [ - "Not able to route PLL pllosc1 Port CLK_OUT_DIV2 (location:BOOT_CLOCK#0) to gearbox module i_ddr_osc3 clock. Reason: Only PLL output port 'CLK_OUT' can use FCLK resource" + "route_clock_result": { + "CLK_OUT_DIV2": [ + "Error: Fail to find any paths first round" ] }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail to route the clock" + "__validation__": true, + "__validation_msg__": "Pass:__check_pll_parameter__", + "config_attributes": [ + ] }, { - "module" : "PLL", - "name" : "pllosc2", - "location_object" : "BOOT_CLOCK#0", - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "properties" : { - }, - "config_attributes" : [ + "module": "PLL", + "name": "pllosc2", + "location_object": "BOOT_CLOCK#0", + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "CLK_IN" : "osc", - "CLK_OUT" : "pllosc2_clk0" + "connectivity": { + "CLK_IN": "osc", + "CLK_OUT": "pllosc2_clk0" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "BOOT_CLOCK", - "post_primitives" : [ + "pre_primitive": "BOOT_CLOCK", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_ddr_osc4" ] }, - "route_clock_result" : { - "CLK_OUT" : [ - "Not able to route clock-capable pin pllosc2 (location:BOOT_CLOCK#0) to gearbox module i_ddr_osc4 clock (module:I_DDR) (location:HR_1_30_15P). Reason: Attemp to use FCLK: hvl_fclk_0_B, but it had been used by PLL:HP_1_CC_18_9P" + "route_clock_result": { + "CLK_OUT": [ + "Error: 'Fast Clock: module PLL pllosc2 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc4 (location: HR_1_30_15P)' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_use_rosc to value 1, had been set with value 0 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'; Fail to find any paths first round" ] }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail to route the clock" + "__validation__": true, + "__validation_msg__": "Pass:__check_pll_parameter__", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "i_buf30", - "location_object" : "clk30", - "location" : "HR_1_CC_38_19P", - "linked_object" : "clk30", - "linked_objects" : { - "clk30" : { - "location" : "HR_1_CC_38_19P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==DEFAULT" + "module": "I_BUF", + "name": "i_buf30", + "location_object": "clk30", + "location": "HR_1_CC_38_19P", + "linked_object": "clk30", + "linked_objects": { + "clk30": { + "location": "HR_1_CC_38_19P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==DEFAULT" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "clk30", - "O" : "ibuf30" + "connectivity": { + "I": "clk30", + "O": "ibuf30" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf30", - "location_object" : "clk30", - "location" : "HR_1_CC_38_19P", - "linked_object" : "clk30", - "linked_objects" : { - "clk30" : { - "location" : "HR_1_CC_38_19P", - "properties" : { - }, - "config_attributes" : [ - { - "CLK_BUF" : "GBOX_TOP_SRC==DEFAULT" + "module": "CLK_BUF", + "name": "clk_buf30", + "location_object": "clk30", + "location": "HR_1_CC_38_19P", + "linked_object": "clk30", + "linked_objects": { + "clk30": { + "location": "HR_1_CC_38_19P", + "properties": { + }, + "config_attributes": [ + { + "CLK_BUF": "GBOX_TOP_SRC==DEFAULT" } ] } }, - "connectivity" : { - "I" : "ibuf30", - "O" : "clkbuf30" + "connectivity": { + "I": "ibuf30", + "O": "clkbuf30" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ "PLL" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__clock_pin_is_valid__,__check_fabric_clock_resource__,__update_fabric_clock_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__clock_pin_is_valid__", + "config_attributes": [ + ] }, { - "module" : "PLL", - "name" : "pll30", - "location_object" : "clk30", - "location" : "HR_1_CC_38_19P", - "linked_object" : "clk30", - "linked_objects" : { - "clk30" : { - "location" : "HR_1_CC_38_19P", - "properties" : { - }, - "config_attributes" : [ + "module": "PLL", + "name": "pll30", + "location_object": "clk30", + "location": "HR_1_CC_38_19P", + "linked_object": "clk30", + "linked_objects": { + "clk30": { + "location": "HR_1_CC_38_19P", + "properties": { + }, + "config_attributes": [ ] } }, - "connectivity" : { - "CLK_IN" : "clkbuf30", - "CLK_OUT" : "pll30_clk" + "connectivity": { + "CLK_IN": "clkbuf30", + "FAST_CLK": "pll30_clk" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "CLK_BUF", - "post_primitives" : [ + "pre_primitive": "CLK_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "FAST_CLK": [ "i_ddr30" ] }, - "route_clock_result" : { - "CLK_OUT" : [ - "Use FCLK: hvl_fclk_1_A (sub-resource: NOT_VCO)" + "route_clock_result": { + "FAST_CLK": [ + "Error: 'Fast Clock: module PLL pll30 port FAST_CLK (location: HR_1_CC_38_19P) -> module I_DDR i_ddr30 (location: HR_2_0_0P)' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_hv_rx_io_sel to value 1, had been set with value 0 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'; Fail to find any paths first round" ] }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Cannot fit in any Pin/FCLK/PLL resource" + "__validation__": true, + "__validation_msg__": "Pass:__pll_clock_pin_is_valid__,__check_pll_parameter__", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "i_buf31", - "location_object" : "clk31", - "location" : "HR_3_CC_38_19P", - "linked_object" : "clk31", - "linked_objects" : { - "clk31" : { - "location" : "HR_3_CC_38_19P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==DEFAULT" + "module": "I_BUF", + "name": "i_buf31", + "location_object": "clk31", + "location": "HR_3_CC_38_19P", + "linked_object": "clk31", + "linked_objects": { + "clk31": { + "location": "HR_3_CC_38_19P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==DEFAULT" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "clk31", - "O" : "ibuf31" + "connectivity": { + "I": "clk31", + "O": "ibuf31" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf31", - "location_object" : "clk31", - "location" : "HR_3_CC_38_19P", - "linked_object" : "clk31", - "linked_objects" : { - "clk31" : { - "location" : "HR_3_CC_38_19P", - "properties" : { - }, - "config_attributes" : [ - { - "CLK_BUF" : "GBOX_TOP_SRC==DEFAULT" + "module": "CLK_BUF", + "name": "clk_buf31", + "location_object": "clk31", + "location": "HR_3_CC_38_19P", + "linked_object": "clk31", + "linked_objects": { + "clk31": { + "location": "HR_3_CC_38_19P", + "properties": { + }, + "config_attributes": [ + { + "CLK_BUF": "GBOX_TOP_SRC==DEFAULT" } ] } }, - "connectivity" : { - "I" : "ibuf31", - "O" : "clkbuf31" + "connectivity": { + "I": "ibuf31", + "O": "clkbuf31" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ "PLL" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__clock_pin_is_valid__,__check_fabric_clock_resource__,__update_fabric_clock_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__clock_pin_is_valid__", + "config_attributes": [ + ] }, { - "module" : "PLL", - "name" : "pll31", - "location_object" : "clk31", - "location" : "HR_3_CC_38_19P", - "linked_object" : "clk31", - "linked_objects" : { - "clk31" : { - "location" : "HR_3_CC_38_19P", - "properties" : { - "OUT0_ROUTE_TO_FABRIC_CLK" : "7" - }, - "config_attributes" : [ - ] - } - }, - "connectivity" : { - "CLK_IN" : "clkbuf31", - "CLK_OUT" : "pll31_clk" - }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "OUT0_ROUTE_TO_FABRIC_CLK" : "7", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" - }, - "flags" : [ + "module": "PLL", + "name": "pll31", + "location_object": "clk31", + "location": "HR_3_CC_38_19P", + "linked_object": "clk31", + "linked_objects": { + "clk31": { + "location": "HR_3_CC_38_19P", + "properties": { + "OUT0_ROUTE_TO_FABRIC_CLK": "7" + }, + "config_attributes": [ + ] + } + }, + "connectivity": { + "CLK_IN": "clkbuf31", + "CLK_OUT": "pll31_clk" + }, + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "7", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" + }, + "flags": [ "PLL" ], - "pre_primitive" : "CLK_BUF", - "post_primitives" : [ + "pre_primitive": "CLK_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_ddr31" ] }, - "route_clock_result" : { - "CLK_OUT" : [ - "Not able to route PLL pll31 Port CLK_OUT (location:HR_3_CC_38_19P) to gearbox module i_ddr31 clock (module:I_DDR) (location:HR_2_2_1P). Reason: PLL #1 (needed by HVR) cannot route to HVL" + "route_clock_result": { + "CLK_OUT": [ + "Error: Fail to find any paths first round" ] }, - "errors" : [ + "errors": [ + "ModelConfigError: 'Core Clock: module PLL pll31 port CLK_OUT (location: HR_3_CC_38_19P) -> core clock slot[7]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_hv_rx_io_sel to value 1, had been set with value 0 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'", + "ModelConfigError: Fail to find any paths first round" ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail to route the clock" + "__validation__": true, + "__validation_msg__": "Pass:__pll_clock_pin_is_valid__,__check_pll_parameter__", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "i_buf40", - "location_object" : "clk40", - "location" : "HR_2_CC_38_19P", - "linked_object" : "clk40", - "linked_objects" : { - "clk40" : { - "location" : "HR_2_CC_38_19P", - "properties" : { - }, - "config_attributes" : [ - { - "I_BUF" : "WEAK_KEEPER==DEFAULT" + "module": "I_BUF", + "name": "i_buf40", + "location_object": "clk40", + "location": "HR_2_CC_38_19P", + "linked_object": "clk40", + "linked_objects": { + "clk40": { + "location": "HR_2_CC_38_19P", + "properties": { + }, + "config_attributes": [ + { + "I_BUF": "WEAK_KEEPER==DEFAULT" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "clk40", - "O" : "ibuf40" + "connectivity": { + "I": "clk40", + "O": "ibuf40" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf40", - "location_object" : "clk40", - "location" : "HR_2_CC_38_19P", - "linked_object" : "clk40", - "linked_objects" : { - "clk40" : { - "location" : "HR_2_CC_38_19P", - "properties" : { - }, - "config_attributes" : [ + "module": "CLK_BUF", + "name": "clk_buf40", + "location_object": "clk40", + "location": "HR_2_CC_38_19P", + "linked_object": "clk40", + "linked_objects": { + "clk40": { + "location": "HR_2_CC_38_19P", + "properties": { + }, + "config_attributes": [ + { + "CLK_BUF": "GBOX_TOP_SRC==DEFAULT" + } ] } }, - "connectivity" : { - "I" : "ibuf40", - "O" : "clkbuf40" + "connectivity": { + "I": "ibuf40", + "O": "clkbuf40" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "o_serdes_clk" ] }, - "route_clock_result" : { - "O" : [ - "Not able to route clock-capable pin clk_buf40 (location:HR_2_CC_38_19P) to gearbox module o_serdes_clk clock (module:O_SERDES_CLK) (location:HR_2_8_4P). Reason: Attemp to use FCLK: hvl_fclk_1_A, but it had been used by PLL:HR_1_CC_38_19P" + "route_clock_result": { + "O": [ + "Pass: " ] }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail to route the clock" + "__validation__": true, + "__validation_msg__": "Pass:__clock_pin_is_valid__", + "config_attributes": [ + { + "TX_CLOCK_IO": "1", + "__location__": "HR_2_8_4P" + }, + { + "__location__": "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + "cfg_rx_fclkio_sel_A_1": "1", + "cfg_rxclk_phase_sel_A_1": "1", + "cfg_vco_clk_sel_A_1": "0" + } + ] }, { - "module" : "I_BUF_DS", - "name" : "i_buf_ds30", - "location_object" : "din30_p", - "location" : "HR_2_0_0P", - "linked_object" : "din30_n+din30_p", - "linked_objects" : { - "din30_n" : { - "location" : "HR_2_1_0N", - "properties" : { - }, - "config_attributes" : [ - { - "DFODTEN" : "DF_odt_enable" + "module": "I_BUF_DS", + "name": "i_buf_ds30", + "location_object": "din30_p", + "location": "HR_2_0_0P", + "linked_object": "din30_n+din30_p", + "linked_objects": { + "din30_n": { + "location": "HR_2_1_0N", + "properties": { + }, + "config_attributes": [ + { + "DFODTEN": "DF_odt_enable" }, { - "I_BUF_DS" : "IOSTANDARD==DEFAULT" + "I_BUF_DS": "IOSTANDARD==DEFAULT" } ] }, - "din30_p" : { - "location" : "HR_2_0_0P", - "properties" : { + "din30_p": { + "location": "HR_2_0_0P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "DFODTEN" : "DF_odt_enable" + "DFODTEN": "DF_odt_enable" }, { - "I_BUF_DS" : "IOSTANDARD==DEFAULT" + "I_BUF_DS": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I_N" : "din30_n", - "I_P" : "din30_p", - "O" : "din30_ds" + "connectivity": { + "I_N": "din30_n", + "I_P": "din30_p", + "O": "din30_ds" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT", - "WEAK_KEEPER" : "NONE" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr30", - "location_object" : "din30_p", - "location" : "HR_2_0_0P", - "linked_object" : "din30_n+din30_p", - "linked_objects" : { - "din30_n" : { - "location" : "HR_2_1_0N", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr30", + "location_object": "din30_p", + "location": "HR_2_0_0P", + "linked_object": "din30_n+din30_p", + "linked_objects": { + "din30_n": { + "location": "HR_2_1_0N", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] }, - "din30_p" : { - "location" : "HR_2_0_0P", - "properties" : { + "din30_p": { + "location": "HR_2_0_0P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_DDR" : "MODE==DDR" + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pll30_clk", - "D" : "din30_ds" + "connectivity": { + "C": "pll30_clk", + "D": "din30_ds" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF_DS", - "post_primitives" : [ + "pre_primitive": "I_BUF_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "I_BUF_DS", - "name" : "i_buf_ds31", - "location_object" : "din31_p", - "location" : "HR_2_2_1P", - "linked_object" : "din31_n+din31_p", - "linked_objects" : { - "din31_n" : { - "location" : "HR_2_3_1N", - "properties" : { - }, - "config_attributes" : [ - { - "DFODTEN" : "DF_odt_enable" + "module": "I_BUF_DS", + "name": "i_buf_ds31", + "location_object": "din31_p", + "location": "HR_2_2_1P", + "linked_object": "din31_n+din31_p", + "linked_objects": { + "din31_n": { + "location": "HR_2_3_1N", + "properties": { + }, + "config_attributes": [ + { + "DFODTEN": "DF_odt_enable" }, { - "I_BUF_DS" : "IOSTANDARD==DEFAULT" + "I_BUF_DS": "IOSTANDARD==DEFAULT" } ] }, - "din31_p" : { - "location" : "HR_2_2_1P", - "properties" : { + "din31_p": { + "location": "HR_2_2_1P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "DFODTEN" : "DF_odt_enable" + "DFODTEN": "DF_odt_enable" }, { - "I_BUF_DS" : "IOSTANDARD==DEFAULT" + "I_BUF_DS": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I_N" : "din31_n", - "I_P" : "din31_p", - "O" : "din31_ds" + "connectivity": { + "I_N": "din31_n", + "I_P": "din31_p", + "O": "din31_ds" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT", - "WEAK_KEEPER" : "NONE" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr31", - "location_object" : "din31_p", - "location" : "HR_2_2_1P", - "linked_object" : "din31_n+din31_p", - "linked_objects" : { - "din31_n" : { - "location" : "HR_2_3_1N", - "properties" : { - }, - "config_attributes" : [ - { - "I_DDR" : "MODE==DDR" + "module": "I_DDR", + "name": "i_ddr31", + "location_object": "din31_p", + "location": "HR_2_2_1P", + "linked_object": "din31_n+din31_p", + "linked_objects": { + "din31_n": { + "location": "HR_2_3_1N", + "properties": { + }, + "config_attributes": [ + { + "I_DDR": "MODE==DDR" } ] }, - "din31_p" : { - "location" : "HR_2_2_1P", - "properties" : { + "din31_p": { + "location": "HR_2_2_1P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_DDR" : "MODE==DDR" + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pll31_clk", - "D" : "din31_ds" + "connectivity": { + "C": "pll31_clk", + "D": "din31_ds" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF_DS", - "post_primitives" : [ + "pre_primitive": "I_BUF_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "O_BUF_DS", - "name" : "o_buf_ds", - "location_object" : "dout30_p", - "location" : "HR_2_4_2P", - "linked_object" : "dout30_n+dout30_p", - "linked_objects" : { - "dout30_n" : { - "location" : "HR_2_7_3N", - "properties" : { - }, - "config_attributes" : [ + "module": "O_BUFT_DS", + "name": "o_buf_ds", + "location_object": "dout30_p", + "location": "HR_2_4_2P", + "linked_object": "dout30_n+dout30_p", + "linked_objects": { + "dout30_n": { + "location": "HR_2_7_3N", + "properties": { + }, + "config_attributes": [ ] }, - "dout30_p" : { - "location" : "HR_2_4_2P", - "properties" : { + "dout30_p": { + "location": "HR_2_4_2P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ ] } }, - "connectivity" : { - "I" : "dout_oddr3x", - "O_N" : "dout30_n", - "O_P" : "dout30_p" + "connectivity": { + "I": "dout_oddr3x", + "O_N": "dout30_n", + "O_P": "dout30_p" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ - "O_BUF_DS" + "flags": [ + "O_BUFT_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Pass:__ds_pin_is_valid__;Fail:__pin_is_differential__" + "__validation__": false, + "__validation_msg__": "Pass:__ds_pin_is_valid__;Fail:__pin_is_differential__", + "config_attributes": [ + ] }, { - "module" : "O_DDR", - "name" : "o_ddr3x", - "location_object" : "dout30_p", - "location" : "HR_2_4_2P", - "linked_object" : "dout30_n+dout30_p", - "linked_objects" : { - "dout30_n" : { - "location" : "HR_2_7_3N", - "properties" : { - }, - "config_attributes" : [ + "module": "O_DDR", + "name": "o_ddr3x", + "location_object": "dout30_p", + "location": "HR_2_4_2P", + "linked_object": "dout30_n+dout30_p", + "linked_objects": { + "dout30_n": { + "location": "HR_2_7_3N", + "properties": { + }, + "config_attributes": [ ] }, - "dout30_p" : { - "location" : "HR_2_4_2P", - "properties" : { + "dout30_p": { + "location": "HR_2_4_2P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ ] } }, - "connectivity" : { - "C" : "pll31_clk", - "Q" : "dout_oddr3x" + "connectivity": { + "C": "pll31_clk", + "Q": "dout_oddr3x" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUF_DS", - "post_primitives" : [ + "pre_primitive": "O_BUFT_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Invalidated because other instance in the chain is invalid" + "__validation__": false, + "__validation_msg__": "Invalidated because other instance in the chain is invalid", + "config_attributes": [ + ] } ] } diff --git a/tests/unittest/ModelConfig/golden/model_config.ppdb.json b/tests/unittest/ModelConfig/golden/model_config.ppdb.json index fd762532f..980edcba8 100644 --- a/tests/unittest/ModelConfig/golden/model_config.ppdb.json +++ b/tests/unittest/ModelConfig/golden/model_config.ppdb.json @@ -1,8 +1,9 @@ { - "messages" : [ + "status": false, + "feature": "IO", + "messages": [ "Preparing Python file: config.py", - "Read resources", - "Validate Instances", + "Validate netlist instances", "Merge properties into instances", " Assign Property:IOSTANDARD value:LVCMOS_18_HP to \"$ibuf$top.$ibuf_clk0\"", " Assign Property:PACKAGE_PIN value:HR_1_CC_38_19P to \"$ibuf$top.$ibuf_clk0\"", @@ -29,9 +30,9 @@ " Overwrite Instance:location value:$obuf$top.$obuf_dout to \"HR_1_6_3P\" (value existing: HP_2_20_10P)", " Overwrite Instance-Object:location value:o_delay to \"HR_1_6_3P\" (value existing: HP_2_20_10P)", " Overwrite Instance:location value:o_delay to \"HR_1_6_3P\" (value existing: HP_2_20_10P)", - "Configure Mapping file initialization", - "Validation using '__primary_validation__' rule", - "Internal error validations", + "Validate instances using '__primary_validation__' rule", + " Error: Skip module:I_BUF name:$ibuf$top.$ibuf_enable location(s):\"\" because it failed in __pin_is_valid__ validation", + "Validate error from netlist", "Assign instance-without-location", " Instance: boot_clock", " Object: BOOT_CLOCK#0", @@ -39,52 +40,220 @@ " Instance: $clkbuf$top.clk0_div", " Object: FABRIC_CLKBUF#0", " Assign location for child from instance-without-location", - "Allocate FCLK routing resource", - " CLKBUF $clkbuf$top.$ibuf_clk0 (location:HR_1_CC_38_19P)", - " Route to gearbox module i_delay (location:HR_1_4_2P)", - " Use FCLK: hvl_fclk_0_A (sub-resource: )", - " CLKBUF clk_buf (location:HP_1_CC_18_9P)", - " Route to gearbox module o_delay (location:HR_1_6_3P)", - " Warning: Not able to route clock-capable pin clk_buf (location:HP_1_CC_18_9P) to gearbox module o_delay clock (module:O_DELAY) (location:HR_1_6_3P). Reason: They are not in same physical bank", - " PLL pll Port CLK_OUT (location:HP_1_CC_18_9P)", - " Route to gearbox module i_serdes (location:HR_2_0_0P)", - " Use FCLK: hvl_fclk_1_A (sub-resource: NOT_VCO)", - " Route to gearbox module i_ddr (location:HP_1_4_2P)", - " Use FCLK: hp_fclk_0_A (sub-resource: NOT_VCO)", - " Route to gearbox module o_serdes (location:HR_2_2_1P)", - " Use FCLK: hvl_fclk_1_A", - " Route to gearbox module o_serdes_clk (location:HR_2_4_2P)", - " Use FCLK: hvl_fclk_1_A", - " CLKBUF $clkbuf$top.$ibuf_clk2 (location:HR_5_CC_38_19P)", - "Allocate ROOT BANK routing resource (and set configuration attributes)", - " CLK_BUF $clkbuf$top.$ibuf_clk0", - " Resource: u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0 (Bank B)(CORE)", - " CLK_BUF $clkbuf$top.$ibuf_clk2", - " Resource: u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1 (Bank B)(CORE)", - " I_SERDES i_serdes", - " Resource: u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1 (Bank A)(CDR)", - "Set CLKBUF remaining configuration attributes (FCLK)", - " Set FCLK configuration attributes", - " CLKBUF $clkbuf$top.$ibuf_clk0 (location:HR_1_CC_38_19P) use hvl_fclk_0_A", - " Set FCLK configuration attributes", - " Skip for HR_5_CC_38_19P", - "Allocate PLL resource (and set PLLREF configuration attributes)", - " PLL pll (location:HP_1_CC_18_9P) uses FCLK 'hp_fclk_0_A, hvl_fclk_1_A'", - " Pin resource: 3, PLL FCLK requested resource: 1, PLL availability: 3", - " Use PLL: pll_0 (sub-resource: )", - " Set PLLREF configuration attributes", - " PLL pll_osc (location:BOOT_CLOCK#0) uses FCLK ''", - " Pin resource: 3, PLL FCLK requested resource: 0, PLL availability: 2", - " Warning: PLL request resource is 0 - does not need to route PLL output to FCLK. Only need to configure PLLREF configuration attributes", - " Use PLL: pll_1 (sub-resource: )", - " Set PLLREF configuration attributes", - "Set PLL remaining configuration attributes (FCLK)", - " Set FCLK configuration attributes", - " PLL pll (location:HP_1_CC_18_9P) use hp_fclk_0_A", - " PLL pll (location:HP_1_CC_18_9P) use hvl_fclk_1_A", - " Set FCLK configuration attributes", - " Skip for PLL:BOOT_CLOCK#0", - "Validation using '__secondary_validation__' rule", + "Prepare routing resource info for fast clock", + "Prepare routing resource info for core clock", + "Solve routing", + " Feature: Fast Clock: module CLK_BUF $clkbuf$top.$ibuf_clk0 port O (location: HR_1_CC_38_19P) -> module I_DELAY i_delay (location: HR_1_4_2P)", + " Status: True", + " TCL Block: u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + " cfg_rx_fclkio_sel_A_0: 1", + " cfg_rxclk_phase_sel_A_0: 1", + " cfg_vco_clk_sel_A_0: 0", + " Feature: Fast Clock: module CLK_BUF clk_buf port O (location: HP_1_CC_18_9P) -> module O_DELAY o_delay (location: HR_1_6_3P)", + " Status: False", + " Msg: Fail to find any paths first round", + " Feature: Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module I_SERDES i_serdes (location: HR_2_0_0P)", + " Status: True", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 0", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " TCL Block: u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + " cfg_rx_fclkio_sel_A_1: 0", + " cfg_rxclk_phase_sel_A_1: 0", + " cfg_vco_clk_sel_A_1: 1", + " Feature: Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr (location: HP_1_4_2P)", + " Status: True", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 0", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_fclk_mux_all", + " cfg_rx_fclkio_sel_A_0: 0", + " cfg_rxclk_phase_sel_A_0: 0", + " cfg_vco_clk_sel_A_0: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " Feature: Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module O_SERDES o_serdes (location: HR_2_2_1P)", + " Status: True", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 0", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " TCL Block: u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + " cfg_rx_fclkio_sel_A_1: 0", + " cfg_rxclk_phase_sel_A_1: 0", + " cfg_vco_clk_sel_A_1: 1", + " Feature: Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module O_SERDES_CLK o_serdes_clk (location: HR_2_4_2P)", + " Status: True", + " TCL Block: HR_2_4_2P", + " TX_CLOCK_IO: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 0", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " TCL Block: u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + " cfg_rx_fclkio_sel_A_1: 0", + " cfg_rxclk_phase_sel_A_1: 0", + " cfg_vco_clk_sel_A_1: 1", + " Feature: Core Clock: module CLK_BUF $clkbuf$top.$ibuf_clk0 port O (location: HR_1_CC_38_19P) -> core clock slot[0]", + " Status: True", + " TCL Block: HR_1_CC_38_19P", + " RX_CLOCK_IO: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0", + " ROOT_MUX_SEL: 9", + " TCL Block: u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0", + " CORE_CLK_ROOT_SEL_B: 18", + " Feature: Core Clock: module CLK_BUF clk_buf port O (location: HP_1_CC_18_9P) -> core clock slot[1]", + " Status: True", + " TCL Block: HP_1_CC_18_9P", + " RX_CLOCK_IO: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1", + " ROOT_MUX_SEL: 0", + " TCL Block: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0", + " CORE_CLK_ROOT_SEL_A: 18", + " Feature: Core Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> core clock slot[2]", + " Status: True", + " Msg: 'Core Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> core clock slot[2]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_div to value 0, had been set with value 1 by 'Core Clock: module PLL pll_osc port CLK_OUT (location: BOOT_CLOCK#0) -> core clock slot[5]'", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 0", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2", + " ROOT_MUX_SEL: 32", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 0", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 0", + " Feature: Core Clock: module CLK_BUF $clkbuf$top.$ibuf_clk2 port O (location: HR_5_CC_38_19P) -> core clock slot[3]", + " Status: True", + " TCL Block: HR_5_CC_38_19P", + " RX_CLOCK_IO: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3", + " ROOT_MUX_SEL: 19", + " TCL Block: u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1", + " CORE_CLK_ROOT_SEL_B: 18", + " Feature: Core Clock: module I_SERDES i_serdes port CLK_OUT (location: HR_2_0_0P) -> core clock slot[4]", + " Status: True", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4", + " ROOT_MUX_SEL: 14", + " TCL Block: u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1", + " CDR_CLK_ROOT_SEL_A: 0", + " Feature: Core Clock: module PLL pll_osc port CLK_OUT (location: BOOT_CLOCK#0) -> core clock slot[5]", + " Status: True", + " Msg: 'Core Clock: module PLL pll_osc port CLK_OUT (location: BOOT_CLOCK#0) -> core clock slot[5]' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_use_div to value 1, had been set with value 0 by 'Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module I_SERDES i_serdes (location: HR_2_0_0P)'", + " TCL Block: u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1", + " pll_DACEN: DACEN_0", + " pll_DSKEWCALBYP: DSKEWCALBYP_0", + " pll_DSKEWCALCNT: 2", + " pll_DSKEWCALEN: DSKEWCALEN_0", + " pll_DSKEWCALIN: 0", + " pll_DSKEWFASTCAL: DSKEWFASTCAL_0", + " pll_DSMEN: DSMEN_0", + " pll_FBDIV: 16", + " pll_FRAC: 0", + " pll_PLLEN: 0", + " pll_POSTDIV1: 2", + " pll_POSTDIV2: 2", + " pll_REFDIV: 1", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5", + " ROOT_MUX_SEL: 36", + " TCL Block: u_GBOX_HP_40X2.u_gbox_pll_refmux_1", + " cfg_pllref_hp_bank_rx_io_sel: 0", + " cfg_pllref_hp_rx_io_sel: 0", + " cfg_pllref_hv_bank_rx_io_sel: 0", + " cfg_pllref_hv_rx_io_sel: 0", + " cfg_pllref_use_div: 1", + " cfg_pllref_use_hv: 0", + " cfg_pllref_use_rosc: 1", + " Feature: Core Clock: module FCLK_BUF $clkbuf$top.clk0_div port O (location: FABRIC_CLKBUF#0) -> core clock slot[6]", + " Status: True", + " TCL Block: u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6", + " ROOT_MUX_SEL: 44", "Set configuration attributes", " Module: I_BUF ($ibuf$top.$ibuf_clk0)", " Object: clk0", @@ -100,10 +269,6 @@ " Property", " Rule CLK_BUF.GBOX_TOP", " Match", - " Rule CLK_BUF.ROOT_BANK_CLKMUX", - " Match", - " Rule CLK_BUF.ROOT_MUX", - " Match", " Module: I_BUF ($ibuf$top.$ibuf_clk1)", " Object: clk1", " Parameter", @@ -112,23 +277,15 @@ " Property", " Rule I_BUF.IOSTANDARD", " Mismatch", - " Module: PLL (pll)", + " Module: CLK_BUF (clk_buf)", " Object: clk1", " Parameter", - " Rule PLL.PLL", - " Match", - " Defined function: parse_pll_parameter", - " Rule PLL.PLLREF_MUX", - " Match", - " Rule PLL.ROOT_MUX0", + " Property", + " Rule CLK_BUF.GBOX_TOP", " Match", - " Defined function: parse_pll_root_mux", - " Rule PLL.ROOT_MUX1", - " Mismatch", - " Rule PLL.ROOT_MUX2", - " Mismatch", - " Rule PLL.ROOT_MUX3", - " Mismatch", + " Module: PLL (pll)", + " Object: clk1", + " Parameter", " Property", " Module: I_BUF ($ibuf$top.$ibuf_clk2)", " Object: clk2", @@ -144,10 +301,6 @@ " Property", " Rule CLK_BUF.GBOX_TOP", " Match", - " Rule CLK_BUF.ROOT_BANK_CLKMUX", - " Match", - " Rule CLK_BUF.ROOT_MUX", - " Match", " Module: I_BUF ($ibuf$top.$ibuf_din)", " Object: din", " Parameter", @@ -187,10 +340,6 @@ " Match", " Rule I_SERDES.DPA_MODE", " Match", - " Rule I_SERDES.ROOT_BANK_CLKMUX", - " Match", - " Rule I_SERDES.ROOT_MUX", - " Match", " Property", " Module: I_BUF ($ibuf$top.$ibuf_din_serdes_clk_out)", " Object: din_serdes_clk_out", @@ -222,8 +371,6 @@ " Defined function: parse_o_serdes_clk_phase_parameter", " Rule O_SERDES_CLK.DDR_MODE", " Match", - " Rule O_SERDES_CLK.IO", - " Match", " Property", " Module: O_BUFT ($obuf$top.$obuf_delay_tap)", " Object: delay_tap[0]", @@ -303,26 +450,10 @@ " Module: BOOT_CLOCK (boot_clock)", " Object: BOOT_CLOCK#0", " Parameter", - " Rule BOOT_CLOCK", - " Mismatch", " Property", " Module: PLL (pll_osc)", " Object: BOOT_CLOCK#0", " Parameter", - " Rule PLL.PLL", - " Match", - " Defined function: parse_pll_parameter", - " Rule PLL.PLLREF_MUX", - " Match", - " Rule PLL.ROOT_MUX0", - " Match", - " Defined function: parse_pll_root_mux", - " Rule PLL.ROOT_MUX1", - " Mismatch", - " Rule PLL.ROOT_MUX2", - " Mismatch", - " Rule PLL.ROOT_MUX3", - " Mismatch", " Property", " Module: I_BUF_DS (i_buf_ds)", " Object: din_n", @@ -350,16 +481,16 @@ " Rule I_DDR", " Match", " Property", - " Module: O_BUF_DS (o_buf_ds)", + " Module: O_BUFT_DS (o_buf_ds)", " Object: dout_n", " Parameter", " Property", - " Rule O_BUF_DS.IOSTANDARD", + " Rule O_BUFT_DS.IOSTANDARD", " Mismatch", " Object: dout_p", " Parameter", " Property", - " Rule O_BUF_DS.IOSTANDARD", + " Rule O_BUFT_DS.IOSTANDARD", " Mismatch", " Module: O_DDR (o_ddr)", " Object: dout_n", @@ -372,16 +503,16 @@ " Rule O_DDR", " Match", " Property", - " Module: O_BUF_DS (o_buf_ds_osc)", + " Module: O_BUFT_DS (o_buf_ds_osc)", " Object: dout_osc_n", " Parameter", " Property", - " Rule O_BUF_DS.IOSTANDARD", + " Rule O_BUFT_DS.IOSTANDARD", " Mismatch", " Object: dout_osc_p", " Parameter", " Property", - " Rule O_BUF_DS.IOSTANDARD", + " Rule O_BUFT_DS.IOSTANDARD", " Mismatch", " Module: O_DDR (o_ddr_osc)", " Object: dout_osc_n", @@ -397,1816 +528,1936 @@ " Module: FCLK_BUF ($clkbuf$top.clk0_div)", " Object: FABRIC_CLKBUF#0", " Parameter", - " Rule FCLK_BUF", - " Match", - " Defined function: parse_fabric_clock_buffer_root_mux", " Property", - "Warning: Generated IO bitstream is invalid" + "Info: Model bitstream generation: model_config.ppdb.json", + "Warning: Skip $ibuf$top.$ibuf_clk0 [I_BUF] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_clk1 [I_BUF] because the config attribute is empty", + "Warning: Skip pll [PLL] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_clk2 [I_BUF] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_din [I_BUF] because the config attribute is empty", + "Warning: Skip i_delay [I_DELAY] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_din_clk2 [I_BUF] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_din_serdes [I_BUF] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] because the config attribute is empty", + "Warning: Skip $ibuf$top.$ibuf_enable [I_BUF] because the location is not set", + "Warning: Skip $ibuf$top.$ibuf_enable [I_BUF] because the location is not set", + "Warning: Skip $ibuf$top.$ibuf_reset [I_BUF] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_clk_out [O_BUFT] because the config attribute is empty", + "Warning: Skip o_serdes_clk [O_SERDES_CLK] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_delay_tap [O_BUFT] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_delay_tap_1 [O_BUFT] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_delay_tap_2 [O_BUFT] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_delay_tap_3 [O_BUFT] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_delay_tap_4 [O_BUFT] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_delay_tap_5 [O_BUFT] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dout [O_BUFT] because the config attribute is empty", + "Warning: Skip o_delay [O_DELAY] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dout_clk2 [O_BUFT] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dout_serdes [O_BUFT] because the config attribute is empty", + "Warning: Skip o_serdes [O_SERDES] because the config attribute is empty", + "Warning: Skip $obuf$top.$obuf_dout_serdes_clk_out [O_BUFT] because the config attribute is empty", + "Warning: Skip boot_clock [BOOT_CLOCK] because the config attribute is empty", + "Warning: Skip boot_clock [BOOT_CLOCK] because the config attribute is empty", + "Warning: Skip pll_osc [PLL] because the config attribute is empty", + "Warning: Skip i_buf_ds [I_BUF_DS] because the config attribute is empty", + "Warning: Skip i_ddr [I_DDR] because the config attribute is empty", + "Warning: Skip o_buf_ds [O_BUFT_DS] because the config attribute is empty", + "Warning: Skip o_ddr [O_DDR] because the config attribute is empty", + "Warning: Skip o_buf_ds_osc [O_BUFT_DS] because the config attribute is empty", + "Warning: Skip o_ddr_osc [O_DDR] because the config attribute is empty", + "Warning: Skip $clkbuf$top.clk0_div [FCLK_BUF] because the config attribute is empty", + "Warning: Generated IO bitstream is invalid" ], - "instances" : [ + "instances": [ { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk0", - "location_object" : "clk0", - "location" : "HR_1_CC_38_19P", - "linked_object" : "clk0", - "linked_objects" : { - "clk0" : { - "location" : "HR_1_CC_38_19P", - "properties" : { - "IOSTANDARD" : "LVCMOS_18_HP", - "PACKAGE_PIN" : "HR_1_CC_38_19P" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk0", + "location_object": "clk0", + "location": "HR_1_CC_38_19P", + "linked_object": "clk0", + "linked_objects": { + "clk0": { + "location": "HR_1_CC_38_19P", + "properties": { + "IOSTANDARD": "LVCMOS_18_HP", + "PACKAGE_PIN": "HR_1_CC_38_19P" }, - "config_attributes" : [ + "config_attributes": [ { - "I_BUF" : "WEAK_KEEPER==NONE" + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==LVCMOS_18_HP" + "I_BUF": "IOSTANDARD==LVCMOS_18_HP" } ] } }, - "connectivity" : { - "I" : "clk0", - "O" : "$ibuf_clk0" + "connectivity": { + "I": "clk0", + "O": "$ibuf_clk0" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "CLK_BUF", - "name" : "$clkbuf$top.$ibuf_clk0", - "location_object" : "clk0", - "location" : "HR_1_CC_38_19P", - "linked_object" : "clk0", - "linked_objects" : { - "clk0" : { - "location" : "HR_1_CC_38_19P", - "properties" : { - "IOSTANDARD" : "LVCMOS_18_HP", - "PACKAGE_PIN" : "HR_1_CC_38_19P", - "ROUTE_TO_FABRIC_CLK" : "0" + "module": "CLK_BUF", + "name": "$clkbuf$top.$ibuf_clk0", + "location_object": "clk0", + "location": "HR_1_CC_38_19P", + "linked_object": "clk0", + "linked_objects": { + "clk0": { + "location": "HR_1_CC_38_19P", + "properties": { + "IOSTANDARD": "LVCMOS_18_HP", + "PACKAGE_PIN": "HR_1_CC_38_19P", + "ROUTE_TO_FABRIC_CLK": "0" }, - "config_attributes" : [ + "config_attributes": [ { - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", - "cfg_rx_fclkio_sel_A_0" : "1" - }, - { - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", - "cfg_rxclk_phase_sel_A_0" : "1" - }, - { - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", - "cfg_vco_clk_sel_A_0" : "0" - }, - { - "CLK_BUF" : "GBOX_TOP_SRC==DEFAULT" - }, - { - "CLK_BUF" : "ROOT_BANK_SRC==B --#MUX=18", - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0" - }, - { - "ROOT_MUX_SEL" : "9", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0" + "CLK_BUF": "GBOX_TOP_SRC==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$ibuf_clk0", - "O" : "$clk_buf_$ibuf_clk0" + "connectivity": { + "I": "$ibuf_clk0", + "O": "$clk_buf_$ibuf_clk0" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "0" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "0" }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "i_delay" ] }, - "route_clock_result" : { - "O" : [ - "Use FCLK: hvl_fclk_0_A (sub-resource: )" + "route_clock_result": { + "O": [ + "Pass: " ] }, - "errors" : [ + "errors": [ ], - "__AB__" : "B", - "__ROOT_BANK_MUX_LOCATION__" : "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0", - "__ROOT_BANK_MUX__" : "18", - "__ROOT_MUX__" : "9", - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__clock_pin_is_valid__,__check_fabric_clock_resource__,__update_fabric_clock_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__clock_pin_is_valid__", + "config_attributes": [ + { + "__location__": "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + "cfg_rx_fclkio_sel_A_0": "1", + "cfg_rxclk_phase_sel_A_0": "1", + "cfg_vco_clk_sel_A_0": "0" + }, + { + "RX_CLOCK_IO": "1", + "__location__": "HR_1_CC_38_19P" + }, + { + "ROOT_MUX_SEL": "9", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0" + }, + { + "CORE_CLK_ROOT_SEL_B": "18", + "__location__": "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0" + } + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk1", - "location_object" : "clk1", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk1", - "linked_objects" : { - "clk1" : { - "location" : "HP_1_CC_18_9P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk1", + "location_object": "clk1", + "location": "HP_1_CC_18_9P", + "linked_object": "clk1", + "linked_objects": { + "clk1": { + "location": "HP_1_CC_18_9P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_BUF" : "WEAK_KEEPER==NONE" + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "clk1", - "O" : "$ibuf_clk1" + "connectivity": { + "I": "clk1", + "O": "$ibuf_clk1" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf", - "location_object" : "clk1", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk1", - "linked_objects" : { - "clk1" : { - "location" : "HP_1_CC_18_9P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "1" + "module": "CLK_BUF", + "name": "clk_buf", + "location_object": "clk1", + "location": "HP_1_CC_18_9P", + "linked_object": "clk1", + "linked_objects": { + "clk1": { + "location": "HP_1_CC_18_9P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "1" }, - "config_attributes" : [ + "config_attributes": [ + { + "CLK_BUF": "GBOX_TOP_SRC==DEFAULT" + } ] } }, - "connectivity" : { - "I" : "$ibuf_clk1", - "O" : "clk1_buf" + "connectivity": { + "I": "$ibuf_clk1", + "O": "clk1_buf" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "1" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "1" }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ "PLL" ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "o_delay" ] }, - "route_clock_result" : { - "O" : [ - "Not able to route clock-capable pin clk_buf (location:HP_1_CC_18_9P) to gearbox module o_delay clock (module:O_DELAY) (location:HR_1_6_3P). Reason: They are not in same physical bank" + "route_clock_result": { + "O": [ + "Error: Fail to find any paths first round" ] }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail to route the clock" + "__validation__": true, + "__validation_msg__": "Pass:__clock_pin_is_valid__", + "config_attributes": [ + { + "RX_CLOCK_IO": "1", + "__location__": "HP_1_CC_18_9P" + }, + { + "ROOT_MUX_SEL": "0", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1" + }, + { + "CORE_CLK_ROOT_SEL_A": "18", + "__location__": "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0" + } + ] }, { - "module" : "PLL", - "name" : "pll", - "location_object" : "clk1", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk1", - "linked_objects" : { - "clk1" : { - "location" : "HP_1_CC_18_9P", - "properties" : { - "OUT0_ROUTE_TO_FABRIC_CLK" : "2" + "module": "PLL", + "name": "pll", + "location_object": "clk1", + "location": "HP_1_CC_18_9P", + "linked_object": "clk1", + "linked_objects": { + "clk1": { + "location": "HP_1_CC_18_9P", + "properties": { + "OUT0_ROUTE_TO_FABRIC_CLK": "2" }, - "config_attributes" : [ - { - "__location__" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", - "cfg_rx_fclkio_sel_A_0" : "0" - }, - { - "__location__" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", - "cfg_rxclk_phase_sel_A_0" : "0" - }, - { - "__location__" : "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", - "cfg_vco_clk_sel_A_0" : "1" - }, - { - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", - "cfg_rx_fclkio_sel_A_1" : "0" - }, - { - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", - "cfg_rxclk_phase_sel_A_1" : "0" - }, - { - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", - "cfg_vco_clk_sel_A_1" : "1" - }, - { - "PLL" : "PLL_SRC==DEFAULT", - "__location__" : "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", - "pll_FBDIV" : "16", - "pll_PLLEN" : "0", - "pll_POSTDIV1" : "2", - "pll_POSTDIV2" : "2", - "pll_REFDIV" : "1" - }, - { - "PLL" : "PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0", - "__location__" : "u_GBOX_HP_40X2.u_gbox_pll_refmux_0" - }, - { - "ROOT_MUX_SEL" : "32", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2" - } + "config_attributes": [ ] } }, - "connectivity" : { - "CLK_IN" : "clk1_buf", - "CLK_OUT" : "pll_clk", - "CLK_OUT_DIV4" : "$delete_wire$499" - }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "OUT0_ROUTE_TO_FABRIC_CLK" : "2", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" - }, - "flags" : [ + "connectivity": { + "CLK_IN": "clk1_buf", + "CLK_OUT": "pll_clk", + "CLK_OUT_DIV4": "$delete_wire$499" + }, + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "2", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" + }, + "flags": [ "PLL" ], - "pre_primitive" : "CLK_BUF", - "post_primitives" : [ + "pre_primitive": "CLK_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_serdes", "i_ddr", "o_serdes", "o_serdes_clk" ] }, - "route_clock_result" : { - "CLK_OUT" : [ - "Use FCLK: hvl_fclk_1_A (sub-resource: NOT_VCO)", - "Use FCLK: hp_fclk_0_A (sub-resource: NOT_VCO)", - "Use FCLK: hvl_fclk_1_A", - "Use FCLK: hvl_fclk_1_A" + "route_clock_result": { + "CLK_OUT": [ + "Pass: ", + "Pass: ", + "Pass: ", + "Pass: " ] }, - "errors" : [ - ], - "__BANK__" : "0", - "__DIV__" : "0", - "__PIN__" : "0", - "__SRC__" : "HP", - "__pll_enable__" : "0", - "__pll_resource__" : "0", - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pll_clock_pin_is_valid__,__check_fabric_clock_resource__,__check_pll_parameter__,__update_fabric_clock_resource__" + "errors": [ + ], + "__validation__": true, + "__validation_msg__": "Pass:__pll_clock_pin_is_valid__,__check_pll_parameter__", + "config_attributes": [ + { + "__location__": "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0", + "pll_DACEN": "DACEN_0", + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSMEN": "DSMEN_0", + "pll_FBDIV": "16", + "pll_FRAC": "0", + "pll_PLLEN": "0", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_REFDIV": "1" + }, + { + "__location__": "u_GBOX_HP_40X2.u_gbox_pll_refmux_0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_use_div": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + }, + { + "__location__": "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all", + "cfg_rx_fclkio_sel_A_1": "0", + "cfg_rxclk_phase_sel_A_1": "0", + "cfg_vco_clk_sel_A_1": "1" + }, + { + "__location__": "u_GBOX_HP_40X2.u_gbox_fclk_mux_all", + "cfg_rx_fclkio_sel_A_0": "0", + "cfg_rxclk_phase_sel_A_0": "0", + "cfg_vco_clk_sel_A_0": "1" + }, + { + "TX_CLOCK_IO": "1", + "__location__": "HR_2_4_2P" + }, + { + "ROOT_MUX_SEL": "32", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2" + } + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk2", - "location_object" : "clk2", - "location" : "HR_5_CC_38_19P", - "linked_object" : "clk2", - "linked_objects" : { - "clk2" : { - "location" : "HR_5_CC_38_19P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk2", + "location_object": "clk2", + "location": "HR_5_CC_38_19P", + "linked_object": "clk2", + "linked_objects": { + "clk2": { + "location": "HR_5_CC_38_19P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_BUF" : "WEAK_KEEPER==NONE" + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "clk2", - "O" : "$ibuf_clk2" + "connectivity": { + "I": "clk2", + "O": "$ibuf_clk2" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "CLK_BUF", - "name" : "$clkbuf$top.$ibuf_clk2", - "location_object" : "clk2", - "location" : "HR_5_CC_38_19P", - "linked_object" : "clk2", - "linked_objects" : { - "clk2" : { - "location" : "HR_5_CC_38_19P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "3" + "module": "CLK_BUF", + "name": "$clkbuf$top.$ibuf_clk2", + "location_object": "clk2", + "location": "HR_5_CC_38_19P", + "linked_object": "clk2", + "linked_objects": { + "clk2": { + "location": "HR_5_CC_38_19P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "3" }, - "config_attributes" : [ + "config_attributes": [ { - "CLK_BUF" : "GBOX_TOP_SRC==DEFAULT" - }, - { - "CLK_BUF" : "ROOT_BANK_SRC==B --#MUX=18", - "__location__" : "u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1" - }, - { - "ROOT_MUX_SEL" : "19", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3" + "CLK_BUF": "GBOX_TOP_SRC==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$ibuf_clk2", - "O" : "$clk_buf_$ibuf_clk2" + "connectivity": { + "I": "$ibuf_clk2", + "O": "$clk_buf_$ibuf_clk2" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "3" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "3" }, - "flags" : [ + "flags": [ "CLK_BUF", "PIN_CLOCK_CORE_ONLY" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__AB__" : "B", - "__ROOT_BANK_MUX_LOCATION__" : "u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1", - "__ROOT_BANK_MUX__" : "18", - "__ROOT_MUX__" : "19", - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__clock_pin_is_valid__,__check_fabric_clock_resource__,__update_fabric_clock_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__clock_pin_is_valid__", + "config_attributes": [ + { + "RX_CLOCK_IO": "1", + "__location__": "HR_5_CC_38_19P" + }, + { + "ROOT_MUX_SEL": "19", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3" + }, + { + "CORE_CLK_ROOT_SEL_B": "18", + "__location__": "u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1" + } + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din", - "location_object" : "din", - "location" : "HR_1_4_2P", - "linked_object" : "din", - "linked_objects" : { - "din" : { - "location" : "HR_1_4_2P", - "properties" : { - "IOSTANDARD" : "LVCMOS_18_HR", - "PACKAGE_PIN" : "HR_1_4_2P" + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din", + "location_object": "din", + "location": "HR_1_4_2P", + "linked_object": "din", + "linked_objects": { + "din": { + "location": "HR_1_4_2P", + "properties": { + "IOSTANDARD": "LVCMOS_18_HR", + "PACKAGE_PIN": "HR_1_4_2P" }, - "config_attributes" : [ + "config_attributes": [ { - "I_BUF" : "WEAK_KEEPER==NONE" + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==LVCMOS_18_HR" + "I_BUF": "IOSTANDARD==LVCMOS_18_HR" } ] } }, - "connectivity" : { - "I" : "din", - "O" : "$ibuf_din" + "connectivity": { + "I": "din", + "O": "$ibuf_din" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DELAY" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DELAY", - "name" : "i_delay", - "location_object" : "din", - "location" : "HR_1_4_2P", - "linked_object" : "din", - "linked_objects" : { - "din" : { - "location" : "HR_1_4_2P", - "properties" : { - "IOSTANDARD" : "LVCMOS_18_HR", - "PACKAGE_PIN" : "HR_1_4_2P" + "module": "I_DELAY", + "name": "i_delay", + "location_object": "din", + "location": "HR_1_4_2P", + "linked_object": "din", + "linked_objects": { + "din": { + "location": "HR_1_4_2P", + "properties": { + "IOSTANDARD": "LVCMOS_18_HR", + "PACKAGE_PIN": "HR_1_4_2P" }, - "config_attributes" : [ + "config_attributes": [ { - "RX_DLY" : "50" + "RX_DLY": "50" } ] } }, - "connectivity" : { - "CLK_IN" : "$clk_buf_$ibuf_clk0", - "I" : "$ibuf_din", - "O" : "din_delay" + "connectivity": { + "CLK_IN": "$clk_buf_$ibuf_clk0", + "I": "$ibuf_din", + "O": "din_delay" }, - "parameters" : { - "DELAY" : "50" + "parameters": { + "DELAY": "50" }, - "flags" : [ + "flags": [ "I_DELAY" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din_clk2", - "location_object" : "din_clk2", - "location" : "HR_5_0_0P", - "linked_object" : "din_clk2", - "linked_objects" : { - "din_clk2" : { - "location" : "HR_5_0_0P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din_clk2", + "location_object": "din_clk2", + "location": "HR_5_0_0P", + "linked_object": "din_clk2", + "linked_objects": { + "din_clk2": { + "location": "HR_5_0_0P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_BUF" : "WEAK_KEEPER==NONE" + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "din_clk2", - "O" : "$ibuf_din_clk2" + "connectivity": { + "I": "din_clk2", + "O": "$ibuf_din_clk2" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din_serdes", - "location_object" : "din_serdes", - "location" : "HR_2_0_0P", - "linked_object" : "din_serdes", - "linked_objects" : { - "din_serdes" : { - "location" : "HR_2_0_0P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din_serdes", + "location_object": "din_serdes", + "location": "HR_2_0_0P", + "linked_object": "din_serdes", + "linked_objects": { + "din_serdes": { + "location": "HR_2_0_0P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "din_serdes", - "O" : "$ibuf_din_serdes" + "connectivity": { + "I": "din_serdes", + "O": "$ibuf_din_serdes" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_SERDES" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_SERDES", - "name" : "i_serdes", - "location_object" : "din_serdes", - "location" : "HR_2_0_0P", - "linked_object" : "din_serdes", - "linked_objects" : { - "din_serdes" : { - "location" : "HR_2_0_0P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "4" + "module": "I_SERDES", + "name": "i_serdes", + "location_object": "din_serdes", + "location": "HR_2_0_0P", + "linked_object": "din_serdes", + "linked_objects": { + "din_serdes": { + "location": "HR_2_0_0P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "4" }, - "config_attributes" : [ - { - "PEER_IS_ON" : "PEER_off", - "RATE" : "8", - "RX_BYPASS" : "RX_gear_on" - }, + "config_attributes": [ { - "I_SERDES" : "DDR_MODE==SDR" + "PEER_IS_ON": "PEER_off", + "RATE": "8", + "RX_BYPASS": "RX_gear_on" }, { - "I_SERDES" : "DPA_MODE==DPA" + "I_SERDES": "DDR_MODE==SDR" }, { - "I_SERDES" : "ROOT_BANK_SRC==A&DPA_MODE==DPA --#MUX=0", - "__location__" : "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1" - }, - { - "ROOT_MUX_SEL" : "10", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4" + "I_SERDES": "DPA_MODE==DPA" } ] } }, - "connectivity" : { - "CLK_IN" : "pll_clk", - "CLK_OUT" : "iserdes_clk_out", - "D" : "$ibuf_din_serdes", - "PLL_CLK" : "pll_clk" + "connectivity": { + "CLK_IN": "pll_clk", + "CLK_OUT": "iserdes_clk_out", + "D": "$ibuf_din_serdes", + "PLL_CLK": "pll_clk" }, - "parameters" : { - "DATA_RATE" : "SDR", - "DPA_MODE" : "DPA", - "ROUTE_TO_FABRIC_CLK" : "4", - "WIDTH" : "8" + "parameters": { + "DATA_RATE": "SDR", + "DPA_MODE": "DPA", + "ROUTE_TO_FABRIC_CLK": "4", + "WIDTH": "8" }, - "flags" : [ + "flags": [ "I_SERDES" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__AB__" : "A", - "__ROOT_BANK_MUX_LOCATION__" : "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1", - "__ROOT_BANK_MUX__" : "0", - "__ROOT_MUX__" : "10", - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__check_data_width_parameter__,__check_data_rate_parameter__,__check_dpa_mode_parameter__" + "__validation__": true, + "__validation_msg__": "Pass:__check_input_data_width_parameter__,__check_data_rate_parameter__,__check_dpa_mode_parameter__", + "config_attributes": [ + { + "ROOT_MUX_SEL": "14", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4" + }, + { + "CDR_CLK_ROOT_SEL_A": "0", + "__location__": "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1" + } + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din_serdes_clk_out", - "location_object" : "din_serdes_clk_out", - "location" : "HR_2_6_3P", - "linked_object" : "din_serdes_clk_out", - "linked_objects" : { - "din_serdes_clk_out" : { - "location" : "HR_2_6_3P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din_serdes_clk_out", + "location_object": "din_serdes_clk_out", + "location": "HR_2_6_3P", + "linked_object": "din_serdes_clk_out", + "linked_objects": { + "din_serdes_clk_out": { + "location": "HR_2_6_3P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_BUF" : "WEAK_KEEPER==NONE" + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "din_serdes_clk_out", - "O" : "$ibuf_din_serdes_clk_out" + "connectivity": { + "I": "din_serdes_clk_out", + "O": "$ibuf_din_serdes_clk_out" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_enable", - "location_object" : "enable", - "location" : "", - "linked_object" : "enable", - "linked_objects" : { - "enable" : { - "location" : "", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_enable", + "location_object": "enable", + "location": "", + "linked_object": "enable", + "linked_objects": { + "enable": { + "location": "", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ ] } }, - "connectivity" : { - "I" : "enable", - "O" : "$ibuf_enable" + "connectivity": { + "I": "enable", + "O": "$ibuf_enable" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "FALSE", - "__validation_msg__" : "Fail:__pin_is_valid__" + "__validation__": false, + "__validation_msg__": "Fail:__pin_is_valid__", + "config_attributes": [ + ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_reset", - "location_object" : "reset", - "location" : "HP_1_0_0P", - "linked_object" : "reset", - "linked_objects" : { - "reset" : { - "location" : "HP_1_0_0P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_reset", + "location_object": "reset", + "location": "HP_1_0_0P", + "linked_object": "reset", + "linked_objects": { + "reset": { + "location": "HP_1_0_0P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_BUF" : "WEAK_KEEPER==NONE" + "I_BUF": "WEAK_KEEPER==NONE" }, { - "I_BUF" : "IOSTANDARD==DEFAULT" + "I_BUF": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "reset", - "O" : "$ibuf_reset" + "connectivity": { + "I": "reset", + "O": "$ibuf_reset" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_clk_out", - "location_object" : "clk_out", - "location" : "HR_2_4_2P", - "linked_object" : "clk_out", - "linked_objects" : { - "clk_out" : { - "location" : "HR_2_4_2P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_clk_out", + "location_object": "clk_out", + "location": "HR_2_4_2P", + "linked_object": "clk_out", + "linked_objects": { + "clk_out": { + "location": "HR_2_4_2P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_clk_out", - "O" : "clk_out" + "connectivity": { + "I": "$obuf_clk_out", + "O": "clk_out" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_SERDES_CLK" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_SERDES_CLK", - "name" : "o_serdes_clk", - "location_object" : "clk_out", - "location" : "HR_2_4_2P", - "linked_object" : "clk_out", - "linked_objects" : { - "clk_out" : { - "location" : "HR_2_4_2P", - "properties" : { + "module": "O_SERDES_CLK", + "name": "o_serdes_clk", + "location_object": "clk_out", + "location": "HR_2_4_2P", + "linked_object": "clk_out", + "linked_objects": { + "clk_out": { + "location": "HR_2_4_2P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "TX_CLK_PHASE" : "TX_phase_270" + "TX_CLK_PHASE": "TX_phase_270" }, { - "O_SERDES_CLK" : "DDR_MODE==SDR" - }, - { - "TX_CLOCK_IO" : "TX_clock_IO" + "O_SERDES_CLK": "DDR_MODE==SDR" } ] } }, - "connectivity" : { - "OUTPUT_CLK" : "$obuf_clk_out", - "PLL_CLK" : "pll_clk" + "connectivity": { + "OUTPUT_CLK": "$obuf_clk_out", + "PLL_CLK": "pll_clk" }, - "parameters" : { - "CLOCK_PHASE" : "270", - "DATA_RATE" : "SDR" + "parameters": { + "CLOCK_PHASE": "270", + "DATA_RATE": "SDR" }, - "flags" : [ + "flags": [ "O_SERDES_CLK" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__check_data_rate_parameter__,__check_clock_phase_parameter__" + "__validation__": true, + "__validation_msg__": "Pass:__check_data_rate_parameter__,__check_clock_phase_parameter__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap", - "location_object" : "delay_tap[0]", - "location" : "HR_2_20_10P", - "linked_object" : "delay_tap[0]", - "linked_objects" : { - "delay_tap[0]" : { - "location" : "HR_2_20_10P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap", + "location_object": "delay_tap[0]", + "location": "HR_2_20_10P", + "linked_object": "delay_tap[0]", + "linked_objects": { + "delay_tap[0]": { + "location": "HR_2_20_10P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_delay_tap[0]", - "O" : "delay_tap[0]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[0]", + "O": "delay_tap[0]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_1", - "location_object" : "delay_tap[1]", - "location" : "HR_2_22_11P", - "linked_object" : "delay_tap[1]", - "linked_objects" : { - "delay_tap[1]" : { - "location" : "HR_2_22_11P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_1", + "location_object": "delay_tap[1]", + "location": "HR_2_22_11P", + "linked_object": "delay_tap[1]", + "linked_objects": { + "delay_tap[1]": { + "location": "HR_2_22_11P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_delay_tap[1]", - "O" : "delay_tap[1]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[1]", + "O": "delay_tap[1]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_2", - "location_object" : "delay_tap[2]", - "location" : "HR_2_24_12P", - "linked_object" : "delay_tap[2]", - "linked_objects" : { - "delay_tap[2]" : { - "location" : "HR_2_24_12P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_2", + "location_object": "delay_tap[2]", + "location": "HR_2_24_12P", + "linked_object": "delay_tap[2]", + "linked_objects": { + "delay_tap[2]": { + "location": "HR_2_24_12P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_delay_tap[2]", - "O" : "delay_tap[2]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[2]", + "O": "delay_tap[2]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_3", - "location_object" : "delay_tap[3]", - "location" : "HR_2_26_13P", - "linked_object" : "delay_tap[3]", - "linked_objects" : { - "delay_tap[3]" : { - "location" : "HR_2_26_13P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_3", + "location_object": "delay_tap[3]", + "location": "HR_2_26_13P", + "linked_object": "delay_tap[3]", + "linked_objects": { + "delay_tap[3]": { + "location": "HR_2_26_13P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_delay_tap[3]", - "O" : "delay_tap[3]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[3]", + "O": "delay_tap[3]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_4", - "location_object" : "delay_tap[4]", - "location" : "HR_2_28_14P", - "linked_object" : "delay_tap[4]", - "linked_objects" : { - "delay_tap[4]" : { - "location" : "HR_2_28_14P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_4", + "location_object": "delay_tap[4]", + "location": "HR_2_28_14P", + "linked_object": "delay_tap[4]", + "linked_objects": { + "delay_tap[4]": { + "location": "HR_2_28_14P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_delay_tap[4]", - "O" : "delay_tap[4]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[4]", + "O": "delay_tap[4]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_5", - "location_object" : "delay_tap[5]", - "location" : "HR_2_30_15P", - "linked_object" : "delay_tap[5]", - "linked_objects" : { - "delay_tap[5]" : { - "location" : "HR_2_30_15P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_5", + "location_object": "delay_tap[5]", + "location": "HR_2_30_15P", + "linked_object": "delay_tap[5]", + "linked_objects": { + "delay_tap[5]": { + "location": "HR_2_30_15P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_delay_tap[5]", - "O" : "delay_tap[5]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[5]", + "O": "delay_tap[5]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout", - "location_object" : "dout", - "location" : "HR_1_6_3P", - "linked_object" : "dout", - "linked_objects" : { - "dout" : { - "location" : "HR_1_6_3P", - "properties" : { - "IOSTANDARD" : "LVCMOS_18_HR", - "PACKAGE_PIN" : "HR_1_6_3P" + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout", + "location_object": "dout", + "location": "HR_1_6_3P", + "linked_object": "dout", + "linked_objects": { + "dout": { + "location": "HR_1_6_3P", + "properties": { + "IOSTANDARD": "LVCMOS_18_HR", + "PACKAGE_PIN": "HR_1_6_3P" }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==LVCMOS_18_HR" + "O_BUFT": "IOSTANDARD==LVCMOS_18_HR" } ] } }, - "connectivity" : { - "I" : "$obuf_dout", - "O" : "dout" + "connectivity": { + "I": "$obuf_dout", + "O": "dout" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DELAY" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_DELAY", - "name" : "o_delay", - "location_object" : "dout", - "location" : "HR_1_6_3P", - "linked_object" : "dout", - "linked_objects" : { - "dout" : { - "location" : "HR_1_6_3P", - "properties" : { - "IOSTANDARD" : "LVCMOS_18_HR", - "PACKAGE_PIN" : "HR_1_6_3P" + "module": "O_DELAY", + "name": "o_delay", + "location_object": "dout", + "location": "HR_1_6_3P", + "linked_object": "dout", + "linked_objects": { + "dout": { + "location": "HR_1_6_3P", + "properties": { + "IOSTANDARD": "LVCMOS_18_HR", + "PACKAGE_PIN": "HR_1_6_3P" }, - "config_attributes" : [ + "config_attributes": [ { - "TX_DLY" : "60" + "TX_DLY": "60" } ] } }, - "connectivity" : { - "CLK_IN" : "clk1_buf", - "I" : "dout_pre_delay", - "O" : "$obuf_dout" + "connectivity": { + "CLK_IN": "clk1_buf", + "I": "$f2g_tx_out_dout_pre_delay", + "O": "$obuf_dout" }, - "parameters" : { - "DELAY" : "60" + "parameters": { + "DELAY": "60" }, - "flags" : [ + "flags": [ "O_DELAY" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout_clk2", - "location_object" : "dout_clk2", - "location" : "HR_5_1_0N", - "linked_object" : "dout_clk2", - "linked_objects" : { - "dout_clk2" : { - "location" : "HR_5_1_0N", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout_clk2", + "location_object": "dout_clk2", + "location": "HR_5_1_0N", + "linked_object": "dout_clk2", + "linked_objects": { + "dout_clk2": { + "location": "HR_5_1_0N", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_dout_clk2", - "O" : "dout_clk2" + "connectivity": { + "I": "$f2g_tx_out_$obuf_dout_clk2", + "O": "dout_clk2" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout_serdes", - "location_object" : "dout_serdes", - "location" : "HR_2_2_1P", - "linked_object" : "dout_serdes", - "linked_objects" : { - "dout_serdes" : { - "location" : "HR_2_2_1P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout_serdes", + "location_object": "dout_serdes", + "location": "HR_2_2_1P", + "linked_object": "dout_serdes", + "linked_objects": { + "dout_serdes": { + "location": "HR_2_2_1P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_dout_serdes", - "O" : "dout_serdes" + "connectivity": { + "I": "$obuf_dout_serdes", + "O": "dout_serdes" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_SERDES" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_SERDES", - "name" : "o_serdes", - "location_object" : "dout_serdes", - "location" : "HR_2_2_1P", - "linked_object" : "dout_serdes", - "linked_objects" : { - "dout_serdes" : { - "location" : "HR_2_2_1P", - "properties" : { + "module": "O_SERDES", + "name": "o_serdes", + "location_object": "dout_serdes", + "location": "HR_2_2_1P", + "linked_object": "dout_serdes", + "linked_objects": { + "dout_serdes": { + "location": "HR_2_2_1P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "PEER_IS_ON" : "PEER_off", - "RATE" : "8", - "TX_BYPASS" : "TX_gear_on" + "PEER_IS_ON": "PEER_off", + "RATE": "8", + "TX_BYPASS": "TX_gear_on" }, { - "O_SERDES" : "DDR_MODE==DDR" + "O_SERDES": "DDR_MODE==DDR" } ] } }, - "connectivity" : { - "CLK_IN" : "pll_clk", - "PLL_CLK" : "pll_clk", - "Q" : "$obuf_dout_serdes" + "connectivity": { + "CLK_IN": "pll_clk", + "PLL_CLK": "pll_clk", + "Q": "$obuf_dout_serdes" }, - "parameters" : { - "DATA_RATE" : "DDR", - "WIDTH" : "8" + "parameters": { + "DATA_RATE": "DDR", + "WIDTH": "8" }, - "flags" : [ + "flags": [ "O_SERDES" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__check_data_width_parameter__,__check_data_rate_parameter__" + "__validation__": true, + "__validation_msg__": "Pass:__check_output_data_width_parameter__,__check_data_rate_parameter__", + "config_attributes": [ + ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout_serdes_clk_out", - "location_object" : "dout_serdes_clk_out", - "location" : "HR_2_7_3N", - "linked_object" : "dout_serdes_clk_out", - "linked_objects" : { - "dout_serdes_clk_out" : { - "location" : "HR_2_7_3N", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout_serdes_clk_out", + "location_object": "dout_serdes_clk_out", + "location": "HR_2_7_3N", + "linked_object": "dout_serdes_clk_out", + "linked_objects": { + "dout_serdes_clk_out": { + "location": "HR_2_7_3N", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUFT" : "IOSTANDARD==DEFAULT" + "O_BUFT": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "$obuf_dout_serdes_clk_out", - "O" : "dout_serdes_clk_out" + "connectivity": { + "I": "$f2g_tx_out_$obuf_dout_serdes_clk_out", + "O": "dout_serdes_clk_out" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__pin_is_valid__,__check_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "BOOT_CLOCK", - "name" : "boot_clock", - "location_object" : "BOOT_CLOCK#0", - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "properties" : { + "module": "BOOT_CLOCK", + "name": "boot_clock", + "location_object": "BOOT_CLOCK#0", + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ ] } }, - "connectivity" : { - "O" : "osc" + "connectivity": { + "O": "osc" }, - "parameters" : { - "PERIOD" : "25" + "parameters": { + "PERIOD": "25" }, - "flags" : [ + "flags": [ "BOOT_CLOCK" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "PLL" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__check_boot_clock_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__check_boot_clock_resource__", + "config_attributes": [ + ] }, { - "module" : "PLL", - "name" : "pll_osc", - "location_object" : "BOOT_CLOCK#0", - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", - "properties" : { - "OUT0_ROUTE_TO_FABRIC_CLK" : "5" + "module": "PLL", + "name": "pll_osc", + "location_object": "BOOT_CLOCK#0", + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "__SKIP_LOCATION_CHECK__:BOOT_CLOCK#0", + "properties": { + "OUT0_ROUTE_TO_FABRIC_CLK": "5" }, - "config_attributes" : [ - { - "PLL" : "PLL_SRC==DEFAULT", - "__location__" : "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1", - "pll_FBDIV" : "16", - "pll_PLLEN" : "0", - "pll_POSTDIV1" : "2", - "pll_POSTDIV2" : "2", - "pll_REFDIV" : "1" - }, - { - "PLL" : "PLLREF_SRC==BOOT_CLOCK --#PIN=UNKNOWN --#BANK=UNKNOWN --#DIV=1", - "__location__" : "u_GBOX_HP_40X2.u_gbox_pll_refmux_1" - }, - { - "ROOT_MUX_SEL" : "36", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5" - } + "config_attributes": [ ] } }, - "connectivity" : { - "CLK_IN" : "osc", - "CLK_OUT" : "osc_pll" + "connectivity": { + "CLK_IN": "osc", + "CLK_OUT": "osc_pll" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "TRUE", - "OUT0_ROUTE_TO_FABRIC_CLK" : "5", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "TRUE", + "OUT0_ROUTE_TO_FABRIC_CLK": "5", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "BOOT_CLOCK", - "post_primitives" : [ - ], - "route_clock_to" : { - }, - "route_clock_result" : { - }, - "errors" : [ - ], - "__BANK__" : "UNKNOWN", - "__DIV__" : "1", - "__PIN__" : "UNKNOWN", - "__SRC__" : "BOOT_CLOCK", - "__pll_enable__" : "0", - "__pll_resource__" : "1", - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__check_fabric_clock_resource__,__check_pll_parameter__,__update_fabric_clock_resource__" + "pre_primitive": "BOOT_CLOCK", + "post_primitives": [ + ], + "route_clock_to": { + }, + "route_clock_result": { + }, + "errors": [ + ], + "__validation__": true, + "__validation_msg__": "Pass:__check_pll_parameter__", + "config_attributes": [ + { + "__location__": "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1", + "pll_DACEN": "DACEN_0", + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSMEN": "DSMEN_0", + "pll_FBDIV": "16", + "pll_FRAC": "0", + "pll_PLLEN": "0", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_REFDIV": "1" + }, + { + "ROOT_MUX_SEL": "36", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5" + }, + { + "__location__": "u_GBOX_HP_40X2.u_gbox_pll_refmux_1", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_use_div": "1", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "1" + } + ] }, { - "module" : "I_BUF_DS", - "name" : "i_buf_ds", - "location_object" : "din_p", - "location" : "HP_1_4_2P", - "linked_object" : "din_n+din_p", - "linked_objects" : { - "din_n" : { - "location" : "HP_1_5_2N", - "properties" : { + "module": "I_BUF_DS", + "name": "i_buf_ds", + "location_object": "din_p", + "location": "HP_1_4_2P", + "linked_object": "din_n+din_p", + "linked_objects": { + "din_n": { + "location": "HP_1_5_2N", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "DFODTEN" : "DF_odt_enable" + "DFODTEN": "DF_odt_enable" }, { - "I_BUF_DS" : "IOSTANDARD==DEFAULT" + "I_BUF_DS": "IOSTANDARD==DEFAULT" } ] }, - "din_p" : { - "location" : "HP_1_4_2P", - "properties" : { + "din_p": { + "location": "HP_1_4_2P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "DFODTEN" : "DF_odt_enable" + "DFODTEN": "DF_odt_enable" }, { - "I_BUF_DS" : "IOSTANDARD==DEFAULT" + "I_BUF_DS": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I_N" : "din_n", - "I_P" : "din_p", - "O" : "i_ddr_d" + "connectivity": { + "I_N": "din_n", + "I_P": "din_p", + "O": "i_ddr_d" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT", - "WEAK_KEEPER" : "NONE" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "I_DDR", - "name" : "i_ddr", - "location_object" : "din_p", - "location" : "HP_1_4_2P", - "linked_object" : "din_n+din_p", - "linked_objects" : { - "din_n" : { - "location" : "HP_1_5_2N", - "properties" : { + "module": "I_DDR", + "name": "i_ddr", + "location_object": "din_p", + "location": "HP_1_4_2P", + "linked_object": "din_n+din_p", + "linked_objects": { + "din_n": { + "location": "HP_1_5_2N", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_DDR" : "MODE==DDR" + "I_DDR": "MODE==DDR" } ] }, - "din_p" : { - "location" : "HP_1_4_2P", - "properties" : { + "din_p": { + "location": "HP_1_4_2P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "I_DDR" : "MODE==DDR" + "I_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pll_clk", - "D" : "i_ddr_d" + "connectivity": { + "C": "pll_clk", + "D": "i_ddr_d" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF_DS", - "post_primitives" : [ + "pre_primitive": "I_BUF_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "O_BUF_DS", - "name" : "o_buf_ds", - "location_object" : "dout_p", - "location" : "HP_1_8_4P", - "linked_object" : "dout_n+dout_p", - "linked_objects" : { - "dout_n" : { - "location" : "HP_1_9_4N", - "properties" : { + "module": "O_BUFT_DS", + "name": "o_buf_ds", + "location_object": "dout_p", + "location": "HP_1_8_4P", + "linked_object": "dout_n+dout_p", + "linked_objects": { + "dout_n": { + "location": "HP_1_9_4N", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUF_DS" : "IOSTANDARD==DEFAULT" + "O_BUFT_DS": "IOSTANDARD==DEFAULT" } ] }, - "dout_p" : { - "location" : "HP_1_8_4P", - "properties" : { + "dout_p": { + "location": "HP_1_8_4P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUF_DS" : "IOSTANDARD==DEFAULT" + "O_BUFT_DS": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "o_buf_ds_i", - "O_N" : "dout_n", - "O_P" : "dout_p" + "connectivity": { + "I": "o_buf_ds_i", + "O_N": "dout_n", + "O_P": "dout_p" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ - "O_BUF_DS" + "flags": [ + "O_BUFT_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_DDR", - "name" : "o_ddr", - "location_object" : "dout_p", - "location" : "HP_1_8_4P", - "linked_object" : "dout_n+dout_p", - "linked_objects" : { - "dout_n" : { - "location" : "HP_1_9_4N", - "properties" : { + "module": "O_DDR", + "name": "o_ddr", + "location_object": "dout_p", + "location": "HP_1_8_4P", + "linked_object": "dout_n+dout_p", + "linked_objects": { + "dout_n": { + "location": "HP_1_9_4N", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_DDR" : "MODE==DDR" + "O_DDR": "MODE==DDR" } ] }, - "dout_p" : { - "location" : "HP_1_8_4P", - "properties" : { + "dout_p": { + "location": "HP_1_8_4P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_DDR" : "MODE==DDR" + "O_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "pll_clk", - "Q" : "o_buf_ds_i" + "connectivity": { + "C": "pll_clk", + "Q": "o_buf_ds_i" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUF_DS", - "post_primitives" : [ + "pre_primitive": "O_BUFT_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "O_BUF_DS", - "name" : "o_buf_ds_osc", - "location_object" : "dout_osc_p", - "location" : "HP_2_22_11P", - "linked_object" : "dout_osc_n+dout_osc_p", - "linked_objects" : { - "dout_osc_n" : { - "location" : "HP_2_23_11N", - "properties" : { + "module": "O_BUFT_DS", + "name": "o_buf_ds_osc", + "location_object": "dout_osc_p", + "location": "HP_2_22_11P", + "linked_object": "dout_osc_n+dout_osc_p", + "linked_objects": { + "dout_osc_n": { + "location": "HP_2_23_11N", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUF_DS" : "IOSTANDARD==DEFAULT" + "O_BUFT_DS": "IOSTANDARD==DEFAULT" } ] }, - "dout_osc_p" : { - "location" : "HP_2_22_11P", - "properties" : { + "dout_osc_p": { + "location": "HP_2_22_11P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_BUF_DS" : "IOSTANDARD==DEFAULT" + "O_BUFT_DS": "IOSTANDARD==DEFAULT" } ] } }, - "connectivity" : { - "I" : "o_buf_ds_i_osc", - "O_N" : "dout_osc_n", - "O_P" : "dout_osc_p" + "connectivity": { + "I": "o_buf_ds_i_osc", + "O_N": "dout_osc_n", + "O_P": "dout_osc_p" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ - "O_BUF_DS" + "flags": [ + "O_BUFT_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__" + "__validation__": true, + "__validation_msg__": "Pass:__ds_pin_is_valid__,__pin_is_differential__,__check_ds_pin_resource__", + "config_attributes": [ + ] }, { - "module" : "O_DDR", - "name" : "o_ddr_osc", - "location_object" : "dout_osc_p", - "location" : "HP_2_22_11P", - "linked_object" : "dout_osc_n+dout_osc_p", - "linked_objects" : { - "dout_osc_n" : { - "location" : "HP_2_23_11N", - "properties" : { + "module": "O_DDR", + "name": "o_ddr_osc", + "location_object": "dout_osc_p", + "location": "HP_2_22_11P", + "linked_object": "dout_osc_n+dout_osc_p", + "linked_objects": { + "dout_osc_n": { + "location": "HP_2_23_11N", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_DDR" : "MODE==DDR" + "O_DDR": "MODE==DDR" } ] }, - "dout_osc_p" : { - "location" : "HP_2_22_11P", - "properties" : { + "dout_osc_p": { + "location": "HP_2_22_11P", + "properties": { }, - "config_attributes" : [ + "config_attributes": [ { - "O_DDR" : "MODE==DDR" + "O_DDR": "MODE==DDR" } ] } }, - "connectivity" : { - "C" : "osc_pll", - "Q" : "o_buf_ds_i_osc" + "connectivity": { + "C": "osc_pll", + "Q": "o_buf_ds_i_osc" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUF_DS", - "post_primitives" : [ + "pre_primitive": "O_BUFT_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + ] }, { - "module" : "FCLK_BUF", - "name" : "$clkbuf$top.clk0_div", - "location_object" : "FABRIC_CLKBUF#0", - "location" : "__SKIP_LOCATION_CHECK__:FABRIC_CLKBUF#0", - "linked_object" : "FABRIC_CLKBUF#0", - "linked_objects" : { - "FABRIC_CLKBUF#0" : { - "location" : "__SKIP_LOCATION_CHECK__:FABRIC_CLKBUF#0", - "properties" : { - "ROUTE_FROM_FABRIC_CLK" : "0", - "ROUTE_TO_FABRIC_CLK" : "6" + "module": "FCLK_BUF", + "name": "$clkbuf$top.clk0_div", + "location_object": "FABRIC_CLKBUF#0", + "location": "__SKIP_LOCATION_CHECK__:FABRIC_CLKBUF#0", + "linked_object": "FABRIC_CLKBUF#0", + "linked_objects": { + "FABRIC_CLKBUF#0": { + "location": "__SKIP_LOCATION_CHECK__:FABRIC_CLKBUF#0", + "properties": { + "ROUTE_FROM_FABRIC_CLK": "0", + "ROUTE_TO_FABRIC_CLK": "6" }, - "config_attributes" : [ - { - "ROOT_MUX_SEL" : "44", - "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6" - } + "config_attributes": [ ] } }, - "connectivity" : { - "I" : "clk0_div", - "O" : "$fclk_buf_clk0_div" + "connectivity": { + "I": "clk0_div", + "O": "$fclk_buf_clk0_div" }, - "parameters" : { - "ROUTE_FROM_FABRIC_CLK" : "0", - "ROUTE_TO_FABRIC_CLK" : "6" + "parameters": { + "ROUTE_FROM_FABRIC_CLK": "0", + "ROUTE_TO_FABRIC_CLK": "6" }, - "flags" : [ + "flags": [ "FCLK_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "route_clock_result" : { + "route_clock_result": { }, - "errors" : [ + "errors": [ ], - "__validation__" : "TRUE", - "__validation_msg__" : "" + "__validation__": true, + "__validation_msg__": "", + "config_attributes": [ + { + "ROOT_MUX_SEL": "44", + "__location__": "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6" + } + ] } ] } diff --git a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.backdoor.txt b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.backdoor.txt index 89347a57c..c6354983e 100644 --- a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.backdoor.txt +++ b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.backdoor.txt @@ -434,7 +434,7 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[10].control = force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[9].control = 42'b000000000000000000000000000000000000100000; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_9 [Customer Name: HP_1_CC_18_9P] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[9].control = 42'b000100000010000000000100000000001000100011; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_A[9].control = 42'b000100000110000000000100000000001000100011; // u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_8 [Customer Name: HP_1_17_8N] force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_hp_40_NS_0.u_gbox_io_cfg_B[8].control = 42'b000000000000000000000000000000000000100000; @@ -497,7 +497,7 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_pgen_cfg0.control = 6'b000000; force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[11:0] = 12'b010000000000; // u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 [Customer Name: ] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[31:12] = 20'b00000000000000000000; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[31:12] = 20'b10010000000000000000; // u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_1 [Customer Name: ] force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[51:32] = 20'b00000000000000000000; @@ -506,7 +506,7 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[51:32] = 20'b000000 force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[57:52] = 6'b001001; // u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1 [Customer Name: ] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[63:58] = 6'b111111; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[63:58] = 6'b000000; // u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2 [Customer Name: ] force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[69:64] = 6'b100000; @@ -515,7 +515,7 @@ force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[69:64] = 6'b100000; force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[75:70] = 6'b010011; // u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4 [Customer Name: ] -force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[81:76] = 6'b001010; +force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[81:76] = 6'b001110; // u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5 [Customer Name: ] force u_dut.u_gbox_hp_NS_BANK_x2.u_gbox_vco_fask_cfg.control[87:82] = 6'b100100; diff --git a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit index 031137784..54632a09d 100644 --- a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit +++ b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit @@ -992,7 +992,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_19 [HR_5_CC_38_19P] RATE - Addr: 0x000006BA, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000006BE, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x000006BF, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000006C0, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000006C0, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x000006C1, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000006C3, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $clkbuf$top.$ibuf_clk2 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x000006C4, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -1004,7 +1004,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_19 [HR_5_CC_38_19P] RX_MIPI_MODE - Addr: 0x000006D7, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x000006D8, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x000006D9, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000006DA, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $clkbuf$top.$ibuf_clk2 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000006DA, Size: 1, Value: (0x00000001) 1 { $clkbuf$top.$ibuf_clk2 [CLK_BUF] [RX_CLOCK_IO:1] } DFEN - Addr: 0x000006DB, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x000006DC, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x000006DD, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk2 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -1880,7 +1880,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_B_0 [HR_5_1_0N] RATE - Addr: 0x00000CCC, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00000CD0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00000CD1, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00000CD2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00000CD2, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00000CD3, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000CD5, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00000CD6, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -1904,7 +1904,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_0 [HR_5_0_0P] RATE - Addr: 0x00000CF6, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00000CFA, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00000CFB, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00000CFC, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00000CFC, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00000CFD, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000CFF, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00000D00, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -1916,7 +1916,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_0 [HR_5_0_0P] RX_MIPI_MODE - Addr: 0x00000D13, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00000D14, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00000D15, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00000D16, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00000D16, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00000D17, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00000D18, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00000D19, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -1951,7 +1951,7 @@ Block u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x00000D42, Size: 5, Value: (0x00000000) 0 CDR_CLK_ROOT_SEL_A - Addr: 0x00000D47, Size: 5, Value: (0x00000000) 0 - CORE_CLK_ROOT_SEL_B - Addr: 0x00000D4C, Size: 5, Value: (0x00000012) 18 { $clkbuf$top.$ibuf_clk2 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==B --#MUX=18] [from HR_5_CC_38_19P] } + CORE_CLK_ROOT_SEL_B - Addr: 0x00000D4C, Size: 5, Value: (0x00000012) 18 { $clkbuf$top.$ibuf_clk2 [CLK_BUF] [CORE_CLK_ROOT_SEL_B:18] [from HR_5_CC_38_19P] } CORE_CLK_ROOT_SEL_A - Addr: 0x00000D51, Size: 5, Value: (0x00000000) 0 Block u_GBOX_HP_40X2.u_HP_GBOX_BK1_B_19 [HP_2_CC_39_19N] Attributes: @@ -2339,52 +2339,52 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK1_A_12 [HP_2_24_12P] MC - Addr: 0x00000FF2, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HP_40X2.u_HP_GBOX_BK1_B_11 [HP_2_23_11N] Attributes: - RATE - Addr: 0x00000FF6, Size: 4, Value: (0x00000003) 3 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00000FFA, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00000FFB, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00000FFC, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00000FFD, Size: 2, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT], o_ddr_osc [O_DDR] [O_DDR:MODE==DDR] } - TX_BYPASS - Addr: 0x00000FFF, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00001000, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00000FF6, Size: 4, Value: (0x00000003) 3 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00000FFA, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00000FFB, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00000FFC, Size: 1, Value: (0x00000000) 0 + TX_DDR_MODE - Addr: 0x00000FFD, Size: 2, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT], o_ddr_osc [O_DDR] [O_DDR:MODE==DDR] } + TX_BYPASS - Addr: 0x00000FFF, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00001000, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00001002, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x00001008, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x0000100A, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x0000100B, Size: 6, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00001011, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00001013, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00001014, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00001015, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001016, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x00001017, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - SR - Addr: 0x00001018, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00001019, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x0000101A, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x0000101B, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - MC - Addr: 0x0000101C, Size: 4, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x00001008, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x0000100A, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x0000100B, Size: 6, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00001011, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00001013, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00001014, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00001015, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001016, Size: 1, Value: (0x00000000) 0 + DFEN - Addr: 0x00001017, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + SR - Addr: 0x00001018, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00001019, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x0000101A, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x0000101B, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + MC - Addr: 0x0000101C, Size: 4, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } Block u_GBOX_HP_40X2.u_HP_GBOX_BK1_A_11 [HP_2_22_11P] Attributes: - RATE - Addr: 0x00001020, Size: 4, Value: (0x00000003) 3 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00001024, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001025, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001026, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00001027, Size: 2, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT], o_ddr_osc [O_DDR] [O_DDR:MODE==DDR] } - TX_BYPASS - Addr: 0x00001029, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x0000102A, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00001020, Size: 4, Value: (0x00000003) 3 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00001024, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001025, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001026, Size: 1, Value: (0x00000000) 0 + TX_DDR_MODE - Addr: 0x00001027, Size: 2, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT], o_ddr_osc [O_DDR] [O_DDR:MODE==DDR] } + TX_BYPASS - Addr: 0x00001029, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x0000102A, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x0000102C, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x00001032, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00001034, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x00001035, Size: 6, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x0000103B, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x0000103D, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x0000103E, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x0000103F, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001040, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x00001041, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - SR - Addr: 0x00001042, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00001043, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00001044, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x00001045, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - MC - Addr: 0x00001046, Size: 4, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x00001032, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00001034, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x00001035, Size: 6, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x0000103B, Size: 2, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x0000103D, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x0000103E, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x0000103F, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001040, Size: 1, Value: (0x00000000) 0 + DFEN - Addr: 0x00001041, Size: 1, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + SR - Addr: 0x00001042, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00001043, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00001044, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x00001045, Size: 1, Value: (0x00000000) 0 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + MC - Addr: 0x00001046, Size: 4, Value: (0x00000001) 1 { o_buf_ds_osc [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } Block u_GBOX_HP_40X2.u_HP_GBOX_BK1_B_10 [HP_2_21_10N] Attributes: RATE - Addr: 0x0000104A, Size: 4, Value: (0x00000000) 0 @@ -3422,19 +3422,19 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_9 [HP_1_CC_18_9P] RATE - Addr: 0x00001758, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000175C, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000175D, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000175E, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000175E, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x0000175F, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x00001761, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x00001761, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001762, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00001764, Size: 6, Value: (0x00000000) 0 RX_DDR_MODE - Addr: 0x0000176A, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x0000176C, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x0000176C, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } RX_DLY - Addr: 0x0000176D, Size: 6, Value: (0x00000000) 0 RX_DPA_MODE - Addr: 0x00001773, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } RX_MIPI_MODE - Addr: 0x00001775, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001776, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001777, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001778, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001778, Size: 1, Value: (0x00000001) 1 { clk_buf [CLK_BUF] [RX_CLOCK_IO:1] } DFEN - Addr: 0x00001779, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x0000177A, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x0000177B, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk1 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -3635,52 +3635,52 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_5 [HP_1_10_5P] MC - Addr: 0x000018CE, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_4 [HP_1_9_4N] Attributes: - RATE - Addr: 0x000018D2, Size: 4, Value: (0x00000003) 3 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x000018D6, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000018D7, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000018D8, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x000018D9, Size: 2, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT], o_ddr [O_DDR] [O_DDR:MODE==DDR] } - TX_BYPASS - Addr: 0x000018DB, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x000018DC, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x000018D2, Size: 4, Value: (0x00000003) 3 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x000018D6, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000018D7, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000018D8, Size: 1, Value: (0x00000000) 0 + TX_DDR_MODE - Addr: 0x000018D9, Size: 2, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT], o_ddr [O_DDR] [O_DDR:MODE==DDR] } + TX_BYPASS - Addr: 0x000018DB, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x000018DC, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x000018DE, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x000018E4, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x000018E6, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x000018E7, Size: 6, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x000018ED, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x000018EF, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x000018F0, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x000018F1, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000018F2, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x000018F3, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - SR - Addr: 0x000018F4, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PE - Addr: 0x000018F5, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x000018F6, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x000018F7, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - MC - Addr: 0x000018F8, Size: 4, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x000018E4, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x000018E6, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x000018E7, Size: 6, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x000018ED, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x000018EF, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x000018F0, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x000018F1, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000018F2, Size: 1, Value: (0x00000000) 0 + DFEN - Addr: 0x000018F3, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + SR - Addr: 0x000018F4, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PE - Addr: 0x000018F5, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x000018F6, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x000018F7, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + MC - Addr: 0x000018F8, Size: 4, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_4 [HP_1_8_4P] Attributes: - RATE - Addr: 0x000018FC, Size: 4, Value: (0x00000003) 3 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00001900, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001901, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001902, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00001903, Size: 2, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT], o_ddr [O_DDR] [O_DDR:MODE==DDR] } - TX_BYPASS - Addr: 0x00001905, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00001906, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x000018FC, Size: 4, Value: (0x00000003) 3 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00001900, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001901, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001902, Size: 1, Value: (0x00000000) 0 + TX_DDR_MODE - Addr: 0x00001903, Size: 2, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT], o_ddr [O_DDR] [O_DDR:MODE==DDR] } + TX_BYPASS - Addr: 0x00001905, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00001906, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00001908, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x0000190E, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00001910, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x00001911, Size: 6, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00001917, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00001919, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x0000191A, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x0000191B, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x0000191C, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x0000191D, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - SR - Addr: 0x0000191E, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PE - Addr: 0x0000191F, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00001920, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x00001921, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } - MC - Addr: 0x00001922, Size: 4, Value: (0x00000001) 1 { o_buf_ds [O_BUF_DS] [O_BUF_DS:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x0000190E, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00001910, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x00001911, Size: 6, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00001917, Size: 2, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00001919, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x0000191A, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x0000191B, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x0000191C, Size: 1, Value: (0x00000000) 0 + DFEN - Addr: 0x0000191D, Size: 1, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + SR - Addr: 0x0000191E, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PE - Addr: 0x0000191F, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00001920, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x00001921, Size: 1, Value: (0x00000000) 0 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } + MC - Addr: 0x00001922, Size: 4, Value: (0x00000001) 1 { o_buf_ds [O_BUFT_DS] [O_BUFT_DS:IOSTANDARD==DEFAULT] } Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_3 [HP_1_7_3N] Attributes: RATE - Addr: 0x00001926, Size: 4, Value: (0x00000000) 0 @@ -3734,7 +3734,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_2 [HP_1_5_2N] RATE - Addr: 0x0000197A, Size: 4, Value: (0x00000003) 3 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000197E, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000197F, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001980, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001980, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001981, Size: 2, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001983, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001984, Size: 2, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -3746,7 +3746,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_2 [HP_1_5_2N] RX_MIPI_MODE - Addr: 0x00001997, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001998, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } RX_MODE - Addr: 0x00001999, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x0000199A, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x0000199A, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x0000199B, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } SR - Addr: 0x0000199C, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PE - Addr: 0x0000199D, Size: 1, Value: (0x00000000) 0 @@ -3758,7 +3758,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_2 [HP_1_4_2P] RATE - Addr: 0x000019A4, Size: 4, Value: (0x00000003) 3 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000019A8, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x000019A9, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000019AA, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000019AA, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x000019AB, Size: 2, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000019AD, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x000019AE, Size: 2, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -3770,7 +3770,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_2 [HP_1_4_2P] RX_MIPI_MODE - Addr: 0x000019C1, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x000019C2, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } RX_MODE - Addr: 0x000019C3, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000019C4, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000019C4, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x000019C5, Size: 1, Value: (0x00000001) 1 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } SR - Addr: 0x000019C6, Size: 1, Value: (0x00000000) 0 { i_buf_ds [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PE - Addr: 0x000019C7, Size: 1, Value: (0x00000000) 0 @@ -3854,7 +3854,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_0 [HP_1_0_0P] RATE - Addr: 0x00001A4C, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001A50, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001A51, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001A52, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001A52, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001A53, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001A55, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001A56, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -3866,7 +3866,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_0 [HP_1_0_0P] RX_MIPI_MODE - Addr: 0x00001A69, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001A6A, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001A6B, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001A6C, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001A6C, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00001A6D, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00001A6E, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00001A6F, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_reset [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -3900,7 +3900,7 @@ Block u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 [] CDR_CLK_ROOT_SEL_B - Addr: 0x00001A88, Size: 5, Value: (0x00000000) 0 CDR_CLK_ROOT_SEL_A - Addr: 0x00001A8D, Size: 5, Value: (0x00000000) 0 CORE_CLK_ROOT_SEL_B - Addr: 0x00001A92, Size: 5, Value: (0x00000000) 0 - CORE_CLK_ROOT_SEL_A - Addr: 0x00001A97, Size: 5, Value: (0x00000000) 0 + CORE_CLK_ROOT_SEL_A - Addr: 0x00001A97, Size: 5, Value: (0x00000012) 18 { clk_buf [CLK_BUF] [CORE_CLK_ROOT_SEL_A:18] [from HP_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_1 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x00001A9C, Size: 5, Value: (0x00000000) 0 @@ -3912,7 +3912,7 @@ Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0 [] ROOT_MUX_SEL - Addr: 0x00001AB0, Size: 6, Value: (0x00000009) 9 { $clkbuf$top.$ibuf_clk0 [CLK_BUF] [ROOT_MUX_SEL:9] [from HR_1_CC_38_19P] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1 [] Attributes: - ROOT_MUX_SEL - Addr: 0x00001AB6, Size: 6, Value: (0x0000003F) 63 + ROOT_MUX_SEL - Addr: 0x00001AB6, Size: 6, Value: (0x00000000) 0 { clk_buf [CLK_BUF] [ROOT_MUX_SEL:0] [from HP_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2 [] Attributes: ROOT_MUX_SEL - Addr: 0x00001ABC, Size: 6, Value: (0x00000020) 32 { pll [PLL] [ROOT_MUX_SEL:32] [from HP_1_CC_18_9P] } @@ -3921,7 +3921,7 @@ Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3 [] ROOT_MUX_SEL - Addr: 0x00001AC2, Size: 6, Value: (0x00000013) 19 { $clkbuf$top.$ibuf_clk2 [CLK_BUF] [ROOT_MUX_SEL:19] [from HR_5_CC_38_19P] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4 [] Attributes: - ROOT_MUX_SEL - Addr: 0x00001AC8, Size: 6, Value: (0x0000000A) 10 { i_serdes [I_SERDES] [ROOT_MUX_SEL:10] [from HR_2_0_0P] } + ROOT_MUX_SEL - Addr: 0x00001AC8, Size: 6, Value: (0x0000000E) 14 { i_serdes [I_SERDES] [ROOT_MUX_SEL:14] [from HR_2_0_0P] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5 [] Attributes: ROOT_MUX_SEL - Addr: 0x00001ACE, Size: 6, Value: (0x00000024) 36 { pll_osc [PLL] [ROOT_MUX_SEL:36] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } @@ -3964,52 +3964,52 @@ Block u_GBOX_HP_40X2.u_bank_osc [] cfg_bank_osc_cal - Addr: 0x00001B19, Size: 6, Value: (0x00000000) 0 Block u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0 [] Attributes: - pll_DSKEWCALBYP - Addr: 0x00001B1F, Size: 1, Value: (0x00000000) 0 { pll [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DSKEWCALIN - Addr: 0x00001B20, Size: 12, Value: (0x00000000) 0 { pll [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DSKEWCALCNT - Addr: 0x00001B2C, Size: 3, Value: (0x00000002) 2 { pll [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DSKEWFASTCAL - Addr: 0x00001B2F, Size: 1, Value: (0x00000000) 0 { pll [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DSKEWCALEN - Addr: 0x00001B30, Size: 1, Value: (0x00000000) 0 { pll [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_FRAC - Addr: 0x00001B31, Size: 24, Value: (0x00000000) 0 { pll [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } + pll_DSKEWCALBYP - Addr: 0x00001B1F, Size: 1, Value: (0x00000000) 0 { pll [PLL] [pll_DSKEWCALBYP:DSKEWCALBYP_0] [from HP_1_CC_18_9P] } + pll_DSKEWCALIN - Addr: 0x00001B20, Size: 12, Value: (0x00000000) 0 { pll [PLL] [pll_DSKEWCALIN:0] [from HP_1_CC_18_9P] } + pll_DSKEWCALCNT - Addr: 0x00001B2C, Size: 3, Value: (0x00000002) 2 { pll [PLL] [pll_DSKEWCALCNT:2] [from HP_1_CC_18_9P] } + pll_DSKEWFASTCAL - Addr: 0x00001B2F, Size: 1, Value: (0x00000000) 0 { pll [PLL] [pll_DSKEWFASTCAL:DSKEWFASTCAL_0] [from HP_1_CC_18_9P] } + pll_DSKEWCALEN - Addr: 0x00001B30, Size: 1, Value: (0x00000000) 0 { pll [PLL] [pll_DSKEWCALEN:DSKEWCALEN_0] [from HP_1_CC_18_9P] } + pll_FRAC - Addr: 0x00001B31, Size: 24, Value: (0x00000000) 0 { pll [PLL] [pll_FRAC:0] [from HP_1_CC_18_9P] } pll_FBDIV - Addr: 0x00001B49, Size: 12, Value: (0x00000010) 16 { pll [PLL] [pll_FBDIV:16] [from HP_1_CC_18_9P] } pll_REFDIV - Addr: 0x00001B55, Size: 6, Value: (0x00000001) 1 { pll [PLL] [pll_REFDIV:1] [from HP_1_CC_18_9P] } pll_PLLEN - Addr: 0x00001B5B, Size: 1, Value: (0x00000000) 0 { pll [PLL] [pll_PLLEN:0] [from HP_1_CC_18_9P] } pll_POSTDIV1 - Addr: 0x00001B5C, Size: 3, Value: (0x00000002) 2 { pll [PLL] [pll_POSTDIV1:2] [from HP_1_CC_18_9P] } pll_POSTDIV2 - Addr: 0x00001B5F, Size: 3, Value: (0x00000002) 2 { pll [PLL] [pll_POSTDIV2:2] [from HP_1_CC_18_9P] } - pll_DSMEN - Addr: 0x00001B62, Size: 1, Value: (0x00000000) 0 { pll [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DACEN - Addr: 0x00001B63, Size: 1, Value: (0x00000000) 0 { pll [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } + pll_DSMEN - Addr: 0x00001B62, Size: 1, Value: (0x00000000) 0 { pll [PLL] [pll_DSMEN:DSMEN_0] [from HP_1_CC_18_9P] } + pll_DACEN - Addr: 0x00001B63, Size: 1, Value: (0x00000000) 0 { pll [PLL] [pll_DACEN:DACEN_0] [from HP_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_pll_refmux_0 [] Attributes: - cfg_pllref_hv_rx_io_sel - Addr: 0x00001B64, Size: 1, Value: (0x00000000) 0 - cfg_pllref_hv_bank_rx_io_sel - Addr: 0x00001B65, Size: 2, Value: (0x00000000) 0 - cfg_pllref_hp_rx_io_sel - Addr: 0x00001B67, Size: 2, Value: (0x00000000) 0 { pll [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } - cfg_pllref_hp_bank_rx_io_sel - Addr: 0x00001B69, Size: 1, Value: (0x00000000) 0 { pll [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } - cfg_pllref_use_hv - Addr: 0x00001B6A, Size: 1, Value: (0x00000000) 0 { pll [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } - cfg_pllref_use_rosc - Addr: 0x00001B6B, Size: 1, Value: (0x00000000) 0 { pll [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } - cfg_pllref_use_div - Addr: 0x00001B6C, Size: 1, Value: (0x00000000) 0 { pll [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } + cfg_pllref_hv_rx_io_sel - Addr: 0x00001B64, Size: 1, Value: (0x00000000) 0 { pll [PLL] [cfg_pllref_hv_rx_io_sel:0] [from HP_1_CC_18_9P] } + cfg_pllref_hv_bank_rx_io_sel - Addr: 0x00001B65, Size: 2, Value: (0x00000000) 0 { pll [PLL] [cfg_pllref_hv_bank_rx_io_sel:0] [from HP_1_CC_18_9P] } + cfg_pllref_hp_rx_io_sel - Addr: 0x00001B67, Size: 2, Value: (0x00000000) 0 { pll [PLL] [cfg_pllref_hp_rx_io_sel:0] [from HP_1_CC_18_9P] } + cfg_pllref_hp_bank_rx_io_sel - Addr: 0x00001B69, Size: 1, Value: (0x00000000) 0 { pll [PLL] [cfg_pllref_hp_bank_rx_io_sel:0] [from HP_1_CC_18_9P] } + cfg_pllref_use_hv - Addr: 0x00001B6A, Size: 1, Value: (0x00000000) 0 { pll [PLL] [cfg_pllref_use_hv:0] [from HP_1_CC_18_9P] } + cfg_pllref_use_rosc - Addr: 0x00001B6B, Size: 1, Value: (0x00000000) 0 { pll [PLL] [cfg_pllref_use_rosc:0] [from HP_1_CC_18_9P] } + cfg_pllref_use_div - Addr: 0x00001B6C, Size: 1, Value: (0x00000000) 0 { pll [PLL] [cfg_pllref_use_div:0] [from HP_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1 [] Attributes: - pll_DSKEWCALBYP - Addr: 0x00001B6D, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [PLL:PLL_SRC==DEFAULT] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } - pll_DSKEWCALIN - Addr: 0x00001B6E, Size: 12, Value: (0x00000000) 0 { pll_osc [PLL] [PLL:PLL_SRC==DEFAULT] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } - pll_DSKEWCALCNT - Addr: 0x00001B7A, Size: 3, Value: (0x00000002) 2 { pll_osc [PLL] [PLL:PLL_SRC==DEFAULT] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } - pll_DSKEWFASTCAL - Addr: 0x00001B7D, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [PLL:PLL_SRC==DEFAULT] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } - pll_DSKEWCALEN - Addr: 0x00001B7E, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [PLL:PLL_SRC==DEFAULT] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } - pll_FRAC - Addr: 0x00001B7F, Size: 24, Value: (0x00000000) 0 { pll_osc [PLL] [PLL:PLL_SRC==DEFAULT] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSKEWCALBYP - Addr: 0x00001B6D, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [pll_DSKEWCALBYP:DSKEWCALBYP_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSKEWCALIN - Addr: 0x00001B6E, Size: 12, Value: (0x00000000) 0 { pll_osc [PLL] [pll_DSKEWCALIN:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSKEWCALCNT - Addr: 0x00001B7A, Size: 3, Value: (0x00000002) 2 { pll_osc [PLL] [pll_DSKEWCALCNT:2] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSKEWFASTCAL - Addr: 0x00001B7D, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [pll_DSKEWFASTCAL:DSKEWFASTCAL_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSKEWCALEN - Addr: 0x00001B7E, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [pll_DSKEWCALEN:DSKEWCALEN_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_FRAC - Addr: 0x00001B7F, Size: 24, Value: (0x00000000) 0 { pll_osc [PLL] [pll_FRAC:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } pll_FBDIV - Addr: 0x00001B97, Size: 12, Value: (0x00000010) 16 { pll_osc [PLL] [pll_FBDIV:16] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } pll_REFDIV - Addr: 0x00001BA3, Size: 6, Value: (0x00000001) 1 { pll_osc [PLL] [pll_REFDIV:1] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } pll_PLLEN - Addr: 0x00001BA9, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [pll_PLLEN:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } pll_POSTDIV1 - Addr: 0x00001BAA, Size: 3, Value: (0x00000002) 2 { pll_osc [PLL] [pll_POSTDIV1:2] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } pll_POSTDIV2 - Addr: 0x00001BAD, Size: 3, Value: (0x00000002) 2 { pll_osc [PLL] [pll_POSTDIV2:2] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } - pll_DSMEN - Addr: 0x00001BB0, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [PLL:PLL_SRC==DEFAULT] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } - pll_DACEN - Addr: 0x00001BB1, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [PLL:PLL_SRC==DEFAULT] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSMEN - Addr: 0x00001BB0, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [pll_DSMEN:DSMEN_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DACEN - Addr: 0x00001BB1, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [pll_DACEN:DACEN_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } Block u_GBOX_HP_40X2.u_gbox_pll_refmux_1 [] Attributes: - cfg_pllref_hv_rx_io_sel - Addr: 0x00001BB2, Size: 1, Value: (0x00000000) 0 - cfg_pllref_hv_bank_rx_io_sel - Addr: 0x00001BB3, Size: 2, Value: (0x00000000) 0 - cfg_pllref_hp_rx_io_sel - Addr: 0x00001BB5, Size: 2, Value: (0x00000000) 0 - cfg_pllref_hp_bank_rx_io_sel - Addr: 0x00001BB7, Size: 1, Value: (0x00000000) 0 - cfg_pllref_use_hv - Addr: 0x00001BB8, Size: 1, Value: (0x00000000) 0 - cfg_pllref_use_rosc - Addr: 0x00001BB9, Size: 1, Value: (0x00000001) 1 { pll_osc [PLL] [PLL:PLLREF_SRC==BOOT_CLOCK --#PIN=UNKNOWN --#BANK=UNKNOWN --#DIV=1] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } - cfg_pllref_use_div - Addr: 0x00001BBA, Size: 1, Value: (0x00000001) 1 { pll_osc [PLL] [PLL:PLLREF_SRC==BOOT_CLOCK --#PIN=UNKNOWN --#BANK=UNKNOWN --#DIV=1] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_hv_rx_io_sel - Addr: 0x00001BB2, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [cfg_pllref_hv_rx_io_sel:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_hv_bank_rx_io_sel - Addr: 0x00001BB3, Size: 2, Value: (0x00000000) 0 { pll_osc [PLL] [cfg_pllref_hv_bank_rx_io_sel:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_hp_rx_io_sel - Addr: 0x00001BB5, Size: 2, Value: (0x00000000) 0 { pll_osc [PLL] [cfg_pllref_hp_rx_io_sel:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_hp_bank_rx_io_sel - Addr: 0x00001BB7, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [cfg_pllref_hp_bank_rx_io_sel:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_use_hv - Addr: 0x00001BB8, Size: 1, Value: (0x00000000) 0 { pll_osc [PLL] [cfg_pllref_use_hv:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_use_rosc - Addr: 0x00001BB9, Size: 1, Value: (0x00000001) 1 { pll_osc [PLL] [cfg_pllref_use_rosc:1] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_use_div - Addr: 0x00001BBA, Size: 1, Value: (0x00000001) 1 { pll_osc [PLL] [cfg_pllref_use_div:1] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_19 [HR_1_CC_39_19N] Attributes: RATE - Addr: 0x00001BBB, Size: 4, Value: (0x00000000) 0 @@ -4039,7 +4039,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_19 [HR_1_CC_38_19P] RATE - Addr: 0x00001BE5, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } MASTER_SLAVE - Addr: 0x00001BE9, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } PEER_IS_ON - Addr: 0x00001BEA, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } - TX_CLOCK_IO - Addr: 0x00001BEB, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } + TX_CLOCK_IO - Addr: 0x00001BEB, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001BEC, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } TX_BYPASS - Addr: 0x00001BEE, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP], $clkbuf$top.$ibuf_clk0 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001BEF, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } @@ -4051,7 +4051,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_19 [HR_1_CC_38_19P] RX_MIPI_MODE - Addr: 0x00001C02, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } TX_MODE - Addr: 0x00001C03, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001C04, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } - RX_CLOCK_IO - Addr: 0x00001C05, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP], $clkbuf$top.$ibuf_clk0 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001C05, Size: 1, Value: (0x00000001) 1 { $clkbuf$top.$ibuf_clk0 [CLK_BUF] [RX_CLOCK_IO:1] } DFEN - Addr: 0x00001C06, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } SR - Addr: 0x00001C07, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HP] } PE - Addr: 0x00001C08, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk0 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -4807,7 +4807,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_3 [HR_1_6_3P] RATE - Addr: 0x00002125, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } MASTER_SLAVE - Addr: 0x00002129, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } PEER_IS_ON - Addr: 0x0000212A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } - TX_CLOCK_IO - Addr: 0x0000212B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + TX_CLOCK_IO - Addr: 0x0000212B, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x0000212C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } TX_BYPASS - Addr: 0x0000212E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } TX_CLK_PHASE - Addr: 0x0000212F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } @@ -4855,7 +4855,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_2 [HR_1_4_2P] RATE - Addr: 0x00002179, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } MASTER_SLAVE - Addr: 0x0000217D, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } PEER_IS_ON - Addr: 0x0000217E, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } - TX_CLOCK_IO - Addr: 0x0000217F, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } + TX_CLOCK_IO - Addr: 0x0000217F, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00002180, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } TX_BYPASS - Addr: 0x00002182, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } TX_CLK_PHASE - Addr: 0x00002183, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } @@ -4867,7 +4867,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_2 [HR_1_4_2P] RX_MIPI_MODE - Addr: 0x00002196, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } TX_MODE - Addr: 0x00002197, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00002198, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } - RX_CLOCK_IO - Addr: 0x00002199, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } + RX_CLOCK_IO - Addr: 0x00002199, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x0000219A, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } SR - Addr: 0x0000219B, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:IOSTANDARD==LVCMOS_18_HR] } PE - Addr: 0x0000219C, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -5191,7 +5191,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_15 [HR_2_30_15P] RATE - Addr: 0x000023C5, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000023C9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x000023CA, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000023CB, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000023CB, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x000023CC, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000023CE, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x000023CF, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -5239,7 +5239,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_14 [HR_2_28_14P] RATE - Addr: 0x00002419, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000241D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000241E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000241F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000241F, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00002420, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002422, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00002423, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -5287,7 +5287,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_13 [HR_2_26_13P] RATE - Addr: 0x0000246D, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002471, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00002472, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00002473, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00002473, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00002474, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002476, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00002477, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -5335,7 +5335,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_12 [HR_2_24_12P] RATE - Addr: 0x000024C1, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000024C5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x000024C6, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000024C7, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000024C7, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x000024C8, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000024CA, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x000024CB, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -5383,7 +5383,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_11 [HR_2_22_11P] RATE - Addr: 0x00002515, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002519, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x0000251C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x0000251E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x0000251F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -5431,7 +5431,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_10 [HR_2_20_10P] RATE - Addr: 0x00002569, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000256D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000256E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000256F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000256F, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00002570, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002572, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00002573, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -5743,7 +5743,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_3 [HR_2_7_3N] RATE - Addr: 0x0000278B, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout_serdes_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000278F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00002790, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00002791, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00002791, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00002792, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002794, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00002795, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -5767,7 +5767,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_3 [HR_2_6_3P] RATE - Addr: 0x000027B5, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000027B9, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x000027BA, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000027BB, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000027BB, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x000027BC, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000027BE, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x000027BF, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -5779,7 +5779,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_3 [HR_2_6_3P] RX_MIPI_MODE - Addr: 0x000027D2, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x000027D3, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x000027D4, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000027D5, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000027D5, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x000027D6, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x000027D7, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x000027D8, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes_clk_out [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -5815,7 +5815,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_2 [HR_2_4_2P] RATE - Addr: 0x00002809, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000280D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000280E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000280F, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [TX_CLOCK_IO:TX_clock_IO] } + TX_CLOCK_IO - Addr: 0x0000280F, Size: 1, Value: (0x00000001) 1 { pll [PLL] [TX_CLOCK_IO:1] [from HP_1_CC_18_9P] } TX_DDR_MODE - Addr: 0x00002810, Size: 2, Value: (0x00000002) 2 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [O_SERDES_CLK:DDR_MODE==SDR] } TX_BYPASS - Addr: 0x00002812, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00002813, Size: 2, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [TX_CLK_PHASE:TX_phase_270] } @@ -5863,7 +5863,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_1 [HR_2_2_1P] RATE - Addr: 0x0000285D, Size: 4, Value: (0x00000008) 8 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [RATE:8] } MASTER_SLAVE - Addr: 0x00002861, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00002862, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [PEER_IS_ON:PEER_off] } - TX_CLOCK_IO - Addr: 0x00002863, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00002863, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00002864, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [O_SERDES:DDR_MODE==DDR] } TX_BYPASS - Addr: 0x00002866, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [TX_BYPASS:TX_gear_on] } TX_CLK_PHASE - Addr: 0x00002867, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -5911,7 +5911,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_0 [HR_2_0_0P] RATE - Addr: 0x000028B1, Size: 4, Value: (0x00000008) 8 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], i_serdes [I_SERDES] [RATE:8] } MASTER_SLAVE - Addr: 0x000028B5, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x000028B6, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], i_serdes [I_SERDES] [PEER_IS_ON:PEER_off] } - TX_CLOCK_IO - Addr: 0x000028B7, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000028B7, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x000028B8, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000028BA, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x000028BB, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -5923,7 +5923,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_0 [HR_2_0_0P] RX_MIPI_MODE - Addr: 0x000028CE, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x000028CF, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x000028D0, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000028D1, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000028D1, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x000028D2, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x000028D3, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din_serdes [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x000028D4, Size: 1, Value: (0x00000000) 0 @@ -5952,11 +5952,11 @@ Block u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x000028E9, Size: 5, Value: (0x00000000) 0 CDR_CLK_ROOT_SEL_A - Addr: 0x000028EE, Size: 5, Value: (0x00000000) 0 - CORE_CLK_ROOT_SEL_B - Addr: 0x000028F3, Size: 5, Value: (0x00000012) 18 { $clkbuf$top.$ibuf_clk0 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==B --#MUX=18] [from HR_1_CC_38_19P] } + CORE_CLK_ROOT_SEL_B - Addr: 0x000028F3, Size: 5, Value: (0x00000012) 18 { $clkbuf$top.$ibuf_clk0 [CLK_BUF] [CORE_CLK_ROOT_SEL_B:18] [from HR_1_CC_38_19P] } CORE_CLK_ROOT_SEL_A - Addr: 0x000028F8, Size: 5, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x000028FD, Size: 5, Value: (0x00000000) 0 - CDR_CLK_ROOT_SEL_A - Addr: 0x00002902, Size: 5, Value: (0x00000000) 0 { i_serdes [I_SERDES] [I_SERDES:ROOT_BANK_SRC==A&DPA_MODE==DPA --#MUX=0] [from HR_2_0_0P] } + CDR_CLK_ROOT_SEL_A - Addr: 0x00002902, Size: 5, Value: (0x00000000) 0 { i_serdes [I_SERDES] [CDR_CLK_ROOT_SEL_A:0] [from HR_2_0_0P] } CORE_CLK_ROOT_SEL_B - Addr: 0x00002907, Size: 5, Value: (0x00000000) 0 CORE_CLK_ROOT_SEL_A - Addr: 0x0000290C, Size: 5, Value: (0x00000000) 0 diff --git a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit index 66adb6034..b3581df3e 100644 --- a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit +++ b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit @@ -32,7 +32,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK0_A_19 [HR_3_CC_38_19P] RATE - Addr: 0x0000002A, Size: 4, Value: (0x00000003) 3 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000002E, Size: 1, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000002F, Size: 1, Value: (0x00000001) 1 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00000030, Size: 1, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00000030, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00000031, Size: 2, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000033, Size: 1, Value: (0x00000001) 1 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf31 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x00000034, Size: 2, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -44,7 +44,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK0_A_19 [HR_3_CC_38_19P] RX_MIPI_MODE - Addr: 0x00000047, Size: 1, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00000048, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00000049, Size: 1, Value: (0x00000001) 1 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x0000004A, Size: 1, Value: (0x00000001) 1 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf31 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_CLOCK_IO - Addr: 0x0000004A, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x0000004B, Size: 1, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x0000004C, Size: 1, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x0000004D, Size: 1, Value: (0x00000000) 0 { i_buf31 [I_BUF] [I_BUF:WEAK_KEEPER==DEFAULT] } @@ -1376,7 +1376,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_11 [HR_5_22_11P] RATE - Addr: 0x0000095A, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000095E, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000095F, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00000960, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00000960, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00000961, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000963, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00000964, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -1388,7 +1388,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_11 [HR_5_22_11P] RX_MIPI_MODE - Addr: 0x00000977, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00000978, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00000979, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x0000097A, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x0000097A, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x0000097B, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x0000097C, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x0000097D, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc3 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -1424,7 +1424,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_10 [HR_5_20_10P] RATE - Addr: 0x000009AE, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000009B2, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x000009B3, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000009B4, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000009B4, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x000009B5, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000009B7, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x000009B8, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -1436,7 +1436,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_10 [HR_5_20_10P] RX_MIPI_MODE - Addr: 0x000009CB, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x000009CC, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x000009CD, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000009CE, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000009CE, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x000009CF, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x000009D0, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x000009D1, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc1 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -1808,7 +1808,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_2 [HR_5_4_2P] RATE - Addr: 0x00000C4E, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00000C52, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00000C53, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00000C54, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00000C54, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00000C55, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_ddr11 [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x00000C57, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00000C58, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -1856,7 +1856,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_1 [HR_5_2_1P] RATE - Addr: 0x00000CA2, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00000CA6, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00000CA7, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00000CA8, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00000CA8, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00000CA9, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00000CAB, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00000CAC, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -1868,7 +1868,7 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_1 [HR_5_2_1P] RX_MIPI_MODE - Addr: 0x00000CBF, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00000CC0, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00000CC1, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00000CC2, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00000CC2, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00000CC3, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00000CC4, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00000CC5, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din11 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -1930,15 +1930,15 @@ Block u_GBOX_HV_40X2_VR.u_HV_PGEN_dummy [] Block u_GBOX_HV_40X2_VR.u_gbox_fclk_mux_all [] Attributes: cfg_rxclk_phase_sel_B_0 - Addr: 0x00000D22, Size: 1, Value: (0x00000000) 0 - cfg_rxclk_phase_sel_B_1 - Addr: 0x00000D23, Size: 1, Value: (0x00000000) 0 + cfg_rxclk_phase_sel_B_1 - Addr: 0x00000D23, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [cfg_rxclk_phase_sel_B_1:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } cfg_rxclk_phase_sel_A_0 - Addr: 0x00000D24, Size: 1, Value: (0x00000000) 0 cfg_rxclk_phase_sel_A_1 - Addr: 0x00000D25, Size: 1, Value: (0x00000000) 0 cfg_rx_fclkio_sel_B_0 - Addr: 0x00000D26, Size: 1, Value: (0x00000000) 0 - cfg_rx_fclkio_sel_B_1 - Addr: 0x00000D27, Size: 1, Value: (0x00000000) 0 + cfg_rx_fclkio_sel_B_1 - Addr: 0x00000D27, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [cfg_rx_fclkio_sel_B_1:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } cfg_rx_fclkio_sel_A_0 - Addr: 0x00000D28, Size: 1, Value: (0x00000000) 0 cfg_rx_fclkio_sel_A_1 - Addr: 0x00000D29, Size: 1, Value: (0x00000000) 0 cfg_vco_clk_sel_B_0 - Addr: 0x00000D2A, Size: 1, Value: (0x00000000) 0 - cfg_vco_clk_sel_B_1 - Addr: 0x00000D2B, Size: 1, Value: (0x00000000) 0 + cfg_vco_clk_sel_B_1 - Addr: 0x00000D2B, Size: 1, Value: (0x00000001) 1 { pllosc0 [PLL] [cfg_vco_clk_sel_B_1:1] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } cfg_vco_clk_sel_A_0 - Addr: 0x00000D2C, Size: 1, Value: (0x00000000) 0 cfg_vco_clk_sel_A_1 - Addr: 0x00000D2D, Size: 1, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_0 [] @@ -2942,7 +2942,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_19 [HP_1_CC_38_19P] RATE - Addr: 0x00001410, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001414, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001415, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001416, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001416, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001417, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001419, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $clkbuf$top.$ibuf_clk20 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x0000141A, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -2954,7 +2954,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_19 [HP_1_CC_38_19P] RX_MIPI_MODE - Addr: 0x0000142D, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x0000142E, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x0000142F, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001430, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $clkbuf$top.$ibuf_clk20 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001430, Size: 1, Value: (0x00000001) 1 { $clkbuf$top.$ibuf_clk20 [CLK_BUF] [RX_CLOCK_IO:1] } DFEN - Addr: 0x00001431, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00001432, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00001433, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -3326,7 +3326,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_11 [HP_1_22_11P] RATE - Addr: 0x000016B0, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000016B4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x000016B5, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000016B6, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000016B6, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x000016B7, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_ddr00 [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x000016B9, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x000016BA, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -3374,7 +3374,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_10 [HP_1_20_10P] RATE - Addr: 0x00001704, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001708, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001709, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000170A, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000170A, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x0000170B, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x0000170D, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x0000170E, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -3386,7 +3386,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_10 [HP_1_20_10P] RX_MIPI_MODE - Addr: 0x00001721, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001722, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001723, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001724, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001724, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00001725, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00001726, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00001727, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din00 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -3422,7 +3422,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_9 [HP_1_CC_18_9P] RATE - Addr: 0x00001758, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000175C, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000175D, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000175E, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000175E, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x0000175F, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001761, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf00 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001762, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -3434,7 +3434,7 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_9 [HP_1_CC_18_9P] RX_MIPI_MODE - Addr: 0x00001775, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001776, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001777, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001778, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf00 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001778, Size: 1, Value: (0x00000001) 1 { clk_buf00 [CLK_BUF] [RX_CLOCK_IO:1] } DFEN - Addr: 0x00001779, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x0000177A, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x0000177B, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk00 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -3899,8 +3899,8 @@ Block u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x00001A88, Size: 5, Value: (0x00000000) 0 CDR_CLK_ROOT_SEL_A - Addr: 0x00001A8D, Size: 5, Value: (0x00000000) 0 - CORE_CLK_ROOT_SEL_B - Addr: 0x00001A92, Size: 5, Value: (0x00000012) 18 { $clkbuf$top.$ibuf_clk20 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==B --#MUX=18] [from HP_1_CC_38_19P] } - CORE_CLK_ROOT_SEL_A - Addr: 0x00001A97, Size: 5, Value: (0x00000012) 18 { clk_buf00 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==A --#MUX=18] [from HP_1_CC_18_9P] } + CORE_CLK_ROOT_SEL_B - Addr: 0x00001A92, Size: 5, Value: (0x00000012) 18 { $clkbuf$top.$ibuf_clk20 [CLK_BUF] [CORE_CLK_ROOT_SEL_B:18] [from HP_1_CC_38_19P] } + CORE_CLK_ROOT_SEL_A - Addr: 0x00001A97, Size: 5, Value: (0x00000012) 18 { clk_buf00 [CLK_BUF] [CORE_CLK_ROOT_SEL_A:18] [from HP_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_1 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x00001A9C, Size: 5, Value: (0x00000000) 0 @@ -3924,7 +3924,7 @@ Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4 [] ROOT_MUX_SEL - Addr: 0x00001AC8, Size: 6, Value: (0x00000023) 35 { pll00 [PLL] [ROOT_MUX_SEL:35] [from HP_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5 [] Attributes: - ROOT_MUX_SEL - Addr: 0x00001ACE, Size: 6, Value: (0x0000003F) 63 + ROOT_MUX_SEL - Addr: 0x00001ACE, Size: 6, Value: (0x00000008) 8 { clk_buf10 [CLK_BUF] [ROOT_MUX_SEL:8] [from HR_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6 [] Attributes: ROOT_MUX_SEL - Addr: 0x00001AD4, Size: 6, Value: (0x00000001) 1 { $clkbuf$top.$ibuf_clk20 [CLK_BUF] [ROOT_MUX_SEL:1] [from HP_1_CC_38_19P] } @@ -3964,52 +3964,52 @@ Block u_GBOX_HP_40X2.u_bank_osc [] cfg_bank_osc_cal - Addr: 0x00001B19, Size: 6, Value: (0x00000000) 0 Block u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0 [] Attributes: - pll_DSKEWCALBYP - Addr: 0x00001B1F, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DSKEWCALIN - Addr: 0x00001B20, Size: 12, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DSKEWCALCNT - Addr: 0x00001B2C, Size: 3, Value: (0x00000002) 2 { pll00 [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DSKEWFASTCAL - Addr: 0x00001B2F, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DSKEWCALEN - Addr: 0x00001B30, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_FRAC - Addr: 0x00001B31, Size: 24, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } + pll_DSKEWCALBYP - Addr: 0x00001B1F, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [pll_DSKEWCALBYP:DSKEWCALBYP_0] [from HP_1_CC_18_9P] } + pll_DSKEWCALIN - Addr: 0x00001B20, Size: 12, Value: (0x00000000) 0 { pll00 [PLL] [pll_DSKEWCALIN:0] [from HP_1_CC_18_9P] } + pll_DSKEWCALCNT - Addr: 0x00001B2C, Size: 3, Value: (0x00000002) 2 { pll00 [PLL] [pll_DSKEWCALCNT:2] [from HP_1_CC_18_9P] } + pll_DSKEWFASTCAL - Addr: 0x00001B2F, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [pll_DSKEWFASTCAL:DSKEWFASTCAL_0] [from HP_1_CC_18_9P] } + pll_DSKEWCALEN - Addr: 0x00001B30, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [pll_DSKEWCALEN:DSKEWCALEN_0] [from HP_1_CC_18_9P] } + pll_FRAC - Addr: 0x00001B31, Size: 24, Value: (0x00000000) 0 { pll00 [PLL] [pll_FRAC:0] [from HP_1_CC_18_9P] } pll_FBDIV - Addr: 0x00001B49, Size: 12, Value: (0x00000010) 16 { pll00 [PLL] [pll_FBDIV:16] [from HP_1_CC_18_9P] } pll_REFDIV - Addr: 0x00001B55, Size: 6, Value: (0x00000001) 1 { pll00 [PLL] [pll_REFDIV:1] [from HP_1_CC_18_9P] } pll_PLLEN - Addr: 0x00001B5B, Size: 1, Value: (0x00000001) 1 { pll00 [PLL] [pll_PLLEN:1] [from HP_1_CC_18_9P] } pll_POSTDIV1 - Addr: 0x00001B5C, Size: 3, Value: (0x00000002) 2 { pll00 [PLL] [pll_POSTDIV1:2] [from HP_1_CC_18_9P] } pll_POSTDIV2 - Addr: 0x00001B5F, Size: 3, Value: (0x00000002) 2 { pll00 [PLL] [pll_POSTDIV2:2] [from HP_1_CC_18_9P] } - pll_DSMEN - Addr: 0x00001B62, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } - pll_DACEN - Addr: 0x00001B63, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLL_SRC==DEFAULT] [from HP_1_CC_18_9P] } + pll_DSMEN - Addr: 0x00001B62, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [pll_DSMEN:DSMEN_0] [from HP_1_CC_18_9P] } + pll_DACEN - Addr: 0x00001B63, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [pll_DACEN:DACEN_0] [from HP_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_pll_refmux_0 [] Attributes: - cfg_pllref_hv_rx_io_sel - Addr: 0x00001B64, Size: 1, Value: (0x00000000) 0 - cfg_pllref_hv_bank_rx_io_sel - Addr: 0x00001B65, Size: 2, Value: (0x00000000) 0 - cfg_pllref_hp_rx_io_sel - Addr: 0x00001B67, Size: 2, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } - cfg_pllref_hp_bank_rx_io_sel - Addr: 0x00001B69, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } - cfg_pllref_use_hv - Addr: 0x00001B6A, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } - cfg_pllref_use_rosc - Addr: 0x00001B6B, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } - cfg_pllref_use_div - Addr: 0x00001B6C, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [PLL:PLLREF_SRC==HP --#PIN=0 --#BANK=0 --#DIV=0] [from HP_1_CC_18_9P] } + cfg_pllref_hv_rx_io_sel - Addr: 0x00001B64, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [cfg_pllref_hv_rx_io_sel:0] [from HP_1_CC_18_9P] } + cfg_pllref_hv_bank_rx_io_sel - Addr: 0x00001B65, Size: 2, Value: (0x00000000) 0 { pll00 [PLL] [cfg_pllref_hv_bank_rx_io_sel:0] [from HP_1_CC_18_9P] } + cfg_pllref_hp_rx_io_sel - Addr: 0x00001B67, Size: 2, Value: (0x00000000) 0 { pll00 [PLL] [cfg_pllref_hp_rx_io_sel:0] [from HP_1_CC_18_9P] } + cfg_pllref_hp_bank_rx_io_sel - Addr: 0x00001B69, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [cfg_pllref_hp_bank_rx_io_sel:0] [from HP_1_CC_18_9P] } + cfg_pllref_use_hv - Addr: 0x00001B6A, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [cfg_pllref_use_hv:0] [from HP_1_CC_18_9P] } + cfg_pllref_use_rosc - Addr: 0x00001B6B, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [cfg_pllref_use_rosc:0] [from HP_1_CC_18_9P] } + cfg_pllref_use_div - Addr: 0x00001B6C, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [cfg_pllref_use_div:0] [from HP_1_CC_18_9P] } Block u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1 [] Attributes: - pll_DSKEWCALBYP - Addr: 0x00001B6D, Size: 1, Value: (0x00000000) 0 - pll_DSKEWCALIN - Addr: 0x00001B6E, Size: 12, Value: (0x00000000) 0 - pll_DSKEWCALCNT - Addr: 0x00001B7A, Size: 3, Value: (0x00000000) 0 - pll_DSKEWFASTCAL - Addr: 0x00001B7D, Size: 1, Value: (0x00000000) 0 - pll_DSKEWCALEN - Addr: 0x00001B7E, Size: 1, Value: (0x00000000) 0 - pll_FRAC - Addr: 0x00001B7F, Size: 24, Value: (0x00000000) 0 - pll_FBDIV - Addr: 0x00001B97, Size: 12, Value: (0x00000000) 0 - pll_REFDIV - Addr: 0x00001BA3, Size: 6, Value: (0x00000000) 0 - pll_PLLEN - Addr: 0x00001BA9, Size: 1, Value: (0x00000000) 0 - pll_POSTDIV1 - Addr: 0x00001BAA, Size: 3, Value: (0x00000000) 0 - pll_POSTDIV2 - Addr: 0x00001BAD, Size: 3, Value: (0x00000000) 0 - pll_DSMEN - Addr: 0x00001BB0, Size: 1, Value: (0x00000000) 0 - pll_DACEN - Addr: 0x00001BB1, Size: 1, Value: (0x00000000) 0 + pll_DSKEWCALBYP - Addr: 0x00001B6D, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [pll_DSKEWCALBYP:DSKEWCALBYP_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSKEWCALIN - Addr: 0x00001B6E, Size: 12, Value: (0x00000000) 0 { pllosc0 [PLL] [pll_DSKEWCALIN:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSKEWCALCNT - Addr: 0x00001B7A, Size: 3, Value: (0x00000002) 2 { pllosc0 [PLL] [pll_DSKEWCALCNT:2] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSKEWFASTCAL - Addr: 0x00001B7D, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [pll_DSKEWFASTCAL:DSKEWFASTCAL_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSKEWCALEN - Addr: 0x00001B7E, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [pll_DSKEWCALEN:DSKEWCALEN_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_FRAC - Addr: 0x00001B7F, Size: 24, Value: (0x00000000) 0 { pllosc0 [PLL] [pll_FRAC:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_FBDIV - Addr: 0x00001B97, Size: 12, Value: (0x00000010) 16 { pllosc0 [PLL] [pll_FBDIV:16] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_REFDIV - Addr: 0x00001BA3, Size: 6, Value: (0x00000001) 1 { pllosc0 [PLL] [pll_REFDIV:1] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_PLLEN - Addr: 0x00001BA9, Size: 1, Value: (0x00000001) 1 { pllosc0 [PLL] [pll_PLLEN:1] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_POSTDIV1 - Addr: 0x00001BAA, Size: 3, Value: (0x00000002) 2 { pllosc0 [PLL] [pll_POSTDIV1:2] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_POSTDIV2 - Addr: 0x00001BAD, Size: 3, Value: (0x00000002) 2 { pllosc0 [PLL] [pll_POSTDIV2:2] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DSMEN - Addr: 0x00001BB0, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [pll_DSMEN:DSMEN_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + pll_DACEN - Addr: 0x00001BB1, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [pll_DACEN:DACEN_0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } Block u_GBOX_HP_40X2.u_gbox_pll_refmux_1 [] Attributes: - cfg_pllref_hv_rx_io_sel - Addr: 0x00001BB2, Size: 1, Value: (0x00000000) 0 - cfg_pllref_hv_bank_rx_io_sel - Addr: 0x00001BB3, Size: 2, Value: (0x00000000) 0 - cfg_pllref_hp_rx_io_sel - Addr: 0x00001BB5, Size: 2, Value: (0x00000000) 0 - cfg_pllref_hp_bank_rx_io_sel - Addr: 0x00001BB7, Size: 1, Value: (0x00000000) 0 - cfg_pllref_use_hv - Addr: 0x00001BB8, Size: 1, Value: (0x00000000) 0 - cfg_pllref_use_rosc - Addr: 0x00001BB9, Size: 1, Value: (0x00000000) 0 - cfg_pllref_use_div - Addr: 0x00001BBA, Size: 1, Value: (0x00000000) 0 + cfg_pllref_hv_rx_io_sel - Addr: 0x00001BB2, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [cfg_pllref_hv_rx_io_sel:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_hv_bank_rx_io_sel - Addr: 0x00001BB3, Size: 2, Value: (0x00000000) 0 { pllosc0 [PLL] [cfg_pllref_hv_bank_rx_io_sel:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_hp_rx_io_sel - Addr: 0x00001BB5, Size: 2, Value: (0x00000000) 0 { pllosc0 [PLL] [cfg_pllref_hp_rx_io_sel:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_hp_bank_rx_io_sel - Addr: 0x00001BB7, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [cfg_pllref_hp_bank_rx_io_sel:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_use_hv - Addr: 0x00001BB8, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [cfg_pllref_use_hv:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_use_rosc - Addr: 0x00001BB9, Size: 1, Value: (0x00000001) 1 { pllosc0 [PLL] [cfg_pllref_use_rosc:1] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } + cfg_pllref_use_div - Addr: 0x00001BBA, Size: 1, Value: (0x00000000) 0 { pllosc0 [PLL] [cfg_pllref_use_div:0] [from __SKIP_LOCATION_CHECK__:BOOT_CLOCK#0] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_19 [HR_1_CC_39_19N] Attributes: RATE - Addr: 0x00001BBB, Size: 4, Value: (0x00000000) 0 @@ -4039,7 +4039,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_19 [HR_1_CC_38_19P] RATE - Addr: 0x00001BE5, Size: 4, Value: (0x00000003) 3 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001BE9, Size: 1, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001BEA, Size: 1, Value: (0x00000001) 1 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001BEB, Size: 1, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001BEB, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001BEC, Size: 2, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001BEE, Size: 1, Value: (0x00000001) 1 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf30 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001BEF, Size: 2, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -4051,7 +4051,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_19 [HR_1_CC_38_19P] RX_MIPI_MODE - Addr: 0x00001C02, Size: 1, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001C03, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001C04, Size: 1, Value: (0x00000001) 1 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001C05, Size: 1, Value: (0x00000001) 1 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf30 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001C05, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00001C06, Size: 1, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00001C07, Size: 1, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00001C08, Size: 1, Value: (0x00000000) 0 { i_buf30 [I_BUF] [I_BUF:WEAK_KEEPER==DEFAULT] } @@ -4231,7 +4231,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_15 [HR_1_30_15P] RATE - Addr: 0x00001D35, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001D39, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001D3A, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001D3B, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001D3B, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001D3C, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001D3E, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001D3F, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -4243,7 +4243,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_15 [HR_1_30_15P] RX_MIPI_MODE - Addr: 0x00001D52, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001D53, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001D54, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001D55, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001D55, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00001D56, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00001D57, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00001D58, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc4 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -4327,7 +4327,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_13 [HR_1_26_13P] RATE - Addr: 0x00001DDD, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001DE1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001DE2, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001DE3, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001DE3, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001DE4, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_ddr12 [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x00001DE6, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001DE7, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -4375,7 +4375,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_12 [HR_1_24_12P] RATE - Addr: 0x00001E31, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001E35, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001E36, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001E37, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001E37, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001E38, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001E3A, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001E3B, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -4387,7 +4387,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_12 [HR_1_24_12P] RX_MIPI_MODE - Addr: 0x00001E4E, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001E4F, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001E50, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001E51, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001E51, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00001E52, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00001E53, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00001E54, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din12 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -4423,7 +4423,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_11 [HR_1_22_11P] RATE - Addr: 0x00001E85, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001E89, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001E8A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001E8B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001E8B, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001E8C, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_ddr01 [O_DDR] [O_DDR:MODE==DDR] } TX_BYPASS - Addr: 0x00001E8E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001E8F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -4471,7 +4471,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_10 [HR_1_20_10P] RATE - Addr: 0x00001ED9, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001EDD, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001EDE, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001EDF, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001EDF, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001EE0, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00001EE2, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001EE3, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -4483,7 +4483,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_10 [HR_1_20_10P] RX_MIPI_MODE - Addr: 0x00001EF6, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001EF7, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001EF8, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001EF9, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001EF9, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00001EFA, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00001EFB, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00001EFC, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_din01 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -4519,19 +4519,19 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_9 [HR_1_CC_18_9P] RATE - Addr: 0x00001F2D, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00001F31, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00001F32, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001F33, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001F33, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00001F34, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x00001F36, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x00001F36, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf10 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x00001F37, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00001F39, Size: 6, Value: (0x00000000) 0 RX_DDR_MODE - Addr: 0x00001F3F, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00001F41, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00001F41, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf10 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } RX_DLY - Addr: 0x00001F42, Size: 6, Value: (0x00000000) 0 RX_DPA_MODE - Addr: 0x00001F48, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } RX_MIPI_MODE - Addr: 0x00001F4A, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00001F4B, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00001F4C, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001F4D, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001F4D, Size: 1, Value: (0x00000001) 1 { clk_buf10 [CLK_BUF] [RX_CLOCK_IO:1] } DFEN - Addr: 0x00001F4E, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00001F4F, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00001F50, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk10 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -4999,19 +4999,19 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_19 [HR_2_CC_38_19P] RATE - Addr: 0x00002275, Size: 4, Value: (0x00000003) 3 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002279, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000227A, Size: 1, Value: (0x00000001) 1 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000227B, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000227B, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x0000227C, Size: 2, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x0000227E, Size: 1, Value: (0x00000001) 1 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x0000227E, Size: 1, Value: (0x00000001) 1 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf40 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } TX_CLK_PHASE - Addr: 0x0000227F, Size: 2, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00002281, Size: 6, Value: (0x00000000) 0 RX_DDR_MODE - Addr: 0x00002287, Size: 2, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00002289, Size: 1, Value: (0x00000001) 1 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00002289, Size: 1, Value: (0x00000001) 1 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], clk_buf40 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] } RX_DLY - Addr: 0x0000228A, Size: 6, Value: (0x00000000) 0 RX_DPA_MODE - Addr: 0x00002290, Size: 2, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } RX_MIPI_MODE - Addr: 0x00002292, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00002293, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00002294, Size: 1, Value: (0x00000001) 1 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00002295, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00002295, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00002296, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x00002297, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x00002298, Size: 1, Value: (0x00000000) 0 { i_buf40 [I_BUF] [I_BUF:WEAK_KEEPER==DEFAULT] } @@ -5383,7 +5383,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_11 [HR_2_22_11P] RATE - Addr: 0x00002515, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002519, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x0000251C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x0000251E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x0000251F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } @@ -5431,7 +5431,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_10 [HR_2_20_10P] RATE - Addr: 0x00002569, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000256D, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000256E, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000256F, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000256F, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00002570, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002572, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00002573, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -5443,7 +5443,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_10 [HR_2_20_10P] RX_MIPI_MODE - Addr: 0x00002586, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00002587, Size: 1, Value: (0x00000000) 0 RX_MODE - Addr: 0x00002588, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00002589, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00002589, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x0000258A, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } SR - Addr: 0x0000258B, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } PE - Addr: 0x0000258C, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_dinosc0 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] } @@ -5719,7 +5719,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_4 [HR_2_8_4P] RATE - Addr: 0x00002761, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002765, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00002766, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00002767, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [TX_CLOCK_IO:TX_clock_IO] } + TX_CLOCK_IO - Addr: 0x00002767, Size: 1, Value: (0x00000001) 1 { clk_buf40 [CLK_BUF] [TX_CLOCK_IO:1] [from HR_2_CC_38_19P] } TX_DDR_MODE - Addr: 0x00002768, Size: 2, Value: (0x00000002) 2 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [O_SERDES_CLK:DDR_MODE==SDR] } TX_BYPASS - Addr: 0x0000276A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x0000276B, Size: 2, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [TX_CLK_PHASE:TX_phase_270] } @@ -5839,7 +5839,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_1 [HR_2_3_1N] RATE - Addr: 0x00002833, Size: 4, Value: (0x00000003) 3 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002837, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00002838, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00002839, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00002839, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x0000283A, Size: 2, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x0000283C, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x0000283D, Size: 2, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -5851,7 +5851,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_1 [HR_2_3_1N] RX_MIPI_MODE - Addr: 0x00002850, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x00002851, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } RX_MODE - Addr: 0x00002852, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00002853, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00002853, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x00002854, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } SR - Addr: 0x00002855, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PE - Addr: 0x00002856, Size: 1, Value: (0x00000000) 0 @@ -5863,7 +5863,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_1 [HR_2_2_1P] RATE - Addr: 0x0000285D, Size: 4, Value: (0x00000003) 3 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x00002861, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x00002862, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00002863, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00002863, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x00002864, Size: 2, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002866, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00002867, Size: 2, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -5875,7 +5875,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_1 [HR_2_2_1P] RX_MIPI_MODE - Addr: 0x0000287A, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x0000287B, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } RX_MODE - Addr: 0x0000287C, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x0000287D, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x0000287D, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x0000287E, Size: 1, Value: (0x00000001) 1 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } SR - Addr: 0x0000287F, Size: 1, Value: (0x00000000) 0 { i_buf_ds31 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PE - Addr: 0x00002880, Size: 1, Value: (0x00000000) 0 @@ -5887,7 +5887,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_0 [HR_2_1_0N] RATE - Addr: 0x00002887, Size: 4, Value: (0x00000003) 3 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x0000288B, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x0000288C, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000288D, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000288D, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x0000288E, Size: 2, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x00002890, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x00002891, Size: 2, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -5899,7 +5899,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_0 [HR_2_1_0N] RX_MIPI_MODE - Addr: 0x000028A4, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x000028A5, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } RX_MODE - Addr: 0x000028A6, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000028A7, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000028A7, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x000028A8, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } SR - Addr: 0x000028A9, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PE - Addr: 0x000028AA, Size: 1, Value: (0x00000000) 0 @@ -5911,7 +5911,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_0 [HR_2_0_0P] RATE - Addr: 0x000028B1, Size: 4, Value: (0x00000003) 3 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } MASTER_SLAVE - Addr: 0x000028B5, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PEER_IS_ON - Addr: 0x000028B6, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000028B7, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000028B7, Size: 1, Value: (0x00000000) 0 TX_DDR_MODE - Addr: 0x000028B8, Size: 2, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_BYPASS - Addr: 0x000028BA, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_CLK_PHASE - Addr: 0x000028BB, Size: 2, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } @@ -5923,7 +5923,7 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_0 [HR_2_0_0P] RX_MIPI_MODE - Addr: 0x000028CE, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } TX_MODE - Addr: 0x000028CF, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } RX_MODE - Addr: 0x000028D0, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000028D1, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000028D1, Size: 1, Value: (0x00000000) 0 DFEN - Addr: 0x000028D2, Size: 1, Value: (0x00000001) 1 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } SR - Addr: 0x000028D3, Size: 1, Value: (0x00000000) 0 { i_buf_ds30 [I_BUF_DS] [I_BUF_DS:IOSTANDARD==DEFAULT] } PE - Addr: 0x000028D4, Size: 1, Value: (0x00000000) 0 @@ -5939,21 +5939,21 @@ Block u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all [] cfg_rxclk_phase_sel_B_0 - Addr: 0x000028DD, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [cfg_rxclk_phase_sel_B_0:0] [from HP_1_CC_18_9P] } cfg_rxclk_phase_sel_B_1 - Addr: 0x000028DE, Size: 1, Value: (0x00000000) 0 cfg_rxclk_phase_sel_A_0 - Addr: 0x000028DF, Size: 1, Value: (0x00000000) 0 - cfg_rxclk_phase_sel_A_1 - Addr: 0x000028E0, Size: 1, Value: (0x00000000) 0 + cfg_rxclk_phase_sel_A_1 - Addr: 0x000028E0, Size: 1, Value: (0x00000001) 1 { clk_buf40 [CLK_BUF] [cfg_rxclk_phase_sel_A_1:1] [from HR_2_CC_38_19P] } cfg_rx_fclkio_sel_B_0 - Addr: 0x000028E1, Size: 1, Value: (0x00000000) 0 { pll00 [PLL] [cfg_rx_fclkio_sel_B_0:0] [from HP_1_CC_18_9P] } cfg_rx_fclkio_sel_B_1 - Addr: 0x000028E2, Size: 1, Value: (0x00000000) 0 cfg_rx_fclkio_sel_A_0 - Addr: 0x000028E3, Size: 1, Value: (0x00000000) 0 - cfg_rx_fclkio_sel_A_1 - Addr: 0x000028E4, Size: 1, Value: (0x00000000) 0 + cfg_rx_fclkio_sel_A_1 - Addr: 0x000028E4, Size: 1, Value: (0x00000001) 1 { clk_buf40 [CLK_BUF] [cfg_rx_fclkio_sel_A_1:1] [from HR_2_CC_38_19P] } cfg_vco_clk_sel_B_0 - Addr: 0x000028E5, Size: 1, Value: (0x00000001) 1 { pll00 [PLL] [cfg_vco_clk_sel_B_0:1] [from HP_1_CC_18_9P] } cfg_vco_clk_sel_B_1 - Addr: 0x000028E6, Size: 1, Value: (0x00000000) 0 cfg_vco_clk_sel_A_0 - Addr: 0x000028E7, Size: 1, Value: (0x00000000) 0 - cfg_vco_clk_sel_A_1 - Addr: 0x000028E8, Size: 1, Value: (0x00000000) 0 + cfg_vco_clk_sel_A_1 - Addr: 0x000028E8, Size: 1, Value: (0x00000000) 0 { clk_buf40 [CLK_BUF] [cfg_vco_clk_sel_A_1:0] [from HR_2_CC_38_19P] } Block u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x000028E9, Size: 5, Value: (0x00000000) 0 CDR_CLK_ROOT_SEL_A - Addr: 0x000028EE, Size: 5, Value: (0x00000000) 0 CORE_CLK_ROOT_SEL_B - Addr: 0x000028F3, Size: 5, Value: (0x00000000) 0 - CORE_CLK_ROOT_SEL_A - Addr: 0x000028F8, Size: 5, Value: (0x00000000) 0 + CORE_CLK_ROOT_SEL_A - Addr: 0x000028F8, Size: 5, Value: (0x00000012) 18 { clk_buf10 [CLK_BUF] [CORE_CLK_ROOT_SEL_A:18] [from HR_1_CC_18_9P] } Block u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1 [] Attributes: CDR_CLK_ROOT_SEL_B - Addr: 0x000028FD, Size: 5, Value: (0x00000000) 0 diff --git a/tests/unittest/ModelConfig/golden/negative_io_routing.json b/tests/unittest/ModelConfig/golden/negative_io_routing.json new file mode 100644 index 000000000..bf0f85e9f --- /dev/null +++ b/tests/unittest/ModelConfig/golden/negative_io_routing.json @@ -0,0 +1,1096 @@ +[ + { + "feature": "Fast Clock: module CLK_BUF clk_buf00 port O (location: HP_1_CC_18_9P) -> module I_DDR i_ddr00 (location: HP_1_20_10P)", + "comments": [ + "clk_buf00", + "O", + "i_ddr00" + ], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "Virgo.hp_40x2.bank0_hpio.gearbox_P[10]->fast_clk" + ], + "filters": [ + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "0" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.bank0_fclk_mux_B->rx_io_clk[0]", + "Virgo.hp_40x2.bank0_fclk_mux_B->fast_clk", + "Virgo.hp_40x2.bank0_hpio->fast_clk_B", + "Virgo.hp_40x2.bank0_hpio.gearbox_P[10]->fast_clk" + ] + ], + "config mux": [ + null, + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_fclk_mux_all": { + "cfg_vco_clk_sel_B_0": "0", + "cfg_rx_fclkio_sel_B_0": "0", + "cfg_rxclk_phase_sel_B_0": "1" + } + }, + null, + null + ], + "status": true + }, + { + "feature": "Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)", + "comments": [ + "pll00", + "CLK_OUT", + "i_ddr01" + ], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[10]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "1", + "OUT1_ROUTE_TO_FABRIC_CLK": "2", + "OUT2_ROUTE_TO_FABRIC_CLK": "3", + "OUT3_ROUTE_TO_FABRIC_CLK": "4", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[0]", + "Virgo.hp_40x2->pll_fout[0]", + "Virgo.hvl_40x2->pll_fout", + "Virgo.hvl_40x2.bank0_fclk_mux_B->vco_clk[1]", + "Virgo.hvl_40x2.bank0_fclk_mux_B->fast_clk", + "Virgo.hvl_40x2.bank0_hpio->fast_clk_B", + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[10]->fast_clk" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "1", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + null, + null, + null, + { + "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all": { + "cfg_vco_clk_sel_B_0": "1", + "cfg_rx_fclkio_sel_B_0": "0", + "cfg_rxclk_phase_sel_B_0": "0" + } + }, + null, + null + ], + "status": true + }, + { + "feature": "Fast Clock: module CLK_BUF clk_buf10 port O (location: HR_1_CC_18_9P) -> module I_DDR i_ddr11 (location: HR_5_2_1P)", + "comments": [ + "clk_buf10", + "O", + "i_ddr11" + ], + "source": "Virgo->HR_1_CC_18_9P", + "destinations": [ + "Virgo.hvr_40x2.bank1_hpio.gearbox_P[1]->fast_clk" + ], + "filters": [ + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "5" + } + }, + "msgs": [ + "Fail to find any paths first round" + ], + "potential paths": [], + "config mux": [], + "status": false + }, + { + "feature": "Fast Clock: module CLK_BUF clk_buf10 port O (location: HR_1_CC_18_9P) -> module I_DDR i_ddr12 (location: HR_1_24_12P)", + "comments": [ + "clk_buf10", + "O", + "i_ddr12" + ], + "source": "Virgo->HR_1_CC_18_9P", + "destinations": [ + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[12]->fast_clk" + ], + "filters": [ + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "5" + } + }, + "msgs": [ + "'Fast Clock: module CLK_BUF clk_buf10 port O (location: HR_1_CC_18_9P) -> module I_DDR i_ddr12 (location: HR_1_24_12P)' had conflict to set config mux hvl_40x2.bank0_fclk_mux_B->vco_clk_sel to value 0, had been set with value 1 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'", + "Fail to find any paths first round" + ], + "potential paths": [], + "config mux": [], + "status": false + }, + { + "feature": "Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc0 (location: HR_2_20_10P)", + "comments": [ + "pllosc0", + "CLK_OUT", + "i_ddr_osc0" + ], + "source": "Virgo.hp_40x2.rc_osc_50mhz->osc", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[10]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc0 (location: HR_2_20_10P)' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_use_rosc to value 1, had been set with value 0 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'", + "Fail to find any paths first round" + ], + "potential paths": [], + "config mux": [], + "status": false + }, + { + "feature": "Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)", + "comments": [ + "pllosc0", + "CLK_OUT", + "i_ddr_osc1" + ], + "source": "Virgo.hp_40x2.rc_osc_50mhz->osc", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo.hvr_40x2.bank1_hpio.gearbox_P[10]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo.hp_40x2.rc_osc_50mhz->osc", + "Virgo.hp_40x2.rc_osc_50mhz->o_osc", + "Virgo.hp_40x2.pll_refmux[1]->rosc_clk", + "Virgo.hp_40x2.pll_refmux[1]->out", + "Virgo.hp_40x2.pll[1]->fref", + "Virgo.hp_40x2.pll[1]->fout[0]", + "Virgo.hp_40x2->pll_fout[1]", + "Virgo.hvr_40x2->pll_fout", + "Virgo.hvr_40x2.bank1_fclk_mux_B->vco_clk[1]", + "Virgo.hvr_40x2.bank1_fclk_mux_B->fast_clk", + "Virgo.hvr_40x2.bank1_hpio->fast_clk_B", + "Virgo.hvr_40x2.bank1_hpio.gearbox_P[10]->fast_clk" + ] + ], + "config mux": [ + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_1": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_1": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "1" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "1", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + null, + null, + null, + { + "u_GBOX_HV_40X2_VR.u_gbox_fclk_mux_all": { + "cfg_vco_clk_sel_B_1": "1", + "cfg_rx_fclkio_sel_B_1": "0", + "cfg_rxclk_phase_sel_B_1": "0" + } + }, + null, + null + ], + "status": true + }, + { + "feature": "Fast Clock: module PLL pllosc1 port CLK_OUT_DIV2 (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc3 (location: HR_5_22_11P)", + "comments": [ + "pllosc1", + "CLK_OUT_DIV2", + "i_ddr_osc3" + ], + "source": "Virgo.hp_40x2.rc_osc_50mhz->osc", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[1]", + "Virgo.hvr_40x2.bank1_hpio.gearbox_P[11]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "Fail to find any paths first round" + ], + "potential paths": [], + "config mux": [], + "status": false + }, + { + "feature": "Fast Clock: module PLL pllosc2 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc4 (location: HR_1_30_15P)", + "comments": [ + "pllosc2", + "CLK_OUT", + "i_ddr_osc4" + ], + "source": "Virgo.hp_40x2.rc_osc_50mhz->osc", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[15]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "'Fast Clock: module PLL pllosc2 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc4 (location: HR_1_30_15P)' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_use_rosc to value 1, had been set with value 0 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'", + "Fail to find any paths first round" + ], + "potential paths": [], + "config mux": [], + "status": false + }, + { + "feature": "Fast Clock: module PLL pll30 port FAST_CLK (location: HR_1_CC_38_19P) -> module I_DDR i_ddr30 (location: HR_2_0_0P)", + "comments": [ + "pll30", + "FAST_CLK", + "i_ddr30" + ], + "source": "Virgo->HR_1_CC_38_19P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->foutvco", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[0]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "'Fast Clock: module PLL pll30 port FAST_CLK (location: HR_1_CC_38_19P) -> module I_DDR i_ddr30 (location: HR_2_0_0P)' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_hv_rx_io_sel to value 1, had been set with value 0 by 'Fast Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr01 (location: HR_1_20_10P)'", + "Fail to find any paths first round" + ], + "potential paths": [], + "config mux": [], + "status": false + }, + { + "feature": "Fast Clock: module PLL pll31 port CLK_OUT (location: HR_3_CC_38_19P) -> module I_DDR i_ddr31 (location: HR_2_2_1P)", + "comments": [ + "pll31", + "CLK_OUT", + "i_ddr31" + ], + "source": "Virgo->HR_3_CC_38_19P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[1]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "7", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "Fail to find any paths first round" + ], + "potential paths": [], + "config mux": [], + "status": false + }, + { + "feature": "Fast Clock: module CLK_BUF clk_buf40 port O (location: HR_2_CC_38_19P) -> module O_SERDES_CLK o_serdes_clk (location: HR_2_8_4P)", + "comments": [ + "clk_buf40", + "O", + "o_serdes_clk" + ], + "source": "Virgo->HR_2_CC_38_19P", + "destinations": [ + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[4]->fast_clk", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[4]->tx_clk" + ], + "filters": [ + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": {} + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HR_2_CC_38_19P", + "Virgo.hvl_40x2->bank1_rx_in[38]", + "Virgo.hvl_40x2.bank1_hpio->rx_in[38]", + "Virgo.hvl_40x2.bank1_hpio->rx_io_clk[1]", + "Virgo.hvl_40x2.bank1_fclk_mux_A->rx_io_clk[1]", + "Virgo.hvl_40x2.bank1_fclk_mux_A->fast_clk", + "Virgo.hvl_40x2.bank1_hpio->fast_clk_A", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[4]->fast_clk", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[4]->tx_clk" + ] + ], + "config mux": [ + null, + null, + null, + null, + null, + { + "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all": { + "cfg_vco_clk_sel_A_1": "0", + "cfg_rx_fclkio_sel_A_1": "1", + "cfg_rxclk_phase_sel_A_1": "1" + } + }, + null, + null, + { + "HR_2_8_4P": { + "TX_CLOCK_IO": "1" + } + } + ], + "status": true + }, + { + "feature": "Core Clock: module CLK_BUF clk_buf00 port O (location: HP_1_CC_18_9P) -> core clock slot[0]", + "comments": [], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "Virgo->fabric_clk[0]" + ], + "filters": [ + "partial:_fclk_mux_", + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "0" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio.gearbox_P[9]->rx_in", + "Virgo.hp_40x2.bank0_hpio.gearbox_P[9]->core_clk", + "Virgo.hp_40x2.bank0_hpio->core_clk[18]", + "Virgo.hp_40x2.bank0_root_bank_clkmux->core_clk_in[18]", + "Virgo.hp_40x2.bank0_root_bank_clkmux->core_clk[0]", + "Virgo.hp_40x2->fabric_clk[0]", + "Virgo->fabric_clk[0]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "HP_1_CC_18_9P": { + "RX_CLOCK_IO": "1" + } + }, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0": { + "CORE_CLK_ROOT_SEL_A": "18" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0": { + "ROOT_MUX_SEL": "0" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> core clock slot[1]", + "comments": [], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo->fabric_clk[1]" + ], + "filters": [ + "partial:_fclk_mux_" + ], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "1", + "OUT1_ROUTE_TO_FABRIC_CLK": "2", + "OUT2_ROUTE_TO_FABRIC_CLK": "3", + "OUT3_ROUTE_TO_FABRIC_CLK": "4", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "'Core Clock: module PLL pll00 port CLK_OUT (location: HP_1_CC_18_9P) -> core clock slot[1]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_rosc to value 0, had been set with value 1 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'" + ], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[0]", + "Virgo.hp_40x2->fabric_clk[1]", + "Virgo->fabric_clk[1]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "1", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1": { + "ROOT_MUX_SEL": "32" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module PLL pll00 port CLK_OUT_DIV2 (location: HP_1_CC_18_9P) -> core clock slot[2]", + "comments": [], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[1]", + "Virgo->fabric_clk[2]" + ], + "filters": [ + "partial:_fclk_mux_" + ], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "1", + "OUT1_ROUTE_TO_FABRIC_CLK": "2", + "OUT2_ROUTE_TO_FABRIC_CLK": "3", + "OUT3_ROUTE_TO_FABRIC_CLK": "4", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "'Core Clock: module PLL pll00 port CLK_OUT_DIV2 (location: HP_1_CC_18_9P) -> core clock slot[2]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_rosc to value 0, had been set with value 1 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'" + ], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[1]", + "Virgo.hp_40x2->fabric_clk[2]", + "Virgo->fabric_clk[2]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "1", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2": { + "ROOT_MUX_SEL": "33" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module PLL pll00 port CLK_OUT_DIV3 (location: HP_1_CC_18_9P) -> core clock slot[3]", + "comments": [], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[2]", + "Virgo->fabric_clk[3]" + ], + "filters": [ + "partial:_fclk_mux_" + ], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "1", + "OUT1_ROUTE_TO_FABRIC_CLK": "2", + "OUT2_ROUTE_TO_FABRIC_CLK": "3", + "OUT3_ROUTE_TO_FABRIC_CLK": "4", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "'Core Clock: module PLL pll00 port CLK_OUT_DIV3 (location: HP_1_CC_18_9P) -> core clock slot[3]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_rosc to value 0, had been set with value 1 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'" + ], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[2]", + "Virgo.hp_40x2->fabric_clk[3]", + "Virgo->fabric_clk[3]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "1", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3": { + "ROOT_MUX_SEL": "34" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module PLL pll00 port CLK_OUT_DIV4 (location: HP_1_CC_18_9P) -> core clock slot[4]", + "comments": [], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[3]", + "Virgo->fabric_clk[4]" + ], + "filters": [ + "partial:_fclk_mux_" + ], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "1", + "OUT1_ROUTE_TO_FABRIC_CLK": "2", + "OUT2_ROUTE_TO_FABRIC_CLK": "3", + "OUT3_ROUTE_TO_FABRIC_CLK": "4", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "'Core Clock: module PLL pll00 port CLK_OUT_DIV4 (location: HP_1_CC_18_9P) -> core clock slot[4]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_rosc to value 0, had been set with value 1 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'" + ], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[3]", + "Virgo.hp_40x2->fabric_clk[4]", + "Virgo->fabric_clk[4]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "1", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4": { + "ROOT_MUX_SEL": "35" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module CLK_BUF clk_buf10 port O (location: HR_1_CC_18_9P) -> core clock slot[5]", + "comments": [], + "source": "Virgo->HR_1_CC_18_9P", + "destinations": [ + "Virgo->fabric_clk[5]" + ], + "filters": [ + "partial:_fclk_mux_", + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "5" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HR_1_CC_18_9P", + "Virgo.hvl_40x2->bank0_rx_in[18]", + "Virgo.hvl_40x2.bank0_hpio->rx_in[18]", + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[9]->rx_in", + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[9]->core_clk", + "Virgo.hvl_40x2.bank0_hpio->core_clk[18]", + "Virgo.hvl_40x2.bank0_root_bank_clkmux->core_clk_in[18]", + "Virgo.hvl_40x2.bank0_root_bank_clkmux->core_clk[0]", + "Virgo.hvl_40x2->bank0_root_core_clk[0]", + "Virgo.hp_40x2->hvl_bank0_root_core_clk[0]", + "Virgo.hp_40x2->fabric_clk[5]", + "Virgo->fabric_clk[5]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "HR_1_CC_18_9P": { + "RX_CLOCK_IO": "1" + } + }, + null, + null, + { + "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0": { + "CORE_CLK_ROOT_SEL_A": "18" + } + }, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5": { + "ROOT_MUX_SEL": "8" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module CLK_BUF $clkbuf$top.$ibuf_clk20 port O (location: HP_1_CC_38_19P) -> core clock slot[6]", + "comments": [], + "source": "Virgo->HP_1_CC_38_19P", + "destinations": [ + "Virgo->fabric_clk[6]" + ], + "filters": [ + "partial:_fclk_mux_", + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "6" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HP_1_CC_38_19P", + "Virgo.hp_40x2->bank0_rx_in[38]", + "Virgo.hp_40x2.bank0_hpio->rx_in[38]", + "Virgo.hp_40x2.bank0_hpio.gearbox_P[19]->rx_in", + "Virgo.hp_40x2.bank0_hpio.gearbox_P[19]->core_clk", + "Virgo.hp_40x2.bank0_hpio->core_clk[38]", + "Virgo.hp_40x2.bank0_root_bank_clkmux->core_clk_in[38]", + "Virgo.hp_40x2.bank0_root_bank_clkmux->core_clk[1]", + "Virgo.hp_40x2->fabric_clk[6]", + "Virgo->fabric_clk[6]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "HP_1_CC_38_19P": { + "RX_CLOCK_IO": "1" + } + }, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0": { + "CORE_CLK_ROOT_SEL_B": "18" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6": { + "ROOT_MUX_SEL": "1" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module PLL pll31 port CLK_OUT (location: HR_3_CC_38_19P) -> core clock slot[7]", + "comments": [], + "source": "Virgo->HR_3_CC_38_19P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo->fabric_clk[7]" + ], + "filters": [ + "partial:_fclk_mux_" + ], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "7", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "1" + } + }, + "msgs": [ + "'Core Clock: module PLL pll31 port CLK_OUT (location: HR_3_CC_38_19P) -> core clock slot[7]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_hv_rx_io_sel to value 1, had been set with value 0 by 'Fast Clock: module PLL pllosc0 port CLK_OUT (location: BOOT_CLOCK#0) -> module I_DDR i_ddr_osc1 (location: HR_5_20_10P)'", + "Fail to find any paths first round" + ], + "potential paths": [], + "config mux": [], + "status": false + } +] \ No newline at end of file diff --git a/tests/unittest/ModelConfig/golden/positive_io_routing.json b/tests/unittest/ModelConfig/golden/positive_io_routing.json new file mode 100644 index 000000000..4e7767f3d --- /dev/null +++ b/tests/unittest/ModelConfig/golden/positive_io_routing.json @@ -0,0 +1,936 @@ +[ + { + "feature": "Fast Clock: module CLK_BUF $clkbuf$top.$ibuf_clk0 port O (location: HR_1_CC_38_19P) -> module I_DELAY i_delay (location: HR_1_4_2P)", + "comments": [ + "$clkbuf$top.$ibuf_clk0", + "O", + "i_delay" + ], + "source": "Virgo->HR_1_CC_38_19P", + "destinations": [ + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[2]->fast_clk" + ], + "filters": [ + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "0" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HR_1_CC_38_19P", + "Virgo.hvl_40x2->bank0_rx_in[38]", + "Virgo.hvl_40x2.bank0_hpio->rx_in[38]", + "Virgo.hvl_40x2.bank0_hpio->rx_io_clk[1]", + "Virgo.hvl_40x2.bank0_fclk_mux_A->rx_io_clk[1]", + "Virgo.hvl_40x2.bank0_fclk_mux_A->fast_clk", + "Virgo.hvl_40x2.bank0_hpio->fast_clk_A", + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[2]->fast_clk" + ] + ], + "config mux": [ + null, + null, + null, + null, + null, + { + "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all": { + "cfg_vco_clk_sel_A_0": "0", + "cfg_rx_fclkio_sel_A_0": "1", + "cfg_rxclk_phase_sel_A_0": "1" + } + }, + null, + null + ], + "status": true + }, + { + "feature": "Fast Clock: module CLK_BUF clk_buf port O (location: HP_1_CC_18_9P) -> module O_DELAY o_delay (location: HR_1_6_3P)", + "comments": [ + "clk_buf", + "O", + "o_delay" + ], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[3]->fast_clk" + ], + "filters": [ + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "1" + } + }, + "msgs": [ + "Fail to find any paths first round" + ], + "potential paths": [], + "config mux": [], + "status": false + }, + { + "feature": "Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module I_SERDES i_serdes (location: HR_2_0_0P)", + "comments": [ + "pll", + "CLK_OUT", + "i_serdes" + ], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[0]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "2", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "0" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[0]", + "Virgo.hp_40x2->pll_fout[0]", + "Virgo.hvl_40x2->pll_fout", + "Virgo.hvl_40x2.bank1_fclk_mux_A->vco_clk[1]", + "Virgo.hvl_40x2.bank1_fclk_mux_A->fast_clk", + "Virgo.hvl_40x2.bank1_hpio->fast_clk_A", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[0]->fast_clk" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "0", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + null, + null, + null, + { + "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all": { + "cfg_vco_clk_sel_A_1": "1", + "cfg_rx_fclkio_sel_A_1": "0", + "cfg_rxclk_phase_sel_A_1": "0" + } + }, + null, + null + ], + "status": true + }, + { + "feature": "Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module I_DDR i_ddr (location: HP_1_4_2P)", + "comments": [ + "pll", + "CLK_OUT", + "i_ddr" + ], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo.hp_40x2.bank0_hpio.gearbox_P[2]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "2", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "0" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[0]", + "Virgo.hp_40x2.bank0_fclk_mux_A->vco_clk[1]", + "Virgo.hp_40x2.bank0_fclk_mux_A->fast_clk", + "Virgo.hp_40x2.bank0_hpio->fast_clk_A", + "Virgo.hp_40x2.bank0_hpio.gearbox_P[2]->fast_clk" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "0", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_fclk_mux_all": { + "cfg_vco_clk_sel_A_0": "1", + "cfg_rx_fclkio_sel_A_0": "0", + "cfg_rxclk_phase_sel_A_0": "0" + } + }, + null, + null + ], + "status": true + }, + { + "feature": "Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module O_SERDES o_serdes (location: HR_2_2_1P)", + "comments": [ + "pll", + "CLK_OUT", + "o_serdes" + ], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[1]->fast_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "2", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "0" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[0]", + "Virgo.hp_40x2->pll_fout[0]", + "Virgo.hvl_40x2->pll_fout", + "Virgo.hvl_40x2.bank1_fclk_mux_A->vco_clk[1]", + "Virgo.hvl_40x2.bank1_fclk_mux_A->fast_clk", + "Virgo.hvl_40x2.bank1_hpio->fast_clk_A", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[1]->fast_clk" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "0", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + null, + null, + null, + { + "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all": { + "cfg_vco_clk_sel_A_1": "1", + "cfg_rx_fclkio_sel_A_1": "0", + "cfg_rxclk_phase_sel_A_1": "0" + } + }, + null, + null + ], + "status": true + }, + { + "feature": "Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module O_SERDES_CLK o_serdes_clk (location: HR_2_4_2P)", + "comments": [ + "pll", + "CLK_OUT", + "o_serdes_clk" + ], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[2]->fast_clk", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[2]->tx_clk" + ], + "filters": [], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "2", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "0" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[0]", + "Virgo.hp_40x2->pll_fout[0]", + "Virgo.hvl_40x2->pll_fout", + "Virgo.hvl_40x2.bank1_fclk_mux_A->vco_clk[1]", + "Virgo.hvl_40x2.bank1_fclk_mux_A->fast_clk", + "Virgo.hvl_40x2.bank1_hpio->fast_clk_A", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[2]->fast_clk", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[2]->tx_clk" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "0", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + null, + null, + null, + { + "u_GBOX_HV_40X2_VL.u_gbox_fclk_mux_all": { + "cfg_vco_clk_sel_A_1": "1", + "cfg_rx_fclkio_sel_A_1": "0", + "cfg_rxclk_phase_sel_A_1": "0" + } + }, + null, + null, + { + "HR_2_4_2P": { + "TX_CLOCK_IO": "1" + } + } + ], + "status": true + }, + { + "feature": "Core Clock: module CLK_BUF $clkbuf$top.$ibuf_clk0 port O (location: HR_1_CC_38_19P) -> core clock slot[0]", + "comments": [], + "source": "Virgo->HR_1_CC_38_19P", + "destinations": [ + "Virgo->fabric_clk[0]" + ], + "filters": [ + "partial:_fclk_mux_", + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "0" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HR_1_CC_38_19P", + "Virgo.hvl_40x2->bank0_rx_in[38]", + "Virgo.hvl_40x2.bank0_hpio->rx_in[38]", + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[19]->rx_in", + "Virgo.hvl_40x2.bank0_hpio.gearbox_P[19]->core_clk", + "Virgo.hvl_40x2.bank0_hpio->core_clk[38]", + "Virgo.hvl_40x2.bank0_root_bank_clkmux->core_clk_in[38]", + "Virgo.hvl_40x2.bank0_root_bank_clkmux->core_clk[1]", + "Virgo.hvl_40x2->bank0_root_core_clk[1]", + "Virgo.hp_40x2->hvl_bank0_root_core_clk[1]", + "Virgo.hp_40x2->fabric_clk[0]", + "Virgo->fabric_clk[0]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "HR_1_CC_38_19P": { + "RX_CLOCK_IO": "1" + } + }, + null, + null, + { + "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0": { + "CORE_CLK_ROOT_SEL_B": "18" + } + }, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_0": { + "ROOT_MUX_SEL": "9" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module CLK_BUF clk_buf port O (location: HP_1_CC_18_9P) -> core clock slot[1]", + "comments": [], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "Virgo->fabric_clk[1]" + ], + "filters": [ + "partial:_fclk_mux_", + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "1" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio.gearbox_P[9]->rx_in", + "Virgo.hp_40x2.bank0_hpio.gearbox_P[9]->core_clk", + "Virgo.hp_40x2.bank0_hpio->core_clk[18]", + "Virgo.hp_40x2.bank0_root_bank_clkmux->core_clk_in[18]", + "Virgo.hp_40x2.bank0_root_bank_clkmux->core_clk[0]", + "Virgo.hp_40x2->fabric_clk[1]", + "Virgo->fabric_clk[1]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "HP_1_CC_18_9P": { + "RX_CLOCK_IO": "1" + } + }, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0": { + "CORE_CLK_ROOT_SEL_A": "18" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_1": { + "ROOT_MUX_SEL": "0" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> core clock slot[2]", + "comments": [], + "source": "Virgo->HP_1_CC_18_9P", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo->fabric_clk[2]" + ], + "filters": [ + "partial:_fclk_mux_" + ], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "2", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "0" + } + }, + "msgs": [ + "'Core Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> core clock slot[2]' had conflict to set config mux hp_40x2.pll_refmux[1]->cfg_pllref_use_div to value 0, had been set with value 1 by 'Core Clock: module PLL pll_osc port CLK_OUT (location: BOOT_CLOCK#0) -> core clock slot[5]'" + ], + "potential paths": [ + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[0]->out", + "Virgo.hp_40x2.pll[0]->fref", + "Virgo.hp_40x2.pll[0]->fout[0]", + "Virgo.hp_40x2->fabric_clk[2]", + "Virgo->fabric_clk[2]" + ], + [ + "Virgo->HP_1_CC_18_9P", + "Virgo.hp_40x2->bank0_rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_in[18]", + "Virgo.hp_40x2.bank0_hpio->rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[1]->bank0_hp_rx_io_clk[0]", + "Virgo.hp_40x2.pll_refmux[1]->out", + "Virgo.hp_40x2.pll[1]->fref", + "Virgo.hp_40x2.pll[1]->fout[0]", + "Virgo.hp_40x2->fabric_clk[2]", + "Virgo->fabric_clk[2]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_use_div": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_0": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "0" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_0": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "0", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_2": { + "ROOT_MUX_SEL": "32" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module CLK_BUF $clkbuf$top.$ibuf_clk2 port O (location: HR_5_CC_38_19P) -> core clock slot[3]", + "comments": [], + "source": "Virgo->HR_5_CC_38_19P", + "destinations": [ + "Virgo->fabric_clk[3]" + ], + "filters": [ + "partial:_fclk_mux_", + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "CLK_BUF": { + "ROUTE_TO_FABRIC_CLK": "3" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->HR_5_CC_38_19P", + "Virgo.hvr_40x2->bank1_rx_in[38]", + "Virgo.hvr_40x2.bank1_hpio->rx_in[38]", + "Virgo.hvr_40x2.bank1_hpio.gearbox_P[19]->rx_in", + "Virgo.hvr_40x2.bank1_hpio.gearbox_P[19]->core_clk", + "Virgo.hvr_40x2.bank1_hpio->core_clk[38]", + "Virgo.hvr_40x2.bank1_root_bank_clkmux->core_clk_in[38]", + "Virgo.hvr_40x2.bank1_root_bank_clkmux->core_clk[1]", + "Virgo.hvr_40x2->bank1_root_core_clk[1]", + "Virgo.hp_40x2->hvr_bank1_root_core_clk[1]", + "Virgo.hp_40x2->fabric_clk[3]", + "Virgo->fabric_clk[3]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "HR_5_CC_38_19P": { + "RX_CLOCK_IO": "1" + } + }, + null, + null, + { + "u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1": { + "CORE_CLK_ROOT_SEL_B": "18" + } + }, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_3": { + "ROOT_MUX_SEL": "19" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module I_SERDES i_serdes port CLK_OUT (location: HR_2_0_0P) -> core clock slot[4]", + "comments": [], + "source": "Virgo.hvl_40x2.bank1_hpio.gearbox_P[0]->fast_clk", + "destinations": [ + "partial:root_bank_clkmux->cdr_clk", + "Virgo->fabric_clk[4]" + ], + "filters": [ + "partial:_fclk_mux_", + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "I_SERDES": { + "DATA_RATE": "SDR", + "DPA_MODE": "DPA", + "ROUTE_TO_FABRIC_CLK": "4", + "WIDTH": "8" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[0]->fast_clk", + "Virgo.hvl_40x2.bank1_hpio.gearbox_P[0]->cdr_clk", + "Virgo.hvl_40x2.bank1_hpio->cdr_clk[0]", + "Virgo.hvl_40x2.bank1_root_bank_clkmux->cdr_clk_in[0]", + "Virgo.hvl_40x2.bank1_root_bank_clkmux->cdr_clk[0]", + "Virgo.hvl_40x2->bank1_root_cdr_clk[0]", + "Virgo.hp_40x2->hvl_bank1_root_cdr_clk[0]", + "Virgo.hp_40x2->fabric_clk[4]", + "Virgo->fabric_clk[4]" + ] + ], + "config mux": [ + null, + null, + null, + null, + { + "u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1": { + "CDR_CLK_ROOT_SEL_A": "0" + } + }, + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_4": { + "ROOT_MUX_SEL": "14" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module PLL pll_osc port CLK_OUT (location: BOOT_CLOCK#0) -> core clock slot[5]", + "comments": [], + "source": "Virgo.hp_40x2.rc_osc_50mhz->osc", + "destinations": [ + "RE:(*s*)pll[(*d*)]->fout[0]", + "Virgo->fabric_clk[5]" + ], + "filters": [ + "partial:_fclk_mux_" + ], + "flags": [], + "parameters": { + "PLL": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "TRUE", + "OUT0_ROUTE_TO_FABRIC_CLK": "5", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34", + "__pll_enable__": "0" + } + }, + "msgs": [ + "'Core Clock: module PLL pll_osc port CLK_OUT (location: BOOT_CLOCK#0) -> core clock slot[5]' had conflict to set config mux hp_40x2.pll_refmux[0]->cfg_pllref_use_div to value 1, had been set with value 0 by 'Fast Clock: module PLL pll port CLK_OUT (location: HP_1_CC_18_9P) -> module I_SERDES i_serdes (location: HR_2_0_0P)'" + ], + "potential paths": [ + [ + "Virgo.hp_40x2.rc_osc_50mhz->osc", + "Virgo.hp_40x2.rc_osc_50mhz->o_osc", + "Virgo.hp_40x2.pll_refmux[1]->rosc_clk", + "Virgo.hp_40x2.pll_refmux[1]->out", + "Virgo.hp_40x2.pll[1]->fref", + "Virgo.hp_40x2.pll[1]->fout[0]", + "Virgo.hp_40x2->fabric_clk[5]", + "Virgo->fabric_clk[5]" + ] + ], + "config mux": [ + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_1": { + "cfg_pllref_use_div": "1" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_pll_refmux_1": { + "cfg_pllref_hv_rx_io_sel": "0", + "cfg_pllref_hv_bank_rx_io_sel": "0", + "cfg_pllref_hp_rx_io_sel": "0", + "cfg_pllref_hp_bank_rx_io_sel": "0", + "cfg_pllref_use_hv": "0", + "cfg_pllref_use_rosc": "1" + } + }, + { + "u_GBOX_HP_40X2.u_gbox_PLLTS16FFCFRACF_1": { + "pll_DSKEWCALBYP": "DSKEWCALBYP_0", + "pll_DSKEWCALIN": "0", + "pll_DSKEWCALCNT": "2", + "pll_DSKEWFASTCAL": "DSKEWFASTCAL_0", + "pll_DSKEWCALEN": "DSKEWCALEN_0", + "pll_FRAC": "0", + "pll_FBDIV": "16", + "pll_REFDIV": "1", + "pll_PLLEN": "0", + "pll_POSTDIV1": "2", + "pll_POSTDIV2": "2", + "pll_DSMEN": "DSMEN_0", + "pll_DACEN": "DACEN_0" + } + }, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5": { + "ROOT_MUX_SEL": "36" + } + }, + null + ], + "status": true + }, + { + "feature": "Core Clock: module FCLK_BUF $clkbuf$top.clk0_div port O (location: FABRIC_CLKBUF#0) -> core clock slot[6]", + "comments": [], + "source": "Virgo->fclk_buf[0]", + "destinations": [ + "Virgo->fabric_clk[6]" + ], + "filters": [ + "partial:_fclk_mux_", + "partial:pll_refmux" + ], + "flags": [], + "parameters": { + "FCLK_BUF": { + "ROUTE_FROM_FABRIC_CLK": "0", + "ROUTE_TO_FABRIC_CLK": "6" + } + }, + "msgs": [], + "potential paths": [ + [ + "Virgo->fclk_buf[0]", + "Virgo.hp_40x2->fclk_buf[0]", + "Virgo.hp_40x2->fabric_clk[6]", + "Virgo->fabric_clk[6]" + ] + ], + "config mux": [ + null, + null, + { + "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6": { + "ROOT_MUX_SEL": "44" + } + }, + null + ], + "status": true + } +] \ No newline at end of file diff --git a/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json b/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json index f26e88e2a..df6e11017 100644 --- a/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json +++ b/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json @@ -1,5 +1,6 @@ { - "messages" : [ + "status": false, + "messages": [ "Start of IO Analysis", " Get Ports", " Detect input port \\clk00 (index=0, width=1, offset=0)", @@ -144,11 +145,12 @@ " Parameter \\IOSTANDARD: \"DEFAULT\"", " Parameter \\WEAK_KEEPER: \"NONE\"", " Data Width: -2", - " Get important connection of cell \\O_BUF_DS \\o_buf_ds", + " Get important connection of cell \\O_BUFT_DS \\o_buf_ds", " Cell port \\O_N is connected to output port \\dout30_n", " Cell port \\O_P is connected to output port \\dout30_p", " Parameter \\DIFFERENTIAL_TERMINATION: \"TRUE\"", " Parameter \\IOSTANDARD: \"DEFAULT\"", + " Parameter \\WEAK_KEEPER: \"NONE\"", " Data Width: -2", " Trace \\I_BUF --> \\CLK_BUF", " Try \\I_BUF $ibuf$top.$ibuf_clk00 out connection: $ibuf_clk00 -> \\clk_buf00", @@ -293,12 +295,12 @@ " Trace \\O_BUFT --> \\O_SERDES", " Trace \\O_BUF_DS --> \\O_DELAY", " Trace \\O_BUF_DS --> \\O_DDR", - " Try \\O_BUF_DS \\o_buf_ds out connection: \\dout_oddr3x -> \\o_ddr3x", - " Connected \\o_ddr3x", - " Data Width: -2", " Trace \\O_BUF_DS --> \\O_SERDES", " Trace \\O_BUFT_DS --> \\O_DELAY", " Trace \\O_BUFT_DS --> \\O_DDR", + " Try \\O_BUFT_DS \\o_buf_ds out connection: \\dout_oddr3x -> \\o_ddr3x", + " Connected \\o_ddr3x", + " Data Width: -2", " Trace \\O_BUFT_DS --> \\O_SERDES", " Trace \\O_DELAY --> \\O_DDR", " Trace \\O_DELAY --> \\O_SERDES", @@ -339,7 +341,7 @@ " \\I_DDR \\i_ddr_osc4 port \\C: \\pllosc2_clk0", " Connected to \\PLL \\pllosc2 port \\CLK_OUT", " \\I_DDR \\i_ddr30 port \\C: \\pll30_clk", - " Connected to \\PLL \\pll30 port \\CLK_OUT", + " Connected to \\PLL \\pll30 port \\FAST_CLK", " \\I_DDR \\i_ddr31 port \\C: \\pll31_clk", " Connected to \\PLL \\pll31 port \\CLK_OUT", " \\O_SERDES_CLK \\o_serdes_clk port \\PLL_CLK: \\clkbuf40", @@ -440,7 +442,7 @@ " Connected to cell \\PLL \\pll30", " Which is a primitive", " Does not meet core_clk checking criteria. Not sending to fabric", - " Module \\PLL \\pll30: clock port \\CLK_OUT, net \\pll30_clk", + " Module \\PLL \\pll30: clock port \\FAST_CLK, net \\pll30_clk", " Connected to cell \\I_DDR \\i_ddr30", " Which is a primitive", " Does not meet core_clk checking criteria. Not sending to fabric", @@ -507,7 +509,7 @@ " IN | clk40 * I_BUF |-> CLK_BUF * |", " IN | din30_n+din30_p * I_BUF_DS |-> I_DDR * |", " IN | din31_n+din31_p * I_BUF_DS |-> I_DDR * |", - " OUT | * O_DDR |-> O_BUF_DS * dout30_n+dout30_p |", + " OUT | * O_DDR |-> O_BUFT_DS * dout30_n+dout30_p |", " | *********************************************************** |", " |-----------------------------------------------------------------------------------------------|", " Final checking is good", @@ -543,15 +545,15 @@ " Determine data signals", " Pin object=clk00, location: HP_1_CC_18_9P", " Data signal from object clk00", - " Fail reason: Object clk00 is primitive \\PLL but data signal is not defined", + " Skip reason: Object clk00 is primitive \\PLL but data signal is not defined", " Pin object=clk10, location: HR_1_CC_18_9P", " Data signal from object clk10", - " Module=I_BUF Linked-object=clk10 Port=O Net=$flatten$auto_814.$ibuf_clk10 - Not found", - " Fail reason: Clock data from object clk10 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk10 Port=O Net=$flatten$auto_805.$ibuf_clk10 - Not found", + " Skip reason: Clock data from object clk10 port O does not need to route to fabric", " Pin object=clk20, location: HP_1_CC_38_19P", " Data signal from object clk20", - " Module=I_BUF Linked-object=clk20 Port=O Net=$flatten$auto_814.$ibuf_clk20 - Not found", - " Fail reason: Clock data from object clk20 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk20 Port=O Net=$flatten$auto_805.$ibuf_clk20 - Not found", + " Skip reason: Clock data from object clk20 port O does not need to route to fabric", " Pin object=din00, location: HP_1_20_10P", " Data signal from object din00", " Module=I_DDR Linked-object=din00 Port=Q Net=din_iddr00[0] - Found", @@ -592,43 +594,43 @@ " Module=I_DDR Linked-object=dinosc4 Port=Q Net=din_iddr_osc4[1] - Found", " Pin object=clk_out, location: HR_2_8_4P", " Data signal from object clk_out", - " Fail reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", + " Skip reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", " Pin object=clk_out_osc, location: HR_2_9_4N", " Data signal from object clk_out_osc", - " Fail reason: Object clk_out_osc is primitive \\O_SERDES_CLK but data signal is not defined", + " Skip reason: Object clk_out_osc is primitive \\O_SERDES_CLK but data signal is not defined", " Pin object=dinoutosc, location: HR_2_22_11P", " Data signal from object dinoutosc", - " Module=O_BUFT Linked-object=dinoutosc Port=I Net=$obuf_dinoutosc - Found", + " Module=O_BUFT Linked-object=dinoutosc Port=I Net=$f2g_tx_out_$obuf_dinoutosc - Found", " Pin object=dout00, location: HP_1_22_11P", " Data signal from object dout00", - " Module=O_DDR Linked-object=dout00 Port=D Net=$auto_802 - Found", - " Module=O_DDR Linked-object=dout00 Port=D Net=$auto_803 - Found", + " Module=O_DDR Linked-object=dout00 Port=D Net=$f2g_tx_out_din_iddr00[0] - Found", + " Module=O_DDR Linked-object=dout00 Port=D Net=$f2g_tx_out_din_iddr00[1] - Found", " Pin object=dout01, location: HR_1_22_11P", " Data signal from object dout01", - " Module=O_DDR Linked-object=dout01 Port=D Net=$auto_804 - Found", - " Module=O_DDR Linked-object=dout01 Port=D Net=$auto_805 - Found", + " Module=O_DDR Linked-object=dout01 Port=D Net=$f2g_tx_out_din_iddr01[0] - Found", + " Module=O_DDR Linked-object=dout01 Port=D Net=$f2g_tx_out_din_iddr01[1] - Found", " Pin object=dout10, location: ", " Pin location is not assigned", " Pin object=dout11, location: HR_5_4_2P", " Data signal from object dout11", - " Module=O_DDR Linked-object=dout11 Port=D Net=dout_oddr11[0] - Found", - " Module=O_DDR Linked-object=dout11 Port=D Net=dout_oddr11[1] - Found", + " Module=O_DDR Linked-object=dout11 Port=D Net=$f2g_tx_out_dout_oddr11[0] - Found", + " Module=O_DDR Linked-object=dout11 Port=D Net=$f2g_tx_out_dout_oddr11[1] - Found", " Pin object=dout12, location: HR_1_26_13P", " Data signal from object dout12", - " Module=O_DDR Linked-object=dout12 Port=D Net=dout_oddr12[0] - Found", - " Module=O_DDR Linked-object=dout12 Port=D Net=dout_oddr12[1] - Found", + " Module=O_DDR Linked-object=dout12 Port=D Net=$f2g_tx_out_dout_oddr12[0] - Found", + " Module=O_DDR Linked-object=dout12 Port=D Net=$f2g_tx_out_dout_oddr12[1] - Found", " Pin object=dout20, location: ", " Pin location is not assigned", " Pin object=clk30, location: HR_1_CC_38_19P", " Data signal from object clk30", - " Fail reason: Object clk30 is primitive \\PLL but data signal is not defined", + " Skip reason: Object clk30 is primitive \\PLL but data signal is not defined", " Pin object=clk31, location: HR_3_CC_38_19P", " Data signal from object clk31", - " Fail reason: Object clk31 is primitive \\PLL but data signal is not defined", + " Skip reason: Object clk31 is primitive \\PLL but data signal is not defined", " Pin object=clk40, location: HR_2_CC_38_19P", " Data signal from object clk40", - " Module=I_BUF Linked-object=clk40 Port=O Net=$auto_814.ibuf40 - Not found", - " Fail reason: Clock data from object clk40 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk40 Port=O Net=$auto_805.ibuf40 - Not found", + " Skip reason: Clock data from object clk40 port O does not need to route to fabric", " Pin object=din30_n, location: HR_2_1_0N", " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=din30_p, location: HR_2_0_0P", @@ -645,8 +647,8 @@ " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=dout30_p, location: HR_2_4_2P", " Data signal from object dout30_p", - " Module=O_DDR Linked-object=dout30_n+dout30_p Port=D Net=$abc$214$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test_negative/./top.v:380$14_Y[0] - Found", - " Module=O_DDR Linked-object=dout30_n+dout30_p Port=D Net=$abc$214$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test_negative/./top.v:380$14_Y[1] - Found", + " Module=O_DDR Linked-object=dout30_n+dout30_p Port=D Net=$f2g_tx_out_$abc$214$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test_negative/./top.v:380$14_Y[0] - Found", + " Module=O_DDR Linked-object=dout30_n+dout30_p Port=D Net=$f2g_tx_out_$abc$214$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test_negative/./top.v:380$14_Y[1] - Found", " Determine internal control signals", " Module=I_BUF LinkedObject=clk00 Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=PLL LinkedObject=clk00 Location=HP_1_CC_18_9P Port=LOCK Signal=out:TO_BE_DETERMINED", @@ -778,2050 +780,2052 @@ " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din31_n+din31_p Location=HR_2_2_1P Port=R Signal=in:TO_BE_DETERMINED", " Skip reason: TO_BE_DETERMINED", + " Module=O_BUFT_DS LinkedObject=dout30_n+dout30_p Location=HR_2_4_2P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_DDR LinkedObject=dout30_n+dout30_p Location=HR_2_4_2P Port=E Signal=in:TO_BE_DETERMINED", " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout30_n+dout30_p Location=HR_2_4_2P Port=R Signal=in:TO_BE_DETERMINED", " Skip reason: TO_BE_DETERMINED", "End of IO Analysis" ], - "instances" : [ + "instances": [ { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk00", - "location_object" : "clk00", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk00", - "linked_objects" : { - "clk00" : { - "location" : "HP_1_CC_18_9P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk00", + "location_object": "clk00", + "location": "HP_1_CC_18_9P", + "linked_object": "clk00", + "linked_objects": { + "clk00": { + "location": "HP_1_CC_18_9P", + "properties": { } } }, - "connectivity" : { - "I" : "clk00", - "O" : "$ibuf_clk00" + "connectivity": { + "I": "clk00", + "O": "$ibuf_clk00" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf00", - "location_object" : "clk00", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk00", - "linked_objects" : { - "clk00" : { - "location" : "HP_1_CC_18_9P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "0" + "module": "CLK_BUF", + "name": "clk_buf00", + "location_object": "clk00", + "location": "HP_1_CC_18_9P", + "linked_object": "clk00", + "linked_objects": { + "clk00": { + "location": "HP_1_CC_18_9P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "0" } } }, - "connectivity" : { - "I" : "$ibuf_clk00", - "O" : "clkbuf00" + "connectivity": { + "I": "$ibuf_clk00", + "O": "clkbuf00" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "0" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "0" }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ "PLL" ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "i_ddr00" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "PLL", - "name" : "pll00", - "location_object" : "clk00", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk00", - "linked_objects" : { - "clk00" : { - "location" : "HP_1_CC_18_9P", - "properties" : { - "OUT0_ROUTE_TO_FABRIC_CLK" : "1", - "OUT1_ROUTE_TO_FABRIC_CLK" : "2", - "OUT2_ROUTE_TO_FABRIC_CLK" : "3", - "OUT3_ROUTE_TO_FABRIC_CLK" : "4" + "module": "PLL", + "name": "pll00", + "location_object": "clk00", + "location": "HP_1_CC_18_9P", + "linked_object": "clk00", + "linked_objects": { + "clk00": { + "location": "HP_1_CC_18_9P", + "properties": { + "OUT0_ROUTE_TO_FABRIC_CLK": "1", + "OUT1_ROUTE_TO_FABRIC_CLK": "2", + "OUT2_ROUTE_TO_FABRIC_CLK": "3", + "OUT3_ROUTE_TO_FABRIC_CLK": "4" } } }, - "connectivity" : { - "CLK_IN" : "clkbuf00", - "CLK_OUT" : "pll00_clk1", - "CLK_OUT_DIV2" : "pll00_clk2", - "CLK_OUT_DIV3" : "pll00_clk3", - "CLK_OUT_DIV4" : "pll00_clk4" - }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "OUT0_ROUTE_TO_FABRIC_CLK" : "1", - "OUT1_ROUTE_TO_FABRIC_CLK" : "2", - "OUT2_ROUTE_TO_FABRIC_CLK" : "3", - "OUT3_ROUTE_TO_FABRIC_CLK" : "4", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" - }, - "flags" : [ + "connectivity": { + "CLK_IN": "clkbuf00", + "CLK_OUT": "pll00_clk1", + "CLK_OUT_DIV2": "pll00_clk2", + "CLK_OUT_DIV3": "pll00_clk3", + "CLK_OUT_DIV4": "pll00_clk4" + }, + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "1", + "OUT1_ROUTE_TO_FABRIC_CLK": "2", + "OUT2_ROUTE_TO_FABRIC_CLK": "3", + "OUT3_ROUTE_TO_FABRIC_CLK": "4", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" + }, + "flags": [ "PLL" ], - "pre_primitive" : "CLK_BUF", - "post_primitives" : [ + "pre_primitive": "CLK_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_ddr01" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk10", - "location_object" : "clk10", - "location" : "HR_1_CC_18_9P", - "linked_object" : "clk10", - "linked_objects" : { - "clk10" : { - "location" : "HR_1_CC_18_9P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk10", + "location_object": "clk10", + "location": "HR_1_CC_18_9P", + "linked_object": "clk10", + "linked_objects": { + "clk10": { + "location": "HR_1_CC_18_9P", + "properties": { } } }, - "connectivity" : { - "I" : "clk10", - "O" : "$ibuf_clk10" + "connectivity": { + "I": "clk10", + "O": "$ibuf_clk10" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf10", - "location_object" : "clk10", - "location" : "HR_1_CC_18_9P", - "linked_object" : "clk10", - "linked_objects" : { - "clk10" : { - "location" : "HR_1_CC_18_9P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "5" + "module": "CLK_BUF", + "name": "clk_buf10", + "location_object": "clk10", + "location": "HR_1_CC_18_9P", + "linked_object": "clk10", + "linked_objects": { + "clk10": { + "location": "HR_1_CC_18_9P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "5" } } }, - "connectivity" : { - "I" : "$ibuf_clk10", - "O" : "clkbuf10" + "connectivity": { + "I": "$ibuf_clk10", + "O": "clkbuf10" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "5" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "5" }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "i_ddr10", "i_ddr11", "i_ddr12" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk20", - "location_object" : "clk20", - "location" : "HP_1_CC_38_19P", - "linked_object" : "clk20", - "linked_objects" : { - "clk20" : { - "location" : "HP_1_CC_38_19P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk20", + "location_object": "clk20", + "location": "HP_1_CC_38_19P", + "linked_object": "clk20", + "linked_objects": { + "clk20": { + "location": "HP_1_CC_38_19P", + "properties": { } } }, - "connectivity" : { - "I" : "clk20", - "O" : "$ibuf_clk20" + "connectivity": { + "I": "clk20", + "O": "$ibuf_clk20" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "CLK_BUF", - "name" : "$clkbuf$top.$ibuf_clk20", - "location_object" : "clk20", - "location" : "HP_1_CC_38_19P", - "linked_object" : "clk20", - "linked_objects" : { - "clk20" : { - "location" : "HP_1_CC_38_19P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "6" + "module": "CLK_BUF", + "name": "$clkbuf$top.$ibuf_clk20", + "location_object": "clk20", + "location": "HP_1_CC_38_19P", + "linked_object": "clk20", + "linked_objects": { + "clk20": { + "location": "HP_1_CC_38_19P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "6" } } }, - "connectivity" : { - "I" : "$ibuf_clk20", - "O" : "$clk_buf_$ibuf_clk20" + "connectivity": { + "I": "$ibuf_clk20", + "O": "$clk_buf_$ibuf_clk20" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "6" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "6" }, - "flags" : [ + "flags": [ "CLK_BUF", "PIN_CLOCK_CORE_ONLY" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din00", - "location_object" : "din00", - "location" : "HP_1_20_10P", - "linked_object" : "din00", - "linked_objects" : { - "din00" : { - "location" : "HP_1_20_10P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din00", + "location_object": "din00", + "location": "HP_1_20_10P", + "linked_object": "din00", + "linked_objects": { + "din00": { + "location": "HP_1_20_10P", + "properties": { } } }, - "connectivity" : { - "I" : "din00", - "O" : "$ibuf_din00" + "connectivity": { + "I": "din00", + "O": "$ibuf_din00" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr00", - "location_object" : "din00", - "location" : "HP_1_20_10P", - "linked_object" : "din00", - "linked_objects" : { - "din00" : { - "location" : "HP_1_20_10P", - "properties" : { + "module": "I_DDR", + "name": "i_ddr00", + "location_object": "din00", + "location": "HP_1_20_10P", + "linked_object": "din00", + "linked_objects": { + "din00": { + "location": "HP_1_20_10P", + "properties": { } } }, - "connectivity" : { - "C" : "clkbuf00", - "D" : "$ibuf_din00" + "connectivity": { + "C": "clkbuf00", + "D": "$ibuf_din00" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din01", - "location_object" : "din01", - "location" : "HR_1_20_10P", - "linked_object" : "din01", - "linked_objects" : { - "din01" : { - "location" : "HR_1_20_10P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din01", + "location_object": "din01", + "location": "HR_1_20_10P", + "linked_object": "din01", + "linked_objects": { + "din01": { + "location": "HR_1_20_10P", + "properties": { } } }, - "connectivity" : { - "I" : "din01", - "O" : "$ibuf_din01" + "connectivity": { + "I": "din01", + "O": "$ibuf_din01" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr01", - "location_object" : "din01", - "location" : "HR_1_20_10P", - "linked_object" : "din01", - "linked_objects" : { - "din01" : { - "location" : "HR_1_20_10P", - "properties" : { + "module": "I_DDR", + "name": "i_ddr01", + "location_object": "din01", + "location": "HR_1_20_10P", + "linked_object": "din01", + "linked_objects": { + "din01": { + "location": "HR_1_20_10P", + "properties": { } } }, - "connectivity" : { - "C" : "pll00_clk1", - "D" : "$ibuf_din01" + "connectivity": { + "C": "pll00_clk1", + "D": "$ibuf_din01" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din10", - "location_object" : "din10", - "location" : "", - "linked_object" : "din10", - "linked_objects" : { - "din10" : { - "location" : "", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din10", + "location_object": "din10", + "location": "", + "linked_object": "din10", + "linked_objects": { + "din10": { + "location": "", + "properties": { } } }, - "connectivity" : { - "I" : "din10", - "O" : "$ibuf_din10" + "connectivity": { + "I": "din10", + "O": "$ibuf_din10" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr10", - "location_object" : "din10", - "location" : "", - "linked_object" : "din10", - "linked_objects" : { - "din10" : { - "location" : "", - "properties" : { + "module": "I_DDR", + "name": "i_ddr10", + "location_object": "din10", + "location": "", + "linked_object": "din10", + "linked_objects": { + "din10": { + "location": "", + "properties": { } } }, - "connectivity" : { - "C" : "clkbuf10", - "D" : "$ibuf_din10" + "connectivity": { + "C": "clkbuf10", + "D": "$ibuf_din10" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din11", - "location_object" : "din11", - "location" : "HR_5_2_1P", - "linked_object" : "din11", - "linked_objects" : { - "din11" : { - "location" : "HR_5_2_1P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din11", + "location_object": "din11", + "location": "HR_5_2_1P", + "linked_object": "din11", + "linked_objects": { + "din11": { + "location": "HR_5_2_1P", + "properties": { } } }, - "connectivity" : { - "I" : "din11", - "O" : "$ibuf_din11" + "connectivity": { + "I": "din11", + "O": "$ibuf_din11" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr11", - "location_object" : "din11", - "location" : "HR_5_2_1P", - "linked_object" : "din11", - "linked_objects" : { - "din11" : { - "location" : "HR_5_2_1P", - "properties" : { + "module": "I_DDR", + "name": "i_ddr11", + "location_object": "din11", + "location": "HR_5_2_1P", + "linked_object": "din11", + "linked_objects": { + "din11": { + "location": "HR_5_2_1P", + "properties": { } } }, - "connectivity" : { - "C" : "clkbuf10", - "D" : "$ibuf_din11" + "connectivity": { + "C": "clkbuf10", + "D": "$ibuf_din11" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din12", - "location_object" : "din12", - "location" : "HR_1_24_12P", - "linked_object" : "din12", - "linked_objects" : { - "din12" : { - "location" : "HR_1_24_12P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din12", + "location_object": "din12", + "location": "HR_1_24_12P", + "linked_object": "din12", + "linked_objects": { + "din12": { + "location": "HR_1_24_12P", + "properties": { } } }, - "connectivity" : { - "I" : "din12", - "O" : "$ibuf_din12" + "connectivity": { + "I": "din12", + "O": "$ibuf_din12" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr12", - "location_object" : "din12", - "location" : "HR_1_24_12P", - "linked_object" : "din12", - "linked_objects" : { - "din12" : { - "location" : "HR_1_24_12P", - "properties" : { + "module": "I_DDR", + "name": "i_ddr12", + "location_object": "din12", + "location": "HR_1_24_12P", + "linked_object": "din12", + "linked_objects": { + "din12": { + "location": "HR_1_24_12P", + "properties": { } } }, - "connectivity" : { - "C" : "clkbuf10", - "D" : "$ibuf_din12" + "connectivity": { + "C": "clkbuf10", + "D": "$ibuf_din12" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din20", - "location_object" : "din20", - "location" : "", - "linked_object" : "din20", - "linked_objects" : { - "din20" : { - "location" : "", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din20", + "location_object": "din20", + "location": "", + "linked_object": "din20", + "linked_objects": { + "din20": { + "location": "", + "properties": { } } }, - "connectivity" : { - "I" : "din20", - "O" : "$ibuf_din20" + "connectivity": { + "I": "din20", + "O": "$ibuf_din20" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc0", - "location_object" : "dinosc0", - "location" : "HR_2_20_10P", - "linked_object" : "dinosc0", - "linked_objects" : { - "dinosc0" : { - "location" : "HR_2_20_10P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc0", + "location_object": "dinosc0", + "location": "HR_2_20_10P", + "linked_object": "dinosc0", + "linked_objects": { + "dinosc0": { + "location": "HR_2_20_10P", + "properties": { } } }, - "connectivity" : { - "I" : "dinosc0", - "O" : "$ibuf_dinosc0" + "connectivity": { + "I": "dinosc0", + "O": "$ibuf_dinosc0" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc0", - "location_object" : "dinosc0", - "location" : "HR_2_20_10P", - "linked_object" : "dinosc0", - "linked_objects" : { - "dinosc0" : { - "location" : "HR_2_20_10P", - "properties" : { + "module": "I_DDR", + "name": "i_ddr_osc0", + "location_object": "dinosc0", + "location": "HR_2_20_10P", + "linked_object": "dinosc0", + "linked_objects": { + "dinosc0": { + "location": "HR_2_20_10P", + "properties": { } } }, - "connectivity" : { - "C" : "pllosc0_clk0", - "D" : "$ibuf_dinosc0" + "connectivity": { + "C": "pllosc0_clk0", + "D": "$ibuf_dinosc0" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc1", - "location_object" : "dinosc1", - "location" : "HR_5_20_10P", - "linked_object" : "dinosc1", - "linked_objects" : { - "dinosc1" : { - "location" : "HR_5_20_10P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc1", + "location_object": "dinosc1", + "location": "HR_5_20_10P", + "linked_object": "dinosc1", + "linked_objects": { + "dinosc1": { + "location": "HR_5_20_10P", + "properties": { } } }, - "connectivity" : { - "I" : "dinosc1", - "O" : "$ibuf_dinosc1" + "connectivity": { + "I": "dinosc1", + "O": "$ibuf_dinosc1" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc1", - "location_object" : "dinosc1", - "location" : "HR_5_20_10P", - "linked_object" : "dinosc1", - "linked_objects" : { - "dinosc1" : { - "location" : "HR_5_20_10P", - "properties" : { + "module": "I_DDR", + "name": "i_ddr_osc1", + "location_object": "dinosc1", + "location": "HR_5_20_10P", + "linked_object": "dinosc1", + "linked_objects": { + "dinosc1": { + "location": "HR_5_20_10P", + "properties": { } } }, - "connectivity" : { - "C" : "pllosc0_clk0", - "D" : "$ibuf_dinosc1" + "connectivity": { + "C": "pllosc0_clk0", + "D": "$ibuf_dinosc1" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc2", - "location_object" : "dinosc2", - "location" : "", - "linked_object" : "dinosc2", - "linked_objects" : { - "dinosc2" : { - "location" : "", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc2", + "location_object": "dinosc2", + "location": "", + "linked_object": "dinosc2", + "linked_objects": { + "dinosc2": { + "location": "", + "properties": { } } }, - "connectivity" : { - "I" : "dinosc2", - "O" : "$ibuf_dinosc2" + "connectivity": { + "I": "dinosc2", + "O": "$ibuf_dinosc2" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc2", - "location_object" : "dinosc2", - "location" : "", - "linked_object" : "dinosc2", - "linked_objects" : { - "dinosc2" : { - "location" : "", - "properties" : { + "module": "I_DDR", + "name": "i_ddr_osc2", + "location_object": "dinosc2", + "location": "", + "linked_object": "dinosc2", + "linked_objects": { + "dinosc2": { + "location": "", + "properties": { } } }, - "connectivity" : { - "C" : "pllosc0_clk0", - "D" : "$ibuf_dinosc2" + "connectivity": { + "C": "pllosc0_clk0", + "D": "$ibuf_dinosc2" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc3", - "location_object" : "dinosc3", - "location" : "HR_5_22_11P", - "linked_object" : "dinosc3", - "linked_objects" : { - "dinosc3" : { - "location" : "HR_5_22_11P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc3", + "location_object": "dinosc3", + "location": "HR_5_22_11P", + "linked_object": "dinosc3", + "linked_objects": { + "dinosc3": { + "location": "HR_5_22_11P", + "properties": { } } }, - "connectivity" : { - "I" : "dinosc3", - "O" : "$ibuf_dinosc3" + "connectivity": { + "I": "dinosc3", + "O": "$ibuf_dinosc3" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc3", - "location_object" : "dinosc3", - "location" : "HR_5_22_11P", - "linked_object" : "dinosc3", - "linked_objects" : { - "dinosc3" : { - "location" : "HR_5_22_11P", - "properties" : { + "module": "I_DDR", + "name": "i_ddr_osc3", + "location_object": "dinosc3", + "location": "HR_5_22_11P", + "linked_object": "dinosc3", + "linked_objects": { + "dinosc3": { + "location": "HR_5_22_11P", + "properties": { } } }, - "connectivity" : { - "C" : "pllosc1_clk1", - "D" : "$ibuf_dinosc3" + "connectivity": { + "C": "pllosc1_clk1", + "D": "$ibuf_dinosc3" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_dinosc4", - "location_object" : "dinosc4", - "location" : "HR_1_30_15P", - "linked_object" : "dinosc4", - "linked_objects" : { - "dinosc4" : { - "location" : "HR_1_30_15P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_dinosc4", + "location_object": "dinosc4", + "location": "HR_1_30_15P", + "linked_object": "dinosc4", + "linked_objects": { + "dinosc4": { + "location": "HR_1_30_15P", + "properties": { } } }, - "connectivity" : { - "I" : "dinosc4", - "O" : "$ibuf_dinosc4" + "connectivity": { + "I": "dinosc4", + "O": "$ibuf_dinosc4" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr_osc4", - "location_object" : "dinosc4", - "location" : "HR_1_30_15P", - "linked_object" : "dinosc4", - "linked_objects" : { - "dinosc4" : { - "location" : "HR_1_30_15P", - "properties" : { + "module": "I_DDR", + "name": "i_ddr_osc4", + "location_object": "dinosc4", + "location": "HR_1_30_15P", + "linked_object": "dinosc4", + "linked_objects": { + "dinosc4": { + "location": "HR_1_30_15P", + "properties": { } } }, - "connectivity" : { - "C" : "pllosc2_clk0", - "D" : "$ibuf_dinosc4" + "connectivity": { + "C": "pllosc2_clk0", + "D": "$ibuf_dinosc4" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_clk_out", - "location_object" : "clk_out", - "location" : "HR_2_8_4P", - "linked_object" : "clk_out", - "linked_objects" : { - "clk_out" : { - "location" : "HR_2_8_4P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_clk_out", + "location_object": "clk_out", + "location": "HR_2_8_4P", + "linked_object": "clk_out", + "linked_objects": { + "clk_out": { + "location": "HR_2_8_4P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_clk_out", - "O" : "clk_out" + "connectivity": { + "I": "$obuf_clk_out", + "O": "clk_out" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_SERDES_CLK" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_SERDES_CLK", - "name" : "o_serdes_clk", - "location_object" : "clk_out", - "location" : "HR_2_8_4P", - "linked_object" : "clk_out", - "linked_objects" : { - "clk_out" : { - "location" : "HR_2_8_4P", - "properties" : { + "module": "O_SERDES_CLK", + "name": "o_serdes_clk", + "location_object": "clk_out", + "location": "HR_2_8_4P", + "linked_object": "clk_out", + "linked_objects": { + "clk_out": { + "location": "HR_2_8_4P", + "properties": { } } }, - "connectivity" : { - "OUTPUT_CLK" : "$obuf_clk_out", - "PLL_CLK" : "clkbuf40" + "connectivity": { + "OUTPUT_CLK": "$obuf_clk_out", + "PLL_CLK": "clkbuf40" }, - "parameters" : { - "CLOCK_PHASE" : "270", - "DATA_RATE" : "SDR" + "parameters": { + "CLOCK_PHASE": "270", + "DATA_RATE": "SDR" }, - "flags" : [ + "flags": [ "O_SERDES_CLK" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_clk_out_osc", - "location_object" : "clk_out_osc", - "location" : "HR_2_9_4N", - "linked_object" : "clk_out_osc", - "linked_objects" : { - "clk_out_osc" : { - "location" : "HR_2_9_4N", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_clk_out_osc", + "location_object": "clk_out_osc", + "location": "HR_2_9_4N", + "linked_object": "clk_out_osc", + "linked_objects": { + "clk_out_osc": { + "location": "HR_2_9_4N", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_clk_out_osc", - "O" : "clk_out_osc" + "connectivity": { + "I": "$obuf_clk_out_osc", + "O": "clk_out_osc" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_SERDES_CLK" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_SERDES_CLK", - "name" : "o_serdes_clk_osc", - "location_object" : "clk_out_osc", - "location" : "HR_2_9_4N", - "linked_object" : "clk_out_osc", - "linked_objects" : { - "clk_out_osc" : { - "location" : "HR_2_9_4N", - "properties" : { + "module": "O_SERDES_CLK", + "name": "o_serdes_clk_osc", + "location_object": "clk_out_osc", + "location": "HR_2_9_4N", + "linked_object": "clk_out_osc", + "linked_objects": { + "clk_out_osc": { + "location": "HR_2_9_4N", + "properties": { } } }, - "connectivity" : { - "OUTPUT_CLK" : "$obuf_clk_out_osc", - "PLL_CLK" : "osc" + "connectivity": { + "OUTPUT_CLK": "$obuf_clk_out_osc", + "PLL_CLK": "osc" }, - "parameters" : { - "CLOCK_PHASE" : "180", - "DATA_RATE" : "DDR" + "parameters": { + "CLOCK_PHASE": "180", + "DATA_RATE": "DDR" }, - "flags" : [ + "flags": [ "O_SERDES_CLK" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ "\\O_SERDES_CLK \\o_serdes_clk_osc fast clock port \\PLL_CLK (net: \\osc) is not routable" ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dinoutosc", - "location_object" : "dinoutosc", - "location" : "HR_2_22_11P", - "linked_object" : "dinoutosc", - "linked_objects" : { - "dinoutosc" : { - "location" : "HR_2_22_11P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dinoutosc", + "location_object": "dinoutosc", + "location": "HR_2_22_11P", + "linked_object": "dinoutosc", + "linked_objects": { + "dinoutosc": { + "location": "HR_2_22_11P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dinoutosc", - "O" : "dinoutosc" + "connectivity": { + "I": "$f2g_tx_out_$obuf_dinoutosc", + "O": "dinoutosc" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout00", - "location_object" : "dout00", - "location" : "HP_1_22_11P", - "linked_object" : "dout00", - "linked_objects" : { - "dout00" : { - "location" : "HP_1_22_11P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout00", + "location_object": "dout00", + "location": "HP_1_22_11P", + "linked_object": "dout00", + "linked_objects": { + "dout00": { + "location": "HP_1_22_11P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout00", - "O" : "dout00" + "connectivity": { + "I": "$obuf_dout00", + "O": "dout00" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_DDR", - "name" : "o_ddr00", - "location_object" : "dout00", - "location" : "HP_1_22_11P", - "linked_object" : "dout00", - "linked_objects" : { - "dout00" : { - "location" : "HP_1_22_11P", - "properties" : { + "module": "O_DDR", + "name": "o_ddr00", + "location_object": "dout00", + "location": "HP_1_22_11P", + "linked_object": "dout00", + "linked_objects": { + "dout00": { + "location": "HP_1_22_11P", + "properties": { } } }, - "connectivity" : { - "C" : "clkbuf00", - "Q" : "$obuf_dout00" + "connectivity": { + "C": "clkbuf00", + "Q": "$obuf_dout00" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout01", - "location_object" : "dout01", - "location" : "HR_1_22_11P", - "linked_object" : "dout01", - "linked_objects" : { - "dout01" : { - "location" : "HR_1_22_11P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout01", + "location_object": "dout01", + "location": "HR_1_22_11P", + "linked_object": "dout01", + "linked_objects": { + "dout01": { + "location": "HR_1_22_11P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout01", - "O" : "dout01" + "connectivity": { + "I": "$obuf_dout01", + "O": "dout01" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_DDR", - "name" : "o_ddr01", - "location_object" : "dout01", - "location" : "HR_1_22_11P", - "linked_object" : "dout01", - "linked_objects" : { - "dout01" : { - "location" : "HR_1_22_11P", - "properties" : { + "module": "O_DDR", + "name": "o_ddr01", + "location_object": "dout01", + "location": "HR_1_22_11P", + "linked_object": "dout01", + "linked_objects": { + "dout01": { + "location": "HR_1_22_11P", + "properties": { } } }, - "connectivity" : { - "C" : "pll00_clk1", - "Q" : "$obuf_dout01" + "connectivity": { + "C": "pll00_clk1", + "Q": "$obuf_dout01" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout10", - "location_object" : "dout10", - "location" : "", - "linked_object" : "dout10", - "linked_objects" : { - "dout10" : { - "location" : "", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout10", + "location_object": "dout10", + "location": "", + "linked_object": "dout10", + "linked_objects": { + "dout10": { + "location": "", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout10", - "O" : "dout10" + "connectivity": { + "I": "$obuf_dout10", + "O": "dout10" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_DDR", - "name" : "o_ddr10", - "location_object" : "dout10", - "location" : "", - "linked_object" : "dout10", - "linked_objects" : { - "dout10" : { - "location" : "", - "properties" : { + "module": "O_DDR", + "name": "o_ddr10", + "location_object": "dout10", + "location": "", + "linked_object": "dout10", + "linked_objects": { + "dout10": { + "location": "", + "properties": { } } }, - "connectivity" : { - "C" : "clkbuf10", - "Q" : "$obuf_dout10" + "connectivity": { + "C": "clkbuf10", + "Q": "$obuf_dout10" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout11", - "location_object" : "dout11", - "location" : "HR_5_4_2P", - "linked_object" : "dout11", - "linked_objects" : { - "dout11" : { - "location" : "HR_5_4_2P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout11", + "location_object": "dout11", + "location": "HR_5_4_2P", + "linked_object": "dout11", + "linked_objects": { + "dout11": { + "location": "HR_5_4_2P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout11", - "O" : "dout11" + "connectivity": { + "I": "$obuf_dout11", + "O": "dout11" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_DDR", - "name" : "o_ddr11", - "location_object" : "dout11", - "location" : "HR_5_4_2P", - "linked_object" : "dout11", - "linked_objects" : { - "dout11" : { - "location" : "HR_5_4_2P", - "properties" : { + "module": "O_DDR", + "name": "o_ddr11", + "location_object": "dout11", + "location": "HR_5_4_2P", + "linked_object": "dout11", + "linked_objects": { + "dout11": { + "location": "HR_5_4_2P", + "properties": { } } }, - "connectivity" : { - "C" : "clkbuf10", - "Q" : "$obuf_dout11" + "connectivity": { + "C": "clkbuf10", + "Q": "$obuf_dout11" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout12", - "location_object" : "dout12", - "location" : "HR_1_26_13P", - "linked_object" : "dout12", - "linked_objects" : { - "dout12" : { - "location" : "HR_1_26_13P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout12", + "location_object": "dout12", + "location": "HR_1_26_13P", + "linked_object": "dout12", + "linked_objects": { + "dout12": { + "location": "HR_1_26_13P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout12", - "O" : "dout12" + "connectivity": { + "I": "$obuf_dout12", + "O": "dout12" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_DDR", - "name" : "o_ddr12", - "location_object" : "dout12", - "location" : "HR_1_26_13P", - "linked_object" : "dout12", - "linked_objects" : { - "dout12" : { - "location" : "HR_1_26_13P", - "properties" : { + "module": "O_DDR", + "name": "o_ddr12", + "location_object": "dout12", + "location": "HR_1_26_13P", + "linked_object": "dout12", + "linked_objects": { + "dout12": { + "location": "HR_1_26_13P", + "properties": { } } }, - "connectivity" : { - "C" : "clkbuf10", - "Q" : "$obuf_dout12" + "connectivity": { + "C": "clkbuf10", + "Q": "$obuf_dout12" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout20", - "location_object" : "dout20", - "location" : "", - "linked_object" : "dout20", - "linked_objects" : { - "dout20" : { - "location" : "", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout20", + "location_object": "dout20", + "location": "", + "linked_object": "dout20", + "linked_objects": { + "dout20": { + "location": "", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout20", - "O" : "dout20" + "connectivity": { + "I": "$f2g_tx_out_$obuf_dout20", + "O": "dout20" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "BOOT_CLOCK", - "name" : "boot_clock", - "location_object" : "BOOT_CLOCK#0", - "location" : "", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "", - "properties" : { + "module": "BOOT_CLOCK", + "name": "boot_clock", + "location_object": "BOOT_CLOCK#0", + "location": "", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "", + "properties": { } } }, - "connectivity" : { - "O" : "osc" + "connectivity": { + "O": "osc" }, - "parameters" : { - "PERIOD" : "25" + "parameters": { + "PERIOD": "25" }, - "flags" : [ + "flags": [ "BOOT_CLOCK" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "PLL", "PLL", "PLL" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "PLL", - "name" : "pllosc0", - "location_object" : "BOOT_CLOCK#0", - "location" : "", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "", - "properties" : { + "module": "PLL", + "name": "pllosc0", + "location_object": "BOOT_CLOCK#0", + "location": "", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "", + "properties": { } } }, - "connectivity" : { - "CLK_IN" : "osc", - "CLK_OUT" : "pllosc0_clk0" + "connectivity": { + "CLK_IN": "osc", + "CLK_OUT": "pllosc0_clk0" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "BOOT_CLOCK", - "post_primitives" : [ + "pre_primitive": "BOOT_CLOCK", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_ddr_osc0", "i_ddr_osc1", "i_ddr_osc2" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "PLL", - "name" : "pllosc1", - "location_object" : "BOOT_CLOCK#0", - "location" : "", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "", - "properties" : { + "module": "PLL", + "name": "pllosc1", + "location_object": "BOOT_CLOCK#0", + "location": "", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "", + "properties": { } } }, - "connectivity" : { - "CLK_IN" : "osc", - "CLK_OUT_DIV2" : "pllosc1_clk1" + "connectivity": { + "CLK_IN": "osc", + "CLK_OUT_DIV2": "pllosc1_clk1" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "BOOT_CLOCK", - "post_primitives" : [ + "pre_primitive": "BOOT_CLOCK", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT_DIV2" : [ + "route_clock_to": { + "CLK_OUT_DIV2": [ "i_ddr_osc3" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "PLL", - "name" : "pllosc2", - "location_object" : "BOOT_CLOCK#0", - "location" : "", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "", - "properties" : { + "module": "PLL", + "name": "pllosc2", + "location_object": "BOOT_CLOCK#0", + "location": "", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "", + "properties": { } } }, - "connectivity" : { - "CLK_IN" : "osc", - "CLK_OUT" : "pllosc2_clk0" + "connectivity": { + "CLK_IN": "osc", + "CLK_OUT": "pllosc2_clk0" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "BOOT_CLOCK", - "post_primitives" : [ + "pre_primitive": "BOOT_CLOCK", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_ddr_osc4" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "i_buf30", - "location_object" : "clk30", - "location" : "HR_1_CC_38_19P", - "linked_object" : "clk30", - "linked_objects" : { - "clk30" : { - "location" : "HR_1_CC_38_19P", - "properties" : { + "module": "I_BUF", + "name": "i_buf30", + "location_object": "clk30", + "location": "HR_1_CC_38_19P", + "linked_object": "clk30", + "linked_objects": { + "clk30": { + "location": "HR_1_CC_38_19P", + "properties": { } } }, - "connectivity" : { - "I" : "clk30", - "O" : "ibuf30" + "connectivity": { + "I": "clk30", + "O": "ibuf30" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf30", - "location_object" : "clk30", - "location" : "HR_1_CC_38_19P", - "linked_object" : "clk30", - "linked_objects" : { - "clk30" : { - "location" : "HR_1_CC_38_19P", - "properties" : { + "module": "CLK_BUF", + "name": "clk_buf30", + "location_object": "clk30", + "location": "HR_1_CC_38_19P", + "linked_object": "clk30", + "linked_objects": { + "clk30": { + "location": "HR_1_CC_38_19P", + "properties": { } } }, - "connectivity" : { - "I" : "ibuf30", - "O" : "clkbuf30" + "connectivity": { + "I": "ibuf30", + "O": "clkbuf30" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ "PLL" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "PLL", - "name" : "pll30", - "location_object" : "clk30", - "location" : "HR_1_CC_38_19P", - "linked_object" : "clk30", - "linked_objects" : { - "clk30" : { - "location" : "HR_1_CC_38_19P", - "properties" : { + "module": "PLL", + "name": "pll30", + "location_object": "clk30", + "location": "HR_1_CC_38_19P", + "linked_object": "clk30", + "linked_objects": { + "clk30": { + "location": "HR_1_CC_38_19P", + "properties": { } } }, - "connectivity" : { - "CLK_IN" : "clkbuf30", - "CLK_OUT" : "pll30_clk" + "connectivity": { + "CLK_IN": "clkbuf30", + "FAST_CLK": "pll30_clk" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "CLK_BUF", - "post_primitives" : [ + "pre_primitive": "CLK_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "FAST_CLK": [ "i_ddr30" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "i_buf31", - "location_object" : "clk31", - "location" : "HR_3_CC_38_19P", - "linked_object" : "clk31", - "linked_objects" : { - "clk31" : { - "location" : "HR_3_CC_38_19P", - "properties" : { + "module": "I_BUF", + "name": "i_buf31", + "location_object": "clk31", + "location": "HR_3_CC_38_19P", + "linked_object": "clk31", + "linked_objects": { + "clk31": { + "location": "HR_3_CC_38_19P", + "properties": { } } }, - "connectivity" : { - "I" : "clk31", - "O" : "ibuf31" + "connectivity": { + "I": "clk31", + "O": "ibuf31" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf31", - "location_object" : "clk31", - "location" : "HR_3_CC_38_19P", - "linked_object" : "clk31", - "linked_objects" : { - "clk31" : { - "location" : "HR_3_CC_38_19P", - "properties" : { + "module": "CLK_BUF", + "name": "clk_buf31", + "location_object": "clk31", + "location": "HR_3_CC_38_19P", + "linked_object": "clk31", + "linked_objects": { + "clk31": { + "location": "HR_3_CC_38_19P", + "properties": { } } }, - "connectivity" : { - "I" : "ibuf31", - "O" : "clkbuf31" + "connectivity": { + "I": "ibuf31", + "O": "clkbuf31" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ "PLL" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "PLL", - "name" : "pll31", - "location_object" : "clk31", - "location" : "HR_3_CC_38_19P", - "linked_object" : "clk31", - "linked_objects" : { - "clk31" : { - "location" : "HR_3_CC_38_19P", - "properties" : { - "OUT0_ROUTE_TO_FABRIC_CLK" : "7" + "module": "PLL", + "name": "pll31", + "location_object": "clk31", + "location": "HR_3_CC_38_19P", + "linked_object": "clk31", + "linked_objects": { + "clk31": { + "location": "HR_3_CC_38_19P", + "properties": { + "OUT0_ROUTE_TO_FABRIC_CLK": "7" } } }, - "connectivity" : { - "CLK_IN" : "clkbuf31", - "CLK_OUT" : "pll31_clk" + "connectivity": { + "CLK_IN": "clkbuf31", + "CLK_OUT": "pll31_clk" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "OUT0_ROUTE_TO_FABRIC_CLK" : "7", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "7", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "CLK_BUF", - "post_primitives" : [ + "pre_primitive": "CLK_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_ddr31" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "i_buf40", - "location_object" : "clk40", - "location" : "HR_2_CC_38_19P", - "linked_object" : "clk40", - "linked_objects" : { - "clk40" : { - "location" : "HR_2_CC_38_19P", - "properties" : { + "module": "I_BUF", + "name": "i_buf40", + "location_object": "clk40", + "location": "HR_2_CC_38_19P", + "linked_object": "clk40", + "linked_objects": { + "clk40": { + "location": "HR_2_CC_38_19P", + "properties": { } } }, - "connectivity" : { - "I" : "clk40", - "O" : "ibuf40" + "connectivity": { + "I": "clk40", + "O": "ibuf40" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf40", - "location_object" : "clk40", - "location" : "HR_2_CC_38_19P", - "linked_object" : "clk40", - "linked_objects" : { - "clk40" : { - "location" : "HR_2_CC_38_19P", - "properties" : { + "module": "CLK_BUF", + "name": "clk_buf40", + "location_object": "clk40", + "location": "HR_2_CC_38_19P", + "linked_object": "clk40", + "linked_objects": { + "clk40": { + "location": "HR_2_CC_38_19P", + "properties": { } } }, - "connectivity" : { - "I" : "ibuf40", - "O" : "clkbuf40" + "connectivity": { + "I": "ibuf40", + "O": "clkbuf40" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "o_serdes_clk" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF_DS", - "name" : "i_buf_ds30", - "location_object" : "din30_p", - "location" : "HR_2_0_0P", - "linked_object" : "din30_n+din30_p", - "linked_objects" : { - "din30_n" : { - "location" : "HR_2_1_0N", - "properties" : { + "module": "I_BUF_DS", + "name": "i_buf_ds30", + "location_object": "din30_p", + "location": "HR_2_0_0P", + "linked_object": "din30_n+din30_p", + "linked_objects": { + "din30_n": { + "location": "HR_2_1_0N", + "properties": { } }, - "din30_p" : { - "location" : "HR_2_0_0P", - "properties" : { + "din30_p": { + "location": "HR_2_0_0P", + "properties": { } } }, - "connectivity" : { - "I_N" : "din30_n", - "I_P" : "din30_p", - "O" : "din30_ds" + "connectivity": { + "I_N": "din30_n", + "I_P": "din30_p", + "O": "din30_ds" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT", - "WEAK_KEEPER" : "NONE" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr30", - "location_object" : "din30_p", - "location" : "HR_2_0_0P", - "linked_object" : "din30_n+din30_p", - "linked_objects" : { - "din30_n" : { - "location" : "HR_2_1_0N", - "properties" : { + "module": "I_DDR", + "name": "i_ddr30", + "location_object": "din30_p", + "location": "HR_2_0_0P", + "linked_object": "din30_n+din30_p", + "linked_objects": { + "din30_n": { + "location": "HR_2_1_0N", + "properties": { } }, - "din30_p" : { - "location" : "HR_2_0_0P", - "properties" : { + "din30_p": { + "location": "HR_2_0_0P", + "properties": { } } }, - "connectivity" : { - "C" : "pll30_clk", - "D" : "din30_ds" + "connectivity": { + "C": "pll30_clk", + "D": "din30_ds" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF_DS", - "post_primitives" : [ + "pre_primitive": "I_BUF_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF_DS", - "name" : "i_buf_ds31", - "location_object" : "din31_p", - "location" : "HR_2_2_1P", - "linked_object" : "din31_n+din31_p", - "linked_objects" : { - "din31_n" : { - "location" : "HR_2_3_1N", - "properties" : { + "module": "I_BUF_DS", + "name": "i_buf_ds31", + "location_object": "din31_p", + "location": "HR_2_2_1P", + "linked_object": "din31_n+din31_p", + "linked_objects": { + "din31_n": { + "location": "HR_2_3_1N", + "properties": { } }, - "din31_p" : { - "location" : "HR_2_2_1P", - "properties" : { + "din31_p": { + "location": "HR_2_2_1P", + "properties": { } } }, - "connectivity" : { - "I_N" : "din31_n", - "I_P" : "din31_p", - "O" : "din31_ds" + "connectivity": { + "I_N": "din31_n", + "I_P": "din31_p", + "O": "din31_ds" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT", - "WEAK_KEEPER" : "NONE" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr31", - "location_object" : "din31_p", - "location" : "HR_2_2_1P", - "linked_object" : "din31_n+din31_p", - "linked_objects" : { - "din31_n" : { - "location" : "HR_2_3_1N", - "properties" : { + "module": "I_DDR", + "name": "i_ddr31", + "location_object": "din31_p", + "location": "HR_2_2_1P", + "linked_object": "din31_n+din31_p", + "linked_objects": { + "din31_n": { + "location": "HR_2_3_1N", + "properties": { } }, - "din31_p" : { - "location" : "HR_2_2_1P", - "properties" : { + "din31_p": { + "location": "HR_2_2_1P", + "properties": { } } }, - "connectivity" : { - "C" : "pll31_clk", - "D" : "din31_ds" + "connectivity": { + "C": "pll31_clk", + "D": "din31_ds" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF_DS", - "post_primitives" : [ + "pre_primitive": "I_BUF_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUF_DS", - "name" : "o_buf_ds", - "location_object" : "dout30_p", - "location" : "HR_2_4_2P", - "linked_object" : "dout30_n+dout30_p", - "linked_objects" : { - "dout30_n" : { - "location" : "HR_2_7_3N", - "properties" : { + "module": "O_BUFT_DS", + "name": "o_buf_ds", + "location_object": "dout30_p", + "location": "HR_2_4_2P", + "linked_object": "dout30_n+dout30_p", + "linked_objects": { + "dout30_n": { + "location": "HR_2_7_3N", + "properties": { } }, - "dout30_p" : { - "location" : "HR_2_4_2P", - "properties" : { + "dout30_p": { + "location": "HR_2_4_2P", + "properties": { } } }, - "connectivity" : { - "I" : "dout_oddr3x", - "O_N" : "dout30_n", - "O_P" : "dout30_p" + "connectivity": { + "I": "dout_oddr3x", + "O_N": "dout30_n", + "O_P": "dout30_p" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ - "O_BUF_DS" + "flags": [ + "O_BUFT_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_DDR", - "name" : "o_ddr3x", - "location_object" : "dout30_p", - "location" : "HR_2_4_2P", - "linked_object" : "dout30_n+dout30_p", - "linked_objects" : { - "dout30_n" : { - "location" : "HR_2_7_3N", - "properties" : { + "module": "O_DDR", + "name": "o_ddr3x", + "location_object": "dout30_p", + "location": "HR_2_4_2P", + "linked_object": "dout30_n+dout30_p", + "linked_objects": { + "dout30_n": { + "location": "HR_2_7_3N", + "properties": { } }, - "dout30_p" : { - "location" : "HR_2_4_2P", - "properties" : { + "dout30_p": { + "location": "HR_2_4_2P", + "properties": { } } }, - "connectivity" : { - "C" : "pll31_clk", - "Q" : "dout_oddr3x" + "connectivity": { + "C": "pll31_clk", + "Q": "dout_oddr3x" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUF_DS", - "post_primitives" : [ + "pre_primitive": "O_BUFT_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] } ] diff --git a/tests/unittest/ModelConfig/model_config_netlist.ppdb.json b/tests/unittest/ModelConfig/model_config_netlist.ppdb.json index 2551720a9..802c02882 100644 --- a/tests/unittest/ModelConfig/model_config_netlist.ppdb.json +++ b/tests/unittest/ModelConfig/model_config_netlist.ppdb.json @@ -1,5 +1,6 @@ { - "messages" : [ + "status": true, + "messages": [ "Start of IO Analysis", " Get Ports", " Detect input port \\clk0 (index=0, width=1, offset=0)", @@ -108,17 +109,19 @@ " Parameter \\IOSTANDARD: \"DEFAULT\"", " Parameter \\WEAK_KEEPER: \"NONE\"", " Data Width: -2", - " Get important connection of cell \\O_BUF_DS \\o_buf_ds", + " Get important connection of cell \\O_BUFT_DS \\o_buf_ds", " Cell port \\O_N is connected to output port \\dout_n", " Cell port \\O_P is connected to output port \\dout_p", " Parameter \\DIFFERENTIAL_TERMINATION: \"TRUE\"", " Parameter \\IOSTANDARD: \"DEFAULT\"", + " Parameter \\WEAK_KEEPER: \"NONE\"", " Data Width: -2", - " Get important connection of cell \\O_BUF_DS \\o_buf_ds_osc", + " Get important connection of cell \\O_BUFT_DS \\o_buf_ds_osc", " Cell port \\O_N is connected to output port \\dout_osc_n", " Cell port \\O_P is connected to output port \\dout_osc_p", " Parameter \\DIFFERENTIAL_TERMINATION: \"TRUE\"", " Parameter \\IOSTANDARD: \"DEFAULT\"", + " Parameter \\WEAK_KEEPER: \"NONE\"", " Data Width: -2", " Trace \\I_BUF --> \\CLK_BUF", " Try \\I_BUF $ibuf$top.$ibuf_clk0 out connection: $ibuf_clk0 -> $clkbuf$top.$ibuf_clk0", @@ -189,15 +192,15 @@ " Data Width: 8", " Trace \\O_BUF_DS --> \\O_DELAY", " Trace \\O_BUF_DS --> \\O_DDR", - " Try \\O_BUF_DS \\o_buf_ds out connection: \\o_buf_ds_i -> \\o_ddr", + " Trace \\O_BUF_DS --> \\O_SERDES", + " Trace \\O_BUFT_DS --> \\O_DELAY", + " Trace \\O_BUFT_DS --> \\O_DDR", + " Try \\O_BUFT_DS \\o_buf_ds out connection: \\o_buf_ds_i -> \\o_ddr", " Connected \\o_ddr", " Data Width: -2", - " Try \\O_BUF_DS \\o_buf_ds_osc out connection: \\o_buf_ds_i_osc -> \\o_ddr_osc", + " Try \\O_BUFT_DS \\o_buf_ds_osc out connection: \\o_buf_ds_i_osc -> \\o_ddr_osc", " Connected \\o_ddr_osc", " Data Width: -2", - " Trace \\O_BUF_DS --> \\O_SERDES", - " Trace \\O_BUFT_DS --> \\O_DELAY", - " Trace \\O_BUFT_DS --> \\O_DDR", " Trace \\O_BUFT_DS --> \\O_SERDES", " Trace \\O_DELAY --> \\O_DDR", " Trace \\O_DELAY --> \\O_SERDES", @@ -329,8 +332,8 @@ " OUT | * O_BUFT * dout_serdes_clk_out |", " IN | BOOT_CLOCK#0 * BOOT_CLOCK |-> PLL * |", " IN | din_n+din_p * I_BUF_DS |-> I_DDR * |", - " OUT | * O_DDR |-> O_BUF_DS * dout_n+dout_p |", - " OUT | * O_DDR |-> O_BUF_DS * dout_osc_n+dout_osc_p |", + " OUT | * O_DDR |-> O_BUFT_DS * dout_n+dout_p |", + " OUT | * O_DDR |-> O_BUFT_DS * dout_osc_n+dout_osc_p |", " IN | FABRIC_CLKBUF#0 * FCLK_BUF * |", " | *********************************************************** |", " |------------------------------------------------------------------------------------------------------|", @@ -365,15 +368,15 @@ " Determine data signals", " Pin object=clk0, location: HR_1_CC_18_9P", " Data signal from object clk0", - " Module=I_BUF Linked-object=clk0 Port=O Net=$flatten$auto_562.$ibuf_clk0 - Not found", - " Fail reason: Clock data from object clk0 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk0 Port=O Net=$flatten$auto_541.$ibuf_clk0 - Not found", + " Skip reason: Clock data from object clk0 port O does not need to route to fabric", " Pin object=clk1, location: HP_1_CC_18_9P", " Data signal from object clk1", - " Fail reason: Object clk1 is primitive \\PLL but data signal is not defined", + " Skip reason: Object clk1 is primitive \\PLL but data signal is not defined", " Pin object=clk2, location: HR_5_CC_38_19P", " Data signal from object clk2", - " Module=I_BUF Linked-object=clk2 Port=O Net=$flatten$auto_562.$ibuf_clk2 - Not found", - " Fail reason: Clock data from object clk2 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk2 Port=O Net=$flatten$auto_541.$ibuf_clk2 - Not found", + " Skip reason: Clock data from object clk2 port O does not need to route to fabric", " Pin object=din, location: HP_1_20_10P", " Data signal from object din", " Module=I_DELAY Linked-object=din Port=O Net=din_delay - Found", @@ -400,44 +403,44 @@ " Module=I_BUF Linked-object=reset Port=O Net=$ibuf_reset - Found", " Pin object=clk_out, location: HR_2_4_2P", " Data signal from object clk_out", - " Fail reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", + " Skip reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", " Pin object=delay_tap[0], location: HR_2_20_10P", " Data signal from object delay_tap[0]", - " Module=O_BUFT Linked-object=delay_tap[0] Port=I Net=$obuf_delay_tap[0] - Found", + " Module=O_BUFT Linked-object=delay_tap[0] Port=I Net=$f2g_tx_out_$obuf_delay_tap[0] - Found", " Pin object=delay_tap[1], location: HR_2_22_11P", " Data signal from object delay_tap[1]", - " Module=O_BUFT Linked-object=delay_tap[1] Port=I Net=$obuf_delay_tap[1] - Found", + " Module=O_BUFT Linked-object=delay_tap[1] Port=I Net=$f2g_tx_out_$obuf_delay_tap[1] - Found", " Pin object=delay_tap[2], location: HR_2_24_12P", " Data signal from object delay_tap[2]", - " Module=O_BUFT Linked-object=delay_tap[2] Port=I Net=$obuf_delay_tap[2] - Found", + " Module=O_BUFT Linked-object=delay_tap[2] Port=I Net=$f2g_tx_out_$obuf_delay_tap[2] - Found", " Pin object=delay_tap[3], location: HR_2_26_13P", " Data signal from object delay_tap[3]", - " Module=O_BUFT Linked-object=delay_tap[3] Port=I Net=$obuf_delay_tap[3] - Found", + " Module=O_BUFT Linked-object=delay_tap[3] Port=I Net=$f2g_tx_out_$obuf_delay_tap[3] - Found", " Pin object=delay_tap[4], location: HR_2_28_14P", " Data signal from object delay_tap[4]", - " Module=O_BUFT Linked-object=delay_tap[4] Port=I Net=$obuf_delay_tap[4] - Found", + " Module=O_BUFT Linked-object=delay_tap[4] Port=I Net=$f2g_tx_out_$obuf_delay_tap[4] - Found", " Pin object=delay_tap[5], location: HR_2_30_15P", " Data signal from object delay_tap[5]", - " Module=O_BUFT Linked-object=delay_tap[5] Port=I Net=$obuf_delay_tap[5] - Found", + " Module=O_BUFT Linked-object=delay_tap[5] Port=I Net=$f2g_tx_out_$obuf_delay_tap[5] - Found", " Pin object=dout, location: HP_2_20_10P", " Data signal from object dout", - " Module=O_DELAY Linked-object=dout Port=I Net=dout_pre_delay - Found", + " Module=O_DELAY Linked-object=dout Port=I Net=$f2g_tx_out_dout_pre_delay - Found", " Pin object=dout_clk2, location: HR_5_1_0N", " Data signal from object dout_clk2", - " Module=O_BUFT Linked-object=dout_clk2 Port=I Net=$obuf_dout_clk2 - Found", + " Module=O_BUFT Linked-object=dout_clk2 Port=I Net=$f2g_tx_out_$obuf_dout_clk2 - Found", " Pin object=dout_serdes, location: HR_2_2_1P", " Data signal from object dout_serdes", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto_540 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto_541 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto_542 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto_543 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto_544 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto_545 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto_546 - Found", - " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$auto_547 - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$f2g_tx_out_serdes_data[0] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$f2g_tx_out_serdes_data[1] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$f2g_tx_out_serdes_data[2] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$f2g_tx_out_serdes_data[3] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$f2g_tx_out_serdes_data[4] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$f2g_tx_out_serdes_data[5] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$f2g_tx_out_serdes_data[6] - Found", + " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$f2g_tx_out_serdes_data[7] - Found", " Pin object=dout_serdes_clk_out, location: HR_2_7_3N", " Data signal from object dout_serdes_clk_out", - " Module=O_BUFT Linked-object=dout_serdes_clk_out Port=I Net=$obuf_dout_serdes_clk_out - Found", + " Module=O_BUFT Linked-object=dout_serdes_clk_out Port=I Net=$f2g_tx_out_$obuf_dout_serdes_clk_out - Found", " Pin object=din_n, location: HP_1_5_2N", " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=din_p, location: HP_1_4_2P", @@ -448,14 +451,14 @@ " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=dout_p, location: HP_1_8_4P", " Data signal from object dout_p", - " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto_536 - Found", - " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto_537 - Found", + " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$f2g_tx_out_o_ddr_d[0] - Found", + " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$f2g_tx_out_o_ddr_d[1] - Found", " Pin object=dout_osc_n, location: HP_2_23_11N", " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=dout_osc_p, location: HP_2_22_11P", " Data signal from object dout_osc_p", - " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto_538 - Found", - " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto_539 - Found", + " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$f2g_tx_out_o_ddr_d[0]_2 - Found", + " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$f2g_tx_out_o_ddr_d[1]_2 - Found", " Determine internal control signals", " Module=I_BUF LinkedObject=clk0 Location=HR_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_BUF LinkedObject=clk1 Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", @@ -523,1274 +526,1278 @@ " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din_n+din_p Location=HP_1_4_2P Port=R Signal=in:TO_BE_DETERMINED", " Skip reason: TO_BE_DETERMINED", + " Module=O_BUFT_DS LinkedObject=dout_n+dout_p Location=HP_1_8_4P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_DDR LinkedObject=dout_n+dout_p Location=HP_1_8_4P Port=E Signal=in:TO_BE_DETERMINED", " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout_n+dout_p Location=HP_1_8_4P Port=R Signal=in:TO_BE_DETERMINED", " Skip reason: TO_BE_DETERMINED", + " Module=O_BUFT_DS LinkedObject=dout_osc_n+dout_osc_p Location=HP_2_22_11P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_DDR LinkedObject=dout_osc_n+dout_osc_p Location=HP_2_22_11P Port=E Signal=in:TO_BE_DETERMINED", " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout_osc_n+dout_osc_p Location=HP_2_22_11P Port=R Signal=in:TO_BE_DETERMINED", " Skip reason: TO_BE_DETERMINED", "End of IO Analysis" ], - "instances" : [ + "instances": [ { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk0", - "location_object" : "clk0", - "location" : "HR_1_CC_18_9P", - "linked_object" : "clk0", - "linked_objects" : { - "clk0" : { - "location" : "HR_1_CC_18_9P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk0", + "location_object": "clk0", + "location": "HR_1_CC_18_9P", + "linked_object": "clk0", + "linked_objects": { + "clk0": { + "location": "HR_1_CC_18_9P", + "properties": { } } }, - "connectivity" : { - "I" : "clk0", - "O" : "$ibuf_clk0" + "connectivity": { + "I": "clk0", + "O": "$ibuf_clk0" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "CLK_BUF", - "name" : "$clkbuf$top.$ibuf_clk0", - "location_object" : "clk0", - "location" : "HR_1_CC_18_9P", - "linked_object" : "clk0", - "linked_objects" : { - "clk0" : { - "location" : "HR_1_CC_18_9P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "0" + "module": "CLK_BUF", + "name": "$clkbuf$top.$ibuf_clk0", + "location_object": "clk0", + "location": "HR_1_CC_18_9P", + "linked_object": "clk0", + "linked_objects": { + "clk0": { + "location": "HR_1_CC_18_9P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "0" } } }, - "connectivity" : { - "I" : "$ibuf_clk0", - "O" : "$clk_buf_$ibuf_clk0" + "connectivity": { + "I": "$ibuf_clk0", + "O": "$clk_buf_$ibuf_clk0" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "0" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "0" }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "i_delay" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk1", - "location_object" : "clk1", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk1", - "linked_objects" : { - "clk1" : { - "location" : "HP_1_CC_18_9P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk1", + "location_object": "clk1", + "location": "HP_1_CC_18_9P", + "linked_object": "clk1", + "linked_objects": { + "clk1": { + "location": "HP_1_CC_18_9P", + "properties": { } } }, - "connectivity" : { - "I" : "clk1", - "O" : "$ibuf_clk1" + "connectivity": { + "I": "clk1", + "O": "$ibuf_clk1" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "CLK_BUF", - "name" : "clk_buf", - "location_object" : "clk1", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk1", - "linked_objects" : { - "clk1" : { - "location" : "HP_1_CC_18_9P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "1" + "module": "CLK_BUF", + "name": "clk_buf", + "location_object": "clk1", + "location": "HP_1_CC_18_9P", + "linked_object": "clk1", + "linked_objects": { + "clk1": { + "location": "HP_1_CC_18_9P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "1" } } }, - "connectivity" : { - "I" : "$ibuf_clk1", - "O" : "clk1_buf" + "connectivity": { + "I": "$ibuf_clk1", + "O": "clk1_buf" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "1" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "1" }, - "flags" : [ + "flags": [ "CLK_BUF" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ "PLL" ], - "route_clock_to" : { - "O" : [ + "route_clock_to": { + "O": [ "o_delay" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "PLL", - "name" : "pll", - "location_object" : "clk1", - "location" : "HP_1_CC_18_9P", - "linked_object" : "clk1", - "linked_objects" : { - "clk1" : { - "location" : "HP_1_CC_18_9P", - "properties" : { - "OUT0_ROUTE_TO_FABRIC_CLK" : "2" + "module": "PLL", + "name": "pll", + "location_object": "clk1", + "location": "HP_1_CC_18_9P", + "linked_object": "clk1", + "linked_objects": { + "clk1": { + "location": "HP_1_CC_18_9P", + "properties": { + "OUT0_ROUTE_TO_FABRIC_CLK": "2" } } }, - "connectivity" : { - "CLK_IN" : "clk1_buf", - "CLK_OUT" : "pll_clk", - "CLK_OUT_DIV4" : "$delete_wire$499" - }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "FALSE", - "OUT0_ROUTE_TO_FABRIC_CLK" : "2", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" - }, - "flags" : [ + "connectivity": { + "CLK_IN": "clk1_buf", + "CLK_OUT": "pll_clk", + "CLK_OUT_DIV4": "$delete_wire$499" + }, + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "FALSE", + "OUT0_ROUTE_TO_FABRIC_CLK": "2", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" + }, + "flags": [ "PLL" ], - "pre_primitive" : "CLK_BUF", - "post_primitives" : [ + "pre_primitive": "CLK_BUF", + "post_primitives": [ ], - "route_clock_to" : { - "CLK_OUT" : [ + "route_clock_to": { + "CLK_OUT": [ "i_serdes", "i_ddr", "o_serdes", "o_serdes_clk" ] }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_clk2", - "location_object" : "clk2", - "location" : "HR_5_CC_38_19P", - "linked_object" : "clk2", - "linked_objects" : { - "clk2" : { - "location" : "HR_5_CC_38_19P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_clk2", + "location_object": "clk2", + "location": "HR_5_CC_38_19P", + "linked_object": "clk2", + "linked_objects": { + "clk2": { + "location": "HR_5_CC_38_19P", + "properties": { } } }, - "connectivity" : { - "I" : "clk2", - "O" : "$ibuf_clk2" + "connectivity": { + "I": "clk2", + "O": "$ibuf_clk2" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "CLK_BUF" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "CLK_BUF", - "name" : "$clkbuf$top.$ibuf_clk2", - "location_object" : "clk2", - "location" : "HR_5_CC_38_19P", - "linked_object" : "clk2", - "linked_objects" : { - "clk2" : { - "location" : "HR_5_CC_38_19P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "3" + "module": "CLK_BUF", + "name": "$clkbuf$top.$ibuf_clk2", + "location_object": "clk2", + "location": "HR_5_CC_38_19P", + "linked_object": "clk2", + "linked_objects": { + "clk2": { + "location": "HR_5_CC_38_19P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "3" } } }, - "connectivity" : { - "I" : "$ibuf_clk2", - "O" : "$clk_buf_$ibuf_clk2" + "connectivity": { + "I": "$ibuf_clk2", + "O": "$clk_buf_$ibuf_clk2" }, - "parameters" : { - "ROUTE_TO_FABRIC_CLK" : "3" + "parameters": { + "ROUTE_TO_FABRIC_CLK": "3" }, - "flags" : [ + "flags": [ "CLK_BUF", "PIN_CLOCK_CORE_ONLY" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din", - "location_object" : "din", - "location" : "HP_1_20_10P", - "linked_object" : "din", - "linked_objects" : { - "din" : { - "location" : "HP_1_20_10P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din", + "location_object": "din", + "location": "HP_1_20_10P", + "linked_object": "din", + "linked_objects": { + "din": { + "location": "HP_1_20_10P", + "properties": { } } }, - "connectivity" : { - "I" : "din", - "O" : "$ibuf_din" + "connectivity": { + "I": "din", + "O": "$ibuf_din" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DELAY" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DELAY", - "name" : "i_delay", - "location_object" : "din", - "location" : "HP_1_20_10P", - "linked_object" : "din", - "linked_objects" : { - "din" : { - "location" : "HP_1_20_10P", - "properties" : { + "module": "I_DELAY", + "name": "i_delay", + "location_object": "din", + "location": "HP_1_20_10P", + "linked_object": "din", + "linked_objects": { + "din": { + "location": "HP_1_20_10P", + "properties": { } } }, - "connectivity" : { - "CLK_IN" : "$clk_buf_$ibuf_clk0", - "I" : "$ibuf_din", - "O" : "din_delay" + "connectivity": { + "CLK_IN": "$clk_buf_$ibuf_clk0", + "I": "$ibuf_din", + "O": "din_delay" }, - "parameters" : { - "DELAY" : "50" + "parameters": { + "DELAY": "50" }, - "flags" : [ + "flags": [ "I_DELAY" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din_clk2", - "location_object" : "din_clk2", - "location" : "HR_5_0_0P", - "linked_object" : "din_clk2", - "linked_objects" : { - "din_clk2" : { - "location" : "HR_5_0_0P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din_clk2", + "location_object": "din_clk2", + "location": "HR_5_0_0P", + "linked_object": "din_clk2", + "linked_objects": { + "din_clk2": { + "location": "HR_5_0_0P", + "properties": { } } }, - "connectivity" : { - "I" : "din_clk2", - "O" : "$ibuf_din_clk2" + "connectivity": { + "I": "din_clk2", + "O": "$ibuf_din_clk2" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din_serdes", - "location_object" : "din_serdes", - "location" : "HR_2_0_0P", - "linked_object" : "din_serdes", - "linked_objects" : { - "din_serdes" : { - "location" : "HR_2_0_0P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din_serdes", + "location_object": "din_serdes", + "location": "HR_2_0_0P", + "linked_object": "din_serdes", + "linked_objects": { + "din_serdes": { + "location": "HR_2_0_0P", + "properties": { } } }, - "connectivity" : { - "I" : "din_serdes", - "O" : "$ibuf_din_serdes" + "connectivity": { + "I": "din_serdes", + "O": "$ibuf_din_serdes" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_SERDES" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_SERDES", - "name" : "i_serdes", - "location_object" : "din_serdes", - "location" : "HR_2_0_0P", - "linked_object" : "din_serdes", - "linked_objects" : { - "din_serdes" : { - "location" : "HR_2_0_0P", - "properties" : { - "ROUTE_TO_FABRIC_CLK" : "4" + "module": "I_SERDES", + "name": "i_serdes", + "location_object": "din_serdes", + "location": "HR_2_0_0P", + "linked_object": "din_serdes", + "linked_objects": { + "din_serdes": { + "location": "HR_2_0_0P", + "properties": { + "ROUTE_TO_FABRIC_CLK": "4" } } }, - "connectivity" : { - "CLK_IN" : "pll_clk", - "CLK_OUT" : "iserdes_clk_out", - "D" : "$ibuf_din_serdes", - "PLL_CLK" : "pll_clk" + "connectivity": { + "CLK_IN": "pll_clk", + "CLK_OUT": "iserdes_clk_out", + "D": "$ibuf_din_serdes", + "PLL_CLK": "pll_clk" }, - "parameters" : { - "DATA_RATE" : "SDR", - "DPA_MODE" : "DPA", - "ROUTE_TO_FABRIC_CLK" : "4", - "WIDTH" : "8" + "parameters": { + "DATA_RATE": "SDR", + "DPA_MODE": "DPA", + "ROUTE_TO_FABRIC_CLK": "4", + "WIDTH": "8" }, - "flags" : [ + "flags": [ "I_SERDES" ], - "pre_primitive" : "I_BUF", - "post_primitives" : [ + "pre_primitive": "I_BUF", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_din_serdes_clk_out", - "location_object" : "din_serdes_clk_out", - "location" : "HR_2_6_3P", - "linked_object" : "din_serdes_clk_out", - "linked_objects" : { - "din_serdes_clk_out" : { - "location" : "HR_2_6_3P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_din_serdes_clk_out", + "location_object": "din_serdes_clk_out", + "location": "HR_2_6_3P", + "linked_object": "din_serdes_clk_out", + "linked_objects": { + "din_serdes_clk_out": { + "location": "HR_2_6_3P", + "properties": { } } }, - "connectivity" : { - "I" : "din_serdes_clk_out", - "O" : "$ibuf_din_serdes_clk_out" + "connectivity": { + "I": "din_serdes_clk_out", + "O": "$ibuf_din_serdes_clk_out" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_enable", - "location_object" : "enable", - "location" : "", - "linked_object" : "enable", - "linked_objects" : { - "enable" : { - "location" : "", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_enable", + "location_object": "enable", + "location": "", + "linked_object": "enable", + "linked_objects": { + "enable": { + "location": "", + "properties": { } } }, - "connectivity" : { - "I" : "enable", - "O" : "$ibuf_enable" + "connectivity": { + "I": "enable", + "O": "$ibuf_enable" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF", - "name" : "$ibuf$top.$ibuf_reset", - "location_object" : "reset", - "location" : "HP_1_0_0P", - "linked_object" : "reset", - "linked_objects" : { - "reset" : { - "location" : "HP_1_0_0P", - "properties" : { + "module": "I_BUF", + "name": "$ibuf$top.$ibuf_reset", + "location_object": "reset", + "location": "HP_1_0_0P", + "linked_object": "reset", + "linked_objects": { + "reset": { + "location": "HP_1_0_0P", + "properties": { } } }, - "connectivity" : { - "I" : "reset", - "O" : "$ibuf_reset" + "connectivity": { + "I": "reset", + "O": "$ibuf_reset" }, - "parameters" : { - "WEAK_KEEPER" : "NONE" + "parameters": { + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_clk_out", - "location_object" : "clk_out", - "location" : "HR_2_4_2P", - "linked_object" : "clk_out", - "linked_objects" : { - "clk_out" : { - "location" : "HR_2_4_2P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_clk_out", + "location_object": "clk_out", + "location": "HR_2_4_2P", + "linked_object": "clk_out", + "linked_objects": { + "clk_out": { + "location": "HR_2_4_2P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_clk_out", - "O" : "clk_out" + "connectivity": { + "I": "$obuf_clk_out", + "O": "clk_out" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_SERDES_CLK" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_SERDES_CLK", - "name" : "o_serdes_clk", - "location_object" : "clk_out", - "location" : "HR_2_4_2P", - "linked_object" : "clk_out", - "linked_objects" : { - "clk_out" : { - "location" : "HR_2_4_2P", - "properties" : { + "module": "O_SERDES_CLK", + "name": "o_serdes_clk", + "location_object": "clk_out", + "location": "HR_2_4_2P", + "linked_object": "clk_out", + "linked_objects": { + "clk_out": { + "location": "HR_2_4_2P", + "properties": { } } }, - "connectivity" : { - "OUTPUT_CLK" : "$obuf_clk_out", - "PLL_CLK" : "pll_clk" + "connectivity": { + "OUTPUT_CLK": "$obuf_clk_out", + "PLL_CLK": "pll_clk" }, - "parameters" : { - "CLOCK_PHASE" : "270", - "DATA_RATE" : "SDR" + "parameters": { + "CLOCK_PHASE": "270", + "DATA_RATE": "SDR" }, - "flags" : [ + "flags": [ "O_SERDES_CLK" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap", - "location_object" : "delay_tap[0]", - "location" : "HR_2_20_10P", - "linked_object" : "delay_tap[0]", - "linked_objects" : { - "delay_tap[0]" : { - "location" : "HR_2_20_10P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap", + "location_object": "delay_tap[0]", + "location": "HR_2_20_10P", + "linked_object": "delay_tap[0]", + "linked_objects": { + "delay_tap[0]": { + "location": "HR_2_20_10P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_delay_tap[0]", - "O" : "delay_tap[0]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[0]", + "O": "delay_tap[0]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_1", - "location_object" : "delay_tap[1]", - "location" : "HR_2_22_11P", - "linked_object" : "delay_tap[1]", - "linked_objects" : { - "delay_tap[1]" : { - "location" : "HR_2_22_11P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_1", + "location_object": "delay_tap[1]", + "location": "HR_2_22_11P", + "linked_object": "delay_tap[1]", + "linked_objects": { + "delay_tap[1]": { + "location": "HR_2_22_11P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_delay_tap[1]", - "O" : "delay_tap[1]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[1]", + "O": "delay_tap[1]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_2", - "location_object" : "delay_tap[2]", - "location" : "HR_2_24_12P", - "linked_object" : "delay_tap[2]", - "linked_objects" : { - "delay_tap[2]" : { - "location" : "HR_2_24_12P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_2", + "location_object": "delay_tap[2]", + "location": "HR_2_24_12P", + "linked_object": "delay_tap[2]", + "linked_objects": { + "delay_tap[2]": { + "location": "HR_2_24_12P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_delay_tap[2]", - "O" : "delay_tap[2]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[2]", + "O": "delay_tap[2]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_3", - "location_object" : "delay_tap[3]", - "location" : "HR_2_26_13P", - "linked_object" : "delay_tap[3]", - "linked_objects" : { - "delay_tap[3]" : { - "location" : "HR_2_26_13P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_3", + "location_object": "delay_tap[3]", + "location": "HR_2_26_13P", + "linked_object": "delay_tap[3]", + "linked_objects": { + "delay_tap[3]": { + "location": "HR_2_26_13P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_delay_tap[3]", - "O" : "delay_tap[3]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[3]", + "O": "delay_tap[3]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_4", - "location_object" : "delay_tap[4]", - "location" : "HR_2_28_14P", - "linked_object" : "delay_tap[4]", - "linked_objects" : { - "delay_tap[4]" : { - "location" : "HR_2_28_14P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_4", + "location_object": "delay_tap[4]", + "location": "HR_2_28_14P", + "linked_object": "delay_tap[4]", + "linked_objects": { + "delay_tap[4]": { + "location": "HR_2_28_14P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_delay_tap[4]", - "O" : "delay_tap[4]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[4]", + "O": "delay_tap[4]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_delay_tap_5", - "location_object" : "delay_tap[5]", - "location" : "HR_2_30_15P", - "linked_object" : "delay_tap[5]", - "linked_objects" : { - "delay_tap[5]" : { - "location" : "HR_2_30_15P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_delay_tap_5", + "location_object": "delay_tap[5]", + "location": "HR_2_30_15P", + "linked_object": "delay_tap[5]", + "linked_objects": { + "delay_tap[5]": { + "location": "HR_2_30_15P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_delay_tap[5]", - "O" : "delay_tap[5]" + "connectivity": { + "I": "$f2g_tx_out_$obuf_delay_tap[5]", + "O": "delay_tap[5]" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout", - "location_object" : "dout", - "location" : "HP_2_20_10P", - "linked_object" : "dout", - "linked_objects" : { - "dout" : { - "location" : "HP_2_20_10P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout", + "location_object": "dout", + "location": "HP_2_20_10P", + "linked_object": "dout", + "linked_objects": { + "dout": { + "location": "HP_2_20_10P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout", - "O" : "dout" + "connectivity": { + "I": "$obuf_dout", + "O": "dout" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DELAY" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_DELAY", - "name" : "o_delay", - "location_object" : "dout", - "location" : "HP_2_20_10P", - "linked_object" : "dout", - "linked_objects" : { - "dout" : { - "location" : "HP_2_20_10P", - "properties" : { + "module": "O_DELAY", + "name": "o_delay", + "location_object": "dout", + "location": "HP_2_20_10P", + "linked_object": "dout", + "linked_objects": { + "dout": { + "location": "HP_2_20_10P", + "properties": { } } }, - "connectivity" : { - "CLK_IN" : "clk1_buf", - "I" : "dout_pre_delay", - "O" : "$obuf_dout" + "connectivity": { + "CLK_IN": "clk1_buf", + "I": "$f2g_tx_out_dout_pre_delay", + "O": "$obuf_dout" }, - "parameters" : { - "DELAY" : "60" + "parameters": { + "DELAY": "60" }, - "flags" : [ + "flags": [ "O_DELAY" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout_clk2", - "location_object" : "dout_clk2", - "location" : "HR_5_1_0N", - "linked_object" : "dout_clk2", - "linked_objects" : { - "dout_clk2" : { - "location" : "HR_5_1_0N", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout_clk2", + "location_object": "dout_clk2", + "location": "HR_5_1_0N", + "linked_object": "dout_clk2", + "linked_objects": { + "dout_clk2": { + "location": "HR_5_1_0N", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout_clk2", - "O" : "dout_clk2" + "connectivity": { + "I": "$f2g_tx_out_$obuf_dout_clk2", + "O": "dout_clk2" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout_serdes", - "location_object" : "dout_serdes", - "location" : "HR_2_2_1P", - "linked_object" : "dout_serdes", - "linked_objects" : { - "dout_serdes" : { - "location" : "HR_2_2_1P", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout_serdes", + "location_object": "dout_serdes", + "location": "HR_2_2_1P", + "linked_object": "dout_serdes", + "linked_objects": { + "dout_serdes": { + "location": "HR_2_2_1P", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout_serdes", - "O" : "dout_serdes" + "connectivity": { + "I": "$obuf_dout_serdes", + "O": "dout_serdes" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_SERDES" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_SERDES", - "name" : "o_serdes", - "location_object" : "dout_serdes", - "location" : "HR_2_2_1P", - "linked_object" : "dout_serdes", - "linked_objects" : { - "dout_serdes" : { - "location" : "HR_2_2_1P", - "properties" : { + "module": "O_SERDES", + "name": "o_serdes", + "location_object": "dout_serdes", + "location": "HR_2_2_1P", + "linked_object": "dout_serdes", + "linked_objects": { + "dout_serdes": { + "location": "HR_2_2_1P", + "properties": { } } }, - "connectivity" : { - "CLK_IN" : "pll_clk", - "PLL_CLK" : "pll_clk", - "Q" : "$obuf_dout_serdes" + "connectivity": { + "CLK_IN": "pll_clk", + "PLL_CLK": "pll_clk", + "Q": "$obuf_dout_serdes" }, - "parameters" : { - "DATA_RATE" : "DDR", - "WIDTH" : "8" + "parameters": { + "DATA_RATE": "DDR", + "WIDTH": "8" }, - "flags" : [ + "flags": [ "O_SERDES" ], - "pre_primitive" : "O_BUFT", - "post_primitives" : [ + "pre_primitive": "O_BUFT", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUFT", - "name" : "$obuf$top.$obuf_dout_serdes_clk_out", - "location_object" : "dout_serdes_clk_out", - "location" : "HR_2_7_3N", - "linked_object" : "dout_serdes_clk_out", - "linked_objects" : { - "dout_serdes_clk_out" : { - "location" : "HR_2_7_3N", - "properties" : { + "module": "O_BUFT", + "name": "$obuf$top.$obuf_dout_serdes_clk_out", + "location_object": "dout_serdes_clk_out", + "location": "HR_2_7_3N", + "linked_object": "dout_serdes_clk_out", + "linked_objects": { + "dout_serdes_clk_out": { + "location": "HR_2_7_3N", + "properties": { } } }, - "connectivity" : { - "I" : "$obuf_dout_serdes_clk_out", - "O" : "dout_serdes_clk_out" + "connectivity": { + "I": "$f2g_tx_out_$obuf_dout_serdes_clk_out", + "O": "dout_serdes_clk_out" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_BUFT" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "BOOT_CLOCK", - "name" : "boot_clock", - "location_object" : "BOOT_CLOCK#0", - "location" : "", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "", - "properties" : { + "module": "BOOT_CLOCK", + "name": "boot_clock", + "location_object": "BOOT_CLOCK#0", + "location": "", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "", + "properties": { } } }, - "connectivity" : { - "O" : "osc" + "connectivity": { + "O": "osc" }, - "parameters" : { - "PERIOD" : "25" + "parameters": { + "PERIOD": "25" }, - "flags" : [ + "flags": [ "BOOT_CLOCK" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "PLL" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "PLL", - "name" : "pll_osc", - "location_object" : "BOOT_CLOCK#0", - "location" : "", - "linked_object" : "BOOT_CLOCK#0", - "linked_objects" : { - "BOOT_CLOCK#0" : { - "location" : "", - "properties" : { - "OUT0_ROUTE_TO_FABRIC_CLK" : "5" + "module": "PLL", + "name": "pll_osc", + "location_object": "BOOT_CLOCK#0", + "location": "", + "linked_object": "BOOT_CLOCK#0", + "linked_objects": { + "BOOT_CLOCK#0": { + "location": "", + "properties": { + "OUT0_ROUTE_TO_FABRIC_CLK": "5" } } }, - "connectivity" : { - "CLK_IN" : "osc", - "CLK_OUT" : "osc_pll" + "connectivity": { + "CLK_IN": "osc", + "CLK_OUT": "osc_pll" }, - "parameters" : { - "DEV_FAMILY" : "VIRGO", - "DIVIDE_CLK_IN_BY_2" : "TRUE", - "OUT0_ROUTE_TO_FABRIC_CLK" : "5", - "PLL_DIV" : "1", - "PLL_MULT" : "16", - "PLL_MULT_FRAC" : "0", - "PLL_POST_DIV" : "34" + "parameters": { + "DEV_FAMILY": "VIRGO", + "DIVIDE_CLK_IN_BY_2": "TRUE", + "OUT0_ROUTE_TO_FABRIC_CLK": "5", + "PLL_DIV": "1", + "PLL_MULT": "16", + "PLL_MULT_FRAC": "0", + "PLL_POST_DIV": "34" }, - "flags" : [ + "flags": [ "PLL" ], - "pre_primitive" : "BOOT_CLOCK", - "post_primitives" : [ + "pre_primitive": "BOOT_CLOCK", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_BUF_DS", - "name" : "i_buf_ds", - "location_object" : "din_p", - "location" : "HP_1_4_2P", - "linked_object" : "din_n+din_p", - "linked_objects" : { - "din_n" : { - "location" : "HP_1_5_2N", - "properties" : { + "module": "I_BUF_DS", + "name": "i_buf_ds", + "location_object": "din_p", + "location": "HP_1_4_2P", + "linked_object": "din_n+din_p", + "linked_objects": { + "din_n": { + "location": "HP_1_5_2N", + "properties": { } }, - "din_p" : { - "location" : "HP_1_4_2P", - "properties" : { + "din_p": { + "location": "HP_1_4_2P", + "properties": { } } }, - "connectivity" : { - "I_N" : "din_n", - "I_P" : "din_p", - "O" : "i_ddr_d" + "connectivity": { + "I_N": "din_n", + "I_P": "din_p", + "O": "i_ddr_d" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT", - "WEAK_KEEPER" : "NONE" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ + "flags": [ "I_BUF_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "I_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "I_DDR", - "name" : "i_ddr", - "location_object" : "din_p", - "location" : "HP_1_4_2P", - "linked_object" : "din_n+din_p", - "linked_objects" : { - "din_n" : { - "location" : "HP_1_5_2N", - "properties" : { + "module": "I_DDR", + "name": "i_ddr", + "location_object": "din_p", + "location": "HP_1_4_2P", + "linked_object": "din_n+din_p", + "linked_objects": { + "din_n": { + "location": "HP_1_5_2N", + "properties": { } }, - "din_p" : { - "location" : "HP_1_4_2P", - "properties" : { + "din_p": { + "location": "HP_1_4_2P", + "properties": { } } }, - "connectivity" : { - "C" : "pll_clk", - "D" : "i_ddr_d" + "connectivity": { + "C": "pll_clk", + "D": "i_ddr_d" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "I_DDR" ], - "pre_primitive" : "I_BUF_DS", - "post_primitives" : [ + "pre_primitive": "I_BUF_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUF_DS", - "name" : "o_buf_ds", - "location_object" : "dout_p", - "location" : "HP_1_8_4P", - "linked_object" : "dout_n+dout_p", - "linked_objects" : { - "dout_n" : { - "location" : "HP_1_9_4N", - "properties" : { + "module": "O_BUFT_DS", + "name": "o_buf_ds", + "location_object": "dout_p", + "location": "HP_1_8_4P", + "linked_object": "dout_n+dout_p", + "linked_objects": { + "dout_n": { + "location": "HP_1_9_4N", + "properties": { } }, - "dout_p" : { - "location" : "HP_1_8_4P", - "properties" : { + "dout_p": { + "location": "HP_1_8_4P", + "properties": { } } }, - "connectivity" : { - "I" : "o_buf_ds_i", - "O_N" : "dout_n", - "O_P" : "dout_p" + "connectivity": { + "I": "o_buf_ds_i", + "O_N": "dout_n", + "O_P": "dout_p" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ - "O_BUF_DS" + "flags": [ + "O_BUFT_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_DDR", - "name" : "o_ddr", - "location_object" : "dout_p", - "location" : "HP_1_8_4P", - "linked_object" : "dout_n+dout_p", - "linked_objects" : { - "dout_n" : { - "location" : "HP_1_9_4N", - "properties" : { + "module": "O_DDR", + "name": "o_ddr", + "location_object": "dout_p", + "location": "HP_1_8_4P", + "linked_object": "dout_n+dout_p", + "linked_objects": { + "dout_n": { + "location": "HP_1_9_4N", + "properties": { } }, - "dout_p" : { - "location" : "HP_1_8_4P", - "properties" : { + "dout_p": { + "location": "HP_1_8_4P", + "properties": { } } }, - "connectivity" : { - "C" : "pll_clk", - "Q" : "o_buf_ds_i" + "connectivity": { + "C": "pll_clk", + "Q": "o_buf_ds_i" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUF_DS", - "post_primitives" : [ + "pre_primitive": "O_BUFT_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_BUF_DS", - "name" : "o_buf_ds_osc", - "location_object" : "dout_osc_p", - "location" : "HP_2_22_11P", - "linked_object" : "dout_osc_n+dout_osc_p", - "linked_objects" : { - "dout_osc_n" : { - "location" : "HP_2_23_11N", - "properties" : { + "module": "O_BUFT_DS", + "name": "o_buf_ds_osc", + "location_object": "dout_osc_p", + "location": "HP_2_22_11P", + "linked_object": "dout_osc_n+dout_osc_p", + "linked_objects": { + "dout_osc_n": { + "location": "HP_2_23_11N", + "properties": { } }, - "dout_osc_p" : { - "location" : "HP_2_22_11P", - "properties" : { + "dout_osc_p": { + "location": "HP_2_22_11P", + "properties": { } } }, - "connectivity" : { - "I" : "o_buf_ds_i_osc", - "O_N" : "dout_osc_n", - "O_P" : "dout_osc_p" + "connectivity": { + "I": "o_buf_ds_i_osc", + "O_N": "dout_osc_n", + "O_P": "dout_osc_p" }, - "parameters" : { - "DIFFERENTIAL_TERMINATION" : "TRUE", - "IOSTANDARD" : "DEFAULT" + "parameters": { + "DIFFERENTIAL_TERMINATION": "TRUE", + "IOSTANDARD": "DEFAULT", + "WEAK_KEEPER": "NONE" }, - "flags" : [ - "O_BUF_DS" + "flags": [ + "O_BUFT_DS" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ "O_DDR" ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "O_DDR", - "name" : "o_ddr_osc", - "location_object" : "dout_osc_p", - "location" : "HP_2_22_11P", - "linked_object" : "dout_osc_n+dout_osc_p", - "linked_objects" : { - "dout_osc_n" : { - "location" : "HP_2_23_11N", - "properties" : { + "module": "O_DDR", + "name": "o_ddr_osc", + "location_object": "dout_osc_p", + "location": "HP_2_22_11P", + "linked_object": "dout_osc_n+dout_osc_p", + "linked_objects": { + "dout_osc_n": { + "location": "HP_2_23_11N", + "properties": { } }, - "dout_osc_p" : { - "location" : "HP_2_22_11P", - "properties" : { + "dout_osc_p": { + "location": "HP_2_22_11P", + "properties": { } } }, - "connectivity" : { - "C" : "osc_pll", - "Q" : "o_buf_ds_i_osc" + "connectivity": { + "C": "osc_pll", + "Q": "o_buf_ds_i_osc" }, - "parameters" : { + "parameters": { }, - "flags" : [ + "flags": [ "O_DDR" ], - "pre_primitive" : "O_BUF_DS", - "post_primitives" : [ + "pre_primitive": "O_BUFT_DS", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] }, { - "module" : "FCLK_BUF", - "name" : "$clkbuf$top.clk0_div", - "location_object" : "FABRIC_CLKBUF#0", - "location" : "", - "linked_object" : "FABRIC_CLKBUF#0", - "linked_objects" : { - "FABRIC_CLKBUF#0" : { - "location" : "", - "properties" : { - "ROUTE_FROM_FABRIC_CLK" : "0", - "ROUTE_TO_FABRIC_CLK" : "6" + "module": "FCLK_BUF", + "name": "$clkbuf$top.clk0_div", + "location_object": "FABRIC_CLKBUF#0", + "location": "", + "linked_object": "FABRIC_CLKBUF#0", + "linked_objects": { + "FABRIC_CLKBUF#0": { + "location": "", + "properties": { + "ROUTE_FROM_FABRIC_CLK": "0", + "ROUTE_TO_FABRIC_CLK": "6" } } }, - "connectivity" : { - "I" : "clk0_div", - "O" : "$fclk_buf_clk0_div" + "connectivity": { + "I": "clk0_div", + "O": "$fclk_buf_clk0_div" }, - "parameters" : { - "ROUTE_FROM_FABRIC_CLK" : "0", - "ROUTE_TO_FABRIC_CLK" : "6" + "parameters": { + "ROUTE_FROM_FABRIC_CLK": "0", + "ROUTE_TO_FABRIC_CLK": "6" }, - "flags" : [ + "flags": [ "FCLK_BUF" ], - "pre_primitive" : "", - "post_primitives" : [ + "pre_primitive": "", + "post_primitives": [ ], - "route_clock_to" : { + "route_clock_to": { }, - "errors" : [ + "errors": [ ] } ] -} \ No newline at end of file +} diff --git a/tests/unittest/ModelConfig/ric/CLK_BUF.api.json b/tests/unittest/ModelConfig/ric/CLK_BUF.api.json index b55d77c54..58614e883 100644 --- a/tests/unittest/ModelConfig/ric/CLK_BUF.api.json +++ b/tests/unittest/ModelConfig/ric/CLK_BUF.api.json @@ -8,46 +8,6 @@ { "attr": "RX_BYPASS", "value": "RX_bypass" - }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_clock_IO" - } - ], - "ROOT_BANK_SRC==A": [ - { - "attr": "CDR_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CDR_CLK_ROOT_SEL_A", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_A", - "value": "#MUX" - } - ], - "ROOT_BANK_SRC==B": [ - { - "attr": "CDR_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CDR_CLK_ROOT_SEL_A", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_B", - "value": "#MUX" - }, - { - "attr": "CORE_CLK_ROOT_SEL_A", - "value": "__DONT__" } ] } diff --git a/tests/unittest/ModelConfig/ric/I_BUF.api.json b/tests/unittest/ModelConfig/ric/I_BUF.api.json index dcebb8f4f..067b0c3c9 100644 --- a/tests/unittest/ModelConfig/ric/I_BUF.api.json +++ b/tests/unittest/ModelConfig/ric/I_BUF.api.json @@ -13,10 +13,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -57,10 +53,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -91,10 +83,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -135,10 +123,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -169,10 +153,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -213,10 +193,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -247,10 +223,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -291,10 +263,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -325,10 +293,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -369,10 +333,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -403,10 +363,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -447,10 +403,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -481,10 +433,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -525,10 +473,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" diff --git a/tests/unittest/ModelConfig/ric/I_BUF_DS.api.json b/tests/unittest/ModelConfig/ric/I_BUF_DS.api.json index 3056b1565..b5fdb543a 100644 --- a/tests/unittest/ModelConfig/ric/I_BUF_DS.api.json +++ b/tests/unittest/ModelConfig/ric/I_BUF_DS.api.json @@ -13,10 +13,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -57,10 +53,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -91,10 +83,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -135,10 +123,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -169,10 +153,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -213,10 +193,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -247,10 +223,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -291,10 +263,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -325,10 +293,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -369,10 +333,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -403,10 +363,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -447,10 +403,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -481,10 +433,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -525,10 +473,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" diff --git a/tests/unittest/ModelConfig/ric/I_SERDES.api.json b/tests/unittest/ModelConfig/ric/I_SERDES.api.json index 16f2b48b8..ef9777792 100644 --- a/tests/unittest/ModelConfig/ric/I_SERDES.api.json +++ b/tests/unittest/ModelConfig/ric/I_SERDES.api.json @@ -97,114 +97,6 @@ "attr": "RX_MIPI_MODE", "value": "RX_mipi_off" } - ], - "ROOT_BANK_SRC==A&DPA_MODE==CDR": [ - { - "attr": "CDR_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CDR_CLK_ROOT_SEL_A", - "value": "#MUX" - }, - { - "attr": "CORE_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_A", - "value": "__DONT__" - } - ], - "ROOT_BANK_SRC==A&DPA_MODE==DPA": [ - { - "attr": "CDR_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CDR_CLK_ROOT_SEL_A", - "value": "#MUX" - }, - { - "attr": "CORE_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_A", - "value": "__DONT__" - } - ], - "ROOT_BANK_SRC==A&DPA_MODE==NONE": [ - { - "attr": "CDR_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CDR_CLK_ROOT_SEL_A", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_A", - "value": "#MUX" - } - ], - "ROOT_BANK_SRC==B&DPA_MODE==CDR": [ - { - "attr": "CDR_CLK_ROOT_SEL_B", - "value": "#MUX" - }, - { - "attr": "CDR_CLK_ROOT_SEL_A", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_A", - "value": "__DONT__" - } - ], - "ROOT_BANK_SRC==B&DPA_MODE==DPA": [ - { - "attr": "CDR_CLK_ROOT_SEL_B", - "value": "#MUX" - }, - { - "attr": "CDR_CLK_ROOT_SEL_A", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_A", - "value": "__DONT__" - } - ], - "ROOT_BANK_SRC==B&DPA_MODE==NONE": [ - { - "attr": "CDR_CLK_ROOT_SEL_B", - "value": "__DONT__" - }, - { - "attr": "CDR_CLK_ROOT_SEL_A", - "value": "__DONT__" - }, - { - "attr": "CORE_CLK_ROOT_SEL_B", - "value": "#MUX" - }, - { - "attr": "CORE_CLK_ROOT_SEL_A", - "value": "__DONT__" - } ] } } \ No newline at end of file diff --git a/tests/unittest/ModelConfig/ric/O_BUF.api.json b/tests/unittest/ModelConfig/ric/O_BUF.api.json index 5f2468dad..765100dd5 100644 --- a/tests/unittest/ModelConfig/ric/O_BUF.api.json +++ b/tests/unittest/ModelConfig/ric/O_BUF.api.json @@ -13,10 +13,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -57,10 +53,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -99,10 +91,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -143,10 +131,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -185,10 +169,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -229,10 +209,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -271,10 +247,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -315,10 +287,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -357,10 +325,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -401,10 +365,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -443,10 +403,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -487,10 +443,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -529,10 +481,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -573,10 +521,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" diff --git a/tests/unittest/ModelConfig/ric/O_BUFT.api.json b/tests/unittest/ModelConfig/ric/O_BUFT.api.json index 77c8dcdf1..c02a83fc6 100644 --- a/tests/unittest/ModelConfig/ric/O_BUFT.api.json +++ b/tests/unittest/ModelConfig/ric/O_BUFT.api.json @@ -13,10 +13,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -57,10 +53,6 @@ "attr": "RX_MODE", "value": "__DONT__" }, - { - "attr": "RX_CLOCK_IO", - "value": "__DONT__" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -99,10 +91,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -143,10 +131,6 @@ "attr": "RX_MODE", "value": "__DONT__" }, - { - "attr": "RX_CLOCK_IO", - "value": "__DONT__" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -185,10 +169,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -229,10 +209,6 @@ "attr": "RX_MODE", "value": "__DONT__" }, - { - "attr": "RX_CLOCK_IO", - "value": "__DONT__" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -271,10 +247,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -315,10 +287,6 @@ "attr": "RX_MODE", "value": "__DONT__" }, - { - "attr": "RX_CLOCK_IO", - "value": "__DONT__" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -357,10 +325,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -401,10 +365,6 @@ "attr": "RX_MODE", "value": "__DONT__" }, - { - "attr": "RX_CLOCK_IO", - "value": "__DONT__" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -443,10 +403,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -487,10 +443,6 @@ "attr": "RX_MODE", "value": "__DONT__" }, - { - "attr": "RX_CLOCK_IO", - "value": "__DONT__" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -529,10 +481,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -573,10 +521,6 @@ "attr": "RX_MODE", "value": "__DONT__" }, - { - "attr": "RX_CLOCK_IO", - "value": "__DONT__" - }, { "attr": "DFEN", "value": "SingleEnded" diff --git a/tests/unittest/ModelConfig/ric/O_BUFT_DS.api.json b/tests/unittest/ModelConfig/ric/O_BUFT_DS.api.json index b62bc9eba..d53f1b769 100644 --- a/tests/unittest/ModelConfig/ric/O_BUFT_DS.api.json +++ b/tests/unittest/ModelConfig/ric/O_BUFT_DS.api.json @@ -13,10 +13,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -57,10 +53,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -99,10 +91,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -143,10 +131,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -185,10 +169,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -229,10 +209,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -271,10 +247,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -315,10 +287,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -357,10 +325,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -401,10 +365,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -443,10 +403,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -487,10 +443,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -529,10 +481,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -573,10 +521,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" diff --git a/tests/unittest/ModelConfig/ric/O_BUF_DS.api.json b/tests/unittest/ModelConfig/ric/O_BUF_DS.api.json index 285932f3d..19a12b857 100644 --- a/tests/unittest/ModelConfig/ric/O_BUF_DS.api.json +++ b/tests/unittest/ModelConfig/ric/O_BUF_DS.api.json @@ -13,10 +13,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -57,10 +53,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -99,10 +91,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -143,10 +131,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -185,10 +169,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -229,10 +209,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -271,10 +247,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -315,10 +287,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -357,10 +325,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -401,10 +365,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -443,10 +403,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -487,10 +443,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" @@ -529,10 +481,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -573,10 +521,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "Differential" diff --git a/tests/unittest/ModelConfig/ric/PLL.api.json b/tests/unittest/ModelConfig/ric/PLL.api.json deleted file mode 100644 index 3af0c5557..000000000 --- a/tests/unittest/ModelConfig/ric/PLL.api.json +++ /dev/null @@ -1,148 +0,0 @@ -{ - "PLL": { - "PLLREF_SRC==BOOT_CLOCK": [ - { - "attr": "cfg_pllref_hv_rx_io_sel", - "value": "__DONT__" - }, - { - "attr": "cfg_pllref_hv_bank_rx_io_sel", - "value": "__DONT__" - }, - { - "attr": "cfg_pllref_hp_rx_io_sel", - "value": "__DONT__" - }, - { - "attr": "cfg_pllref_hp_bank_rx_io_sel", - "value": "__DONT__" - }, - { - "attr": "cfg_pllref_use_hv", - "value": "__DONT__" - }, - { - "attr": "cfg_pllref_use_rosc", - "value": "pllref_use_rosc_1" - }, - { - "attr": "cfg_pllref_use_div", - "value": "#DIV" - } - ], - "PLLREF_SRC==HP": [ - { - "attr": "cfg_pllref_hv_rx_io_sel", - "value": "__DONT__" - }, - { - "attr": "cfg_pllref_hv_bank_rx_io_sel", - "value": "__DONT__" - }, - { - "attr": "cfg_pllref_hp_rx_io_sel", - "value": "#PIN" - }, - { - "attr": "cfg_pllref_hp_bank_rx_io_sel", - "value": "#BANK" - }, - { - "attr": "cfg_pllref_use_hv", - "value": "pllref_use_hv_0" - }, - { - "attr": "cfg_pllref_use_rosc", - "value": "pllref_use_rosc_0" - }, - { - "attr": "cfg_pllref_use_div", - "value": "#DIV" - } - ], - "PLLREF_SRC==HV": [ - { - "attr": "cfg_pllref_hv_rx_io_sel", - "value": "#PIN" - }, - { - "attr": "cfg_pllref_hv_bank_rx_io_sel", - "value": "#BANK" - }, - { - "attr": "cfg_pllref_hp_rx_io_sel", - "value": "__DONT__" - }, - { - "attr": "cfg_pllref_hp_bank_rx_io_sel", - "value": "__DONT__" - }, - { - "attr": "cfg_pllref_use_hv", - "value": "pllref_use_hv_1" - }, - { - "attr": "cfg_pllref_use_rosc", - "value": "pllref_use_rosc_0" - }, - { - "attr": "cfg_pllref_use_div", - "value": "#DIV" - } - ], - "PLL_SRC==DEFAULT": [ - { - "attr": "pll_DSKEWCALBYP", - "value": "DSKEWCALBYP_0" - }, - { - "attr": "pll_DSKEWCALIN", - "value": "0" - }, - { - "attr": "pll_DSKEWCALCNT", - "value": "2" - }, - { - "attr": "pll_DSKEWFASTCAL", - "value": "DSKEWFASTCAL_0" - }, - { - "attr": "pll_DSKEWCALEN", - "value": "DSKEWCALEN_0" - }, - { - "attr": "pll_FRAC", - "value": "0" - }, - { - "attr": "pll_FBDIV", - "value": "__DONT__" - }, - { - "attr": "pll_REFDIV", - "value": "__DONT__" - }, - { - "attr": "pll_PLLEN", - "value": "__DONT__" - }, - { - "attr": "pll_POSTDIV1", - "value": "__DONT__" - }, - { - "attr": "pll_POSTDIV2", - "value": "__DONT__" - }, - { - "attr": "pll_DSMEN", - "value": "DSMEN_0" - }, - { - "attr": "pll_DACEN", - "value": "DACEN_0" - } - ] - } -} \ No newline at end of file diff --git a/tests/unittest/ModelConfig/ric/gbox_mode.api.json b/tests/unittest/ModelConfig/ric/gbox_mode.api.json index b551d4953..b628ebbaa 100644 --- a/tests/unittest/ModelConfig/ric/gbox_mode.api.json +++ b/tests/unittest/ModelConfig/ric/gbox_mode.api.json @@ -13,10 +13,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -61,10 +57,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -103,10 +95,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -151,10 +139,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -193,10 +177,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -241,10 +221,6 @@ "attr": "RX_MODE", "value": "RX_enable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -283,10 +259,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -331,10 +303,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded" @@ -373,10 +341,6 @@ "attr": "PEER_IS_ON", "value": "PEER_on" }, - { - "attr": "TX_CLOCK_IO", - "value": "TX_normal_IO" - }, { "attr": "TX_DDR_MODE", "value": "TX_direct" @@ -421,10 +385,6 @@ "attr": "RX_MODE", "value": "RX_disable" }, - { - "attr": "RX_CLOCK_IO", - "value": "RX_normal_IO" - }, { "attr": "DFEN", "value": "SingleEnded"