From 7487f92cda134d34c8e840f353213d8d1cfb85f1 Mon Sep 17 00:00:00 2001 From: NadeemYaseen Date: Thu, 3 Oct 2024 17:36:34 +0000 Subject: [PATCH 1/6] Added SIM change files from 1.5.7 --- blackbox_models/cell_sim_blackbox.v | 80 ++++++++++++++++++++++++- sim_models/verilog/DLY_SEL_DCODER.v | 74 ++++++++++++++++++++--- sim_models/verilog/DLY_SEL_DECODER.v | 89 ++++++++++++++++++++++++++++ 3 files changed, 231 insertions(+), 12 deletions(-) create mode 100644 sim_models/verilog/DLY_SEL_DECODER.v diff --git a/blackbox_models/cell_sim_blackbox.v b/blackbox_models/cell_sim_blackbox.v index b3c2234..563533f 100644 --- a/blackbox_models/cell_sim_blackbox.v +++ b/blackbox_models/cell_sim_blackbox.v @@ -94,7 +94,62 @@ module DLY_SEL_DCODER ( input logic DLY_ADJ, input logic DLY_INCDEC, input logic [4:0] DLY_ADDR, - output reg [2:0] DLY_CNTRL[31:0] + output reg [2:0] DLY0_CNTRL, + output reg [2:0] DLY1_CNTRL, + output reg [2:0] DLY2_CNTRL, + output reg [2:0] DLY3_CNTRL, + output reg [2:0] DLY4_CNTRL, + output reg [2:0] DLY5_CNTRL, + output reg [2:0] DLY6_CNTRL, + output reg [2:0] DLY7_CNTRL, + output reg [2:0] DLY8_CNTRL, + output reg [2:0] DLY9_CNTRL, + output reg [2:0] DLY10_CNTRL, + output reg [2:0] DLY11_CNTRL, + output reg [2:0] DLY12_CNTRL, + output reg [2:0] DLY13_CNTRL, + output reg [2:0] DLY14_CNTRL, + output reg [2:0] DLY15_CNTRL, + output reg [2:0] DLY16_CNTRL, + output reg [2:0] DLY17_CNTRL, + output reg [2:0] DLY18_CNTRL, + output reg [2:0] DLY19_CNTRL +); +endmodule +`endcelldefine +// +// DLY_SEL_DECODER black box model +// Address Decoder +// +// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved. +// +`celldefine +(* blackbox *) +module DLY_SEL_DECODER ( + input logic DLY_LOAD, + input logic DLY_ADJ, + input logic DLY_INCDEC, + input logic [4:0] DLY_ADDR, + output reg [2:0] DLY0_CNTRL, + output reg [2:0] DLY1_CNTRL, + output reg [2:0] DLY2_CNTRL, + output reg [2:0] DLY3_CNTRL, + output reg [2:0] DLY4_CNTRL, + output reg [2:0] DLY5_CNTRL, + output reg [2:0] DLY6_CNTRL, + output reg [2:0] DLY7_CNTRL, + output reg [2:0] DLY8_CNTRL, + output reg [2:0] DLY9_CNTRL, + output reg [2:0] DLY10_CNTRL, + output reg [2:0] DLY11_CNTRL, + output reg [2:0] DLY12_CNTRL, + output reg [2:0] DLY13_CNTRL, + output reg [2:0] DLY14_CNTRL, + output reg [2:0] DLY15_CNTRL, + output reg [2:0] DLY16_CNTRL, + output reg [2:0] DLY17_CNTRL, + output reg [2:0] DLY18_CNTRL, + output reg [2:0] DLY19_CNTRL ); endmodule `endcelldefine @@ -107,9 +162,28 @@ endmodule `celldefine (* blackbox *) module DLY_VALUE_MUX ( - input logic [5:0] DLY_TAP_VAL_ARRAY[19:0], + input logic [5:0] DLY_TAP0_VAL, + input logic [5:0] DLY_TAP1_VAL, + input logic [5:0] DLY_TAP2_VAL, + input logic [5:0] DLY_TAP3_VAL, + input logic [5:0] DLY_TAP4_VAL, + input logic [5:0] DLY_TAP5_VAL, + input logic [5:0] DLY_TAP6_VAL, + input logic [5:0] DLY_TAP7_VAL, + input logic [5:0] DLY_TAP8_VAL, + input logic [5:0] DLY_TAP9_VAL, + input logic [5:0] DLY_TAP10_VAL, + input logic [5:0] DLY_TAP11_VAL, + input logic [5:0] DLY_TAP12_VAL, + input logic [5:0] DLY_TAP13_VAL, + input logic [5:0] DLY_TAP14_VAL, + input logic [5:0] DLY_TAP15_VAL, + input logic [5:0] DLY_TAP16_VAL, + input logic [5:0] DLY_TAP17_VAL, + input logic [5:0] DLY_TAP18_VAL, + input logic [5:0] DLY_TAP19_VAL, input logic [4:0] DLY_ADDR, - output logic [5:0] DLY_TAP_VALUE + output reg [5:0] DLY_TAP_VALUE ); endmodule `endcelldefine diff --git a/sim_models/verilog/DLY_SEL_DCODER.v b/sim_models/verilog/DLY_SEL_DCODER.v index c3a50f2..1df79d5 100644 --- a/sim_models/verilog/DLY_SEL_DCODER.v +++ b/sim_models/verilog/DLY_SEL_DCODER.v @@ -12,20 +12,76 @@ module DLY_SEL_DCODER ( input DLY_ADJ, // Delay adjust input input DLY_INCDEC, // Delay increment / decrement input input [4:0] DLY_ADDR, // Input Address - output reg [2:0] DLY_CNTRL[31:0] // Output Bus + output reg [2:0] DLY0_CNTRL, // Output Bus + output reg [2:0] DLY1_CNTRL, // Output Bus + output reg [2:0] DLY2_CNTRL, // Output Bus + output reg [2:0] DLY3_CNTRL, // Output Bus + output reg [2:0] DLY4_CNTRL, // Output Bus + output reg [2:0] DLY5_CNTRL, // Output Bus + output reg [2:0] DLY6_CNTRL, // Output Bus + output reg [2:0] DLY7_CNTRL, // Output Bus + output reg [2:0] DLY8_CNTRL, // Output Bus + output reg [2:0] DLY9_CNTRL, // Output Bus + output reg [2:0] DLY10_CNTRL, // Output Bus + output reg [2:0] DLY11_CNTRL, // Output Bus + output reg [2:0] DLY12_CNTRL, // Output Bus + output reg [2:0] DLY13_CNTRL, // Output Bus + output reg [2:0] DLY14_CNTRL, // Output Bus + output reg [2:0] DLY15_CNTRL, // Output Bus + output reg [2:0] DLY16_CNTRL, // Output Bus + output reg [2:0] DLY17_CNTRL, // Output Bus + output reg [2:0] DLY18_CNTRL, // Output Bus + output reg [2:0] DLY19_CNTRL // Output Bus ); always @(*) begin - for(integer i=0; i<32;i=i+1) - begin - DLY_CNTRL[i] = 3'b000; - end - if (DLY_ADDR < 5'd20) - begin - DLY_CNTRL[DLY_ADDR] = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - end + DLY0_CNTRL = 3'b000; + DLY1_CNTRL = 3'b000; + DLY2_CNTRL = 3'b000; + DLY3_CNTRL = 3'b000; + DLY4_CNTRL = 3'b000; + DLY5_CNTRL = 3'b000; + DLY6_CNTRL = 3'b000; + DLY7_CNTRL = 3'b000; + DLY8_CNTRL = 3'b000; + DLY9_CNTRL = 3'b000; + DLY10_CNTRL = 3'b000; + DLY11_CNTRL = 3'b000; + DLY12_CNTRL = 3'b000; + DLY13_CNTRL = 3'b000; + DLY14_CNTRL = 3'b000; + DLY15_CNTRL = 3'b000; + DLY16_CNTRL = 3'b000; + DLY17_CNTRL = 3'b000; + DLY18_CNTRL = 3'b000; + DLY19_CNTRL = 3'b000; + + case(DLY_ADDR) + 5'd0: DLY0_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd1: DLY1_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd2: DLY2_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd3: DLY3_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd4: DLY4_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd5: DLY5_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd6: DLY6_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd7: DLY7_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd8: DLY8_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd9: DLY9_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd10: DLY10_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd11: DLY11_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd12: DLY12_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd13: DLY13_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd14: DLY14_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd15: DLY15_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd16: DLY16_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd17: DLY17_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd18: DLY18_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd19: DLY19_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + + endcase + end diff --git a/sim_models/verilog/DLY_SEL_DECODER.v b/sim_models/verilog/DLY_SEL_DECODER.v new file mode 100644 index 0000000..4bf4d79 --- /dev/null +++ b/sim_models/verilog/DLY_SEL_DECODER.v @@ -0,0 +1,89 @@ +`timescale 1ps/1ps +`celldefine +// +// DLY_SEL_DECODER simulation model +// Address Decoder +// +// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. +// + +module DLY_SEL_DECODER ( + input DLY_LOAD, // Delay load input + input DLY_ADJ, // Delay adjust input + input DLY_INCDEC, // Delay increment / decrement input + input [4:0] DLY_ADDR, // Input Address + output reg [2:0] DLY0_CNTRL, // Output Bus + output reg [2:0] DLY1_CNTRL, // Output Bus + output reg [2:0] DLY2_CNTRL, // Output Bus + output reg [2:0] DLY3_CNTRL, // Output Bus + output reg [2:0] DLY4_CNTRL, // Output Bus + output reg [2:0] DLY5_CNTRL, // Output Bus + output reg [2:0] DLY6_CNTRL, // Output Bus + output reg [2:0] DLY7_CNTRL, // Output Bus + output reg [2:0] DLY8_CNTRL, // Output Bus + output reg [2:0] DLY9_CNTRL, // Output Bus + output reg [2:0] DLY10_CNTRL, // Output Bus + output reg [2:0] DLY11_CNTRL, // Output Bus + output reg [2:0] DLY12_CNTRL, // Output Bus + output reg [2:0] DLY13_CNTRL, // Output Bus + output reg [2:0] DLY14_CNTRL, // Output Bus + output reg [2:0] DLY15_CNTRL, // Output Bus + output reg [2:0] DLY16_CNTRL, // Output Bus + output reg [2:0] DLY17_CNTRL, // Output Bus + output reg [2:0] DLY18_CNTRL, // Output Bus + output reg [2:0] DLY19_CNTRL // Output Bus +); + + +always @(*) +begin + DLY0_CNTRL = 3'b000; + DLY1_CNTRL = 3'b000; + DLY2_CNTRL = 3'b000; + DLY3_CNTRL = 3'b000; + DLY4_CNTRL = 3'b000; + DLY5_CNTRL = 3'b000; + DLY6_CNTRL = 3'b000; + DLY7_CNTRL = 3'b000; + DLY8_CNTRL = 3'b000; + DLY9_CNTRL = 3'b000; + DLY10_CNTRL = 3'b000; + DLY11_CNTRL = 3'b000; + DLY12_CNTRL = 3'b000; + DLY13_CNTRL = 3'b000; + DLY14_CNTRL = 3'b000; + DLY15_CNTRL = 3'b000; + DLY16_CNTRL = 3'b000; + DLY17_CNTRL = 3'b000; + DLY18_CNTRL = 3'b000; + DLY19_CNTRL = 3'b000; + + case(DLY_ADDR) + 5'd0: DLY0_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd1: DLY1_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd2: DLY2_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd3: DLY3_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd4: DLY4_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd5: DLY5_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd6: DLY6_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd7: DLY7_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd8: DLY8_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd9: DLY9_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd10: DLY10_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd11: DLY11_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd12: DLY12_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd13: DLY13_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd14: DLY14_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd15: DLY15_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd16: DLY16_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd17: DLY17_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd18: DLY18_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + 5'd19: DLY19_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; + + endcase + +end + + +endmodule +`endcelldefine From c806ffff9646b349d29262cfcb56ea675840fba2 Mon Sep 17 00:00:00 2001 From: moinijaz Date: Mon, 7 Oct 2024 12:41:18 +0500 Subject: [PATCH 2/6] DLY_SEL_SECODER tb updated --- sim_models/tb/DLY_SEL_DECODER_tb.v | 2 +- tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sim_models/tb/DLY_SEL_DECODER_tb.v b/sim_models/tb/DLY_SEL_DECODER_tb.v index b55be7d..0625f23 100644 --- a/sim_models/tb/DLY_SEL_DECODER_tb.v +++ b/sim_models/tb/DLY_SEL_DECODER_tb.v @@ -1,5 +1,5 @@ -module DLY_SEL_DCODER_tb; +module DLY_SEL_DECODER_tb; // Parameters diff --git a/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v b/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v index b55be7d..0625f23 100644 --- a/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v +++ b/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v @@ -1,5 +1,5 @@ -module DLY_SEL_DCODER_tb; +module DLY_SEL_DECODER_tb; // Parameters From 924b6f824e7b7bc8ffc2206fe12b9b67fea5125c Mon Sep 17 00:00:00 2001 From: moinijaz Date: Mon, 7 Oct 2024 12:42:13 +0500 Subject: [PATCH 3/6] DLY_SEL_SECODER tb updated --- sim_models/tb/DLY_SEL_DECODER_tb.v | 2 +- tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sim_models/tb/DLY_SEL_DECODER_tb.v b/sim_models/tb/DLY_SEL_DECODER_tb.v index 0625f23..e9e1e5e 100644 --- a/sim_models/tb/DLY_SEL_DECODER_tb.v +++ b/sim_models/tb/DLY_SEL_DECODER_tb.v @@ -10,7 +10,7 @@ module DLY_SEL_DECODER_tb; reg [4:0] DLY_ADDR; wire [2:0] DLY_CNTRL[31:0]; - DLY_SEL_DCODER DLY_SEL_DCODER_inst ( + DLY_SEL_DECODER DLY_SEL_DECODER_inst ( .DLY_LOAD(DLY_LOAD), .DLY_ADJ(DLY_ADJ), .DLY_INCDEC(DLY_INCDEC), diff --git a/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v b/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v index 0625f23..e9e1e5e 100644 --- a/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v +++ b/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v @@ -10,7 +10,7 @@ module DLY_SEL_DECODER_tb; reg [4:0] DLY_ADDR; wire [2:0] DLY_CNTRL[31:0]; - DLY_SEL_DCODER DLY_SEL_DCODER_inst ( + DLY_SEL_DECODER DLY_SEL_DECODER_inst ( .DLY_LOAD(DLY_LOAD), .DLY_ADJ(DLY_ADJ), .DLY_INCDEC(DLY_INCDEC), From bf0c314ba220d5013874f77d3a4101eb0210e509 Mon Sep 17 00:00:00 2001 From: moinijaz Date: Mon, 7 Oct 2024 12:42:35 +0500 Subject: [PATCH 4/6] DLY_SEL_DCODER renamed --- sim_models/verilog/DLY_SEL_DCODER.v | 89 ----------------------------- 1 file changed, 89 deletions(-) delete mode 100644 sim_models/verilog/DLY_SEL_DCODER.v diff --git a/sim_models/verilog/DLY_SEL_DCODER.v b/sim_models/verilog/DLY_SEL_DCODER.v deleted file mode 100644 index 1df79d5..0000000 --- a/sim_models/verilog/DLY_SEL_DCODER.v +++ /dev/null @@ -1,89 +0,0 @@ -`timescale 1ps/1ps -`celldefine -// -// DLY_SEL_DCODER simulation model -// Address Decoder -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module DLY_SEL_DCODER ( - input DLY_LOAD, // Delay load input - input DLY_ADJ, // Delay adjust input - input DLY_INCDEC, // Delay increment / decrement input - input [4:0] DLY_ADDR, // Input Address - output reg [2:0] DLY0_CNTRL, // Output Bus - output reg [2:0] DLY1_CNTRL, // Output Bus - output reg [2:0] DLY2_CNTRL, // Output Bus - output reg [2:0] DLY3_CNTRL, // Output Bus - output reg [2:0] DLY4_CNTRL, // Output Bus - output reg [2:0] DLY5_CNTRL, // Output Bus - output reg [2:0] DLY6_CNTRL, // Output Bus - output reg [2:0] DLY7_CNTRL, // Output Bus - output reg [2:0] DLY8_CNTRL, // Output Bus - output reg [2:0] DLY9_CNTRL, // Output Bus - output reg [2:0] DLY10_CNTRL, // Output Bus - output reg [2:0] DLY11_CNTRL, // Output Bus - output reg [2:0] DLY12_CNTRL, // Output Bus - output reg [2:0] DLY13_CNTRL, // Output Bus - output reg [2:0] DLY14_CNTRL, // Output Bus - output reg [2:0] DLY15_CNTRL, // Output Bus - output reg [2:0] DLY16_CNTRL, // Output Bus - output reg [2:0] DLY17_CNTRL, // Output Bus - output reg [2:0] DLY18_CNTRL, // Output Bus - output reg [2:0] DLY19_CNTRL // Output Bus -); - - -always @(*) -begin - DLY0_CNTRL = 3'b000; - DLY1_CNTRL = 3'b000; - DLY2_CNTRL = 3'b000; - DLY3_CNTRL = 3'b000; - DLY4_CNTRL = 3'b000; - DLY5_CNTRL = 3'b000; - DLY6_CNTRL = 3'b000; - DLY7_CNTRL = 3'b000; - DLY8_CNTRL = 3'b000; - DLY9_CNTRL = 3'b000; - DLY10_CNTRL = 3'b000; - DLY11_CNTRL = 3'b000; - DLY12_CNTRL = 3'b000; - DLY13_CNTRL = 3'b000; - DLY14_CNTRL = 3'b000; - DLY15_CNTRL = 3'b000; - DLY16_CNTRL = 3'b000; - DLY17_CNTRL = 3'b000; - DLY18_CNTRL = 3'b000; - DLY19_CNTRL = 3'b000; - - case(DLY_ADDR) - 5'd0: DLY0_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd1: DLY1_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd2: DLY2_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd3: DLY3_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd4: DLY4_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd5: DLY5_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd6: DLY6_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd7: DLY7_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd8: DLY8_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd9: DLY9_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd10: DLY10_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd11: DLY11_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd12: DLY12_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd13: DLY13_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd14: DLY14_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd15: DLY15_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd16: DLY16_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd17: DLY17_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd18: DLY18_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - 5'd19: DLY19_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC}; - - endcase - -end - - -endmodule -`endcelldefine From 24fb40f3823768a7e32e655bd18cbff91588ea36 Mon Sep 17 00:00:00 2001 From: moinijaz Date: Mon, 7 Oct 2024 12:45:44 +0500 Subject: [PATCH 5/6] DLY_SEL_DECODER tb updated --- sim_models/tb/DLY_SEL_DECODER_tb.v | 223 +++++++++++++++++++----- tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v | 223 +++++++++++++++++++----- 2 files changed, 352 insertions(+), 94 deletions(-) diff --git a/sim_models/tb/DLY_SEL_DECODER_tb.v b/sim_models/tb/DLY_SEL_DECODER_tb.v index e9e1e5e..a725d0b 100644 --- a/sim_models/tb/DLY_SEL_DECODER_tb.v +++ b/sim_models/tb/DLY_SEL_DECODER_tb.v @@ -4,62 +4,191 @@ module DLY_SEL_DECODER_tb; // Parameters //Ports - reg DLY_LOAD; - reg DLY_ADJ; - reg DLY_INCDEC; + reg DLY_LOAD; + reg DLY_ADJ; + reg DLY_INCDEC; reg [4:0] DLY_ADDR; - wire [2:0] DLY_CNTRL[31:0]; + wire [2:0] DLY0_CNTRL; + wire [2:0] DLY1_CNTRL; + wire [2:0] DLY2_CNTRL; + wire [2:0] DLY3_CNTRL; + wire [2:0] DLY4_CNTRL; + wire [2:0] DLY5_CNTRL; + wire [2:0] DLY6_CNTRL; + wire [2:0] DLY7_CNTRL; + wire [2:0] DLY8_CNTRL; + wire [2:0] DLY9_CNTRL; + wire [2:0] DLY10_CNTRL; + wire [2:0] DLY11_CNTRL; + wire [2:0] DLY12_CNTRL; + wire [2:0] DLY13_CNTRL; + wire [2:0] DLY14_CNTRL; + wire [2:0] DLY15_CNTRL; + wire [2:0] DLY16_CNTRL; + wire [2:0] DLY17_CNTRL; + wire [2:0] DLY18_CNTRL; + wire [2:0] DLY19_CNTRL; + + integer error=0; DLY_SEL_DECODER DLY_SEL_DECODER_inst ( .DLY_LOAD(DLY_LOAD), .DLY_ADJ(DLY_ADJ), .DLY_INCDEC(DLY_INCDEC), .DLY_ADDR(DLY_ADDR), - .DLY_CNTRL(DLY_CNTRL) + .DLY0_CNTRL(DLY0_CNTRL), + .DLY1_CNTRL(DLY1_CNTRL), + .DLY2_CNTRL(DLY2_CNTRL), + .DLY3_CNTRL(DLY3_CNTRL), + .DLY4_CNTRL(DLY4_CNTRL), + .DLY5_CNTRL(DLY5_CNTRL), + .DLY6_CNTRL(DLY6_CNTRL), + .DLY7_CNTRL(DLY7_CNTRL), + .DLY8_CNTRL(DLY8_CNTRL), + .DLY9_CNTRL(DLY9_CNTRL), + .DLY10_CNTRL(DLY10_CNTRL), + .DLY11_CNTRL(DLY11_CNTRL), + .DLY12_CNTRL(DLY12_CNTRL), + .DLY13_CNTRL(DLY13_CNTRL), + .DLY14_CNTRL(DLY14_CNTRL), + .DLY15_CNTRL(DLY15_CNTRL), + .DLY16_CNTRL(DLY16_CNTRL), + .DLY17_CNTRL(DLY17_CNTRL), + .DLY18_CNTRL(DLY18_CNTRL), + .DLY19_CNTRL(DLY19_CNTRL) ); -initial -begin - DLY_LOAD=0; - DLY_ADJ=0; - DLY_INCDEC=0; - DLY_ADDR=0; - #5; - repeat(5) - begin - DLY_LOAD=$urandom; - DLY_ADJ=$urandom; - DLY_INCDEC=$urandom; - DLY_ADDR=$urandom; - #10; - // $display("Bus Array Content:"); - // for (integer i = 0; i < 32; i = i + 1) begin - // $display("DLY_CNTRL[%0d] = %b", i, DLY_CNTRL[i]); - // #2; - // end - if(DLY_ADDR<20) - begin - if(DLY_CNTRL[DLY_ADDR]==={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) - $display("Test Passed"); - else - $display("Test Failed"); - end - else - begin - if(DLY_CNTRL[DLY_ADDR]===3'b000) - $display("Test Passed"); - else - $display("Test Failed"); - end - #100; - end - #1000; - $finish; -end -initial -begin + + initial + begin + DLY_LOAD=0; + DLY_ADJ=0; + DLY_INCDEC=0; + DLY_ADDR=0; + #5; + repeat(100) + begin + DLY_LOAD=$urandom; + DLY_ADJ=$urandom; + DLY_INCDEC=$urandom; + DLY_ADDR=$urandom; + #10; + if(DLY_ADDR===0) + begin + if(DLY0_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + + if(DLY_ADDR===1) + begin + if(DLY1_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + + if(DLY_ADDR===2) + begin + if(DLY2_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===3) + begin + if(DLY3_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===4) + begin + if(DLY4_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===5) + begin + if(DLY5_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===6) + begin + if(DLY6_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===7) + begin + if(DLY7_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===8) + begin + if(DLY8_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===9) + begin + if(DLY9_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===10) + begin + if(DLY10_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===11) + begin + if(DLY11_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===12) + begin + if(DLY12_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===13) + begin + if(DLY13_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===14) + begin + if(DLY14_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===15) + begin + if(DLY15_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===16) + begin + if(DLY16_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===17) + begin + if(DLY17_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===18) + begin + if(DLY18_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===19) + begin + if(DLY19_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + + #100; + end + if(error===0) + $display("Test Passed"); + else + $display("Test Failed"); + #1000; + $finish; + end + initial + begin $dumpfile("waves.vcd"); $dumpvars; -end -endmodule + end +endmodule \ No newline at end of file diff --git a/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v b/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v index e9e1e5e..a725d0b 100644 --- a/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v +++ b/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v @@ -4,62 +4,191 @@ module DLY_SEL_DECODER_tb; // Parameters //Ports - reg DLY_LOAD; - reg DLY_ADJ; - reg DLY_INCDEC; + reg DLY_LOAD; + reg DLY_ADJ; + reg DLY_INCDEC; reg [4:0] DLY_ADDR; - wire [2:0] DLY_CNTRL[31:0]; + wire [2:0] DLY0_CNTRL; + wire [2:0] DLY1_CNTRL; + wire [2:0] DLY2_CNTRL; + wire [2:0] DLY3_CNTRL; + wire [2:0] DLY4_CNTRL; + wire [2:0] DLY5_CNTRL; + wire [2:0] DLY6_CNTRL; + wire [2:0] DLY7_CNTRL; + wire [2:0] DLY8_CNTRL; + wire [2:0] DLY9_CNTRL; + wire [2:0] DLY10_CNTRL; + wire [2:0] DLY11_CNTRL; + wire [2:0] DLY12_CNTRL; + wire [2:0] DLY13_CNTRL; + wire [2:0] DLY14_CNTRL; + wire [2:0] DLY15_CNTRL; + wire [2:0] DLY16_CNTRL; + wire [2:0] DLY17_CNTRL; + wire [2:0] DLY18_CNTRL; + wire [2:0] DLY19_CNTRL; + + integer error=0; DLY_SEL_DECODER DLY_SEL_DECODER_inst ( .DLY_LOAD(DLY_LOAD), .DLY_ADJ(DLY_ADJ), .DLY_INCDEC(DLY_INCDEC), .DLY_ADDR(DLY_ADDR), - .DLY_CNTRL(DLY_CNTRL) + .DLY0_CNTRL(DLY0_CNTRL), + .DLY1_CNTRL(DLY1_CNTRL), + .DLY2_CNTRL(DLY2_CNTRL), + .DLY3_CNTRL(DLY3_CNTRL), + .DLY4_CNTRL(DLY4_CNTRL), + .DLY5_CNTRL(DLY5_CNTRL), + .DLY6_CNTRL(DLY6_CNTRL), + .DLY7_CNTRL(DLY7_CNTRL), + .DLY8_CNTRL(DLY8_CNTRL), + .DLY9_CNTRL(DLY9_CNTRL), + .DLY10_CNTRL(DLY10_CNTRL), + .DLY11_CNTRL(DLY11_CNTRL), + .DLY12_CNTRL(DLY12_CNTRL), + .DLY13_CNTRL(DLY13_CNTRL), + .DLY14_CNTRL(DLY14_CNTRL), + .DLY15_CNTRL(DLY15_CNTRL), + .DLY16_CNTRL(DLY16_CNTRL), + .DLY17_CNTRL(DLY17_CNTRL), + .DLY18_CNTRL(DLY18_CNTRL), + .DLY19_CNTRL(DLY19_CNTRL) ); -initial -begin - DLY_LOAD=0; - DLY_ADJ=0; - DLY_INCDEC=0; - DLY_ADDR=0; - #5; - repeat(5) - begin - DLY_LOAD=$urandom; - DLY_ADJ=$urandom; - DLY_INCDEC=$urandom; - DLY_ADDR=$urandom; - #10; - // $display("Bus Array Content:"); - // for (integer i = 0; i < 32; i = i + 1) begin - // $display("DLY_CNTRL[%0d] = %b", i, DLY_CNTRL[i]); - // #2; - // end - if(DLY_ADDR<20) - begin - if(DLY_CNTRL[DLY_ADDR]==={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) - $display("Test Passed"); - else - $display("Test Failed"); - end - else - begin - if(DLY_CNTRL[DLY_ADDR]===3'b000) - $display("Test Passed"); - else - $display("Test Failed"); - end - #100; - end - #1000; - $finish; -end -initial -begin + + initial + begin + DLY_LOAD=0; + DLY_ADJ=0; + DLY_INCDEC=0; + DLY_ADDR=0; + #5; + repeat(100) + begin + DLY_LOAD=$urandom; + DLY_ADJ=$urandom; + DLY_INCDEC=$urandom; + DLY_ADDR=$urandom; + #10; + if(DLY_ADDR===0) + begin + if(DLY0_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + + if(DLY_ADDR===1) + begin + if(DLY1_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + + if(DLY_ADDR===2) + begin + if(DLY2_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===3) + begin + if(DLY3_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===4) + begin + if(DLY4_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===5) + begin + if(DLY5_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===6) + begin + if(DLY6_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===7) + begin + if(DLY7_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===8) + begin + if(DLY8_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===9) + begin + if(DLY9_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===10) + begin + if(DLY10_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===11) + begin + if(DLY11_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===12) + begin + if(DLY12_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===13) + begin + if(DLY13_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===14) + begin + if(DLY14_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===15) + begin + if(DLY15_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===16) + begin + if(DLY16_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===17) + begin + if(DLY17_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===18) + begin + if(DLY18_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + if(DLY_ADDR===19) + begin + if(DLY19_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC}) + error++; + end + + #100; + end + if(error===0) + $display("Test Passed"); + else + $display("Test Failed"); + #1000; + $finish; + end + initial + begin $dumpfile("waves.vcd"); $dumpvars; -end -endmodule + end +endmodule \ No newline at end of file From eb0b0e4c3600e60b8713721072cb70d0a0106ea1 Mon Sep 17 00:00:00 2001 From: moinijaz Date: Mon, 7 Oct 2024 17:31:58 +0500 Subject: [PATCH 6/6] merged main into this branch --- sim_models/tb/DLY_SEL_DECODER_tb.v | 5 ----- tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v | 5 ----- 2 files changed, 10 deletions(-) diff --git a/sim_models/tb/DLY_SEL_DECODER_tb.v b/sim_models/tb/DLY_SEL_DECODER_tb.v index 29d2970..a725d0b 100644 --- a/sim_models/tb/DLY_SEL_DECODER_tb.v +++ b/sim_models/tb/DLY_SEL_DECODER_tb.v @@ -28,11 +28,6 @@ module DLY_SEL_DECODER_tb; wire [2:0] DLY17_CNTRL; wire [2:0] DLY18_CNTRL; wire [2:0] DLY19_CNTRL; -<<<<<<< HEAD -======= - - integer error=0; ->>>>>>> 505331e58b8bc815c4d764074c09ee8d1cbe367e integer error=0; diff --git a/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v b/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v index 29d2970..a725d0b 100644 --- a/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v +++ b/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v @@ -28,11 +28,6 @@ module DLY_SEL_DECODER_tb; wire [2:0] DLY17_CNTRL; wire [2:0] DLY18_CNTRL; wire [2:0] DLY19_CNTRL; -<<<<<<< HEAD -======= - - integer error=0; ->>>>>>> 505331e58b8bc815c4d764074c09ee8d1cbe367e integer error=0;