diff --git a/sim_models/tb/MIPI_TX_tb.v b/sim_models/tb/MIPI_TX_tb.v
index 92161a8..dffce20 100644
--- a/sim_models/tb/MIPI_TX_tb.v
+++ b/sim_models/tb/MIPI_TX_tb.v
@@ -151,4 +151,4 @@ module MIPI_TX_tb;
     $dumpfile("waves.vcd");
     $dumpvars;
 	end
-endmodule
+endmodule
\ No newline at end of file
diff --git a/sim_models/tb/SOC_FPGA_INTF_IRQ_tb.v b/sim_models/tb/SOC_FPGA_INTF_IRQ_tb.v
new file mode 100644
index 0000000..e3fc69c
--- /dev/null
+++ b/sim_models/tb/SOC_FPGA_INTF_IRQ_tb.v
@@ -0,0 +1,51 @@
+
+module SOC_FPGA_INTF_IRQ_tb;
+  reg IRQ_CLK;
+  reg IRQ_RST_N;
+  reg [3:0] IRQ_SRC;
+  wire [3:0] IRQ_SET;
+
+  reg [3:0] irq_src;
+
+    SOC_FPGA_INTF_IRQ soc_fpga_intf_irq(
+    .IRQ_SRC(IRQ_SRC),
+    .IRQ_SET(IRQ_SET),
+    .IRQ_CLK(IRQ_CLK),
+    .IRQ_RST_N(IRQ_RST_N)
+    );
+
+    initial begin
+      //generating clock
+      IRQ_CLK = 0;
+      forever #5 IRQ_CLK = ~IRQ_CLK;
+    end
+
+    initial begin
+      IRQ_SRC = 0;
+      IRQ_RST_N = 0;
+
+      repeat(2) @(posedge IRQ_CLK);
+      IRQ_RST_N = 1;
+
+      for (int i=0; i<10; i++) begin
+        IRQ_SRC = $random();
+        @(posedge IRQ_CLK);
+      end
+
+      $finish;
+
+    end
+
+    always @(posedge IRQ_CLK) irq_src <= IRQ_SRC;
+
+    initial begin 
+      forever begin
+        if(IRQ_RST_N)
+         if (IRQ_SET == irq_src) 
+          $info("True IRQ_SET");
+         else $error("False IRQ_SET %0d , IRQ_SRC %0d ", IRQ_SET ,irq_src );
+        @(posedge IRQ_CLK);
+      end
+    end
+
+endmodule
diff --git a/sim_models/tb/SOC_FPGA_INTF_JTAG_tb.v b/sim_models/tb/SOC_FPGA_INTF_JTAG_tb.v
new file mode 100644
index 0000000..6577479
--- /dev/null
+++ b/sim_models/tb/SOC_FPGA_INTF_JTAG_tb.v
@@ -0,0 +1,71 @@
+`timescale 1ns/1ps
+
+module SOC_FPGA_INTF_JTAG_tb;
+
+  // Inputs
+  reg BOOT_JTAG_TCK;
+  reg BOOT_JTAG_TDO;
+  reg BOOT_JTAG_EN;
+
+  // Outputs
+  wire BOOT_JTAG_TDI;
+  wire BOOT_JTAG_TMS;
+  wire BOOT_JTAG_TRSTN;
+
+  reg [3:0] tdo;
+
+  SOC_FPGA_INTF_JTAG dut (
+    .BOOT_JTAG_TCK(BOOT_JTAG_TCK),
+    .BOOT_JTAG_TDI(BOOT_JTAG_TDI),
+    .BOOT_JTAG_TDO(BOOT_JTAG_TDO),
+    .BOOT_JTAG_TMS(BOOT_JTAG_TMS),
+    .BOOT_JTAG_TRSTN(BOOT_JTAG_TRSTN),
+    .BOOT_JTAG_EN(BOOT_JTAG_EN)
+  );
+
+
+  initial begin
+    BOOT_JTAG_TCK = 0;
+    forever #5 BOOT_JTAG_TCK = ~BOOT_JTAG_TCK;
+  end
+
+
+  // Stimulus
+  initial begin
+
+    BOOT_JTAG_TDO = 1'b0;
+    BOOT_JTAG_EN = 1'b0;
+
+    #10;
+
+    for (int i=0; i<10; i++) begin
+        BOOT_JTAG_TDO = ~BOOT_JTAG_TDO;
+      @(posedge BOOT_JTAG_TCK);
+    end
+
+    #10;
+
+    BOOT_JTAG_EN = 1'b1;
+
+    for (int i=0; i<10; i++) begin
+        BOOT_JTAG_TDO = ~BOOT_JTAG_TDO;
+      @(posedge BOOT_JTAG_TCK);
+    end
+
+    #10;
+    $finish;
+  end
+
+  always @(posedge BOOT_JTAG_TCK) tdo <= BOOT_JTAG_TDO;
+
+    initial begin 
+      forever begin
+        if(BOOT_JTAG_TRSTN && BOOT_JTAG_TMS)
+         if (BOOT_JTAG_TDI == tdo) 
+          $info("True BOOT_JTAG_TDI");
+         else $error("False BOOT_JTAG_TDI %0d , BOOT_JTAG_TDO %0d ", BOOT_JTAG_TDI ,tdo );
+        @(posedge BOOT_JTAG_TCK);
+      end
+    end
+
+endmodule
diff --git a/sim_models/verilog/DLY_SEL_DCODER.v b/sim_models/verilog/DLY_SEL_DCODER.v
deleted file mode 100644
index 1df79d5..0000000
--- a/sim_models/verilog/DLY_SEL_DCODER.v
+++ /dev/null
@@ -1,89 +0,0 @@
-`timescale 1ps/1ps
-`celldefine
-//
-// DLY_SEL_DCODER simulation model
-// Address Decoder
-//
-// Copyright (c) 2023 Rapid Silicon, Inc.  All rights reserved.
-//
-
-module DLY_SEL_DCODER (
-  input DLY_LOAD, // Delay load input
-  input DLY_ADJ, // Delay adjust input
-  input DLY_INCDEC, // Delay increment / decrement input
-  input [4:0] DLY_ADDR, // Input Address
-  output reg [2:0] DLY0_CNTRL, // Output Bus
-  output reg [2:0] DLY1_CNTRL, // Output Bus
-  output reg [2:0] DLY2_CNTRL, // Output Bus
-  output reg [2:0] DLY3_CNTRL, // Output Bus
-  output reg [2:0] DLY4_CNTRL, // Output Bus
-  output reg [2:0] DLY5_CNTRL, // Output Bus
-  output reg [2:0] DLY6_CNTRL, // Output Bus
-  output reg [2:0] DLY7_CNTRL, // Output Bus
-  output reg [2:0] DLY8_CNTRL, // Output Bus
-  output reg [2:0] DLY9_CNTRL, // Output Bus
-  output reg [2:0] DLY10_CNTRL, // Output Bus
-  output reg [2:0] DLY11_CNTRL, // Output Bus
-  output reg [2:0] DLY12_CNTRL, // Output Bus
-  output reg [2:0] DLY13_CNTRL, // Output Bus
-  output reg [2:0] DLY14_CNTRL, // Output Bus
-  output reg [2:0] DLY15_CNTRL, // Output Bus
-  output reg [2:0] DLY16_CNTRL, // Output Bus
-  output reg [2:0] DLY17_CNTRL, // Output Bus
-  output reg [2:0] DLY18_CNTRL, // Output Bus
-  output reg [2:0] DLY19_CNTRL // Output Bus
-);
-
-
-always @(*) 
-begin
-  DLY0_CNTRL  = 3'b000;
-  DLY1_CNTRL  = 3'b000;
-  DLY2_CNTRL  = 3'b000;
-  DLY3_CNTRL  = 3'b000;
-  DLY4_CNTRL  = 3'b000;
-  DLY5_CNTRL  = 3'b000;
-  DLY6_CNTRL  = 3'b000;
-  DLY7_CNTRL  = 3'b000;
-  DLY8_CNTRL  = 3'b000;
-  DLY9_CNTRL  = 3'b000;
-  DLY10_CNTRL = 3'b000;
-  DLY11_CNTRL = 3'b000;
-  DLY12_CNTRL = 3'b000;
-  DLY13_CNTRL = 3'b000;
-  DLY14_CNTRL = 3'b000;
-  DLY15_CNTRL = 3'b000;
-  DLY16_CNTRL = 3'b000;
-  DLY17_CNTRL = 3'b000;
-  DLY18_CNTRL = 3'b000;
-  DLY19_CNTRL = 3'b000;
-
-  case(DLY_ADDR)
-    5'd0:  DLY0_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd1:  DLY1_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd2:  DLY2_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd3:  DLY3_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd4:  DLY4_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd5:  DLY5_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd6:  DLY6_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd7:  DLY7_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd8:  DLY8_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd9:  DLY9_CNTRL  = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd10: DLY10_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd11: DLY11_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd12: DLY12_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd13: DLY13_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd14: DLY14_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd15: DLY15_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd16: DLY16_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd17: DLY17_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd18: DLY18_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-    5'd19: DLY19_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
-  
-  endcase
-
-end
-
-
-endmodule
-`endcelldefine
diff --git a/specs_internal/DLY_SEL_DECODER.yaml b/specs_internal/DLY_SEL_DECODER.yaml
new file mode 100644
index 0000000..f2c1351
--- /dev/null
+++ b/specs_internal/DLY_SEL_DECODER.yaml
@@ -0,0 +1,144 @@
+# Periphery Primitives Parameters and Properties (P4)
+#
+# This file contains the list of Verilog parameters and SDC properties that are
+# allowed for periphery primitives.
+#
+# See https://rapidsilicon.atlassian.net/wiki/spaces/RS/pages/214368265/Periphery+Primitive+Parameters+and+Properties+Definitions+P4DEF for more details
+#
+# The name needs to match the filename root
+# name: <primitive name>
+# desc: <optional description>
+#
+# ports:
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#
+# # set as Verilog parameter
+# parameters:
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>  
+#
+# # set in SDC or by synthesis attribute
+# properties:
+#    <property_name>:
+#        desc: <description>
+#        values: 
+#          - <enum_name>
+#          - <enum_name>
+#    <property_name>:
+#        desc: <description>
+#          - <enum_name>
+#          - <enum_name>
+#
+# primitive name should match the filename root.
+name: DLY_SEL_DECODER
+desc: Address Decoder
+category: periphery
+timescale: 1ps/1ps
+
+ports:
+   DLY_LOAD:
+     dir: input
+     desc: Delay load input
+   DLY_ADJ:
+     dir: input
+     desc: Delay adjust input
+   DLY_INCDEC:
+     dir: input
+     desc: Delay increment / decrement input
+   DLY_ADDR[4:0]:
+     dir: input
+     desc: Input Address
+   DLY0_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY1_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY2_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY3_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY4_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY5_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY6_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY7_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY8_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY9_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY10_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY11_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY12_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY13_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY14_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY15_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY16_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY17_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY18_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY19_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+     
\ No newline at end of file
diff --git a/specs_internal/DLY_VALUE_MUX.yaml b/specs_internal/DLY_VALUE_MUX.yaml
new file mode 100644
index 0000000..c028094
--- /dev/null
+++ b/specs_internal/DLY_VALUE_MUX.yaml
@@ -0,0 +1,118 @@
+# Periphery Primitives Parameters and Properties (P4)
+#
+# This file contains the list of Verilog parameters and SDC properties that are
+# allowed for periphery primitives.
+#
+# See https://rapidsilicon.atlassian.net/wiki/spaces/RS/pages/214368265/Periphery+Primitive+Parameters+and+Properties+Definitions+P4DEF for more details
+#
+# The name needs to match the filename root
+# name: <primitive name>
+# desc: <optional description>
+#
+# ports:
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#
+# # set as Verilog parameter
+# parameters:
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>  
+#
+# # set in SDC or by synthesis attribute
+# properties:
+#    <property_name>:
+#        desc: <description>
+#        values: 
+#          - <enum_name>
+#          - <enum_name>
+#    <property_name>:
+#        desc: <description>
+#          - <enum_name>
+#          - <enum_name>
+#
+# primitive name should match the filename root.
+name: DLY_VALUE_MUX
+desc: Multiplexer
+category: periphery
+timescale: 1ps/1ps
+
+ports:
+   DLY_TAP0_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP1_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP2_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP3_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP4_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP5_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP6_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP7_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP8_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP9_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP10_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP11_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP12_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP13_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP14_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP15_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP16_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP17_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP18_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_TAP19_VAL[5:0]:
+     dir: input
+     desc: Delay Tap Value Input Port
+   DLY_ADDR[4:0]:
+     dir: input
+     desc: Input Address
+   DLY_TAP_VALUE[5:0]:
+     dir: output
+     desc: Delay Tap Value Output Port
+     type: reg
diff --git a/specs_internal/MIPI_RX.yaml b/specs_internal/MIPI_RX.yaml
new file mode 100644
index 0000000..1008127
--- /dev/null
+++ b/specs_internal/MIPI_RX.yaml
@@ -0,0 +1,128 @@
+# Periphery Primitives Parameters and Properties (P4)
+#
+# This file contains the list of Verilog parameters and SDC properties that are
+# allowed for periphery primitives.
+#
+# See https://rapidsilicon.atlassian.net/wiki/spaces/RS/pages/214368265/Periphery+Primitive+Parameters+and+Properties+Definitions+P4DEF for more details
+#
+# The name needs to match the filename root
+# name: <primitive name>
+# desc: <optional description>
+#
+# ports:
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#
+# # set as Verilog parameter
+# parameters:
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>  
+#
+# # set in SDC or by synthesis attribute
+# properties:
+#    <property_name>:
+#        desc: <description>
+#        values: 
+#          - <enum_name>
+#          - <enum_name>
+#    <property_name>:
+#        desc: <description>
+#          - <enum_name>
+#          - <enum_name>
+#
+# primitive name should match the filename root.
+name: MIPI_RX
+desc: MIPI Receiver
+category: periphery
+
+ports:
+   RST:
+     dir: input
+     desc: Active-low, asynchronous reset
+   RX_CLK:
+     dir: input
+     desc: MIPI RX_IO clock input, PLL_CLK
+   PLL_LOCK:
+     dir: input
+     desc: PLL lock input
+   CLK_IN: 
+     dir: input
+     desc: Fabric core clock input
+     bb_attributes: clkbuf_sink
+   RX_DP:
+     dir: input
+     desc: MIPI RX Data Positive input From I_BUF
+   RX_DN:
+     dir: input
+     desc: MIPI RX Data Negative input from I_BUF
+   HS_EN:
+     dir: input
+     desc: EN HS Data input (From Fabric). Active high signal. This is a common signal between MIPI RX/TX interface. 
+   LP_EN:
+     dir: input
+     desc: EN LP Data input (From Fabric). This is a common signal between MIPI RX/TX interface.
+   RX_TERM_EN:
+     dir: input
+     desc: EN Differential Termination
+   BITSLIP_ADJ:
+     dir: input
+     desc: BITSLIP_ADJ input from Fabric
+   DLY_LOAD:
+     dir: input
+     desc: Delay load input, from Fabric 
+   DLY_ADJ:
+     dir: input
+     desc: Delay adjust input, from Fabric
+   DLY_INCDEC:
+     dir: input
+     desc: Delay increment / decrement input, from Fabric
+   DLY_TAP_VALUE[5:0]:
+     dir: output
+     desc: Delay tap value output to fabric
+   HS_RX_DATA[WIDTH-1:0]:
+     dir: output
+     desc: HS RX Data output to Fabric
+   HS_RXD_VALID:
+     dir: output
+     desc: HS RX Parallel DATA is VALID
+   RX_OE:
+     dir: output
+     desc: IBUF OE signal for MIPI I_BUF
+   LP_RX_DP:
+     dir: output
+     desc: LP RX Data positive output to the Fabric
+   LP_RX_DN:
+     dir: output
+     desc: LP RX Data negative output to the Fabric
+
+# set as Verilog parameter in netlist    
+parameters:
+    WIDTH:
+      desc: Width of input data to serializer (3-10)
+      type: integer
+      default: 4
+      range: 3 .. 10
+    EN_IDLY:
+      desc: True or False
+      default: "FALSE"
+      values:
+        - "TRUE"
+        - "FALSE"
+    DELAY:
+      desc: Fixed TAP delay value (0-63)
+      type: integer
+      default: 0
+      range: 0 .. 63
+
diff --git a/specs_internal/MIPI_TX.yaml b/specs_internal/MIPI_TX.yaml
new file mode 100644
index 0000000..4756b28
--- /dev/null
+++ b/specs_internal/MIPI_TX.yaml
@@ -0,0 +1,134 @@
+# Periphery Primitives Parameters and Properties (P4)
+#
+# This file contains the list of Verilog parameters and SDC properties that are
+# allowed for periphery primitives.
+#
+# See https://rapidsilicon.atlassian.net/wiki/spaces/RS/pages/214368265/Periphery+Primitive+Parameters+and+Properties+Definitions+P4DEF for more details
+#
+# The name needs to match the filename root
+# name: <primitive name>
+# desc: <optional description>
+#
+# ports:
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#
+# # set as Verilog parameter
+# parameters:
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>  
+#
+# # set in SDC or by synthesis attribute
+# properties:
+#    <property_name>:
+#        desc: <description>
+#        values: 
+#          - <enum_name>
+#          - <enum_name>
+#    <property_name>:
+#        desc: <description>
+#          - <enum_name>
+#          - <enum_name>
+#
+# primitive name should match the filename root.
+name: MIPI_TX
+desc: MIPI Transmitter
+category: periphery
+
+ports:
+   RST:
+     dir: input
+     desc: Active-low, asynchronous reset
+   RX_CLK:
+     dir: input
+     desc: MIPI RX_IO clock input, PLL_CLK
+   PLL_LOCK:
+     dir: input
+     desc: PLL lock input
+   CLK_IN: 
+     dir: input
+     desc: Fabric core clock input
+     bb_attributes: clkbuf_sink
+   HS_TX_DATA[WIDTH-1:0]:
+     dir: input
+     desc: Parallel Data input bus from fabric
+   HS_TXD_VALID:
+     dir: input
+     desc: Load word input from Fabric
+   HS_EN:
+     dir: input
+     desc: EN HS Data Transmission (From Fabric)
+   TX_LP_DP:
+     dir: input
+     desc: LP TX Data positive from the Fabric
+   TX_LP_DN:
+     dir: input
+     desc: LP TX Data negative from the Fabric
+   LP_EN:
+     dir: input
+     desc: EN LP Data Transmission (From Fabric). Active high signal. This is a common signal between MIPI RX/TX interface.
+   TX_ODT_EN:
+     dir: input
+     desc: EN Termination
+   DLY_LOAD:
+     dir: input
+     desc: Delay load input, from Fabric 
+   DLY_ADJ:
+     dir: input
+     desc: Delay adjust input, from Fabric
+   DLY_INCDEC:
+     dir: input
+     desc: Delay increment / decrement input, from Fabric
+   TX_OE:
+     dir: output
+     desc: IBUF OE signal for MIPI O_BUF
+   TX_DP:
+     dir: output
+     desc: Serial Data output to O_BUF
+   TX_DN:
+     dir: output
+     desc: Serial Data output to O_BUF
+   CHANNEL_BOND_SYNC_IN:
+     dir: input
+     desc: Channel bond sync input
+   CHANNEL_BOND_SYNC_OUT:
+     dir: output
+     desc: Channel bond sync output
+
+# set as Verilog parameter in netlist    
+parameters:
+    WIDTH:
+      desc: Width of input data to serializer (3-10)
+      type: integer
+      default: 4
+      range: 3 .. 10
+    EN_ODLY:
+      desc: True or False
+      default: "FALSE"
+      values:
+        - "TRUE"
+        - "FALSE"
+    LANE_MODE:
+      desc: Master or Slave
+      default: "Master"
+      values:
+        - "Master"
+        - "Slave"
+    DELAY:
+      desc: Fixed TAP delay value (0-63)
+      type: integer
+      default: 0
+      range: 0 .. 63
+