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Forcing correct rd_clk in different FIFO_MODEs #135

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Merged
merged 2 commits into from
Oct 28, 2024
Merged

Forcing correct rd_clk in different FIFO_MODEs #135

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c5b98e0
forcing rd_clk in FIFO_MODEs
Sarmad-Salman Oct 28, 2024
c6d916b
forcing rd_clk in FIFO_MODEs
Sarmad-Salman Oct 28, 2024
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7 changes: 5 additions & 2 deletions sim_models/primitives_mapping/FIFO/fifo18kx2_to_rs_tdp_36k_mapping.v
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Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,7 @@ wire [17:0] wrt_data2;
wire [17:0] rd_data2;
wire [17:0] fifo1_flags;
wire [17:0] fifo2_flags;
wire rd_clk1, rd_clk2;

assign OVERFLOW1 = fifo1_flags[0];
assign PROG_FULL1 = fifo1_flags[1];
Expand All @@ -122,6 +123,8 @@ assign UNDERFLOW2 = fifo2_flags[4];
assign PROG_EMPTY2 = fifo2_flags[5];
assign ALMOST_EMPTY2 = fifo2_flags[6];
assign EMPTY2 = fifo2_flags[7];
assign rd_clk1 = (FIFO_TYPE1 == "SYNCHRONOUS") ? WR_CLK1 : RD_CLK1;
assign rd_clk2 = (FIFO_TYPE2 == "SYNCHRONOUS") ? WR_CLK2 : RD_CLK2;

if (DATA_READ_WIDTH1 == 5'd18) begin
assign RD_DATA1 = {rd_data1[17], rd_data1[15:8], rd_data1[16], rd_data1[7:0]};
Expand Down Expand Up @@ -155,7 +158,7 @@ RS_TDP36K_FIFO_18KX2 (
.WEN_A1(WR_EN1),
.REN_B1(RD_EN1),
.CLK_A1(WR_CLK1),
.CLK_B1(RD_CLK1),
.CLK_B1(rd_clk1),
.WDATA_A1(wrt_data1),
.RDATA_A1(fifo1_flags),
.RDATA_B1(rd_data1),
Expand All @@ -168,7 +171,7 @@ RS_TDP36K_FIFO_18KX2 (
.RDATA_B2(rd_data2),
.FLUSH2(RESET2),
.CLK_A2(WR_CLK2),
.CLK_B2(RD_CLK2),
.CLK_B2(rd_clk2),

.WEN_B1(1'b0),
.REN_A1(1'b0),
Expand Down
6 changes: 4 additions & 2 deletions sim_models/primitives_mapping/FIFO/fifo36k_to_rs_tdp_36k_mapping.v
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Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,7 @@ wire [35:0] wrt_data;
wire [35:0] rd_data;
wire [17:0] fifo_flags;
wire [17:0] unused_rdataA2;
wire rd_clk;

assign OVERFLOW = fifo_flags[0];
assign PROG_FULL = fifo_flags[1];
Expand All @@ -68,6 +69,7 @@ assign UNDERFLOW = fifo_flags[4];
assign PROG_EMPTY = fifo_flags[5];
assign ALMOST_EMPTY = fifo_flags[6];
assign EMPTY = fifo_flags[7];
assign rd_clk = (FIFO_TYPE == "SYNCHRONOUS") ? WR_CLK : RD_CLK;

if (DATA_READ_WIDTH == 6'd36) begin
assign RD_DATA = {rd_data[35], rd_data[33:26], rd_data[34], rd_data[25:18], rd_data[17], rd_data[15:8], rd_data[16], rd_data[7:0]};
Expand All @@ -93,15 +95,15 @@ end
.WEN_A1(WR_EN),
.REN_B1(RD_EN),
.CLK_A1(WR_CLK),
.CLK_B1(RD_CLK),
.CLK_B1(rd_clk),
.WDATA_A1(wrt_data[17:0]),
.WDATA_A2(wrt_data[35:18]),
.RDATA_A1(fifo_flags),
.RDATA_B1(rd_data[17:0]),
.RDATA_B2(rd_data[35:18]),
.FLUSH1(RESET),
.CLK_A2(WR_CLK),
.CLK_B2(RD_CLK),
.CLK_B2(rd_clk),

.WEN_B1(1'b0),
.REN_A1(1'b0),
Expand Down