diff --git a/CMakeLists.txt b/CMakeLists.txt index 81f7c4acd..53fa5d109 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -17,7 +17,7 @@ set(VERSION_MINOR 0) -set(VERSION_PATCH 378) +set(VERSION_PATCH 379) diff --git a/design_edit/Makefile b/design_edit/Makefile index 2288249bf..5f97aa4ed 100644 --- a/design_edit/Makefile +++ b/design_edit/Makefile @@ -67,7 +67,7 @@ VERILOG_MODULES = $(COMMON)/cells_sim.v \ $(GENESIS3)/FPGA_PRIMITIVES_MODELS/sim_models/verilog/DSP38.v NAME = design-edit -SOURCES = src/primitives_extractor.cc src/rs_design_edit.cc +SOURCES = src/primitives_extractor.cc src/rs_design_edit.cc src/netlist_checker.cc OBJS := $(SOURCES:cc=o) diff --git a/design_edit/Tests/GJC-1/GJC-1.ys b/design_edit/Tests/GJC-1/GJC-1.ys deleted file mode 100644 index 6f82b1a7b..000000000 --- a/design_edit/Tests/GJC-1/GJC-1.ys +++ /dev/null @@ -1,22 +0,0 @@ - -# Yosys synthesis script for ${TOP_MODULE} -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog flop2flop.v - -# Technology mapping -hierarchy -auto-top - - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 34848 -max_reg 69696 -max_device_dsp 154 -max_device_bram 154 -max_device_carry_length 48 -max_dsp 154 -max_bram 154 -max_carry_length 48 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -sdc flop2flop.sdc -json ./tmp/io_config.json -w ./tmp//wrapper_flop2flop_post_synth.v ./tmp//wrapper_flop2flop_post_synth.eblif -write_verilog -noexpr -nodec -v ./tmp/flop2flop_post_synth.v -write_blif -param ./tmp/flop2flop_post_synth.eblif - - \ No newline at end of file diff --git a/design_edit/Tests/GJC-1/flop2flop.sdc b/design_edit/Tests/GJC-1/flop2flop.sdc deleted file mode 100644 index f389a39b7..000000000 --- a/design_edit/Tests/GJC-1/flop2flop.sdc +++ /dev/null @@ -1,17 +0,0 @@ -set_top_module flop2flop -# -name is used for creating virtual clock and for actual clock -name option will not be used -create_clock -period 5 clk -# set_clock_uncertainty 0.005 clk -set_input_delay 1 -clock clk [get_ports {din}] -set_output_delay 1 -clock clk [get_ports {dout}] - -# pin locations -set_property mode Mode_BP_SDR_A_RX HR_3_0_0P -set_pin_loc din HR_3_0_0P - -set_property mode Mode_BP_SDR_A_RX HR_2_0_0P -set_pin_loc clk HR_2_0_0P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_0P -set_pin_loc dout HR_5_0_0P - diff --git a/design_edit/Tests/GJC-1/flop2flop.v b/design_edit/Tests/GJC-1/flop2flop.v deleted file mode 100644 index bd132c2bf..000000000 --- a/design_edit/Tests/GJC-1/flop2flop.v +++ /dev/null @@ -1,30 +0,0 @@ -///////////////////////////////////////// -// Functionality: flop to flop path -// Author: George Chen -//////////////////////////////////////// -// `timescale 1ns / 1ps - - -module flop2flop( - din, - dout, - clk); - -input din; -input clk; -output reg dout; - -reg q1 ; - - -always @(posedge clk) - begin - q1 <= din ; - end - -always @(posedge clk) - begin - dout <= q1 ; - end - -endmodule diff --git a/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.eblif b/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.eblif deleted file mode 100644 index 8bcea21a3..000000000 --- a/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.eblif +++ /dev/null @@ -1,12 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_flop2flop -.inputs $iopadmap$din $auto$clkbufmap.cc:295:execute$430 -.outputs $iopadmap$dout -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$430 D=$iopadmap$din E=$true Q=q1 R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$430 D=q1 E=$true Q=$iopadmap$dout R=$true -.end diff --git a/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.v b/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.v deleted file mode 100644 index 9f9343b64..000000000 --- a/design_edit/Tests/GJC-1/gold/flop2flop_post_synth.v +++ /dev/null @@ -1,54 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_flop2flop(_13_, _00_, _12_); - output _00_; - input _12_; - input _13_; - wire _00_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire _01_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire _02_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _03_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _04_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _05_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire _06_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire _07_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire _08_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _09_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _10_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _11_; - wire _12_; - wire _13_; - wire _14_; - (* keep = 32'h00000001 *) - (* src = "flop2flop.v:17.5-17.7" *) - wire q1; - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _15_ ( - .C(_12_), - .D(_13_), - .E(1'h1), - .Q(q1), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _16_ ( - .C(_12_), - .D(q1), - .E(1'h1), - .Q(_00_), - .R(1'h1) - ); -endmodule diff --git a/design_edit/Tests/GJC-1/gold/io_config.json b/design_edit/Tests/GJC-1/gold/io_config.json deleted file mode 100644 index 49be3ddd1..000000000 --- a/design_edit/Tests/GJC-1/gold/io_config.json +++ /dev/null @@ -1,123 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\clk (index=0, width=1, offset=0)", - " Detect input port \\din (index=0, width=1, offset=0)", - " Detect output port \\dout (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$flop2flop.clk", - " Cell port \\I is connected to input port \\clk", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$flop2flop.din", - " Cell port \\I is connected to input port \\din", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$flop2flop.dout", - " Cell port \\O is connected to output port \\dout", - " Trace Clock Buffer", - " Try \\I_BUF $iopadmap$flop2flop.clk out connection: $iopadmap$clk", - " Connected $auto$clkbufmap.cc:262:execute$428", - " Additional Connection: $auto$clkbufmap.cc:263:execute$429", - " Assign location HR_3_0_0P (and properties) to Port din", - " Assign location HR_2_0_0P (and properties) to Port clk", - " Assign location HR_5_0_0P (and properties) to Port dout", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$flop2flop.clk", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HR_2_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "clk", - "O" : "$iopadmap$clk" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk_#0", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HR_2_0_0P", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk", - "O" : "$auto$clkbufmap.cc:263:execute$429" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$428", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HR_2_0_0P", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$429", - "O" : "$auto$clkbufmap.cc:295:execute$430" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$flop2flop.din", - "linked_object" : "din", - "linked_objects" : { - "din" : { - "location" : "HR_3_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "din", - "O" : "$iopadmap$din" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$flop2flop.dout", - "linked_object" : "dout", - "linked_objects" : { - "dout" : { - "location" : "HR_5_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$dout", - "O" : "dout" - }, - "parameters" : { - } - } - ] -} diff --git a/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.eblif b/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.eblif deleted file mode 100644 index 08dd7e278..000000000 --- a/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.eblif +++ /dev/null @@ -1,29 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model flop2flop -.inputs din clk -.outputs dout -.names $false -.names $true -1 -.names $undef -.subckt fabric_flop2flop $auto$clkbufmap.cc:295:execute$430=$auto$clkbufmap.cc:295:execute$430 $iopadmap$din=$iopadmap$din $iopadmap$dout=$iopadmap$dout -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$clk O=$flatten$auto$rs_design_edit.cc:682:execute$436.$auto$clkbufmap.cc:295:execute$430 -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$436.clk O=$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$436.din O=$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$din -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$dout O=$auto$rs_design_edit.cc:682:execute$436.dout -.names $flatten$auto$rs_design_edit.cc:682:execute$436.$auto$clkbufmap.cc:295:execute$430 $auto$clkbufmap.cc:295:execute$430 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$din $iopadmap$din -1 1 -.names $iopadmap$dout $flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$dout -1 1 -.names clk $auto$rs_design_edit.cc:682:execute$436.clk -1 1 -.names din $auto$rs_design_edit.cc:682:execute$436.din -1 1 -.names $auto$rs_design_edit.cc:682:execute$436.dout dout -1 1 -.end diff --git a/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.v b/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.v deleted file mode 100644 index 155204900..000000000 --- a/design_edit/Tests/GJC-1/gold/wrapper_flop2flop_post_synth.v +++ /dev/null @@ -1,76 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module flop2flop(din, dout, clk); - input din; - input clk; - output dout; - (* src = "flop2flop.v:13.7-13.10" *) - wire \$auto$rs_design_edit.cc:682:execute$436.din ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$436.$auto$clkbufmap.cc:295:execute$430 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$clk ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$din ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$dout ; - (* src = "flop2flop.v:14.7-14.10" *) - wire \$auto$rs_design_edit.cc:682:execute$436.clk ; - (* keep = 32'd1 *) - (* src = "flop2flop.v:15.12-15.16" *) - wire \$auto$rs_design_edit.cc:682:execute$436.dout ; - (* src = "flop2flop.v:13.7-13.10" *) - (* src = "flop2flop.v:13.7-13.10" *) - wire din; - wire \$iopadmap$dout ; - wire \$iopadmap$din ; - (* src = "flop2flop.v:14.7-14.10" *) - (* src = "flop2flop.v:14.7-14.10" *) - wire clk; - wire \$auto$clkbufmap.cc:295:execute$430 ; - (* keep = 32'd1 *) - (* src = "flop2flop.v:15.12-15.16" *) - (* keep = 32'd1 *) - (* src = "flop2flop.v:15.12-15.16" *) - wire dout; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$flop2flop.dout ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$dout ), - .O(\$auto$rs_design_edit.cc:682:execute$436.dout ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$436.$auto$clkbufmap.cc:262:execute$428 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$436.$auto$clkbufmap.cc:295:execute$430 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$flop2flop.clk ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$436.clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$clk ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$flop2flop.din ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$436.din ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$din ) - ); - fabric_flop2flop \$auto$rs_design_edit.cc:680:execute$435 ( - .\$auto$clkbufmap.cc:295:execute$430 (\$auto$clkbufmap.cc:295:execute$430 ), - .\$iopadmap$din (\$iopadmap$din ), - .\$iopadmap$dout (\$iopadmap$dout ) - ); - assign \$auto$clkbufmap.cc:295:execute$430 = \$flatten$auto$rs_design_edit.cc:682:execute$436.$auto$clkbufmap.cc:295:execute$430 ; - assign \$iopadmap$din = \$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$din ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$436.$iopadmap$dout = \$iopadmap$dout ; - assign \$auto$rs_design_edit.cc:682:execute$436.clk = clk; - assign \$auto$rs_design_edit.cc:682:execute$436.din = din; - assign dout = \$auto$rs_design_edit.cc:682:execute$436.dout ; -endmodule diff --git a/design_edit/Tests/GJC-1/new_sdc.txt b/design_edit/Tests/GJC-1/new_sdc.txt deleted file mode 100644 index 6808efd59..000000000 --- a/design_edit/Tests/GJC-1/new_sdc.txt +++ /dev/null @@ -1,12 +0,0 @@ -name: HR_5_0_0P - pin: dout - properties: - mode : Mode_BP_SDR_A_TX -name: HR_2_0_0P - pin: clk - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_0P - pin: din - properties: - mode : Mode_BP_SDR_A_RX diff --git a/design_edit/Tests/GJC-1/raptor.tcl b/design_edit/Tests/GJC-1/raptor.tcl deleted file mode 100644 index 58fc94a19..000000000 --- a/design_edit/Tests/GJC-1/raptor.tcl +++ /dev/null @@ -1,13 +0,0 @@ -create_design flop2flop -target_device GEMINI_COMPACT_10x8 -add_design_file flop2flop.v -#add_constraint_file flop2flop.sdc -ipgenerate -analyze -synth_options -inferred_io -synth -#packing -#place -#route -#sta - diff --git a/design_edit/Tests/GJC-1/synthesis/flop2flop_post_synth.eblif b/design_edit/Tests/GJC-1/synthesis/flop2flop_post_synth.eblif deleted file mode 100644 index 453cae1d0..000000000 --- a/design_edit/Tests/GJC-1/synthesis/flop2flop_post_synth.eblif +++ /dev/null @@ -1,20 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model flop2flop -.inputs din clk -.outputs dout -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:294:execute$430 D=$iopadmap$din E=$true Q=q1 R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:294:execute$430 D=q1 E=$true Q=$iopadmap$dout R=$true -.subckt CLK_BUF I=$auto$clkbufmap.cc:262:execute$429 O=$auto$clkbufmap.cc:294:execute$430 -.subckt I_BUF EN=$true I=clk O=$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=din O=$iopadmap$din -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$iopadmap$dout O=dout -.names $iopadmap$clk $auto$clkbufmap.cc:262:execute$429 -1 1 -.end diff --git a/design_edit/Tests/GJC-1/synthesis/flop2flop_post_synth.v b/design_edit/Tests/GJC-1/synthesis/flop2flop_post_synth.v deleted file mode 100644 index 7370d3852..000000000 --- a/design_edit/Tests/GJC-1/synthesis/flop2flop_post_synth.v +++ /dev/null @@ -1,100 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module flop2flop(din, dout, clk); - input clk; - input din; - output dout; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _00_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _01_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _02_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire _03_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire _04_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire _05_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _06_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _07_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _08_; - wire _09_; - (* src = "flop2flop.v:14.7-14.10" *) - (* src = "flop2flop.v:14.7-14.10" *) - wire clk; - (* src = "flop2flop.v:13.7-13.10" *) - (* src = "flop2flop.v:13.7-13.10" *) - wire din; - (* keep = 32'h00000001 *) - (* src = "flop2flop.v:15.12-15.16" *) - (* keep = 32'h00000001 *) - (* src = "flop2flop.v:15.12-15.16" *) - wire dout; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire _10_; - wire _11_; - wire _12_; - wire _13_; - wire _14_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire _15_; - (* keep = 32'h00000001 *) - (* src = "flop2flop.v:17.5-17.7" *) - wire q1; - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) _16_ ( - .O(_09_), - .EN(1'h1), - .I(clk) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) _17_ ( - .O(_12_), - .EN(1'h1), - .I(din) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF _18_ ( - .O(dout), - .I(_14_) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF _19_ ( - .O(_11_), - .I(_13_) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _20_ ( - .C(_11_), - .D(_12_), - .E(1'h1), - .Q(q1), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _21_ ( - .C(_11_), - .D(q1), - .E(1'h1), - .Q(_14_), - .R(1'h1) - ); - assign _13_ = _09_; -endmodule diff --git a/design_edit/Tests/GJC-2/GJC-2.ys b/design_edit/Tests/GJC-2/GJC-2.ys deleted file mode 100644 index 827bdcf9a..000000000 --- a/design_edit/Tests/GJC-2/GJC-2.ys +++ /dev/null @@ -1,23 +0,0 @@ - -# Yosys synthesis script for ${TOP_MODULE} -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog flop2flop2flop.v - -# Technology mapping -hierarchy -auto-top - - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -sdc flop2flop2flop.sdc -json ./tmp/io_config.json -w ./tmp//wrapper_flop2flop2flop_post_synth.v ./tmp//wrapper_flop2flop2flop_post_synth.eblif - -write_verilog -noexpr -nodec -v ./tmp/flop2flop2flop_post_synth.v -write_blif -param ./tmp/flop2flop2flop_post_synth.eblif - - \ No newline at end of file diff --git a/design_edit/Tests/GJC-2/flop2flop2flop.sdc b/design_edit/Tests/GJC-2/flop2flop2flop.sdc deleted file mode 100644 index 75f6b3716..000000000 --- a/design_edit/Tests/GJC-2/flop2flop2flop.sdc +++ /dev/null @@ -1,18 +0,0 @@ -set_top_module flop2flop2flop -# -name is used for creating virtual clock and for actual clock -name option will not be used -create_clock -period 5 clk -# set_clock_uncertainty 0.005 clk -set_input_delay 1 -clock clk [get_ports {din}] -set_output_delay 1 -clock clk [get_ports {dout}] - -# pin locations -set_property mode Mode_BP_SDR_A_RX HR_2_6_3P -set_pin_loc din HR_2_6_3P -set_property registered HR_2_6_3P - -set_property mode Mode_BP_SDR_A_RX HP_2_CC_10_5P -set_pin_loc clk HP_2_CC_10_5P - -set_property mode Mode_BP_SDR_A_TX HR_5_12_6P -set_pin_loc dout HR_5_12_6P -set_property registered HR_5_12_6P diff --git a/design_edit/Tests/GJC-2/flop2flop2flop.v b/design_edit/Tests/GJC-2/flop2flop2flop.v deleted file mode 100644 index 71b4b960f..000000000 --- a/design_edit/Tests/GJC-2/flop2flop2flop.v +++ /dev/null @@ -1,36 +0,0 @@ -///////////////////////////////////////// -// Functionality: flop to flop path -// Author: George Chen -//////////////////////////////////////// -// `timescale 1ns / 1ps - - -module flop2flop2flop( - din, - dout, - clk); - -input din; -input clk; -output reg dout; - -reg q1 ; - reg q2 ; - - -always @(posedge clk) - begin - q1 <= din ; - end - -always @(posedge clk) - begin - q2 <= q1 ; - end - -always @(posedge clk) - begin - dout <= q2 ; - end - -endmodule diff --git a/design_edit/Tests/GJC-2/gold/flop2flop2flop_post_synth.eblif b/design_edit/Tests/GJC-2/gold/flop2flop2flop_post_synth.eblif deleted file mode 100644 index 835ef9b39..000000000 --- a/design_edit/Tests/GJC-2/gold/flop2flop2flop_post_synth.eblif +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_flop2flop2flop -.inputs $auto$clkbufmap.cc:295:execute$446 $iopadmap$din -.outputs $iopadmap$dout -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$446 D=$iopadmap$din E=$true Q=q1 R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$446 D=q1 E=$true Q=q2 R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$446 D=q2 E=$true Q=$iopadmap$dout R=$true -.end diff --git a/design_edit/Tests/GJC-2/gold/flop2flop2flop_post_synth.v b/design_edit/Tests/GJC-2/gold/flop2flop2flop_post_synth.v deleted file mode 100644 index 2e7062c83..000000000 --- a/design_edit/Tests/GJC-2/gold/flop2flop2flop_post_synth.v +++ /dev/null @@ -1,66 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_flop2flop2flop(_12_, _13_, _00_); - output _00_; - input _12_; - input _13_; - wire _00_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire _01_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire _02_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire _03_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire _04_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire _05_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _06_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _07_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _08_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _09_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _10_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _11_; - wire _12_; - wire _13_; - wire _14_; - (* keep = 32'h00000001 *) - (* src = "flop2flop2flop.v:17.5-17.7" *) - wire q1; - (* keep = 32'h00000001 *) - (* src = "flop2flop2flop.v:18.8-18.10" *) - wire q2; - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _15_ ( - .C(_12_), - .D(q1), - .E(1'h1), - .Q(q2), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _16_ ( - .C(_12_), - .D(q2), - .E(1'h1), - .Q(_00_), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _17_ ( - .C(_12_), - .D(_13_), - .E(1'h1), - .Q(q1), - .R(1'h1) - ); -endmodule diff --git a/design_edit/Tests/GJC-2/gold/io_config.json b/design_edit/Tests/GJC-2/gold/io_config.json deleted file mode 100644 index 2ea926fad..000000000 --- a/design_edit/Tests/GJC-2/gold/io_config.json +++ /dev/null @@ -1,123 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\clk (index=0, width=1, offset=0)", - " Detect input port \\din (index=0, width=1, offset=0)", - " Detect output port \\dout (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$flop2flop2flop.clk", - " Cell port \\I is connected to input port \\clk", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$flop2flop2flop.din", - " Cell port \\I is connected to input port \\din", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$flop2flop2flop.dout", - " Cell port \\O is connected to output port \\dout", - " Trace Clock Buffer", - " Try \\I_BUF $iopadmap$flop2flop2flop.clk out connection: $iopadmap$clk", - " Connected $auto$clkbufmap.cc:262:execute$444", - " Additional Connection: $auto$clkbufmap.cc:263:execute$445", - " Assign location HR_2_6_3P (and properties) to Port din", - " Assign location HP_2_CC_10_5P (and properties) to Port clk", - " Assign location HR_5_12_6P (and properties) to Port dout", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$flop2flop2flop.clk", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HP_2_CC_10_5P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "clk", - "O" : "$iopadmap$clk" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk_#0", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HP_2_CC_10_5P", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk", - "O" : "$auto$clkbufmap.cc:263:execute$445" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$444", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HP_2_CC_10_5P", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$445", - "O" : "$auto$clkbufmap.cc:295:execute$446" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$flop2flop2flop.din", - "linked_object" : "din", - "linked_objects" : { - "din" : { - "location" : "HR_2_6_3P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "din", - "O" : "$iopadmap$din" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$flop2flop2flop.dout", - "linked_object" : "dout", - "linked_objects" : { - "dout" : { - "location" : "HR_5_12_6P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$dout", - "O" : "dout" - }, - "parameters" : { - } - } - ] -} diff --git a/design_edit/Tests/GJC-2/gold/wrapper_flop2flop2flop_post_synth.eblif b/design_edit/Tests/GJC-2/gold/wrapper_flop2flop2flop_post_synth.eblif deleted file mode 100644 index d825539c9..000000000 --- a/design_edit/Tests/GJC-2/gold/wrapper_flop2flop2flop_post_synth.eblif +++ /dev/null @@ -1,29 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model flop2flop2flop -.inputs din clk -.outputs dout -.names $false -.names $true -1 -.names $undef -.subckt fabric_flop2flop2flop $auto$clkbufmap.cc:295:execute$446=$auto$clkbufmap.cc:295:execute$446 $iopadmap$din=$iopadmap$din $iopadmap$dout=$iopadmap$dout -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$clk O=$flatten$auto$rs_design_edit.cc:682:execute$452.$auto$clkbufmap.cc:295:execute$446 -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$452.clk O=$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$452.din O=$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$din -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$dout O=$auto$rs_design_edit.cc:682:execute$452.dout -.names $flatten$auto$rs_design_edit.cc:682:execute$452.$auto$clkbufmap.cc:295:execute$446 $auto$clkbufmap.cc:295:execute$446 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$din $iopadmap$din -1 1 -.names $iopadmap$dout $flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$dout -1 1 -.names clk $auto$rs_design_edit.cc:682:execute$452.clk -1 1 -.names din $auto$rs_design_edit.cc:682:execute$452.din -1 1 -.names $auto$rs_design_edit.cc:682:execute$452.dout dout -1 1 -.end diff --git a/design_edit/Tests/GJC-2/gold/wrapper_flop2flop2flop_post_synth.v b/design_edit/Tests/GJC-2/gold/wrapper_flop2flop2flop_post_synth.v deleted file mode 100644 index c3060f7e5..000000000 --- a/design_edit/Tests/GJC-2/gold/wrapper_flop2flop2flop_post_synth.v +++ /dev/null @@ -1,76 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module flop2flop2flop(din, dout, clk); - input clk; - input din; - output dout; - (* src = "flop2flop2flop.v:14.7-14.10" *) - wire \$auto$rs_design_edit.cc:682:execute$452.clk ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$452.$auto$clkbufmap.cc:295:execute$446 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$clk ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$din ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$dout ; - (* src = "flop2flop2flop.v:13.7-13.10" *) - wire \$auto$rs_design_edit.cc:682:execute$452.din ; - (* keep = 32'd1 *) - (* src = "flop2flop2flop.v:15.12-15.16" *) - wire \$auto$rs_design_edit.cc:682:execute$452.dout ; - (* src = "flop2flop2flop.v:14.7-14.10" *) - (* src = "flop2flop2flop.v:14.7-14.10" *) - wire clk; - wire \$iopadmap$dout ; - wire \$iopadmap$din ; - (* src = "flop2flop2flop.v:13.7-13.10" *) - (* src = "flop2flop2flop.v:13.7-13.10" *) - wire din; - wire \$auto$clkbufmap.cc:295:execute$446 ; - (* keep = 32'd1 *) - (* src = "flop2flop2flop.v:15.12-15.16" *) - (* keep = 32'd1 *) - (* src = "flop2flop2flop.v:15.12-15.16" *) - wire dout; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$flop2flop2flop.din ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$452.din ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$din ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$flop2flop2flop.dout ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$dout ), - .O(\$auto$rs_design_edit.cc:682:execute$452.dout ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$452.$auto$clkbufmap.cc:262:execute$444 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$452.$auto$clkbufmap.cc:295:execute$446 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$flop2flop2flop.clk ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$452.clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$clk ) - ); - fabric_flop2flop2flop \$auto$rs_design_edit.cc:680:execute$451 ( - .\$auto$clkbufmap.cc:295:execute$446 (\$auto$clkbufmap.cc:295:execute$446 ), - .\$iopadmap$din (\$iopadmap$din ), - .\$iopadmap$dout (\$iopadmap$dout ) - ); - assign \$auto$clkbufmap.cc:295:execute$446 = \$flatten$auto$rs_design_edit.cc:682:execute$452.$auto$clkbufmap.cc:295:execute$446 ; - assign \$iopadmap$din = \$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$din ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$452.$iopadmap$dout = \$iopadmap$dout ; - assign \$auto$rs_design_edit.cc:682:execute$452.clk = clk; - assign \$auto$rs_design_edit.cc:682:execute$452.din = din; - assign dout = \$auto$rs_design_edit.cc:682:execute$452.dout ; -endmodule diff --git a/design_edit/Tests/GJC-2/new_sdc.txt b/design_edit/Tests/GJC-2/new_sdc.txt deleted file mode 100644 index 8e8ed1784..000000000 --- a/design_edit/Tests/GJC-2/new_sdc.txt +++ /dev/null @@ -1,12 +0,0 @@ -name: HR_5_12_6P - pin: dout - properties: - mode : Mode_BP_SDR_A_TX -name: HP_2_CC_10_5P - pin: clk - properties: - mode : Mode_BP_SDR_A_RX -name: HR_2_6_3P - pin: din - properties: - mode : Mode_BP_SDR_A_RX diff --git a/design_edit/Tests/GJC-2/raptor.tcl b/design_edit/Tests/GJC-2/raptor.tcl deleted file mode 100644 index 7f09c7af7..000000000 --- a/design_edit/Tests/GJC-2/raptor.tcl +++ /dev/null @@ -1,12 +0,0 @@ -create_design flop2flop2flop -target_device 1GE100-ES1 -add_design_file flop2flop2flop.v -#add_constraint_file flop2flop2flop.sdc -ipgenerate -analyze -synth -#packing -#place -#route -#sta - diff --git a/design_edit/Tests/GJC-2/synthesis/flop2flop2flop_post_synth.eblif b/design_edit/Tests/GJC-2/synthesis/flop2flop2flop_post_synth.eblif deleted file mode 100644 index 63bf5ea4f..000000000 --- a/design_edit/Tests/GJC-2/synthesis/flop2flop2flop_post_synth.eblif +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model flop2flop2flop -.inputs din clk -.outputs dout -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=clk D=din E=$true Q=q1 R=$true -.subckt DFFRE C=clk D=q1 E=$true Q=q2 R=$true -.subckt DFFRE C=clk D=q2 E=$true Q=dout R=$true -.end diff --git a/design_edit/Tests/GJC-2/synthesis/flop2flop2flop_post_synth.v b/design_edit/Tests/GJC-2/synthesis/flop2flop2flop_post_synth.v deleted file mode 100644 index bf07e14aa..000000000 --- a/design_edit/Tests/GJC-2/synthesis/flop2flop2flop_post_synth.v +++ /dev/null @@ -1,51 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module flop2flop2flop(din, dout, clk); - input clk; - input din; - output dout; - (* src = "flop2flop2flop.v:14.7-14.10" *) - (* src = "flop2flop2flop.v:14.7-14.10" *) - wire clk; - (* src = "flop2flop2flop.v:13.7-13.10" *) - (* src = "flop2flop2flop.v:13.7-13.10" *) - wire din; - (* keep = 32'h00000001 *) - (* src = "flop2flop2flop.v:15.12-15.16" *) - (* keep = 32'h00000001 *) - (* src = "flop2flop2flop.v:15.12-15.16" *) - wire dout; - (* keep = 32'h00000001 *) - (* src = "flop2flop2flop.v:17.5-17.7" *) - wire q1; - (* keep = 32'h00000001 *) - (* src = "flop2flop2flop.v:18.8-18.10" *) - wire q2; - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _0_ ( - .C(clk), - .D(din), - .E(1'h1), - .Q(q1), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _1_ ( - .C(clk), - .D(q1), - .E(1'h1), - .Q(q2), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _2_ ( - .C(clk), - .D(q2), - .E(1'h1), - .Q(dout), - .R(1'h1) - ); -endmodule diff --git a/design_edit/Tests/GJC-6/GJC-6.ys b/design_edit/Tests/GJC-6/GJC-6.ys deleted file mode 100644 index 41975ea70..000000000 --- a/design_edit/Tests/GJC-6/GJC-6.ys +++ /dev/null @@ -1,27 +0,0 @@ - -# Yosys synthesis script for tristate -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog tristate.v - -# Technology mapping -hierarchy -top tristate - -setattr -set keep 1 w:\clk -setattr -set keep 1 w:\din -setattr -set keep 1 w:\oe -setattr -set keep 1 w:\tristate_out - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -sdc tristate.sdc -json ./tmp/io_config.json -w ./tmp//wrapper_tristate_post_synth.v ./tmp//wrapper_tristate_post_synth.eblif - -write_verilog -noexpr -nodec -v ./tmp/tristate_post_synth.v -write_blif -param ./tmp/tristate_post_synth.eblif - - \ No newline at end of file diff --git a/design_edit/Tests/GJC-6/gold/io_config.json b/design_edit/Tests/GJC-6/gold/io_config.json deleted file mode 100644 index c1f987015..000000000 --- a/design_edit/Tests/GJC-6/gold/io_config.json +++ /dev/null @@ -1,148 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\clk (index=0, width=1, offset=0)", - " Detect input port \\din (index=0, width=1, offset=0)", - " Detect input port \\oe (index=0, width=1, offset=0)", - " Detect output port \\tristate_out (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$tristate.clk", - " Cell port \\I is connected to input port \\clk", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$tristate.din", - " Cell port \\I is connected to input port \\din", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$tristate.oe", - " Cell port \\I is connected to input port \\oe", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$tristate.tristate_out", - " Cell port \\O is connected to output port \\tristate_out", - " Trace Clock Buffer", - " Try \\I_BUF $iopadmap$tristate.clk out connection: $iopadmap$clk", - " Connected $auto$clkbufmap.cc:262:execute$443", - " Additional Connection: $auto$clkbufmap.cc:263:execute$444", - " Assign location HR_2_6_3P (and properties) to Port din", - " Assign location HR_2_8_4P (and properties) to Port oe", - " Assign location HP_2_CC_10_5P (and properties) to Port clk", - " Assign location HR_5_12_6P (and properties) to Port tristate_out", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$tristate.clk", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HP_2_CC_10_5P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "clk", - "O" : "$iopadmap$clk" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk_#0", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HP_2_CC_10_5P", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk", - "O" : "$auto$clkbufmap.cc:263:execute$444" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$443", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HP_2_CC_10_5P", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$444", - "O" : "$auto$clkbufmap.cc:295:execute$445" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$tristate.din", - "linked_object" : "din", - "linked_objects" : { - "din" : { - "location" : "HR_2_6_3P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "din", - "O" : "$iopadmap$din" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$tristate.oe", - "linked_object" : "oe", - "linked_objects" : { - "oe" : { - "location" : "HR_2_8_4P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "oe", - "O" : "$iopadmap$oe" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$tristate.tristate_out", - "linked_object" : "tristate_out", - "linked_objects" : { - "tristate_out" : { - "location" : "HR_5_12_6P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$tristate_out", - "O" : "tristate_out" - }, - "parameters" : { - } - } - ] -} diff --git a/design_edit/Tests/GJC-6/gold/tristate_post_synth.eblif b/design_edit/Tests/GJC-6/gold/tristate_post_synth.eblif deleted file mode 100644 index d3f9a145f..000000000 --- a/design_edit/Tests/GJC-6/gold/tristate_post_synth.eblif +++ /dev/null @@ -1,14 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_tristate -.inputs $iopadmap$oe $iopadmap$din $auto$clkbufmap.cc:295:execute$445 -.outputs $iopadmap$tristate_out -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$445 D=$iopadmap$din E=$true Q=q1 R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$445 D=q1 E=$true Q=q2 R=$true -.subckt LUT2 A[0]=$iopadmap$oe A[1]=q2 Y=$iopadmap$tristate_out -.param INIT_VALUE 1000 -.end diff --git a/design_edit/Tests/GJC-6/gold/tristate_post_synth.v b/design_edit/Tests/GJC-6/gold/tristate_post_synth.v deleted file mode 100644 index 1a5f79c74..000000000 --- a/design_edit/Tests/GJC-6/gold/tristate_post_synth.v +++ /dev/null @@ -1,77 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_tristate(_19_, _20_, _00_, _18_); - output _00_; - input _18_; - input _19_; - input _20_; - wire _00_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire _01_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire _02_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _03_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _04_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _05_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _06_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _07_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _08_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire _09_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire _10_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire _11_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _12_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _13_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _14_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] _15_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _16_; - wire _17_; - wire _18_; - wire _19_; - (* keep = 32'h00000001 *) - (* src = "tristate.v:19.8-19.10" *) - wire q1; - (* keep = 32'h00000001 *) - (* src = "tristate.v:20.8-20.10" *) - wire q2; - wire _20_; - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h8) - ) _21_ ( - .A({ q2, _19_ }), - .Y(_00_) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _22_ ( - .C(_18_), - .D(_20_), - .E(1'h1), - .Q(q1), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _23_ ( - .C(_18_), - .D(q1), - .E(1'h1), - .Q(q2), - .R(1'h1) - ); -endmodule diff --git a/design_edit/Tests/GJC-6/gold/wrapper_tristate_post_synth.eblif b/design_edit/Tests/GJC-6/gold/wrapper_tristate_post_synth.eblif deleted file mode 100644 index efdd297dd..000000000 --- a/design_edit/Tests/GJC-6/gold/wrapper_tristate_post_synth.eblif +++ /dev/null @@ -1,35 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model tristate -.inputs din oe clk -.outputs tristate_out -.names $false -.names $true -1 -.names $undef -.subckt fabric_tristate $auto$clkbufmap.cc:295:execute$445=$auto$clkbufmap.cc:295:execute$445 $iopadmap$din=$iopadmap$din $iopadmap$oe=$iopadmap$oe $iopadmap$tristate_out=$iopadmap$tristate_out -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$clk O=$flatten$auto$rs_design_edit.cc:682:execute$453.$auto$clkbufmap.cc:295:execute$445 -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$453.clk O=$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$453.din O=$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$din -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$453.oe O=$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$oe -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$tristate_out O=$auto$rs_design_edit.cc:682:execute$453.tristate_out -.names $flatten$auto$rs_design_edit.cc:682:execute$453.$auto$clkbufmap.cc:295:execute$445 $auto$clkbufmap.cc:295:execute$445 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$din $iopadmap$din -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$oe $iopadmap$oe -1 1 -.names $iopadmap$tristate_out $flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$tristate_out -1 1 -.names clk $auto$rs_design_edit.cc:682:execute$453.clk -1 1 -.names din $auto$rs_design_edit.cc:682:execute$453.din -1 1 -.names oe $auto$rs_design_edit.cc:682:execute$453.oe -1 1 -.names $auto$rs_design_edit.cc:682:execute$453.tristate_out tristate_out -1 1 -.end diff --git a/design_edit/Tests/GJC-6/gold/wrapper_tristate_post_synth.v b/design_edit/Tests/GJC-6/gold/wrapper_tristate_post_synth.v deleted file mode 100644 index 963708249..000000000 --- a/design_edit/Tests/GJC-6/gold/wrapper_tristate_post_synth.v +++ /dev/null @@ -1,106 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module tristate(din, oe, tristate_out, clk); - input oe; - input clk; - input din; - output tristate_out; - (* keep = 32'd1 *) - (* src = "tristate.v:16.10-16.12" *) - wire \$auto$rs_design_edit.cc:682:execute$453.oe ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$453.$auto$clkbufmap.cc:295:execute$445 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$clk ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$din ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$oe ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$tristate_out ; - (* keep = 32'd1 *) - (* src = "tristate.v:17.11-17.23" *) - wire \$auto$rs_design_edit.cc:682:execute$453.tristate_out ; - (* keep = 32'd1 *) - (* src = "tristate.v:15.10-15.13" *) - wire \$auto$rs_design_edit.cc:682:execute$453.clk ; - (* keep = 32'd1 *) - (* src = "tristate.v:14.10-14.13" *) - wire \$auto$rs_design_edit.cc:682:execute$453.din ; - (* keep = 32'd1 *) - (* src = "tristate.v:16.10-16.12" *) - (* keep = 32'd1 *) - (* src = "tristate.v:16.10-16.12" *) - wire oe; - (* keep = 32'd1 *) - (* src = "tristate.v:15.10-15.13" *) - (* keep = 32'd1 *) - (* src = "tristate.v:15.10-15.13" *) - wire clk; - wire \$iopadmap$tristate_out ; - wire \$iopadmap$oe ; - wire \$iopadmap$din ; - (* keep = 32'd1 *) - (* src = "tristate.v:14.10-14.13" *) - (* keep = 32'd1 *) - (* src = "tristate.v:14.10-14.13" *) - wire din; - wire \$auto$clkbufmap.cc:295:execute$445 ; - (* keep = 32'd1 *) - (* src = "tristate.v:17.11-17.23" *) - (* keep = 32'd1 *) - (* src = "tristate.v:17.11-17.23" *) - wire tristate_out; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$tristate.oe ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$453.oe ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$oe ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$tristate.tristate_out ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$tristate_out ), - .O(\$auto$rs_design_edit.cc:682:execute$453.tristate_out ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$453.$auto$clkbufmap.cc:262:execute$443 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$453.$auto$clkbufmap.cc:295:execute$445 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$tristate.clk ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$453.clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$clk ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$tristate.din ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$453.din ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$din ) - ); - fabric_tristate \$auto$rs_design_edit.cc:680:execute$452 ( - .\$auto$clkbufmap.cc:295:execute$445 (\$auto$clkbufmap.cc:295:execute$445 ), - .\$iopadmap$din (\$iopadmap$din ), - .\$iopadmap$oe (\$iopadmap$oe ), - .\$iopadmap$tristate_out (\$iopadmap$tristate_out ) - ); - assign \$auto$clkbufmap.cc:295:execute$445 = \$flatten$auto$rs_design_edit.cc:682:execute$453.$auto$clkbufmap.cc:295:execute$445 ; - assign \$iopadmap$din = \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$din ; - assign \$iopadmap$oe = \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$oe ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$453.$iopadmap$tristate_out = \$iopadmap$tristate_out ; - assign \$auto$rs_design_edit.cc:682:execute$453.clk = clk; - assign \$auto$rs_design_edit.cc:682:execute$453.din = din; - assign \$auto$rs_design_edit.cc:682:execute$453.oe = oe; - assign tristate_out = \$auto$rs_design_edit.cc:682:execute$453.tristate_out ; -endmodule diff --git a/design_edit/Tests/GJC-6/new_sdc.txt b/design_edit/Tests/GJC-6/new_sdc.txt deleted file mode 100644 index 1724c47f6..000000000 --- a/design_edit/Tests/GJC-6/new_sdc.txt +++ /dev/null @@ -1,16 +0,0 @@ -name: HR_5_12_6P - pin: tristate_out - properties: - mode : Mode_BP_SDR_A_TX -name: HP_2_CC_10_5P - pin: clk - properties: - mode : Mode_BP_SDR_A_RX -name: HR_2_8_4P - pin: oe - properties: - mode : Mode_BP_SDR_A_RX -name: HR_2_6_3P - pin: din - properties: - mode : Mode_BP_SDR_A_RX diff --git a/design_edit/Tests/GJC-6/raptor.tcl b/design_edit/Tests/GJC-6/raptor.tcl deleted file mode 100644 index 5b47531dd..000000000 --- a/design_edit/Tests/GJC-6/raptor.tcl +++ /dev/null @@ -1,12 +0,0 @@ -create_design tristate -target_device 1GE100-ES1 -add_design_file tristate.v -add_constraint_file tristate.sdc -ipgenerate -analyze -synth -#packing -#place -#route -#sta - diff --git a/design_edit/Tests/GJC-6/synthesis/tristate_post_synth.eblif b/design_edit/Tests/GJC-6/synthesis/tristate_post_synth.eblif deleted file mode 100644 index 3bbc09290..000000000 --- a/design_edit/Tests/GJC-6/synthesis/tristate_post_synth.eblif +++ /dev/null @@ -1,14 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model tristate -.inputs din oe clk -.outputs tristate_out -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=clk D=din E=$true Q=q1 R=$true -.subckt DFFRE C=clk D=q1 E=$true Q=q2 R=$true -.subckt LUT2 A[0]=oe A[1]=q2 Y=tristate_out -.param INIT_VALUE 1000 -.end diff --git a/design_edit/Tests/GJC-6/synthesis/tristate_post_synth.v b/design_edit/Tests/GJC-6/synthesis/tristate_post_synth.v deleted file mode 100644 index d7ea5cf3c..000000000 --- a/design_edit/Tests/GJC-6/synthesis/tristate_post_synth.v +++ /dev/null @@ -1,64 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module tristate(din, oe, tristate_out, clk); - input clk; - input din; - input oe; - output tristate_out; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] _0_; - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _1_; - (* keep = 32'h00000001 *) - (* src = "tristate.v:15.10-15.13" *) - (* keep = 32'h00000001 *) - (* src = "tristate.v:15.10-15.13" *) - wire clk; - (* keep = 32'h00000001 *) - (* src = "tristate.v:14.10-14.13" *) - (* keep = 32'h00000001 *) - (* src = "tristate.v:14.10-14.13" *) - wire din; - (* keep = 32'h00000001 *) - (* src = "tristate.v:16.10-16.12" *) - (* keep = 32'h00000001 *) - (* src = "tristate.v:16.10-16.12" *) - wire oe; - (* keep = 32'h00000001 *) - (* src = "tristate.v:19.8-19.10" *) - wire q1; - (* keep = 32'h00000001 *) - (* src = "tristate.v:20.8-20.10" *) - wire q2; - (* keep = 32'h00000001 *) - (* src = "tristate.v:17.11-17.23" *) - (* keep = 32'h00000001 *) - (* src = "tristate.v:17.11-17.23" *) - wire tristate_out; - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h8) - ) _2_ ( - .Y(tristate_out), - .A({ q2, oe }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _3_ ( - .C(clk), - .D(q1), - .E(1'h1), - .Q(q2), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/ii/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _4_ ( - .C(clk), - .D(din), - .E(1'h1), - .Q(q1), - .R(1'h1) - ); -endmodule diff --git a/design_edit/Tests/GJC-6/tristate.sdc b/design_edit/Tests/GJC-6/tristate.sdc deleted file mode 100644 index 63db2158a..000000000 --- a/design_edit/Tests/GJC-6/tristate.sdc +++ /dev/null @@ -1,20 +0,0 @@ -set_top_module tristate -# -name is used for creating virtual clock and for actual clock -name option will not be used -create_clock -period 5 clk -# set_clock_uncertainty 0.005 clk -set_input_delay 1 -clock clk [get_ports {din}] -set_input_delay 1 -clock clk [get_ports {oe}] -set_output_delay 1 -clock clk [get_ports {tristate_out}] - -# pin locations -set_property mode Mode_BP_SDR_A_RX HR_2_6_3P -set_pin_loc din HR_2_6_3P - -set_property mode Mode_BP_SDR_A_RX HR_2_8_4P -set_pin_loc oe HR_2_8_4P - -set_property mode Mode_BP_SDR_A_RX HP_2_CC_10_5P -set_pin_loc clk HP_2_CC_10_5P - -set_property mode Mode_BP_SDR_A_TX HR_5_12_6P -set_pin_loc tristate_out HR_5_12_6P diff --git a/design_edit/Tests/GJC-6/tristate.v b/design_edit/Tests/GJC-6/tristate.v deleted file mode 100644 index 19c430906..000000000 --- a/design_edit/Tests/GJC-6/tristate.v +++ /dev/null @@ -1,35 +0,0 @@ -///////////////////////////////////////// -// Functionality: flop to flop path -// Author: George Chen -//////////////////////////////////////// -// `timescale 1ns / 1ps - - -module tristate( - din, - oe, - tristate_out, - clk); - - input din; - input clk; - input oe; - output tristate_out; - - reg q1 ; - reg q2 ; - -always @(posedge clk) - begin - q1 <= din ; - end - -always @(posedge clk) - begin - q2 <= q1 ; - end - - -assign tristate_out = oe ? q2 : 1'bz ; - -endmodule diff --git a/design_edit/Tests/GJC-9/GJC-9.ys b/design_edit/Tests/GJC-9/GJC-9.ys deleted file mode 100644 index b44634875..000000000 --- a/design_edit/Tests/GJC-9/GJC-9.ys +++ /dev/null @@ -1,26 +0,0 @@ - -# Yosys synthesis script for ft -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ft.v - -# Technology mapping -hierarchy -top ft - -setattr -set keep 1 w:\clk -setattr -set keep 1 w:\din -setattr -set keep 1 w:\dout - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 17472 -max_reg 34944 -max_device_dsp 56 -max_device_bram 56 -max_device_carry_length 336 -max_dsp 56 -max_bram 56 -max_carry_length 336 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -sdc ft.sdc -json ./tmp/io_config.json -w ./tmp//wrapper_ft_post_synth.v ./tmp//wrapper_ft_post_synth.eblif - -write_verilog -noexpr -nodec -v ./tmp/ft_post_synth.v -write_blif -param ./tmp/ft_post_synth.eblif - - \ No newline at end of file diff --git a/design_edit/Tests/GJC-9/ft.sdc b/design_edit/Tests/GJC-9/ft.sdc deleted file mode 100644 index e5e03afab..000000000 --- a/design_edit/Tests/GJC-9/ft.sdc +++ /dev/null @@ -1,12 +0,0 @@ -set_top_module ft -# -name is used for creating virtual clock and for actual clock -name option will not be used -create_clock -period 5 -name clk -set_input_delay 1 -clock clk [get_ports {din}] -set_output_delay 1 -clock clk [get_ports {dout}] - -# pin locations -set_property mode Mode_BP_SDR_A_RX HR_2_6_3P -set_pin_loc din HR_2_6_3P - -set_property mode Mode_BP_SDR_A_TX HR_3_12_6P -set_pin_loc dout HR_3_12_6P diff --git a/design_edit/Tests/GJC-9/ft.v b/design_edit/Tests/GJC-9/ft.v deleted file mode 100644 index d06153172..000000000 --- a/design_edit/Tests/GJC-9/ft.v +++ /dev/null @@ -1,15 +0,0 @@ -///////////////////////////////////////// -// Functionality: feedthrough path -// Author: George Chen -//////////////////////////////////////// -// `timescale 1ns / 1ps - - -module ft( din, dout); - - input din; - output dout; - - assign dout = din ; - -endmodule diff --git a/design_edit/Tests/GJC-9/gold/ft_post_synth.eblif b/design_edit/Tests/GJC-9/gold/ft_post_synth.eblif deleted file mode 100644 index b99e5a964..000000000 --- a/design_edit/Tests/GJC-9/gold/ft_post_synth.eblif +++ /dev/null @@ -1,12 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_ft -.inputs $iopadmap$din -.outputs $iopadmap$dout -.names $false -.names $true -1 -.names $undef -.names $iopadmap$din $iopadmap$dout -1 1 -.end diff --git a/design_edit/Tests/GJC-9/gold/ft_post_synth.v b/design_edit/Tests/GJC-9/gold/ft_post_synth.v deleted file mode 100644 index 38fdc0e80..000000000 --- a/design_edit/Tests/GJC-9/gold/ft_post_synth.v +++ /dev/null @@ -1,21 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_ft(_7_, _6_); - input _6_; - output _7_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _0_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _1_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _2_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire _3_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire _4_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire _5_; - wire _6_; - wire _7_; - assign _7_ = _6_; -endmodule diff --git a/design_edit/Tests/GJC-9/gold/io_config.json b/design_edit/Tests/GJC-9/gold/io_config.json deleted file mode 100644 index c483d2ceb..000000000 --- a/design_edit/Tests/GJC-9/gold/io_config.json +++ /dev/null @@ -1,59 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\din (index=0, width=1, offset=0)", - " Detect output port \\dout (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$ft.din", - " Cell port \\I is connected to input port \\din", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$ft.dout", - " Cell port \\O is connected to output port \\dout", - " Trace Clock Buffer", - " Assign location HR_2_6_3P (and properties) to Port din", - " Assign location HR_3_12_6P (and properties) to Port dout", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$ft.din", - "linked_object" : "din", - "linked_objects" : { - "din" : { - "location" : "HR_2_6_3P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "din", - "O" : "$iopadmap$din" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$ft.dout", - "linked_object" : "dout", - "linked_objects" : { - "dout" : { - "location" : "HR_3_12_6P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$dout", - "O" : "dout" - }, - "parameters" : { - } - } - ] -} diff --git a/design_edit/Tests/GJC-9/gold/wrapper_ft_post_synth.eblif b/design_edit/Tests/GJC-9/gold/wrapper_ft_post_synth.eblif deleted file mode 100644 index 793af0044..000000000 --- a/design_edit/Tests/GJC-9/gold/wrapper_ft_post_synth.eblif +++ /dev/null @@ -1,22 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model ft -.inputs din -.outputs dout -.names $false -.names $true -1 -.names $undef -.subckt fabric_ft $iopadmap$din=$iopadmap$din $iopadmap$dout=$iopadmap$dout -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$395.din O=$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$din -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$dout O=$auto$rs_design_edit.cc:682:execute$395.dout -.names $flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$din $iopadmap$din -1 1 -.names $iopadmap$dout $flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$dout -1 1 -.names din $auto$rs_design_edit.cc:682:execute$395.din -1 1 -.names $auto$rs_design_edit.cc:682:execute$395.dout dout -1 1 -.end diff --git a/design_edit/Tests/GJC-9/gold/wrapper_ft_post_synth.v b/design_edit/Tests/GJC-9/gold/wrapper_ft_post_synth.v deleted file mode 100644 index 741620148..000000000 --- a/design_edit/Tests/GJC-9/gold/wrapper_ft_post_synth.v +++ /dev/null @@ -1,51 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module ft(din, dout); - input din; - output dout; - wire \$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$din ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$dout ; - (* keep = 32'd1 *) - (* src = "ft.v:11.10-11.14" *) - wire \$auto$rs_design_edit.cc:682:execute$395.dout ; - (* keep = 32'd1 *) - (* src = "ft.v:10.9-10.12" *) - wire \$auto$rs_design_edit.cc:682:execute$395.din ; - (* keep = 32'd1 *) - (* src = "ft.v:10.9-10.12" *) - (* keep = 32'd1 *) - (* src = "ft.v:10.9-10.12" *) - wire din; - (* keep = 32'd1 *) - (* src = "ft.v:11.10-11.14" *) - (* keep = 32'd1 *) - (* src = "ft.v:11.10-11.14" *) - wire dout; - wire \$iopadmap$dout ; - wire \$iopadmap$din ; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$ft.dout ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$dout ), - .O(\$auto$rs_design_edit.cc:682:execute$395.dout ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$ft.din ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$395.din ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$din ) - ); - fabric_ft \$auto$rs_design_edit.cc:680:execute$394 ( - .\$iopadmap$din (\$iopadmap$din ), - .\$iopadmap$dout (\$iopadmap$dout ) - ); - assign \$iopadmap$din = \$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$din ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$395.$iopadmap$dout = \$iopadmap$dout ; - assign \$auto$rs_design_edit.cc:682:execute$395.din = din; - assign dout = \$auto$rs_design_edit.cc:682:execute$395.dout ; -endmodule diff --git a/design_edit/Tests/GJC-9/new_sdc.txt b/design_edit/Tests/GJC-9/new_sdc.txt deleted file mode 100644 index fcd5ceca0..000000000 --- a/design_edit/Tests/GJC-9/new_sdc.txt +++ /dev/null @@ -1,8 +0,0 @@ -name: HR_3_12_6P - pin: dout - properties: - mode : Mode_BP_SDR_A_TX -name: HR_2_6_3P - pin: din - properties: - mode : Mode_BP_SDR_A_RX diff --git a/design_edit/Tests/GJC-9/raptor.tcl b/design_edit/Tests/GJC-9/raptor.tcl deleted file mode 100644 index 6660dbe34..000000000 --- a/design_edit/Tests/GJC-9/raptor.tcl +++ /dev/null @@ -1,12 +0,0 @@ -create_design ft -target_device 1GVTC -add_design_file ft.v -add_constraint_file ft.sdc -ipgenerate -analyze -synth -#packing -#place -#route -#sta - diff --git a/design_edit/Tests/GJC-9/synthesis/ft_post_synth.eblif b/design_edit/Tests/GJC-9/synthesis/ft_post_synth.eblif deleted file mode 100644 index fb6db0fe0..000000000 --- a/design_edit/Tests/GJC-9/synthesis/ft_post_synth.eblif +++ /dev/null @@ -1,12 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model ft -.inputs din -.outputs dout -.names $false -.names $true -1 -.names $undef -.names din dout -1 1 -.end diff --git a/design_edit/Tests/GJC-9/synthesis/ft_post_synth.v b/design_edit/Tests/GJC-9/synthesis/ft_post_synth.v deleted file mode 100644 index d1cda6cab..000000000 --- a/design_edit/Tests/GJC-9/synthesis/ft_post_synth.v +++ /dev/null @@ -1,17 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module ft(din, dout); - input din; - output dout; - (* keep = 32'h00000001 *) - (* src = "ft.v:10.9-10.12" *) - (* keep = 32'h00000001 *) - (* src = "ft.v:10.9-10.12" *) - wire din; - (* keep = 32'h00000001 *) - (* src = "ft.v:11.10-11.14" *) - (* keep = 32'h00000001 *) - (* src = "ft.v:11.10-11.14" *) - wire dout; - assign dout = din; -endmodule diff --git a/design_edit/Tests/GJC19/GJC19.ys b/design_edit/Tests/GJC19/GJC19.ys index d86e17a52..27d4b6be5 100644 --- a/design_edit/Tests/GJC19/GJC19.ys +++ b/design_edit/Tests/GJC19/GJC19.ys @@ -19,7 +19,7 @@ hierarchy -auto-top plugin -i design-edit design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_GJC19_post_synth.v ./tmp//wrapper_GJC19_post_synth.eblif -write_verilog -noexpr -nodec -v ./tmp/fabric_GJC19_post_synth.v +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_GJC19_post_synth.v write_blif -param ./tmp/fabric_GJC19_post_synth.eblif \ No newline at end of file diff --git a/design_edit/Tests/LUT_to_IDELAY/LUT_to_IDELAY.ys b/design_edit/Tests/I_BUF_TO_I_DELAY/I_BUF_TO_I_DELAY.ys similarity index 52% rename from design_edit/Tests/LUT_to_IDELAY/LUT_to_IDELAY.ys rename to design_edit/Tests/I_BUF_TO_I_DELAY/I_BUF_TO_I_DELAY.ys index 2ee6c53f8..6eedb182e 100644 --- a/design_edit/Tests/LUT_to_IDELAY/LUT_to_IDELAY.ys +++ b/design_edit/Tests/I_BUF_TO_I_DELAY/I_BUF_TO_I_DELAY.ys @@ -3,15 +3,15 @@ # Read source files read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v verilog_defines -read_verilog ./rtl/LUT_to_IDELAY.v +read_verilog ./rtl/I_BUF_TO_I_DELAY.v # Technology mapping hierarchy -auto-top plugin -i design-edit -design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_LUT_to_IDELAY_post_synth.v ./tmp//wrapper_LUT_to_IDELAY_post_synth.eblif +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_BUF_TO_I_DELAY_post_synth.v ./tmp//wrapper_I_BUF_TO_I_DELAY_post_synth.eblif -write_verilog -noexpr -nodec -v ./tmp/fabric_LUT_to_IDELAY_post_synth.v -write_blif -param ./tmp/fabric_LUT_to_IDELAY_post_synth.eblif +write_verilog -noexpr -nodec -v ./tmp/fabric_I_BUF_TO_I_DELAY_post_synth.v +write_blif -param ./tmp/fabric_I_BUF_TO_I_DELAY_post_synth.eblif \ No newline at end of file diff --git a/design_edit/Tests/LUT_to_IDELAY/pin_constraints.pin b/design_edit/Tests/I_BUF_TO_I_DELAY/pin_constraints.pin similarity index 100% rename from design_edit/Tests/LUT_to_IDELAY/pin_constraints.pin rename to design_edit/Tests/I_BUF_TO_I_DELAY/pin_constraints.pin diff --git a/design_edit/Tests/LUT_to_IDELAY/rtl/LUT_to_IDELAY.v b/design_edit/Tests/I_BUF_TO_I_DELAY/rtl/I_BUF_TO_I_DELAY.v similarity index 100% rename from design_edit/Tests/LUT_to_IDELAY/rtl/LUT_to_IDELAY.v rename to design_edit/Tests/I_BUF_TO_I_DELAY/rtl/I_BUF_TO_I_DELAY.v diff --git a/design_edit/Tests/I_BUF_to_IDDR_ctrl/I_BUF_to_IDDR_ctrl.ys b/design_edit/Tests/I_BUF_to_IDDR_ctrl/I_BUF_to_IDDR_ctrl.ys new file mode 100644 index 000000000..4d9802ed0 --- /dev/null +++ b/design_edit/Tests/I_BUF_to_IDDR_ctrl/I_BUF_to_IDDR_ctrl.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_BUF_to_IDDR_ctrl.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_BUF_to_IDDR_ctrl.v +#write_blif -param ./tmp/I_BUF_to_IDDR_ctrl.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_BUF_to_IDDR_ctrl.v ./tmp//wrapper_I_BUF_to_IDDR_ctrl.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_BUF_to_IDDR_ctrl.v +write_blif -param ./tmp/fabric_I_BUF_to_IDDR_ctrl.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_BUF_to_IDDR_ctrl/pin_constraints.pin b/design_edit/Tests/I_BUF_to_IDDR_ctrl/pin_constraints.pin new file mode 100644 index 000000000..990c57c03 --- /dev/null +++ b/design_edit/Tests/I_BUF_to_IDDR_ctrl/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clk_i_buf HP_1_CC_18_9P + +set_pin_loc dly_inc_pulse_inv_buf HP_1_0_0P + +set_pin_loc data_i HP_1_1_0N + +set_pin_loc enable_buf HP_1_4_2P + +set_pin_loc reset_n_buf HP_1_3_1N + +set_pin_loc data_o_buf[0] HP_1_6_3P + +set_pin_loc data_o_buf[1] HP_1_8_4P \ No newline at end of file diff --git a/design_edit/Tests/I_BUF_to_IDDR_ctrl/rtl/I_BUF_to_IDDR_ctrl.v b/design_edit/Tests/I_BUF_to_IDDR_ctrl/rtl/I_BUF_to_IDDR_ctrl.v new file mode 100644 index 000000000..2bcb5ecdc --- /dev/null +++ b/design_edit/Tests/I_BUF_to_IDDR_ctrl/rtl/I_BUF_to_IDDR_ctrl.v @@ -0,0 +1,296 @@ +/* Generated by Yosys 0.44 (git sha1 86a09ee26, g++ 11.2.1 -fPIC -O3) */ + +module GJC31(data_i, reset_n_buf, enable_buf, clk_i_buf, dly_inc_pulse_inv_buf, data_o_buf); + input clk_i_buf; + input data_i; + output [1:0] data_o_buf; + input dly_inc_pulse_inv_buf; + input enable_buf; + input reset_n_buf; + wire \$abc$238$auto_53 ; + wire \$abc$250$li0_li0 ; + wire \$abc$250$li1_li1 ; + wire \$abc$250$li2_li2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire \$f2g_in_en_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire \$f2g_trx_dly_adj_dly_adj ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire \$f2g_trx_dly_inc_dly_adj ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:22.9-22.15" *) + wire \$f2g_trx_dly_ld_dly_ld ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:24.10-24.17" *) + wire \$f2g_trx_reset_n_reset_n ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \$f2g_tx_out_data_o[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \$f2g_tx_out_data_o[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire \$ofab_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.16-26.25" *) + wire clk_buf_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.10-26.15" *) + wire clk_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:15.18-15.27" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:15.18-15.27" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.26-26.33" *) + wire clk_pll; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:12.18-12.24" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:21.10-21.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:21.22-21.40" *) + wire data_i_buf_delayed; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \data_o[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \data_o[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:17.24-17.34" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:17.24-17.34" *) + wire [1:0] data_o_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:20.16-20.24" *) + wire \data_reg[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:20.16-20.24" *) + wire \data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:27.10-27.27" *) + wire dly_inc_pulse_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:16.18-16.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:16.18-16.39" *) + wire dly_inc_pulse_inv_buf; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:22.9-22.15" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire enable; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:14.18-14.28" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:14.18-14.28" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:24.10-24.17" *) + wire reset_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:13.18-13.29" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:13.18-13.29" *) + wire reset_n_buf; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_251 ( + .C(clk_i), + .D(\$abc$250$li0_li0 ), + .E(\$abc$238$auto_53 ), + .Q(\data_o[0] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_252 ( + .C(clk_i), + .D(\$abc$250$li1_li1 ), + .E(\$abc$238$auto_53 ), + .Q(\data_o[1] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_253 ( + .C(clk_i), + .D(\$abc$250$li2_li2 ), + .E(\$abc$238$auto_53 ), + .Q(dly_ld), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$596$auto_597 ( + .A({ \data_reg[1] , reset_n }), + .Y(\$abc$250$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$596$auto_598 ( + .A({ \data_reg[0] , reset_n }), + .Y(\$abc$250$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'hb) + ) \$abc$596$auto_599 ( + .A({ reset_n, enable }), + .Y(\$abc$238$auto_53 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$596$auto_600 ( + .A(dly_inc_pulse_inv), + .Y(dly_adj) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$596$auto_601 ( + .A(reset_n), + .Y(\$abc$250$li2_li2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_in_en_enable_1 ( + .I(enable), + .O(\$f2g_in_en_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_adj_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_inc_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_1 ( + .I(dly_ld), + .O(\$f2g_trx_dly_ld_dly_ld ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_n_1 ( + .I(reset_n), + .O(\$f2g_trx_reset_n_reset_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_o[0]_1 ( + .I(\data_o[0] ), + .O(\$f2g_tx_out_data_o[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_o[1]_1 ( + .I(\data_o[1] ), + .O(\$f2g_tx_out_data_o[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_1 ( + .I(enable), + .O(\$ofab_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:31.39-31.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(reset_n_buf), + .O(reset_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:32.39-32.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(enable_buf), + .O(enable) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:33.39-33.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_buf_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:34.39-34.93" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_inc_pulse_inv_buf), + .O(dly_inc_pulse_inv) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:42.60-46.10" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000020), + .PLL_MULT(32'sh00000064), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen ( + .CLK_IN(clk_pll), + .CLK_OUT(clk_i), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:40.13-40.45" *) + CLK_BUF clock_buffer ( + .I(clk_buf_i), + .O(clk_pll) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:51.11-51.46" *) + I_BUF data_buf ( + .EN(\$f2g_in_en_enable ), + .I(data_i), + .O(data_i_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:58.11-58.76" *) + I_DDR data_i_ddr ( + .C(clk_i), + .D(data_i_buf_delayed), + .E(enable ), + .Q({ \data_reg[1] , \data_reg[0] }), + .R(\$f2g_trx_reset_n_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:52.13-57.52" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) data_i_delay ( + .CLK_IN(clk_i), + .DLY_ADJ(\$f2g_trx_dly_adj_dly_adj ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_adj ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld ), + .I(data_i_buf), + .O(data_i_buf_delayed) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:35.11-35.44" *) + O_BUFT obuf0_ ( + .I(\$f2g_tx_out_data_o[0] ), + .O(data_o_buf[0]), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:36.11-36.44" *) + O_BUFT obuf1_ ( + .I(\$f2g_tx_out_data_o[1] ), + .O(data_o_buf[1]), + .T(1'h1) + ); +endmodule diff --git a/design_edit/Tests/I_BUF_to_I_SERDES/I_BUF_to_I_SERDES.ys b/design_edit/Tests/I_BUF_to_I_SERDES/I_BUF_to_I_SERDES.ys new file mode 100644 index 000000000..fb4f569db --- /dev/null +++ b/design_edit/Tests/I_BUF_to_I_SERDES/I_BUF_to_I_SERDES.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_BUF_to_I_SERDES.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_BUF_to_I_SERDES.v +#write_blif -param ./tmp/I_BUF_to_I_SERDES.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_BUF_to_I_SERDES.v ./tmp//wrapper_I_BUF_to_I_SERDES.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_BUF_to_I_SERDES.v +write_blif -param ./tmp/fabric_I_BUF_to_I_SERDES.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_BUF_to_I_SERDES/pin_constraints.pin b/design_edit/Tests/I_BUF_to_I_SERDES/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/I_BUF_to_I_SERDES/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/I_BUF_to_I_SERDES/rtl/I_BUF_to_I_SERDES.v b/design_edit/Tests/I_BUF_to_I_SERDES/rtl/I_BUF_to_I_SERDES.v new file mode 100644 index 000000000..3b9732a9c --- /dev/null +++ b/design_edit/Tests/I_BUF_to_I_SERDES/rtl/I_BUF_to_I_SERDES.v @@ -0,0 +1,783 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_buf), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/I_BUF_to_I_SERDES_in_ctrl/I_BUF_to_I_SERDES_in_ctrl.ys b/design_edit/Tests/I_BUF_to_I_SERDES_in_ctrl/I_BUF_to_I_SERDES_in_ctrl.ys new file mode 100644 index 000000000..e903da3b0 --- /dev/null +++ b/design_edit/Tests/I_BUF_to_I_SERDES_in_ctrl/I_BUF_to_I_SERDES_in_ctrl.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_BUF_to_I_SERDES_in_ctrl.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_BUF_to_I_SERDES_in_ctrl.v +#write_blif -param ./tmp/I_BUF_to_I_SERDES_in_ctrl.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_BUF_to_I_SERDES_in_ctrl.v ./tmp//wrapper_I_BUF_to_I_SERDES_in_ctrl.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_BUF_to_I_SERDES_in_ctrl.v +write_blif -param ./tmp/fabric_I_BUF_to_I_SERDES_in_ctrl.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_BUF_to_I_SERDES_in_ctrl/pin_constraints.pin b/design_edit/Tests/I_BUF_to_I_SERDES_in_ctrl/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/I_BUF_to_I_SERDES_in_ctrl/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/I_BUF_to_I_SERDES_in_ctrl/rtl/I_BUF_to_I_SERDES_in_ctrl.v b/design_edit/Tests/I_BUF_to_I_SERDES_in_ctrl/rtl/I_BUF_to_I_SERDES_in_ctrl.v new file mode 100644 index 000000000..14474f722 --- /dev/null +++ b/design_edit/Tests/I_BUF_to_I_SERDES_in_ctrl/rtl/I_BUF_to_I_SERDES_in_ctrl.v @@ -0,0 +1,783 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(bitslip_ctrl_n_buf ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/I_BUF_to_O_SERDES/I_BUF_to_O_SERDES.ys b/design_edit/Tests/I_BUF_to_O_SERDES/I_BUF_to_O_SERDES.ys new file mode 100644 index 000000000..d42818d28 --- /dev/null +++ b/design_edit/Tests/I_BUF_to_O_SERDES/I_BUF_to_O_SERDES.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_BUF_to_O_SERDES.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_BUF_to_O_SERDES.v +#write_blif -param ./tmp/I_BUF_to_O_SERDES.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_BUF_to_O_SERDES.v ./tmp//wrapper_I_BUF_to_O_SERDES.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_BUF_to_O_SERDES.v +write_blif -param ./tmp/fabric_I_BUF_to_O_SERDES.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_BUF_to_O_SERDES/pin_constraints.pin b/design_edit/Tests/I_BUF_to_O_SERDES/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/I_BUF_to_O_SERDES/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/I_BUF_to_O_SERDES/rtl/I_BUF_to_O_SERDES.v b/design_edit/Tests/I_BUF_to_O_SERDES/rtl/I_BUF_to_O_SERDES.v new file mode 100644 index 000000000..6b1faa1c6 --- /dev/null +++ b/design_edit/Tests/I_BUF_to_O_SERDES/rtl/I_BUF_to_O_SERDES.v @@ -0,0 +1,794 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + wire \$data_i_serdes ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$data_i_serdes , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$delay_in ( + .EN(1'h1), + .I(\$f2g_tx_out_data_i_serdes_reg[9] ), + .O(\$data_i_serdes ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/I_DDR_to_I_BUF/I_DDR_to_I_BUF.ys b/design_edit/Tests/I_DDR_to_I_BUF/I_DDR_to_I_BUF.ys new file mode 100644 index 000000000..d09061811 --- /dev/null +++ b/design_edit/Tests/I_DDR_to_I_BUF/I_DDR_to_I_BUF.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_DDR_to_I_BUF.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_DDR_to_I_BUF.v +#write_blif -param ./tmp/I_DDR_to_I_BUF.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_DDR_to_I_BUF.v ./tmp//wrapper_I_DDR_to_I_BUF.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_DDR_to_I_BUF.v +write_blif -param ./tmp/fabric_I_DDR_to_I_BUF.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_DDR_to_I_BUF/pin_constraints.pin b/design_edit/Tests/I_DDR_to_I_BUF/pin_constraints.pin new file mode 100644 index 000000000..990c57c03 --- /dev/null +++ b/design_edit/Tests/I_DDR_to_I_BUF/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clk_i_buf HP_1_CC_18_9P + +set_pin_loc dly_inc_pulse_inv_buf HP_1_0_0P + +set_pin_loc data_i HP_1_1_0N + +set_pin_loc enable_buf HP_1_4_2P + +set_pin_loc reset_n_buf HP_1_3_1N + +set_pin_loc data_o_buf[0] HP_1_6_3P + +set_pin_loc data_o_buf[1] HP_1_8_4P \ No newline at end of file diff --git a/design_edit/Tests/I_DDR_to_I_BUF/rtl/I_DDR_to_I_BUF.v b/design_edit/Tests/I_DDR_to_I_BUF/rtl/I_DDR_to_I_BUF.v new file mode 100644 index 000000000..cd2773042 --- /dev/null +++ b/design_edit/Tests/I_DDR_to_I_BUF/rtl/I_DDR_to_I_BUF.v @@ -0,0 +1,305 @@ +/* Generated by Yosys 0.44 (git sha1 86a09ee26, g++ 11.2.1 -fPIC -O3) */ + +module GJC31(data_i, reset_n_buf, enable_buf, clk_i_buf, dly_inc_pulse_inv_buf, data_o_buf); + input clk_i_buf; + input data_i; + output [1:0] data_o_buf; + input dly_inc_pulse_inv_buf; + input enable_buf; + input reset_n_buf; + wire \$abc$238$auto_53 ; + wire \$abc$250$li0_li0 ; + wire \$abc$250$li1_li1 ; + wire \$abc$250$li2_li2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire \$f2g_in_en_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire \$f2g_trx_dly_adj_dly_adj ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire \$f2g_trx_dly_inc_dly_adj ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:22.9-22.15" *) + wire \$f2g_trx_dly_ld_dly_ld ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:24.10-24.17" *) + wire \$f2g_trx_reset_n_reset_n ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \$f2g_tx_out_data_o[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \$f2g_tx_out_data_o[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire \$ofab_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.16-26.25" *) + wire clk_buf_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.10-26.15" *) + wire clk_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:15.18-15.27" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:15.18-15.27" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.26-26.33" *) + wire clk_pll; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:12.18-12.24" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:21.10-21.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:21.22-21.40" *) + wire data_i_buf_delayed; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \data_o[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \data_o[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:17.24-17.34" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:17.24-17.34" *) + wire [1:0] data_o_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:20.16-20.24" *) + wire \data_reg_ ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:20.16-20.24" *) + wire \data_reg[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:20.16-20.24" *) + wire \data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:27.10-27.27" *) + wire dly_inc_pulse_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:16.18-16.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:16.18-16.39" *) + wire dly_inc_pulse_inv_buf; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:22.9-22.15" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire enable; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:14.18-14.28" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:14.18-14.28" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:24.10-24.17" *) + wire reset_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:13.18-13.29" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:13.18-13.29" *) + wire reset_n_buf; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_251 ( + .C(clk_i), + .D(\$abc$250$li0_li0 ), + .E(\$abc$238$auto_53 ), + .Q(\data_o[0] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_252 ( + .C(clk_i), + .D(\$abc$250$li1_li1 ), + .E(\$abc$238$auto_53 ), + .Q(\data_o[1] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_253 ( + .C(clk_i), + .D(\$abc$250$li2_li2 ), + .E(\$abc$238$auto_53 ), + .Q(dly_ld), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$596$auto_597 ( + .A({ \data_reg[1] , reset_n }), + .Y(\$abc$250$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$596$auto_598 ( + .A({ \data_reg[0] , reset_n }), + .Y(\$abc$250$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'hb) + ) \$abc$596$auto_599 ( + .A({ reset_n, enable }), + .Y(\$abc$238$auto_53 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$596$auto_600 ( + .A(dly_inc_pulse_inv), + .Y(dly_adj) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$596$auto_601 ( + .A(reset_n), + .Y(\$abc$250$li2_li2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_in_en_enable_1 ( + .I(enable), + .O(\$f2g_in_en_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_adj_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_inc_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_1 ( + .I(dly_ld), + .O(\$f2g_trx_dly_ld_dly_ld ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_n_1 ( + .I(reset_n), + .O(\$f2g_trx_reset_n_reset_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_o[0]_1 ( + .I(\data_o[0] ), + .O(\$f2g_tx_out_data_o[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_o[1]_1 ( + .I(\data_o[1] ), + .O(\$f2g_tx_out_data_o[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_1 ( + .I(enable), + .O(\$ofab_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:31.39-31.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(reset_n_buf), + .O(reset_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:32.39-32.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(enable_buf), + .O(enable) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:33.39-33.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_buf_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:34.39-34.93" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_inc_pulse_inv_buf), + .O(dly_inc_pulse_inv) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:42.60-46.10" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000020), + .PLL_MULT(32'sh00000064), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen ( + .CLK_IN(clk_pll), + .CLK_OUT(clk_i), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:40.13-40.45" *) + CLK_BUF clock_buffer ( + .I(clk_buf_i), + .O(clk_pll) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:51.11-51.46" *) + I_BUF data_buf ( + .EN(\$f2g_in_en_enable ), + .I(data_i), + .O(data_i_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:58.11-58.76" *) + I_DDR data_i_ddr ( + .C(clk_i), + .D(data_i_buf_delayed), + .E(\$ofab_enable ), + .Q({ \data_reg[1] , \data_reg_ }), + .R(\$f2g_trx_reset_n_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:52.13-57.52" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) data_i_delay ( + .CLK_IN(clk_i), + .DLY_ADJ(\$f2g_trx_dly_adj_dly_adj ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_adj ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld ), + .I(data_i_buf), + .O(data_i_buf_delayed) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:51.11-51.46" *) + I_BUF dreg ( + .EN(\$f2g_in_en_enable ), + .I(\data_reg_ ), + .O(\data_reg[0] ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:35.11-35.44" *) + O_BUFT obuf0_ ( + .I(\$f2g_tx_out_data_o[0] ), + .O(data_o_buf[0]), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:36.11-36.44" *) + O_BUFT obuf1_ ( + .I(\$f2g_tx_out_data_o[1] ), + .O(data_o_buf[1]), + .T(1'h1) + ); +endmodule diff --git a/design_edit/Tests/I_DELAY_octrl_to_I_BUF/I_DELAY_octrl_to_I_BUF.ys b/design_edit/Tests/I_DELAY_octrl_to_I_BUF/I_DELAY_octrl_to_I_BUF.ys new file mode 100644 index 000000000..d71b8e034 --- /dev/null +++ b/design_edit/Tests/I_DELAY_octrl_to_I_BUF/I_DELAY_octrl_to_I_BUF.ys @@ -0,0 +1,17 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_DELAY_octrl_to_I_BUF.v + +# Technology mapping +hierarchy -auto-top + +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_DELAY_octrl_to_I_BUF_post_synth.v ./tmp//wrapper_I_DELAY_octrl_to_I_BUF_post_synth.eblif + +write_verilog -noexpr -nodec -v ./tmp/fabric_I_DELAY_octrl_to_I_BUF_post_synth.v +write_blif -param ./tmp/fabric_I_DELAY_octrl_to_I_BUF_post_synth.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_DELAY_octrl_to_I_BUF/pin_constraints.pin b/design_edit/Tests/I_DELAY_octrl_to_I_BUF/pin_constraints.pin new file mode 100644 index 000000000..901583ed2 --- /dev/null +++ b/design_edit/Tests/I_DELAY_octrl_to_I_BUF/pin_constraints.pin @@ -0,0 +1 @@ +set_pin_loc clk_i_buf HP_1_CC_18_9P diff --git a/design_edit/Tests/I_DELAY_octrl_to_I_BUF/rtl/I_DELAY_octrl_to_I_BUF.v b/design_edit/Tests/I_DELAY_octrl_to_I_BUF/rtl/I_DELAY_octrl_to_I_BUF.v new file mode 100644 index 000000000..3b0a53bcf --- /dev/null +++ b/design_edit/Tests/I_DELAY_octrl_to_I_BUF/rtl/I_DELAY_octrl_to_I_BUF.v @@ -0,0 +1,308 @@ +/* Generated by Yosys 0.38 (git sha1 6c475f1f1, gcc 11.2.1 -fPIC -Os) */ + +module GJC19(clk_i_buf, data_i, dly_incdec_buf, dly_ld_buf, dly_adj_buf, data_o_inv_delayed_buf, dly_tap_val_inv_buf); + input clk_i_buf; + input data_i; + output data_o_inv_delayed_buf; + input dly_adj_buf; + input dly_incdec_buf; + input dly_ld_buf; + output [5:0] dly_tap_val_inv_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.26-21.37" *) + wire \$f2g_trx_dly_adj_dly_adj_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.10-21.24" *) + wire \$f2g_trx_dly_inc_dly_incdec_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.39-21.49" *) + wire \$f2g_trx_dly_ld_dly_ld_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:24.10-24.19" *) + wire clk_buf_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:25.10-25.15" *) + wire clk_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:10.16-10.25" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:10.16-10.25" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:11.16-11.22" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:11.16-11.22" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:19.10-19.16" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:30.10-30.28" *) + wire data_o_inv_delayed; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:15.17-15.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:15.17-15.39" *) + wire data_o_inv_delayed_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:28.10-28.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:14.16-14.27" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:14.16-14.27" *) + wire dly_adj_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.26-21.37" *) + wire dly_adj_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:26.10-26.20" *) + wire dly_incdec; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:12.16-12.30" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:12.16-12.30" *) + wire dly_incdec_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.10-21.24" *) + wire dly_incdec_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:27.10-27.16" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:13.16-13.26" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:13.16-13.26" *) + wire dly_ld_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.39-21.49" *) + wire dly_ld_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:16.23-16.42" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:16.23-16.42" *) + wire [5:0] dly_tap_val_inv_buf; + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_481 ( + .A(data_o), + .Y(data_o_inv_delayed) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_482 ( + .A(dly_incdec), + .Y(dly_incdec_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_483 ( + .A(dly_adj), + .Y(dly_adj_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_484 ( + .A(dly_ld), + .Y(dly_ld_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_486 ( + .A(\dly_tap_val[4] ), + .Y(\dly_tap_val_inv[4] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_487 ( + .A(\dly_tap_val[3] ), + .Y(\dly_tap_val_inv[3] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_488 ( + .A(\dly_tap_val[2] ), + .Y(\dly_tap_val_inv[2] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_489 ( + .A(\dly_tap_val[1] ), + .Y(\dly_tap_val_inv[1] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_490 ( + .A(\dly_tap_val[0] ), + .Y(\dly_tap_val_inv[0] ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_incdec_inv_1 ( + .I(dly_incdec_inv), + .O(\$f2g_trx_dly_inc_dly_incdec_inv ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_inv_1 ( + .I(dly_ld_inv), + .O(\$f2g_trx_dly_ld_dly_ld_inv ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[0]_1 ( + .I(\$ifab_dly_tap_val[0] ), + .O(\dly_tap_val[0] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[1]_1 ( + .I(\$ifab_dly_tap_val[1] ), + .O(\dly_tap_val[1] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[2]_1 ( + .I(\$ifab_dly_tap_val[2] ), + .O(\dly_tap_val[2] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[3]_1 ( + .I(\$ifab_dly_tap_val[3] ), + .O(\dly_tap_val[3] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[4]_1 ( + .I(\$ifab_dly_tap_val[4] ), + .O(\dly_tap_val[4] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:33.39-33.69" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_i) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:34.39-34.79" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(dly_incdec_buf), + .O(dly_incdec) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:35.39-35.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(dly_ld_buf), + .O(dly_ld) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:36.39-36.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_adj_buf), + .O(dly_adj) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:47.13-47.43" *) + CLK_BUF clock_buffer ( + .I(clk_i), + .O(clk_buf_i) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:56.11-56.46" *) + I_BUF data_buf ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:57.13-63.40" *) + I_DELAY #( + .DELAY(32'h00000000) + ) data_i_delay ( + .CLK_IN(clk_buf_i), + .DLY_ADJ(dly_adj_inv ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_incdec_inv ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld_inv ), + .DLY_TAP_VALUE({ \dly_tap_val_inv[5] , \$ifab_dly_tap_val[4] , \$ifab_dly_tap_val[3] , \$ifab_dly_tap_val[2] , \$ifab_dly_tap_val[1] , \$ifab_dly_tap_val[0] }), + .I(data_i_buf), + .O(data_o) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:37.11-37.62" *) + O_BUF obuf00_ ( + .I(data_o_inv_delayed), + .O(data_o_inv_delayed_buf) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:38.11-38.62" *) + O_BUF obuf0_ ( + .I(\dly_tap_val_inv[0] ), + .O(dly_tap_val_inv_buf[0]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:39.11-39.62" *) + O_BUF obuf1_ ( + .I(\dly_tap_val_inv[1] ), + .O(dly_tap_val_inv_buf[1]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:40.11-40.62" *) + O_BUF obuf2_ ( + .I(\dly_tap_val_inv[2] ), + .O(dly_tap_val_inv_buf[2]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:41.11-41.62" *) + O_BUF obuf3_ ( + .I(\dly_tap_val_inv[3] ), + .O(dly_tap_val_inv_buf[3]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:42.11-42.62" *) + O_BUF obuf4_ ( + .I(\dly_tap_val_inv[4] ), + .O(dly_tap_val_inv_buf[4]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:43.11-43.62" *) + I_BUF obuf5_ ( + .EN(1'h1), + .I(\dly_tap_val_inv[5] ), + .O(dly_tap_val_inv_buf[5]) + ); +endmodule diff --git a/design_edit/Tests/I_DELAY_to_I_BUF/I_DELAY_to_I_BUF.ys b/design_edit/Tests/I_DELAY_to_I_BUF/I_DELAY_to_I_BUF.ys new file mode 100644 index 000000000..0b1982e5d --- /dev/null +++ b/design_edit/Tests/I_DELAY_to_I_BUF/I_DELAY_to_I_BUF.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_DELAY_to_I_BUF.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_DELAY_to_I_BUF.v +#write_blif -param ./tmp/I_DELAY_to_I_BUF.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_DELAY_to_I_BUF.v ./tmp//wrapper_I_DELAY_to_I_BUF.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_DELAY_to_I_BUF.v +write_blif -param ./tmp/fabric_I_DELAY_to_I_BUF.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_DELAY_to_I_BUF/pin_constraints.pin b/design_edit/Tests/I_DELAY_to_I_BUF/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/I_DELAY_to_I_BUF/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/I_DELAY_to_I_BUF/rtl/I_DELAY_to_I_BUF.v b/design_edit/Tests/I_DELAY_to_I_BUF/rtl/I_DELAY_to_I_BUF.v new file mode 100644 index 000000000..1586685b9 --- /dev/null +++ b/design_edit/Tests/I_DELAY_to_I_BUF/rtl/I_DELAY_to_I_BUF.v @@ -0,0 +1,795 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay_; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$idelay_out ( + .EN(1'h1), + .I(data_i_delay_), + .O(data_i_delay) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay_) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/I_DELAY_to_I_DDR/I_DELAY_to_I_DDR.ys b/design_edit/Tests/I_DELAY_to_I_DDR/I_DELAY_to_I_DDR.ys new file mode 100644 index 000000000..33f527a57 --- /dev/null +++ b/design_edit/Tests/I_DELAY_to_I_DDR/I_DELAY_to_I_DDR.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_DELAY_to_I_DDR.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_DELAY_to_I_DDR.v +#write_blif -param ./tmp/I_DELAY_to_I_DDR.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_DELAY_to_I_DDR.v ./tmp//wrapper_I_DELAY_to_I_DDR.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_DELAY_to_I_DDR.v +write_blif -param ./tmp/fabric_I_DELAY_to_I_DDR.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_DELAY_to_I_DDR/pin_constraints.pin b/design_edit/Tests/I_DELAY_to_I_DDR/pin_constraints.pin new file mode 100644 index 000000000..990c57c03 --- /dev/null +++ b/design_edit/Tests/I_DELAY_to_I_DDR/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clk_i_buf HP_1_CC_18_9P + +set_pin_loc dly_inc_pulse_inv_buf HP_1_0_0P + +set_pin_loc data_i HP_1_1_0N + +set_pin_loc enable_buf HP_1_4_2P + +set_pin_loc reset_n_buf HP_1_3_1N + +set_pin_loc data_o_buf[0] HP_1_6_3P + +set_pin_loc data_o_buf[1] HP_1_8_4P \ No newline at end of file diff --git a/design_edit/Tests/I_DELAY_to_I_DDR/rtl/I_DELAY_to_I_DDR.v b/design_edit/Tests/I_DELAY_to_I_DDR/rtl/I_DELAY_to_I_DDR.v new file mode 100644 index 000000000..d2b6e3933 --- /dev/null +++ b/design_edit/Tests/I_DELAY_to_I_DDR/rtl/I_DELAY_to_I_DDR.v @@ -0,0 +1,296 @@ +/* Generated by Yosys 0.44 (git sha1 86a09ee26, g++ 11.2.1 -fPIC -O3) */ + +module GJC31(data_i, reset_n_buf, enable_buf, clk_i_buf, dly_inc_pulse_inv_buf, data_o_buf); + input clk_i_buf; + input data_i; + output [1:0] data_o_buf; + input dly_inc_pulse_inv_buf; + input enable_buf; + input reset_n_buf; + wire \$abc$238$auto_53 ; + wire \$abc$250$li0_li0 ; + wire \$abc$250$li1_li1 ; + wire \$abc$250$li2_li2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire \$f2g_in_en_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire \$f2g_trx_dly_adj_dly_adj ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire \$f2g_trx_dly_inc_dly_adj ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:22.9-22.15" *) + wire \$f2g_trx_dly_ld_dly_ld ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:24.10-24.17" *) + wire \$f2g_trx_reset_n_reset_n ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \$f2g_tx_out_data_o[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \$f2g_tx_out_data_o[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire \$ofab_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.16-26.25" *) + wire clk_buf_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.10-26.15" *) + wire clk_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:15.18-15.27" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:15.18-15.27" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.26-26.33" *) + wire clk_pll; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:12.18-12.24" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:21.10-21.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:21.22-21.40" *) + wire data_i_buf_delayed; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \data_o[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \data_o[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:17.24-17.34" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:17.24-17.34" *) + wire [1:0] data_o_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:20.16-20.24" *) + wire \data_reg[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:20.16-20.24" *) + wire \data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:27.10-27.27" *) + wire dly_inc_pulse_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:16.18-16.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:16.18-16.39" *) + wire dly_inc_pulse_inv_buf; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:22.9-22.15" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire enable; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:14.18-14.28" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:14.18-14.28" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:24.10-24.17" *) + wire reset_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:13.18-13.29" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:13.18-13.29" *) + wire reset_n_buf; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_251 ( + .C(clk_i), + .D(\$abc$250$li0_li0 ), + .E(\$abc$238$auto_53 ), + .Q(\data_o[0] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_252 ( + .C(clk_i), + .D(\$abc$250$li1_li1 ), + .E(\$abc$238$auto_53 ), + .Q(\data_o[1] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_253 ( + .C(clk_i), + .D(\$abc$250$li2_li2 ), + .E(\$abc$238$auto_53 ), + .Q(dly_ld), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$596$auto_597 ( + .A({ \data_reg[1] , reset_n }), + .Y(\$abc$250$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$596$auto_598 ( + .A({ \data_reg[0] , reset_n }), + .Y(\$abc$250$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'hb) + ) \$abc$596$auto_599 ( + .A({ reset_n, enable }), + .Y(\$abc$238$auto_53 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$596$auto_600 ( + .A(dly_inc_pulse_inv), + .Y(dly_adj) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$596$auto_601 ( + .A(reset_n), + .Y(\$abc$250$li2_li2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_in_en_enable_1 ( + .I(enable), + .O(\$f2g_in_en_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_adj_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_inc_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_1 ( + .I(dly_ld), + .O(\$f2g_trx_dly_ld_dly_ld ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_n_1 ( + .I(reset_n), + .O(\$f2g_trx_reset_n_reset_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_o[0]_1 ( + .I(\data_o[0] ), + .O(\$f2g_tx_out_data_o[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_o[1]_1 ( + .I(\data_o[1] ), + .O(\$f2g_tx_out_data_o[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_1 ( + .I(enable), + .O(\$ofab_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:31.39-31.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(reset_n_buf), + .O(reset_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:32.39-32.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(enable_buf), + .O(enable) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:33.39-33.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_buf_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:34.39-34.93" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_inc_pulse_inv_buf), + .O(dly_inc_pulse_inv) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:42.60-46.10" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000020), + .PLL_MULT(32'sh00000064), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen ( + .CLK_IN(clk_pll), + .CLK_OUT(clk_i), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:40.13-40.45" *) + CLK_BUF clock_buffer ( + .I(clk_buf_i), + .O(clk_pll) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:51.11-51.46" *) + I_BUF data_buf ( + .EN(\$f2g_in_en_enable ), + .I(data_i), + .O(data_i_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:58.11-58.76" *) + I_DDR data_i_ddr ( + .C(clk_i), + .D(data_i_buf_delayed), + .E(\$ofab_enable ), + .Q({ \data_reg[1] , \data_reg[0] }), + .R(\$f2g_trx_reset_n_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:52.13-57.52" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) data_i_delay ( + .CLK_IN(clk_i), + .DLY_ADJ(\$f2g_trx_dly_adj_dly_adj ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_adj ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld ), + .I(data_i_buf), + .O(data_i_buf_delayed) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:35.11-35.44" *) + O_BUFT obuf0_ ( + .I(\$f2g_tx_out_data_o[0] ), + .O(data_o_buf[0]), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:36.11-36.44" *) + O_BUFT obuf1_ ( + .I(\$f2g_tx_out_data_o[1] ), + .O(data_o_buf[1]), + .T(1'h1) + ); +endmodule diff --git a/design_edit/Tests/I_DELAY_to_I_SERDES/I_DELAY_to_I_SERDES.ys b/design_edit/Tests/I_DELAY_to_I_SERDES/I_DELAY_to_I_SERDES.ys new file mode 100644 index 000000000..f378d08c9 --- /dev/null +++ b/design_edit/Tests/I_DELAY_to_I_SERDES/I_DELAY_to_I_SERDES.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_DELAY_to_I_SERDES.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_DELAY_to_I_SERDES.v +#write_blif -param ./tmp/I_DELAY_to_I_SERDES.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_DELAY_to_I_SERDES.v ./tmp//wrapper_I_DELAY_to_I_SERDES.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_DELAY_to_I_SERDES.v +write_blif -param ./tmp/fabric_I_DELAY_to_I_SERDES.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_DELAY_to_I_SERDES/pin_constraints.pin b/design_edit/Tests/I_DELAY_to_I_SERDES/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/I_DELAY_to_I_SERDES/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/I_DELAY_to_I_SERDES/rtl/I_DELAY_to_I_SERDES.v b/design_edit/Tests/I_DELAY_to_I_SERDES/rtl/I_DELAY_to_I_SERDES.v new file mode 100644 index 000000000..97de56883 --- /dev/null +++ b/design_edit/Tests/I_DELAY_to_I_SERDES/rtl/I_DELAY_to_I_SERDES.v @@ -0,0 +1,783 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/I_SERDES_octrl_to_ibuf/I_SERDES_octrl_to_ibuf.ys b/design_edit/Tests/I_SERDES_octrl_to_ibuf/I_SERDES_octrl_to_ibuf.ys new file mode 100644 index 000000000..8b3210a89 --- /dev/null +++ b/design_edit/Tests/I_SERDES_octrl_to_ibuf/I_SERDES_octrl_to_ibuf.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_SERDES_octrl_to_ibuf.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_SERDES_octrl_to_ibuf.v +#write_blif -param ./tmp/I_SERDES_octrl_to_ibuf.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_SERDES_octrl_to_ibuf.v ./tmp//wrapper_I_SERDES_octrl_to_ibuf.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_SERDES_octrl_to_ibuf.v +write_blif -param ./tmp/fabric_I_SERDES_octrl_to_ibuf.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_SERDES_octrl_to_ibuf/pin_constraints.pin b/design_edit/Tests/I_SERDES_octrl_to_ibuf/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/I_SERDES_octrl_to_ibuf/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/I_SERDES_octrl_to_ibuf/rtl/I_SERDES_octrl_to_ibuf.v b/design_edit/Tests/I_SERDES_octrl_to_ibuf/rtl/I_SERDES_octrl_to_ibuf.v new file mode 100644 index 000000000..b1a1c255a --- /dev/null +++ b/design_edit/Tests/I_SERDES_octrl_to_ibuf/rtl/I_SERDES_octrl_to_ibuf.v @@ -0,0 +1,795 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock_ ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock_ ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$serdes_dpa_lock ( + .EN(1'h1), + .I(\$ifab_serdes_dpa_lock_ ), + .O(\$ifab_serdes_dpa_lock ) + ); +endmodule + diff --git a/design_edit/Tests/I_SERDES_to_I_BUF/I_SERDES_to_I_BUF.ys b/design_edit/Tests/I_SERDES_to_I_BUF/I_SERDES_to_I_BUF.ys new file mode 100644 index 000000000..43e0bfbe5 --- /dev/null +++ b/design_edit/Tests/I_SERDES_to_I_BUF/I_SERDES_to_I_BUF.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/I_SERDES_to_I_BUF.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/I_SERDES_to_I_BUF.v +#write_blif -param ./tmp/I_SERDES_to_I_BUF.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_I_SERDES_to_I_BUF.v ./tmp//wrapper_I_SERDES_to_I_BUF.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_I_SERDES_to_I_BUF.v +write_blif -param ./tmp/fabric_I_SERDES_to_I_BUF.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/I_SERDES_to_I_BUF/pin_constraints.pin b/design_edit/Tests/I_SERDES_to_I_BUF/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/I_SERDES_to_I_BUF/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/I_SERDES_to_I_BUF/rtl/I_SERDES_to_I_BUF.v b/design_edit/Tests/I_SERDES_to_I_BUF/rtl/I_SERDES_to_I_BUF.v new file mode 100644 index 000000000..6c3c807e8 --- /dev/null +++ b/design_edit/Tests/I_SERDES_to_I_BUF/rtl/I_SERDES_to_I_BUF.v @@ -0,0 +1,795 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes_ ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$data_i_serdes ( + .EN(1'h1), + .I(\data_i_serdes_ ), + .O(\data_i_serdes[9] ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes_ , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/LUT_to_IDELAY/rtl/GJC19.v b/design_edit/Tests/LUT_to_IDELAY/rtl/GJC19.v deleted file mode 100644 index 6a4b3318c..000000000 --- a/design_edit/Tests/LUT_to_IDELAY/rtl/GJC19.v +++ /dev/null @@ -1,64 +0,0 @@ -//*********************************************************** -// Functionality: Input is delayed according to controls then -// inverted and sent out through output buffer -// Author: Azfar -//*********************************************************** - - - -module GJC19 ( - input wire clk_i_buf, - input wire data_i, - input wire dly_incdec_buf, - input wire dly_ld_buf, - input wire dly_adj_buf, - output wire data_o_inv_delayed_buf, - output wire [5:0] dly_tap_val_inv_buf -); - - wire data_o; - wire [5:0] dly_tap_val; - wire dly_incdec_inv, dly_adj_inv, dly_ld_inv; - wire enable; - wire data_i_buf; - wire clk_buf_i; - wire clk_i; - wire dly_incdec; - wire dly_ld; - wire dly_adj; - wire const1; - wire data_o_inv_delayed; - wire [5:0] dly_tap_val_inv; - - I_BUF #(.WEAK_KEEPER("PULLDOWN")) buf0_ (clk_i_buf,const1,clk_i); - I_BUF #(.WEAK_KEEPER("PULLDOWN")) buf1_ (dly_incdec_buf,const1,dly_incdec); - I_BUF #(.WEAK_KEEPER("PULLDOWN")) buf2_ (dly_ld_buf,const1,dly_ld); - I_BUF #(.WEAK_KEEPER("PULLDOWN")) buf3_ (dly_adj_buf,const1,dly_adj); - O_BUF obuf00_ (data_o_inv_delayed,data_o_inv_delayed_buf); - O_BUF obuf0_ (dly_tap_val_inv[0], dly_tap_val_inv_buf[0]); - O_BUF obuf1_ (dly_tap_val_inv[1], dly_tap_val_inv_buf[1]); - O_BUF obuf2_ (dly_tap_val_inv[2], dly_tap_val_inv_buf[2]); - O_BUF obuf3_ (dly_tap_val_inv[3], dly_tap_val_inv_buf[3]); - O_BUF obuf4_ (dly_tap_val_inv[4], dly_tap_val_inv_buf[4]); - O_BUF obuf5_ (dly_tap_val_inv[5], dly_tap_val_inv_buf[5]); - - assign const1 = 1; - - CLK_BUF clock_buffer (clk_i,clk_buf_i); - - assign data_o_inv_delayed = ~data_o; - assign enable = 1; - assign dly_incdec_inv = ~dly_incdec; - assign dly_adj_inv = ~dly_adj; - assign dly_ld_inv = ~dly_ld; - assign dly_tap_val_inv = ~dly_tap_val; - - I_BUF data_buf (data_i,enable,data_i_buf); - I_DELAY data_i_delay ( .I(data_i_buf), - .DLY_LOAD(dly_ld_inv), - .DLY_ADJ(dly_adj_inv), - .DLY_INCDEC(dly_incdec_inv), - .DLY_TAP_VALUE(dly_tap_val), - .CLK_IN(clk_buf_i), - .O(data_o)); -endmodule \ No newline at end of file diff --git a/design_edit/Tests/LUT_to_IDELAY_ctrl/LUT_to_IDELAY_ctrl.ys b/design_edit/Tests/LUT_to_IDELAY_ctrl/LUT_to_IDELAY_ctrl.ys new file mode 100644 index 000000000..996025a16 --- /dev/null +++ b/design_edit/Tests/LUT_to_IDELAY_ctrl/LUT_to_IDELAY_ctrl.ys @@ -0,0 +1,17 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/LUT_to_IDELAY_ctrl.v + +# Technology mapping +hierarchy -auto-top + +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_LUT_to_IDELAY_ctrl_post_synth.v ./tmp//wrapper_LUT_to_IDELAY_ctrl_post_synth.eblif + +write_verilog -noexpr -nodec -v ./tmp/fabric_LUT_to_IDELAY_ctrl_post_synth.v +write_blif -param ./tmp/fabric_LUT_to_IDELAY_ctrl_post_synth.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/LUT_to_IDELAY_ctrl/pin_constraints.pin b/design_edit/Tests/LUT_to_IDELAY_ctrl/pin_constraints.pin new file mode 100644 index 000000000..901583ed2 --- /dev/null +++ b/design_edit/Tests/LUT_to_IDELAY_ctrl/pin_constraints.pin @@ -0,0 +1 @@ +set_pin_loc clk_i_buf HP_1_CC_18_9P diff --git a/design_edit/Tests/LUT_to_IDELAY_ctrl/rtl/LUT_to_IDELAY_ctrl.v b/design_edit/Tests/LUT_to_IDELAY_ctrl/rtl/LUT_to_IDELAY_ctrl.v new file mode 100644 index 000000000..a96ff86f0 --- /dev/null +++ b/design_edit/Tests/LUT_to_IDELAY_ctrl/rtl/LUT_to_IDELAY_ctrl.v @@ -0,0 +1,315 @@ +/* Generated by Yosys 0.38 (git sha1 6c475f1f1, gcc 11.2.1 -fPIC -Os) */ + +module GJC19(clk_i_buf, data_i, dly_incdec_buf, dly_ld_buf, dly_adj_buf, data_o_inv_delayed_buf, dly_tap_val_inv_buf); + input clk_i_buf; + input data_i; + output data_o_inv_delayed_buf; + input dly_adj_buf; + input dly_incdec_buf; + input dly_ld_buf; + output [5:0] dly_tap_val_inv_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.26-21.37" *) + wire \$f2g_trx_dly_adj_dly_adj_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.10-21.24" *) + wire \$f2g_trx_dly_inc_dly_incdec_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.39-21.49" *) + wire \$f2g_trx_dly_ld_dly_ld_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:24.10-24.19" *) + wire clk_buf_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:25.10-25.15" *) + wire clk_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:10.16-10.25" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:10.16-10.25" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:11.16-11.22" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:11.16-11.22" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:19.10-19.16" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:30.10-30.28" *) + wire data_o_inv_delayed; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:15.17-15.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:15.17-15.39" *) + wire data_o_inv_delayed_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:28.10-28.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:14.16-14.27" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:14.16-14.27" *) + wire dly_adj_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.26-21.37" *) + wire dly_adj_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:26.10-26.20" *) + wire dly_incdec; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:12.16-12.30" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:12.16-12.30" *) + wire dly_incdec_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.10-21.24" *) + wire dly_incdec_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:27.10-27.16" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:13.16-13.26" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:13.16-13.26" *) + wire dly_ld_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.39-21.49" *) + wire dly_ld_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:16.23-16.42" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:16.23-16.42" *) + wire [5:0] dly_tap_val_inv_buf; + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_481 ( + .A(data_o), + .Y(data_o_inv_delayed) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_482 ( + .A(dly_incdec), + .Y(dly_incdec_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_483 ( + .A(dly_adj), + .Y(dly_adj_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_484 ( + .A(dly_ld), + .Y(dly_ld_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_485 ( + .A(\dly_tap_val[5] ), + .Y(\dly_tap_val_inv[5] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_486 ( + .A(\dly_tap_val[4] ), + .Y(\dly_tap_val_inv[4] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_487 ( + .A(\dly_tap_val[3] ), + .Y(\dly_tap_val_inv[3] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_488 ( + .A(\dly_tap_val[2] ), + .Y(\dly_tap_val_inv[2] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_489 ( + .A(\dly_tap_val[1] ), + .Y(\dly_tap_val_inv[1] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_490 ( + .A(\dly_tap_val[0] ), + .Y(\dly_tap_val_inv[0] ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_incdec_inv_1 ( + .I(dly_incdec_inv), + .O(\$f2g_trx_dly_inc_dly_incdec_inv ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_inv_1 ( + .I(dly_ld_inv), + .O(\$f2g_trx_dly_ld_dly_ld_inv ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[0]_1 ( + .I(\$ifab_dly_tap_val[0] ), + .O(\dly_tap_val[0] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[1]_1 ( + .I(\$ifab_dly_tap_val[1] ), + .O(\dly_tap_val[1] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[2]_1 ( + .I(\$ifab_dly_tap_val[2] ), + .O(\dly_tap_val[2] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[3]_1 ( + .I(\$ifab_dly_tap_val[3] ), + .O(\dly_tap_val[3] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[4]_1 ( + .I(\$ifab_dly_tap_val[4] ), + .O(\dly_tap_val[4] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:33.39-33.69" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_i) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:34.39-34.79" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(dly_incdec_buf), + .O(dly_incdec) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:35.39-35.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(dly_ld_buf), + .O(dly_ld) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:36.39-36.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_adj_buf), + .O(dly_adj) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:47.13-47.43" *) + CLK_BUF clock_buffer ( + .I(clk_i), + .O(clk_buf_i) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:56.11-56.46" *) + I_BUF data_buf ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:57.13-63.40" *) + I_DELAY #( + .DELAY(32'h00000000) + ) data_i_delay ( + .CLK_IN(clk_buf_i), + .DLY_ADJ(dly_adj_inv ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_incdec_inv ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld_inv ), + .DLY_TAP_VALUE({ \dly_tap_val[5] , \$ifab_dly_tap_val[4] , \$ifab_dly_tap_val[3] , \$ifab_dly_tap_val[2] , \$ifab_dly_tap_val[1] , \$ifab_dly_tap_val[0] }), + .I(data_i_buf), + .O(data_o) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:37.11-37.62" *) + O_BUF obuf00_ ( + .I(data_o_inv_delayed), + .O(data_o_inv_delayed_buf) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:38.11-38.62" *) + O_BUF obuf0_ ( + .I(\dly_tap_val_inv[0] ), + .O(dly_tap_val_inv_buf[0]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:39.11-39.62" *) + O_BUF obuf1_ ( + .I(\dly_tap_val_inv[1] ), + .O(dly_tap_val_inv_buf[1]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:40.11-40.62" *) + O_BUF obuf2_ ( + .I(\dly_tap_val_inv[2] ), + .O(dly_tap_val_inv_buf[2]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:41.11-41.62" *) + O_BUF obuf3_ ( + .I(\dly_tap_val_inv[3] ), + .O(dly_tap_val_inv_buf[3]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:42.11-42.62" *) + O_BUF obuf4_ ( + .I(\dly_tap_val_inv[4] ), + .O(dly_tap_val_inv_buf[4]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:43.11-43.62" *) + O_BUF obuf5_ ( + .I(\dly_tap_val_inv[5] ), + .O(dly_tap_val_inv_buf[5]) + ); +endmodule diff --git a/design_edit/Tests/O_BUF_to_ODDR_ctrl/O_BUF_to_ODDR_ctrl.ys b/design_edit/Tests/O_BUF_to_ODDR_ctrl/O_BUF_to_ODDR_ctrl.ys new file mode 100644 index 000000000..45206e45d --- /dev/null +++ b/design_edit/Tests/O_BUF_to_ODDR_ctrl/O_BUF_to_ODDR_ctrl.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/O_BUF_to_ODDR_ctrl.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/O_BUF_to_ODDR_ctrl.v +#write_blif -param ./tmp/O_BUF_to_ODDR_ctrl.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_O_BUF_to_ODDR_ctrl.v ./tmp//wrapper_O_BUF_to_ODDR_ctrl.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_O_BUF_to_ODDR_ctrl.v +write_blif -param ./tmp/fabric_O_BUF_to_ODDR_ctrl.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/O_BUF_to_ODDR_ctrl/pin_constraints.pin b/design_edit/Tests/O_BUF_to_ODDR_ctrl/pin_constraints.pin new file mode 100644 index 000000000..98d12bbc2 --- /dev/null +++ b/design_edit/Tests/O_BUF_to_ODDR_ctrl/pin_constraints.pin @@ -0,0 +1,21 @@ +set_property mode Mode_BP_SDR_A_RX HP_1_CC_18_9P +set_pin_loc clk_i_buf HP_1_CC_18_9P + +set_property mode Mode_BP_SDR_A_RX HP_1_0_0P +set_pin_loc dly_inc_pulse_inv_buf HP_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HP_1_2_1P +set_pin_loc data_i_buf[0] HP_1_2_1P + +set_property mode Mode_BP_SDR_A_RX HP_1_8_4P +set_pin_loc data_i_buf[1] HP_1_8_4P + +set_property mode Mode_BP_SDR_A_RX HP_1_6_3P +set_pin_loc enable_buf HP_1_6_3P + +set_property mode Mode_BP_SDR_A_RX HP_1_10_5P +set_pin_loc reset_n_buf HP_1_10_5P + +set_property mode Mode_BP_DDR_A_TX HP_1_12_6P +set_pin_loc data_o HP_1_12_6P + diff --git a/design_edit/Tests/O_BUF_to_ODDR_ctrl/rtl/O_BUF_to_ODDR_ctrl.v b/design_edit/Tests/O_BUF_to_ODDR_ctrl/rtl/O_BUF_to_ODDR_ctrl.v new file mode 100644 index 000000000..7ef0246cf --- /dev/null +++ b/design_edit/Tests/O_BUF_to_ODDR_ctrl/rtl/O_BUF_to_ODDR_ctrl.v @@ -0,0 +1,293 @@ +/* Generated by Yosys 0.44 (git sha1 86a09ee26, g++ 11.2.1 -fPIC -O3) */ + +module GJC21(data_i_buf, reset_n_buf, enable_buf, clk_i_buf, dly_inc_pulse_inv_buf, data_o); + input clk_i_buf; + input [1:0] data_i_buf; + output data_o; + input dly_inc_pulse_inv_buf; + input enable_buf; + input reset_n_buf; + wire \$abc$237$auto_52 ; + wire \$abc$249$li0_li0 ; + wire \$abc$249$li1_li1 ; + wire \$abc$249$li2_li2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire \$f2g_trx_dly_adj_dly_adj ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire \$f2g_trx_dly_inc_dly_adj ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:21.9-21.15" *) + wire \$f2g_trx_dly_ld_dly_ld ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:23.10-23.17" *) + wire \$f2g_trx_reset_n_reset_n ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \$f2g_tx_out_data_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \$f2g_tx_out_data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:24.10-24.16" *) + wire \$ofab_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:25.16-25.25" *) + wire clk_buf_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:25.10-25.15" *) + wire clk_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:14.18-14.27" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:14.18-14.27" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:27.17-27.23" *) + wire \data_i[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:27.17-27.23" *) + wire \data_i[1] ; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:11.24-11.34" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:11.24-11.34" *) + wire [1:0] data_i_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:16.18-16.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:16.18-16.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:20.10-20.20" *) + wire data_o_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:20.22-20.36" *) + wire data_o_delayed; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \data_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:26.10-26.27" *) + wire dly_inc_pulse_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:15.18-15.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:15.18-15.39" *) + wire dly_inc_pulse_inv_buf; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:21.9-21.15" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:24.10-24.16" *) + wire enable; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:24.10-24.16" *) + wire enable_; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:13.18-13.28" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:13.18-13.28" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:23.10-23.17" *) + wire reset_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:12.18-12.29" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:12.18-12.29" *) + wire reset_n_buf; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_250 ( + .C(clk_i), + .D(\$abc$249$li0_li0 ), + .E(\$abc$237$auto_52 ), + .Q(\data_reg[0] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_251 ( + .C(clk_i), + .D(\$abc$249$li1_li1 ), + .E(\$abc$237$auto_52 ), + .Q(\data_reg[1] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_252 ( + .C(clk_i), + .D(\$abc$249$li2_li2 ), + .E(\$abc$237$auto_52 ), + .Q(dly_ld), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$595$auto_596 ( + .A({ \data_i[1] , reset_n }), + .Y(\$abc$249$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$595$auto_597 ( + .A({ \data_i[0] , reset_n }), + .Y(\$abc$249$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'hb) + ) \$abc$595$auto_598 ( + .A({ reset_n, enable }), + .Y(\$abc$237$auto_52 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$595$auto_599 ( + .A(dly_inc_pulse_inv), + .Y(dly_adj) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$595$auto_600 ( + .A(reset_n), + .Y(\$abc$249$li2_li2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_adj_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_inc_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_1 ( + .I(dly_ld), + .O(\$f2g_trx_dly_ld_dly_ld ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_n_1 ( + .I(reset_n), + .O(\$f2g_trx_reset_n_reset_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_reg[0]_1 ( + .I(\data_reg[0] ), + .O(\$f2g_tx_out_data_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_reg[1]_1 ( + .I(\data_reg[1] ), + .O(\$f2g_tx_out_data_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_1 ( + .I(enable), + .O(\$ofab_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:30.39-30.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(reset_n_buf), + .O(reset_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:31.39-31.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(enable_buf), + .O(enable) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:32.39-32.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_buf_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:33.39-33.93" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_inc_pulse_inv_buf), + .O(dly_inc_pulse_inv) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:34.39-34.77" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf4_ ( + .EN(1'h1), + .I(data_i_buf[0]), + .O(\data_i[0] ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:35.39-35.77" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf5_ ( + .EN(1'h1), + .I(data_i_buf[1]), + .O(\data_i[1] ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:39.13-39.43" *) + CLK_BUF clock_buffer ( + .I(clk_buf_i), + .O(clk_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:51.11-51.68" *) + O_DDR data_o_ddr ( + .C(clk_i), + .D({ \$f2g_tx_out_data_reg[1] , \$f2g_tx_out_data_reg[0] }), + .E(enable_ ), + .Q(data_o_delayed), + .R(\$f2g_trx_reset_n_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:45.13-50.44" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) data_o_delay ( + .CLK_IN(clk_i), + .DLY_ADJ(\$f2g_trx_dly_adj_dly_adj ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_adj ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld ), + .I(data_o_delayed), + .O(data_o_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:44.11-44.38" *) + O_BUFT ddr_buf ( + .I(data_o_buf), + .O(data_o), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:44.11-44.38" *) + O_BUFT en_buf ( + .I(enable), + .O(enable_), + .T(1'h1) + ); +endmodule diff --git a/design_edit/Tests/O_BUF_to_O_DDR/O_BUF_to_O_DDR.ys b/design_edit/Tests/O_BUF_to_O_DDR/O_BUF_to_O_DDR.ys new file mode 100644 index 000000000..24e2b90b2 --- /dev/null +++ b/design_edit/Tests/O_BUF_to_O_DDR/O_BUF_to_O_DDR.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/O_BUF_to_O_DDR.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/O_BUF_to_O_DDR.v +#write_blif -param ./tmp/O_BUF_to_O_DDR.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_O_BUF_to_O_DDR.v ./tmp//wrapper_O_BUF_to_O_DDR.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_O_BUF_to_O_DDR.v +write_blif -param ./tmp/fabric_O_BUF_to_O_DDR.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/O_BUF_to_O_DDR/pin_constraints.pin b/design_edit/Tests/O_BUF_to_O_DDR/pin_constraints.pin new file mode 100644 index 000000000..98d12bbc2 --- /dev/null +++ b/design_edit/Tests/O_BUF_to_O_DDR/pin_constraints.pin @@ -0,0 +1,21 @@ +set_property mode Mode_BP_SDR_A_RX HP_1_CC_18_9P +set_pin_loc clk_i_buf HP_1_CC_18_9P + +set_property mode Mode_BP_SDR_A_RX HP_1_0_0P +set_pin_loc dly_inc_pulse_inv_buf HP_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HP_1_2_1P +set_pin_loc data_i_buf[0] HP_1_2_1P + +set_property mode Mode_BP_SDR_A_RX HP_1_8_4P +set_pin_loc data_i_buf[1] HP_1_8_4P + +set_property mode Mode_BP_SDR_A_RX HP_1_6_3P +set_pin_loc enable_buf HP_1_6_3P + +set_property mode Mode_BP_SDR_A_RX HP_1_10_5P +set_pin_loc reset_n_buf HP_1_10_5P + +set_property mode Mode_BP_DDR_A_TX HP_1_12_6P +set_pin_loc data_o HP_1_12_6P + diff --git a/design_edit/Tests/O_BUF_to_O_DDR/rtl/O_BUF_to_O_DDR.v b/design_edit/Tests/O_BUF_to_O_DDR/rtl/O_BUF_to_O_DDR.v new file mode 100644 index 000000000..79fb81d54 --- /dev/null +++ b/design_edit/Tests/O_BUF_to_O_DDR/rtl/O_BUF_to_O_DDR.v @@ -0,0 +1,295 @@ +/* Generated by Yosys 0.44 (git sha1 86a09ee26, g++ 11.2.1 -fPIC -O3) */ + +module GJC21(data_i_buf, reset_n_buf, enable_buf, clk_i_buf, dly_inc_pulse_inv_buf, data_o); + input clk_i_buf; + input [1:0] data_i_buf; + output data_o; + input dly_inc_pulse_inv_buf; + input enable_buf; + input reset_n_buf; + wire \$abc$237$auto_52 ; + wire \$abc$249$li0_li0 ; + wire \$abc$249$li1_li1 ; + wire \$abc$249$li2_li2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire \$f2g_trx_dly_adj_dly_adj ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire \$f2g_trx_dly_inc_dly_adj ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:21.9-21.15" *) + wire \$f2g_trx_dly_ld_dly_ld ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:23.10-23.17" *) + wire \$f2g_trx_reset_n_reset_n ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \$f2g_tx_out_data_reg_ ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \$f2g_tx_out_data_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \$f2g_tx_out_data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:24.10-24.16" *) + wire \$ofab_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:25.16-25.25" *) + wire clk_buf_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:25.10-25.15" *) + wire clk_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:14.18-14.27" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:14.18-14.27" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:27.17-27.23" *) + wire \data_i[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:27.17-27.23" *) + wire \data_i[1] ; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:11.24-11.34" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:11.24-11.34" *) + wire [1:0] data_i_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:16.18-16.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:16.18-16.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:20.10-20.20" *) + wire data_o_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:20.22-20.36" *) + wire data_o_delayed; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \data_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:26.10-26.27" *) + wire dly_inc_pulse_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:15.18-15.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:15.18-15.39" *) + wire dly_inc_pulse_inv_buf; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:21.9-21.15" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:24.10-24.16" *) + wire enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:13.18-13.28" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:13.18-13.28" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:23.10-23.17" *) + wire reset_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:12.18-12.29" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:12.18-12.29" *) + wire reset_n_buf; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_250 ( + .C(clk_i), + .D(\$abc$249$li0_li0 ), + .E(\$abc$237$auto_52 ), + .Q(\data_reg[0] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_251 ( + .C(clk_i), + .D(\$abc$249$li1_li1 ), + .E(\$abc$237$auto_52 ), + .Q(\data_reg[1] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_252 ( + .C(clk_i), + .D(\$abc$249$li2_li2 ), + .E(\$abc$237$auto_52 ), + .Q(dly_ld), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$595$auto_596 ( + .A({ \data_i[1] , reset_n }), + .Y(\$abc$249$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$595$auto_597 ( + .A({ \data_i[0] , reset_n }), + .Y(\$abc$249$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'hb) + ) \$abc$595$auto_598 ( + .A({ reset_n, enable }), + .Y(\$abc$237$auto_52 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$595$auto_599 ( + .A(dly_inc_pulse_inv), + .Y(dly_adj) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$595$auto_600 ( + .A(reset_n), + .Y(\$abc$249$li2_li2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_adj_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_inc_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_1 ( + .I(dly_ld), + .O(\$f2g_trx_dly_ld_dly_ld ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_n_1 ( + .I(reset_n), + .O(\$f2g_trx_reset_n_reset_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_reg[0]_1 ( + .I(\data_reg[0] ), + .O(\$f2g_tx_out_data_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_reg[1]_1 ( + .I(\data_reg[1] ), + .O(\$f2g_tx_out_data_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_1 ( + .I(enable), + .O(\$ofab_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:30.39-30.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(reset_n_buf), + .O(reset_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:31.39-31.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(enable_buf), + .O(enable) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:32.39-32.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_buf_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:33.39-33.93" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_inc_pulse_inv_buf), + .O(dly_inc_pulse_inv) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:34.39-34.77" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf4_ ( + .EN(1'h1), + .I(data_i_buf[0]), + .O(\data_i[0] ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:35.39-35.77" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf5_ ( + .EN(1'h1), + .I(data_i_buf[1]), + .O(\data_i[1] ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:39.13-39.43" *) + CLK_BUF clock_buffer ( + .I(clk_buf_i), + .O(clk_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:51.11-51.68" *) + O_DDR data_o_ddr ( + .C(clk_i), + .D({ \$f2g_tx_out_data_reg_ , \$f2g_tx_out_data_reg[0] }), + .E(\$ofab_enable ), + .Q(data_o_delayed), + .R(\$f2g_trx_reset_n_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:45.13-50.44" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) data_o_delay ( + .CLK_IN(clk_i), + .DLY_ADJ(\$f2g_trx_dly_adj_dly_adj ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_adj ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld ), + .I(data_o_delayed), + .O(data_o_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:44.11-44.38" *) + O_BUFT dreg ( + .I(\$f2g_tx_out_data_reg[1] ), + .O(\$f2g_tx_out_data_reg_ ), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:44.11-44.38" *) + O_BUFT ddr_buf ( + .I(data_o_buf), + .O(data_o), + .T(1'h1) + ); +endmodule diff --git a/design_edit/Tests/O_BUF_to_O_DELAY/O_BUF_to_O_DELAY.ys b/design_edit/Tests/O_BUF_to_O_DELAY/O_BUF_to_O_DELAY.ys new file mode 100644 index 000000000..a17e6d039 --- /dev/null +++ b/design_edit/Tests/O_BUF_to_O_DELAY/O_BUF_to_O_DELAY.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/O_BUF_to_O_DELAY.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/O_BUF_to_O_DELAY.v +#write_blif -param ./tmp/O_BUF_to_O_DELAY.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_O_BUF_to_O_DELAY.v ./tmp//wrapper_O_BUF_to_O_DELAY.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_O_BUF_to_O_DELAY.v +write_blif -param ./tmp/fabric_O_BUF_to_O_DELAY.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/O_BUF_to_O_DELAY/pin_constraints.pin b/design_edit/Tests/O_BUF_to_O_DELAY/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/O_BUF_to_O_DELAY/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/O_BUF_to_O_DELAY/rtl/O_BUF_to_O_DELAY.v b/design_edit/Tests/O_BUF_to_O_DELAY/rtl/O_BUF_to_O_DELAY.v new file mode 100644 index 000000000..b22151a36 --- /dev/null +++ b/design_edit/Tests/O_BUF_to_O_DELAY/rtl/O_BUF_to_O_DELAY.v @@ -0,0 +1,792 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in_; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT dly_in ( + .I(delay_in), + .O(delay_in_), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in_), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/O_BUF_to_O_SERDES/O_BUF_to_O_SERDES.ys b/design_edit/Tests/O_BUF_to_O_SERDES/O_BUF_to_O_SERDES.ys new file mode 100644 index 000000000..edf906d11 --- /dev/null +++ b/design_edit/Tests/O_BUF_to_O_SERDES/O_BUF_to_O_SERDES.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/O_BUF_to_O_SERDES.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/O_BUF_to_O_SERDES.v +#write_blif -param ./tmp/O_BUF_to_O_SERDES.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_O_BUF_to_O_SERDES.v ./tmp//wrapper_O_BUF_to_O_SERDES.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_O_BUF_to_O_SERDES.v +write_blif -param ./tmp/fabric_O_BUF_to_O_SERDES.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/O_BUF_to_O_SERDES/pin_constraints.pin b/design_edit/Tests/O_BUF_to_O_SERDES/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/O_BUF_to_O_SERDES/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/O_BUF_to_O_SERDES/rtl/O_BUF_to_O_SERDES.v b/design_edit/Tests/O_BUF_to_O_SERDES/rtl/O_BUF_to_O_SERDES.v new file mode 100644 index 000000000..7fccc1ae8 --- /dev/null +++ b/design_edit/Tests/O_BUF_to_O_SERDES/rtl/O_BUF_to_O_SERDES.v @@ -0,0 +1,795 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg_ ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$f2g_tx_out_data_i_serdes_reg ( + .I(\$f2g_tx_out_data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg_ ), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg_ , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/O_DDR_to_O_DELAY/O_DDR_to_O_DELAY.ys b/design_edit/Tests/O_DDR_to_O_DELAY/O_DDR_to_O_DELAY.ys new file mode 100644 index 000000000..e16ff06d1 --- /dev/null +++ b/design_edit/Tests/O_DDR_to_O_DELAY/O_DDR_to_O_DELAY.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/O_DDR_to_O_DELAY.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/O_DDR_to_O_DELAY.v +#write_blif -param ./tmp/O_DDR_to_O_DELAY.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_O_DDR_to_O_DELAY.v ./tmp//wrapper_O_DDR_to_O_DELAY.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_O_DDR_to_O_DELAY.v +write_blif -param ./tmp/fabric_O_DDR_to_O_DELAY.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/O_DDR_to_O_DELAY/pin_constraints.pin b/design_edit/Tests/O_DDR_to_O_DELAY/pin_constraints.pin new file mode 100644 index 000000000..98d12bbc2 --- /dev/null +++ b/design_edit/Tests/O_DDR_to_O_DELAY/pin_constraints.pin @@ -0,0 +1,21 @@ +set_property mode Mode_BP_SDR_A_RX HP_1_CC_18_9P +set_pin_loc clk_i_buf HP_1_CC_18_9P + +set_property mode Mode_BP_SDR_A_RX HP_1_0_0P +set_pin_loc dly_inc_pulse_inv_buf HP_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HP_1_2_1P +set_pin_loc data_i_buf[0] HP_1_2_1P + +set_property mode Mode_BP_SDR_A_RX HP_1_8_4P +set_pin_loc data_i_buf[1] HP_1_8_4P + +set_property mode Mode_BP_SDR_A_RX HP_1_6_3P +set_pin_loc enable_buf HP_1_6_3P + +set_property mode Mode_BP_SDR_A_RX HP_1_10_5P +set_pin_loc reset_n_buf HP_1_10_5P + +set_property mode Mode_BP_DDR_A_TX HP_1_12_6P +set_pin_loc data_o HP_1_12_6P + diff --git a/design_edit/Tests/O_DDR_to_O_DELAY/rtl/O_DDR_to_O_DELAY.v b/design_edit/Tests/O_DDR_to_O_DELAY/rtl/O_DDR_to_O_DELAY.v new file mode 100644 index 000000000..59fc6f3c4 --- /dev/null +++ b/design_edit/Tests/O_DDR_to_O_DELAY/rtl/O_DDR_to_O_DELAY.v @@ -0,0 +1,284 @@ +/* Generated by Yosys 0.44 (git sha1 86a09ee26, g++ 11.2.1 -fPIC -O3) */ + +module GJC21(data_i_buf, reset_n_buf, enable_buf, clk_i_buf, dly_inc_pulse_inv_buf, data_o); + input clk_i_buf; + input [1:0] data_i_buf; + output data_o; + input dly_inc_pulse_inv_buf; + input enable_buf; + input reset_n_buf; + wire \$abc$237$auto_52 ; + wire \$abc$249$li0_li0 ; + wire \$abc$249$li1_li1 ; + wire \$abc$249$li2_li2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire \$f2g_trx_dly_adj_dly_adj ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire \$f2g_trx_dly_inc_dly_adj ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:21.9-21.15" *) + wire \$f2g_trx_dly_ld_dly_ld ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:23.10-23.17" *) + wire \$f2g_trx_reset_n_reset_n ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \$f2g_tx_out_data_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \$f2g_tx_out_data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:24.10-24.16" *) + wire \$ofab_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:25.16-25.25" *) + wire clk_buf_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:25.10-25.15" *) + wire clk_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:14.18-14.27" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:14.18-14.27" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:27.17-27.23" *) + wire \data_i[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:27.17-27.23" *) + wire \data_i[1] ; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:11.24-11.34" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:11.24-11.34" *) + wire [1:0] data_i_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:16.18-16.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:16.18-16.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:20.10-20.20" *) + wire data_o_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:20.22-20.36" *) + wire data_o_delayed; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \data_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:26.10-26.27" *) + wire dly_inc_pulse_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:15.18-15.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:15.18-15.39" *) + wire dly_inc_pulse_inv_buf; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:21.9-21.15" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:24.10-24.16" *) + wire enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:13.18-13.28" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:13.18-13.28" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:23.10-23.17" *) + wire reset_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:12.18-12.29" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:12.18-12.29" *) + wire reset_n_buf; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_250 ( + .C(clk_i), + .D(\$abc$249$li0_li0 ), + .E(\$abc$237$auto_52 ), + .Q(\data_reg[0] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_251 ( + .C(clk_i), + .D(\$abc$249$li1_li1 ), + .E(\$abc$237$auto_52 ), + .Q(\data_reg[1] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_252 ( + .C(clk_i), + .D(\$abc$249$li2_li2 ), + .E(\$abc$237$auto_52 ), + .Q(dly_ld), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$595$auto_596 ( + .A({ \data_i[1] , reset_n }), + .Y(\$abc$249$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$595$auto_597 ( + .A({ \data_i[0] , reset_n }), + .Y(\$abc$249$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'hb) + ) \$abc$595$auto_598 ( + .A({ reset_n, enable }), + .Y(\$abc$237$auto_52 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$595$auto_599 ( + .A(dly_inc_pulse_inv), + .Y(dly_adj) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$595$auto_600 ( + .A(reset_n), + .Y(\$abc$249$li2_li2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_adj_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_inc_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_1 ( + .I(dly_ld), + .O(\$f2g_trx_dly_ld_dly_ld ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_n_1 ( + .I(reset_n), + .O(\$f2g_trx_reset_n_reset_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_reg[0]_1 ( + .I(\data_reg[0] ), + .O(\$f2g_tx_out_data_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_reg[1]_1 ( + .I(\data_reg[1] ), + .O(\$f2g_tx_out_data_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_1 ( + .I(enable), + .O(\$ofab_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:30.39-30.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(reset_n_buf), + .O(reset_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:31.39-31.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(enable_buf), + .O(enable) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:32.39-32.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_buf_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:33.39-33.93" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_inc_pulse_inv_buf), + .O(dly_inc_pulse_inv) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:34.39-34.77" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf4_ ( + .EN(1'h1), + .I(data_i_buf[0]), + .O(\data_i[0] ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:35.39-35.77" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf5_ ( + .EN(1'h1), + .I(data_i_buf[1]), + .O(\data_i[1] ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:39.13-39.43" *) + CLK_BUF clock_buffer ( + .I(clk_buf_i), + .O(clk_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:51.11-51.68" *) + O_DDR data_o_ddr ( + .C(clk_i), + .D({ \$f2g_tx_out_data_reg[1] , \$f2g_tx_out_data_reg[0] }), + .E(\$ofab_enable ), + .Q(data_o_delayed), + .R(\$f2g_trx_reset_n_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:45.13-50.44" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) data_o_delay ( + .CLK_IN(clk_i), + .DLY_ADJ(\$f2g_trx_dly_adj_dly_adj ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_adj ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld ), + .I(data_o_delayed), + .O(data_o_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:44.11-44.38" *) + O_BUFT ddr_buf ( + .I(data_o_buf), + .O(data_o), + .T(1'h1) + ); +endmodule diff --git a/design_edit/Tests/O_DDR_to_output/O_DDR_to_output.ys b/design_edit/Tests/O_DDR_to_output/O_DDR_to_output.ys new file mode 100644 index 000000000..0fd98703e --- /dev/null +++ b/design_edit/Tests/O_DDR_to_output/O_DDR_to_output.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/O_DDR_to_output.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/O_DDR_to_output.v +#write_blif -param ./tmp/O_DDR_to_output.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_O_DDR_to_output.v ./tmp//wrapper_O_DDR_to_output.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_O_DDR_to_output.v +write_blif -param ./tmp/fabric_O_DDR_to_output.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/O_DDR_to_output/pin_constraints.pin b/design_edit/Tests/O_DDR_to_output/pin_constraints.pin new file mode 100644 index 000000000..98d12bbc2 --- /dev/null +++ b/design_edit/Tests/O_DDR_to_output/pin_constraints.pin @@ -0,0 +1,21 @@ +set_property mode Mode_BP_SDR_A_RX HP_1_CC_18_9P +set_pin_loc clk_i_buf HP_1_CC_18_9P + +set_property mode Mode_BP_SDR_A_RX HP_1_0_0P +set_pin_loc dly_inc_pulse_inv_buf HP_1_0_0P + +set_property mode Mode_BP_SDR_A_RX HP_1_2_1P +set_pin_loc data_i_buf[0] HP_1_2_1P + +set_property mode Mode_BP_SDR_A_RX HP_1_8_4P +set_pin_loc data_i_buf[1] HP_1_8_4P + +set_property mode Mode_BP_SDR_A_RX HP_1_6_3P +set_pin_loc enable_buf HP_1_6_3P + +set_property mode Mode_BP_SDR_A_RX HP_1_10_5P +set_pin_loc reset_n_buf HP_1_10_5P + +set_property mode Mode_BP_DDR_A_TX HP_1_12_6P +set_pin_loc data_o HP_1_12_6P + diff --git a/design_edit/Tests/O_DDR_to_output/rtl/O_DDR_to_output.v b/design_edit/Tests/O_DDR_to_output/rtl/O_DDR_to_output.v new file mode 100644 index 000000000..674e595f5 --- /dev/null +++ b/design_edit/Tests/O_DDR_to_output/rtl/O_DDR_to_output.v @@ -0,0 +1,277 @@ +/* Generated by Yosys 0.44 (git sha1 86a09ee26, g++ 11.2.1 -fPIC -O3) */ + +module GJC21(data_i_buf, reset_n_buf, enable_buf, clk_i_buf, dly_inc_pulse_inv_buf, data_o); + input clk_i_buf; + input [1:0] data_i_buf; + output data_o; + input dly_inc_pulse_inv_buf; + input enable_buf; + input reset_n_buf; + wire \$abc$237$auto_52 ; + wire \$abc$249$li0_li0 ; + wire \$abc$249$li1_li1 ; + wire \$abc$249$li2_li2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire \$f2g_trx_dly_adj_dly_adj ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire \$f2g_trx_dly_inc_dly_adj ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:21.9-21.15" *) + wire \$f2g_trx_dly_ld_dly_ld ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:23.10-23.17" *) + wire \$f2g_trx_reset_n_reset_n ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \$f2g_tx_out_data_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \$f2g_tx_out_data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:24.10-24.16" *) + wire \$ofab_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:25.16-25.25" *) + wire clk_buf_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:25.10-25.15" *) + wire clk_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:14.18-14.27" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:14.18-14.27" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:27.17-27.23" *) + wire \data_i[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:27.17-27.23" *) + wire \data_i[1] ; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:11.24-11.34" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:11.24-11.34" *) + wire [1:0] data_i_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:16.18-16.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:16.18-16.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:20.10-20.20" *) + wire data_o_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:20.22-20.36" *) + wire data_o_delayed; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \data_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:19.15-19.23" *) + wire \data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:22.10-22.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:26.10-26.27" *) + wire dly_inc_pulse_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:15.18-15.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:15.18-15.39" *) + wire dly_inc_pulse_inv_buf; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:21.9-21.15" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:24.10-24.16" *) + wire enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:13.18-13.28" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:13.18-13.28" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:23.10-23.17" *) + wire reset_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:12.18-12.29" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:12.18-12.29" *) + wire reset_n_buf; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_250 ( + .C(clk_i), + .D(\$abc$249$li0_li0 ), + .E(\$abc$237$auto_52 ), + .Q(\data_reg[0] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_251 ( + .C(clk_i), + .D(\$abc$249$li1_li1 ), + .E(\$abc$237$auto_52 ), + .Q(\data_reg[1] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$249$auto_252 ( + .C(clk_i), + .D(\$abc$249$li2_li2 ), + .E(\$abc$237$auto_52 ), + .Q(dly_ld), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$595$auto_596 ( + .A({ \data_i[1] , reset_n }), + .Y(\$abc$249$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$595$auto_597 ( + .A({ \data_i[0] , reset_n }), + .Y(\$abc$249$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'hb) + ) \$abc$595$auto_598 ( + .A({ reset_n, enable }), + .Y(\$abc$237$auto_52 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$595$auto_599 ( + .A(dly_inc_pulse_inv), + .Y(dly_adj) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$595$auto_600 ( + .A(reset_n), + .Y(\$abc$249$li2_li2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_adj_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_inc_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_1 ( + .I(dly_ld), + .O(\$f2g_trx_dly_ld_dly_ld ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_n_1 ( + .I(reset_n), + .O(\$f2g_trx_reset_n_reset_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_reg[0]_1 ( + .I(\data_reg[0] ), + .O(\$f2g_tx_out_data_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_reg[1]_1 ( + .I(\data_reg[1] ), + .O(\$f2g_tx_out_data_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_1 ( + .I(enable), + .O(\$ofab_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:30.39-30.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(reset_n_buf), + .O(reset_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:31.39-31.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(enable_buf), + .O(enable) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:32.39-32.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_buf_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:33.39-33.93" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_inc_pulse_inv_buf), + .O(dly_inc_pulse_inv) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:34.39-34.77" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf4_ ( + .EN(1'h1), + .I(data_i_buf[0]), + .O(\data_i[0] ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:35.39-35.77" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf5_ ( + .EN(1'h1), + .I(data_i_buf[1]), + .O(\data_i[1] ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:39.13-39.43" *) + CLK_BUF clock_buffer ( + .I(clk_buf_i), + .O(clk_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:51.11-51.68" *) + O_DDR data_o_ddr ( + .C(clk_i), + .D({ \$f2g_tx_out_data_reg[1] , \$f2g_tx_out_data_reg[0] }), + .E(\$ofab_enable ), + .Q(data_o), + .R(\$f2g_trx_reset_n_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC21/results_dir/.././rtl/GJC21.v:45.13-50.44" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) data_o_delay ( + .CLK_IN(clk_i), + .DLY_ADJ(\$f2g_trx_dly_adj_dly_adj ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_adj ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld ), + .I(data_o_delayed), + .O(data_o_buf) + ); +endmodule diff --git a/design_edit/Tests/O_DELAY_to_fabric/O_DELAY_to_fabric.ys b/design_edit/Tests/O_DELAY_to_fabric/O_DELAY_to_fabric.ys new file mode 100644 index 000000000..0841dd2f9 --- /dev/null +++ b/design_edit/Tests/O_DELAY_to_fabric/O_DELAY_to_fabric.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/O_DELAY_to_fabric.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/O_DELAY_to_fabric.v +#write_blif -param ./tmp/O_DELAY_to_fabric.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_O_DELAY_to_fabric.v ./tmp//wrapper_O_DELAY_to_fabric.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_O_DELAY_to_fabric.v +write_blif -param ./tmp/fabric_O_DELAY_to_fabric.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/O_DELAY_to_fabric/pin_constraints.pin b/design_edit/Tests/O_DELAY_to_fabric/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/O_DELAY_to_fabric/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/O_DELAY_to_fabric/rtl/O_DELAY_to_fabric.v b/design_edit/Tests/O_DELAY_to_fabric/rtl/O_DELAY_to_fabric.v new file mode 100644 index 000000000..ce01f0878 --- /dev/null +++ b/design_edit/Tests/O_DELAY_to_fabric/rtl/O_DELAY_to_fabric.v @@ -0,0 +1,793 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out_; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out_) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_482 ( + .A(delay_out_ ), + .Y(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/O_SERDES_octrl_O_BUF/O_SERDES_octrl_O_BUF.ys b/design_edit/Tests/O_SERDES_octrl_O_BUF/O_SERDES_octrl_O_BUF.ys new file mode 100644 index 000000000..4184edde3 --- /dev/null +++ b/design_edit/Tests/O_SERDES_octrl_O_BUF/O_SERDES_octrl_O_BUF.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/O_SERDES_octrl_O_BUF.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/O_SERDES_octrl_O_BUF.v +#write_blif -param ./tmp/O_SERDES_octrl_O_BUF.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_O_SERDES_octrl_O_BUF.v ./tmp//wrapper_O_SERDES_octrl_O_BUF.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_O_SERDES_octrl_O_BUF.v +write_blif -param ./tmp/fabric_O_SERDES_octrl_O_BUF.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/O_SERDES_octrl_O_BUF/pin_constraints.pin b/design_edit/Tests/O_SERDES_octrl_O_BUF/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/O_SERDES_octrl_O_BUF/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/O_SERDES_octrl_O_BUF/rtl/O_SERDES_octrl_O_BUF.v b/design_edit/Tests/O_SERDES_octrl_O_BUF/rtl/O_SERDES_octrl_O_BUF.v new file mode 100644 index 000000000..277fc1017 --- /dev/null +++ b/design_edit/Tests/O_SERDES_octrl_O_BUF/rtl/O_SERDES_octrl_O_BUF.v @@ -0,0 +1,778 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$f2g_tx_oe_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/O_SERDES_to_output/O_SERDES_to_output.ys b/design_edit/Tests/O_SERDES_to_output/O_SERDES_to_output.ys new file mode 100644 index 000000000..27aeef153 --- /dev/null +++ b/design_edit/Tests/O_SERDES_to_output/O_SERDES_to_output.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/O_SERDES_to_output.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/O_SERDES_to_output.v +#write_blif -param ./tmp/O_SERDES_to_output.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_O_SERDES_to_output.v ./tmp//wrapper_O_SERDES_to_output.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_O_SERDES_to_output.v +write_blif -param ./tmp/fabric_O_SERDES_to_output.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/O_SERDES_to_output/pin_constraints.pin b/design_edit/Tests/O_SERDES_to_output/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/O_SERDES_to_output/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/O_SERDES_to_output/rtl/O_SERDES_to_output.v b/design_edit/Tests/O_SERDES_to_output/rtl/O_SERDES_to_output.v new file mode 100644 index 000000000..a0e2d7569 --- /dev/null +++ b/design_edit/Tests/O_SERDES_to_output/rtl/O_SERDES_to_output.v @@ -0,0 +1,766 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in_; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(data_o), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/and2_2clks/Src/and2x2.v b/design_edit/Tests/and2_2clks/Src/and2x2.v deleted file mode 100644 index 08ae3fe71..000000000 --- a/design_edit/Tests/and2_2clks/Src/and2x2.v +++ /dev/null @@ -1,46 +0,0 @@ -`timescale 1ns / 1ps -//////////////////////////////////////////////////////// -// Rapid Silicon Raptor Example Design // -// and2_verilog // -// and2.v - Top-level file of simple 2-input AND gate // -//////////////////////////////////////////////////////// - -module and2 ( - input a, - input b, - input clk, - input reset, - output reg c = 1'b0 -); - - reg a_reg, b_reg = 1'b0; - - always@(posedge clk) - if (reset) begin - a_reg <= 1'b0; - b_reg <= 1'b0; - c <= 1'b0; - end else begin - a_reg <= a; - b_reg <= b; - c <= a_reg & b_reg; - end - -endmodule - - -module and2x2 ( - input a, - input b, - input clk1, - input clk2, - input reset, - output wire c1, - output wire c2 -); - - and2 u1 (a,b, clk1, reset, c1); - and2 u2 (a,b, clk2, reset, c2); - - -endmodule diff --git a/design_edit/Tests/and2_2clks/Src/testbench_and2.v b/design_edit/Tests/and2_2clks/Src/testbench_and2.v deleted file mode 100644 index d5eccc2ee..000000000 --- a/design_edit/Tests/and2_2clks/Src/testbench_and2.v +++ /dev/null @@ -1,96 +0,0 @@ -`timescale 1ns / 1ps -///////////////////////////////////////////// -// Rapid Silicon Raptor Example Design // -// and2_verilog // -// testbench_and2.v - Testbench for design // -///////////////////////////////////////////// - -module testbench_and2; - - // Simulation parameters - parameter period = 10; - - // DUT inputs - reg a = 1'b0; - reg b = 1'b0; - reg clk1 = 1'b0; - reg clk2 = 1'b1; - reg reset = 1'b1; - - // DUT output - wire c1,c2; - - // Check signals - reg reset_delay = 1'b0; - reg [1:0] a_delay = 2'b00, b_delay = 2'b00; - wire a_delay_by_2 = a_delay[0]; - wire b_delay_by_2 = b_delay[0]; - integer error_cnt = 0; - - and2x2 DUT ( - .a(a), - .b(b), - .clk1(clk1), - .clk2(clk2), - .reset(reset), - .c1(c1), - .c2(c2) - ); - - // Clock - always - #period clk1 = ~clk1; - - always - #period clk2 = ~clk2; - - // Stimulus - initial begin - // Assert reset for 100 ns - #100; - @(posedge clk1); - #1 reset = 1'b0; - repeat (2) begin - @(posedge clk1); - #1 a = ~a; - @(posedge clk1); - #1 b = ~b; - end - repeat (2) - @(posedge clk1); - $display ("\n\nSimulation completed at simulation time %t with %d error(s).\n", $realtime, error_cnt); - $finish; - end - - // Self-checking - initial begin - $display(""); - // Wait 100 ns - #100; - forever begin - @(posedge clk1); - #1 reset_delay = reset; - a_delay = {a, a_delay[1]}; - b_delay = {b, b_delay[1]}; - #(period-2); - if (reset_delay && (c1 != 1'b0)) begin - $display("\nError @ %t: Design in reset but output is not zero.", $realtime); - error_cnt = error_cnt + 1; - end else if (!reset_delay && (c1 != (a_delay[0] && b_delay[0]))) begin - $display("\nError @ %t: c=%b where a=%b and b=%b",$realtime, c1, a_delay[0], b_delay[0]); - error_cnt = error_cnt + 1; - end else - $write("."); - end - end - - initial - $timeformat(-9,0," ns", 5); - - initial begin - $dumpfile("and2.vcd"); - $dumpvars(0,testbench_and2); - end - -endmodule - diff --git a/design_edit/Tests/and2_2clks/and2_2clks.ys b/design_edit/Tests/and2_2clks/and2_2clks.ys deleted file mode 100644 index d4815e23a..000000000 --- a/design_edit/Tests/and2_2clks/and2_2clks.ys +++ /dev/null @@ -1,21 +0,0 @@ -# Yosys synthesis script for O_SERDES_primitive_inst -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./Src/and2x2.v - - -# Technology mapping -hierarchy -top and2x2 -write_rtlil design.rtlil - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal delay -effort high -carry auto -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_verilog -noexpr -nodec -norename -v ./tmp/and2x2_post_synth.v -write_blif -param ./tmp/and2x2_post_synth.eblif - -plugin -i design-edit -design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp/wrapper_and2x2_post_synth.v ./tmp/wrapper_and2x2_post_synth.eblif -write_verilog -noexpr -nodec -norename -v ./tmp/fab_and2x2.v -write_blif -param ./tmp/fab_and2x2.eblif \ No newline at end of file diff --git a/design_edit/Tests/and2_2clks/constraints.sdc b/design_edit/Tests/and2_2clks/constraints.sdc deleted file mode 100644 index b8f54a4b1..000000000 --- a/design_edit/Tests/and2_2clks/constraints.sdc +++ /dev/null @@ -1,8 +0,0 @@ -# SDC file example - -# Setting a clock frequency of 200 MHz (5nS period) -create_clock -period 5 [get_ports {clk1}] -name clk1 -create_clock -period 5 [get_ports {clk2}] -name clk2 -set_clock_groups -group [get_clocks {clk1}] -group [get_clocks {clk2}] -physically_exclusive -create_clock -name clk3 -period 6 -set_false_path -from [get_clocks {clk1}] -to [get_clocks {clk2}] diff --git a/design_edit/Tests/and2_2clks/gold/and2x2_post_synth.eblif b/design_edit/Tests/and2_2clks/gold/and2x2_post_synth.eblif deleted file mode 100644 index dae20aaef..000000000 --- a/design_edit/Tests/and2_2clks/gold/and2x2_post_synth.eblif +++ /dev/null @@ -1,46 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model and2x2 -.inputs a b clk1 clk2 reset -.outputs c1 c2 -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$568 D=$abc$212$flatten\u1.$0\a_reg[0:0] E=$true Q=u1.a_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$568 D=$abc$212$flatten\u1.$0\b_reg[0:0] E=$true Q=u1.b_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$568 D=$abc$236$li2_li2 E=$true Q=$iopadmap$c1 R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$571 D=$abc$212$flatten\u1.$0\a_reg[0:0] E=$true Q=u2.a_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$571 D=$abc$212$flatten\u1.$0\b_reg[0:0] E=$true Q=u2.b_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$571 D=$abc$249$li2_li2 E=$true Q=$iopadmap$c2 R=$true -.subckt LUT3 A[0]=$iopadmap$reset A[1]=u2.b_reg A[2]=u2.a_reg Y=$abc$249$li2_li2 -.param INIT_VALUE 01000000 -.subckt LUT2 A[0]=$iopadmap$reset A[1]=$iopadmap$a Y=$abc$212$flatten\u1.$0\a_reg[0:0] -.param INIT_VALUE 0100 -.subckt LUT3 A[0]=$iopadmap$reset A[1]=u1.b_reg A[2]=u1.a_reg Y=$abc$236$li2_li2 -.param INIT_VALUE 01000000 -.subckt LUT2 A[0]=$iopadmap$reset A[1]=$iopadmap$b Y=$abc$212$flatten\u1.$0\b_reg[0:0] -.param INIT_VALUE 0100 -.subckt CLK_BUF I=$auto$clkbufmap.cc:263:execute$567 O=$auto$clkbufmap.cc:295:execute$568 -.subckt CLK_BUF I=$auto$clkbufmap.cc:263:execute$570 O=$auto$clkbufmap.cc:295:execute$571 -.subckt I_BUF EN=$true I=a O=$iopadmap$a -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=b O=$iopadmap$b -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$iopadmap$c1 O=c1 -.subckt O_BUF I=$iopadmap$c2 O=c2 -.subckt I_BUF EN=$true I=clk1 O=$iopadmap$clk1 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=clk2 O=$iopadmap$clk2 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=reset O=$iopadmap$reset -.param WEAK_KEEPER "NONE" -.names $iopadmap$c1 u1.c -1 1 -.names $iopadmap$c2 u2.c -1 1 -.names $iopadmap$clk1 $auto$clkbufmap.cc:263:execute$567 -1 1 -.names $iopadmap$clk2 $auto$clkbufmap.cc:263:execute$570 -1 1 -.end diff --git a/design_edit/Tests/and2_2clks/gold/and2x2_post_synth.v b/design_edit/Tests/and2_2clks/gold/and2x2_post_synth.v deleted file mode 100644 index a1cb4b705..000000000 --- a/design_edit/Tests/and2_2clks/gold/and2x2_post_synth.v +++ /dev/null @@ -1,315 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module and2x2(a, b, clk1, clk2, reset, c1, c2); - input clk2; - input a; - input b; - output c1; - output c2; - input clk1; - input reset; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap584$abc$561$auto$blifparse.cc:515:parse_blif$564.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap584$abc$561$auto$blifparse.cc:515:parse_blif$564.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap583$abc$561$auto$blifparse.cc:515:parse_blif$562.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap583$abc$561$auto$blifparse.cc:515:parse_blif$562.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap582$abc$561$auto$blifparse.cc:515:parse_blif$563.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap582$abc$561$auto$blifparse.cc:515:parse_blif$563.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap581$abc$561$auto$blifparse.cc:515:parse_blif$565.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap581$abc$561$auto$blifparse.cc:515:parse_blif$565.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap580$iopadmap$and2x2.b.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap580$iopadmap$and2x2.b.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap580$iopadmap$and2x2.b.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap579$iopadmap$and2x2.reset.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap579$iopadmap$and2x2.reset.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap579$iopadmap$and2x2.reset.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap578$iopadmap$and2x2.clk1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap578$iopadmap$and2x2.clk1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap578$iopadmap$and2x2.clk1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap577$iopadmap$and2x2.c2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap577$iopadmap$and2x2.c2.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap577$iopadmap$and2x2.c2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap576$iopadmap$and2x2.c1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap576$iopadmap$and2x2.c1.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap576$iopadmap$and2x2.c1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap575$iopadmap$and2x2.clk2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap575$iopadmap$and2x2.clk2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap575$iopadmap$and2x2.clk2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap574$iopadmap$and2x2.a.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap574$iopadmap$and2x2.a.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap574$iopadmap$and2x2.a.O ; - wire \$iopadmap$clk2 ; - (* src = "./Src/and2x2.v:36.9-36.13" *) - (* src = "./Src/and2x2.v:36.9-36.13" *) - wire clk2; - (* src = "./Src/and2x2.v:33.9-33.10" *) - (* src = "./Src/and2x2.v:33.9-33.10" *) - wire a; - (* src = "./Src/and2x2.v:34.9-34.10" *) - (* src = "./Src/and2x2.v:34.9-34.10" *) - wire b; - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:38.15-38.17" *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:38.15-38.17" *) - wire c1; - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:39.15-39.17" *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:39.15-39.17" *) - wire c2; - (* src = "./Src/and2x2.v:35.9-35.13" *) - (* src = "./Src/and2x2.v:35.9-35.13" *) - wire clk1; - (* src = "./Src/and2x2.v:37.9-37.14" *) - (* src = "./Src/and2x2.v:37.9-37.14" *) - wire reset; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap573$auto$clkbufmap.cc:262:execute$566.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap572$auto$clkbufmap.cc:262:execute$569.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap572$auto$clkbufmap.cc:262:execute$569.O ; - wire \$auto$clkbufmap.cc:295:execute$571 ; - wire \$iopadmap$a ; - wire \$auto$clkbufmap.cc:295:execute$568 ; - wire \$auto$clkbufmap.cc:263:execute$567 ; - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:18.3-27.8" *) - wire \$abc$212$flatten\u1.$0\a_reg[0:0] ; - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:18.3-27.8" *) - wire \$abc$212$flatten\u1.$0\b_reg[0:0] ; - wire \$abc$236$li2_li2 ; - wire \$abc$249$li2_li2 ; - wire \$iopadmap$b ; - (* init = 1'h0 *) - wire \$iopadmap$c1 ; - (* init = 1'h0 *) - wire \$iopadmap$c2 ; - wire \$iopadmap$clk1 ; - wire \$auto$clkbufmap.cc:263:execute$570 ; - wire \$iopadmap$reset ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap573$auto$clkbufmap.cc:262:execute$566.I ; - (* hdlname = "u1 a_reg" *) - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:16.7-16.12" *) - wire \u1.a_reg ; - (* hdlname = "u1 b_reg" *) - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:16.14-16.19" *) - wire \u1.b_reg ; - (* hdlname = "u1 c" *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:13.14-13.15" *) - wire \u1.c ; - (* hdlname = "u2 a_reg" *) - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:43.9-43.34|./Src/and2x2.v:16.7-16.12" *) - wire \u2.a_reg ; - (* hdlname = "u2 b_reg" *) - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:43.9-43.34|./Src/and2x2.v:16.14-16.19" *) - wire \u2.b_reg ; - (* hdlname = "u2 c" *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:43.9-43.34|./Src/and2x2.v:13.14-13.15" *) - wire \u2.c ; - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$561$auto$blifparse.cc:515:parse_blif$564 ( - .Y(\$abc$236$li2_li2 ), - .A({ \u1.a_reg , \u1.b_reg , \$iopadmap$reset }) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$and2x2.c2 ( - .O(c2), - .I(\$iopadmap$c2 ) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$and2x2.c1 ( - .O(c1), - .I(\$iopadmap$c1 ) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2x2.clk2 ( - .O(\$iopadmap$clk2 ), - .EN(1'h1), - .I(clk2) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2x2.reset ( - .O(\$iopadmap$reset ), - .EN(1'h1), - .I(reset) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2x2.clk1 ( - .O(\$iopadmap$clk1 ), - .EN(1'h1), - .I(clk1) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2x2.a ( - .O(\$iopadmap$a ), - .EN(1'h1), - .I(a) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$clkbufmap.cc:262:execute$566 ( - .O(\$auto$clkbufmap.cc:295:execute$568 ), - .I(\$auto$clkbufmap.cc:263:execute$567 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$clkbufmap.cc:262:execute$569 ( - .O(\$auto$clkbufmap.cc:295:execute$571 ), - .I(\$auto$clkbufmap.cc:263:execute$570 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$236$auto$blifparse.cc:362:parse_blif$237 ( - .C(\$auto$clkbufmap.cc:295:execute$568 ), - .D(\$abc$212$flatten\u1.$0\a_reg[0:0] ), - .E(1'h1), - .Q(\u1.a_reg ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$236$auto$blifparse.cc:362:parse_blif$238 ( - .C(\$auto$clkbufmap.cc:295:execute$568 ), - .D(\$abc$212$flatten\u1.$0\b_reg[0:0] ), - .E(1'h1), - .Q(\u1.b_reg ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$236$auto$blifparse.cc:362:parse_blif$239 ( - .C(\$auto$clkbufmap.cc:295:execute$568 ), - .D(\$abc$236$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c1 ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$249$auto$blifparse.cc:362:parse_blif$250 ( - .C(\$auto$clkbufmap.cc:295:execute$571 ), - .D(\$abc$212$flatten\u1.$0\a_reg[0:0] ), - .E(1'h1), - .Q(\u2.a_reg ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$249$auto$blifparse.cc:362:parse_blif$251 ( - .C(\$auto$clkbufmap.cc:295:execute$571 ), - .D(\$abc$212$flatten\u1.$0\b_reg[0:0] ), - .E(1'h1), - .Q(\u2.b_reg ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$249$auto$blifparse.cc:362:parse_blif$252 ( - .C(\$auto$clkbufmap.cc:295:execute$571 ), - .D(\$abc$249$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c2 ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$561$auto$blifparse.cc:515:parse_blif$563 ( - .Y(\$abc$212$flatten\u1.$0\a_reg[0:0] ), - .A({ \$iopadmap$a , \$iopadmap$reset }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$561$auto$blifparse.cc:515:parse_blif$565 ( - .Y(\$abc$212$flatten\u1.$0\b_reg[0:0] ), - .A({ \$iopadmap$b , \$iopadmap$reset }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$561$auto$blifparse.cc:515:parse_blif$562 ( - .Y(\$abc$249$li2_li2 ), - .A({ \u2.a_reg , \u2.b_reg , \$iopadmap$reset }) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2x2.b ( - .O(\$iopadmap$b ), - .EN(1'h1), - .I(b) - ); - assign \u1.c = \$iopadmap$c1 ; - assign \u2.c = \$iopadmap$c2 ; - assign \$auto$clkbufmap.cc:263:execute$567 = \$iopadmap$clk1 ; - assign \$auto$clkbufmap.cc:263:execute$570 = \$iopadmap$clk2 ; -endmodule diff --git a/design_edit/Tests/and2_2clks/gold/fab_and2x2.eblif b/design_edit/Tests/and2_2clks/gold/fab_and2x2.eblif deleted file mode 100644 index 45152c168..000000000 --- a/design_edit/Tests/and2_2clks/gold/fab_and2x2.eblif +++ /dev/null @@ -1,28 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_and2x2 -.inputs $iopadmap$b $auto$clkbufmap.cc:295:execute$568 $auto$clkbufmap.cc:295:execute$571 $iopadmap$reset $iopadmap$a -.outputs $iopadmap$c2 $iopadmap$c1 -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$568 D=$abc$212$flatten\u1.$0\a_reg[0:0] E=$true Q=u1.a_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$568 D=$abc$212$flatten\u1.$0\b_reg[0:0] E=$true Q=u1.b_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$568 D=$abc$236$li2_li2 E=$true Q=$iopadmap$c1 R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$571 D=$abc$212$flatten\u1.$0\a_reg[0:0] E=$true Q=u2.a_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$571 D=$abc$212$flatten\u1.$0\b_reg[0:0] E=$true Q=u2.b_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$571 D=$abc$249$li2_li2 E=$true Q=$iopadmap$c2 R=$true -.subckt LUT3 A[0]=$iopadmap$reset A[1]=u2.b_reg A[2]=u2.a_reg Y=$abc$249$li2_li2 -.param INIT_VALUE 01000000 -.subckt LUT2 A[0]=$iopadmap$reset A[1]=$iopadmap$a Y=$abc$212$flatten\u1.$0\a_reg[0:0] -.param INIT_VALUE 0100 -.subckt LUT3 A[0]=$iopadmap$reset A[1]=u1.b_reg A[2]=u1.a_reg Y=$abc$236$li2_li2 -.param INIT_VALUE 01000000 -.subckt LUT2 A[0]=$iopadmap$reset A[1]=$iopadmap$b Y=$abc$212$flatten\u1.$0\b_reg[0:0] -.param INIT_VALUE 0100 -.names $iopadmap$c1 u1.c -1 1 -.names $iopadmap$c2 u2.c -1 1 -.end diff --git a/design_edit/Tests/and2_2clks/gold/fab_and2x2.v b/design_edit/Tests/and2_2clks/gold/fab_and2x2.v deleted file mode 100644 index 8edbf4cf3..000000000 --- a/design_edit/Tests/and2_2clks/gold/fab_and2x2.v +++ /dev/null @@ -1,212 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_and2x2(\$iopadmap$c2 , \$iopadmap$b , \$auto$clkbufmap.cc:295:execute$568 , \$auto$clkbufmap.cc:295:execute$571 , \$iopadmap$reset , \$iopadmap$c1 , \$iopadmap$a ); - input \$iopadmap$b ; - output \$iopadmap$c1 ; - output \$iopadmap$c2 ; - input \$iopadmap$reset ; - input \$iopadmap$a ; - input \$auto$clkbufmap.cc:295:execute$568 ; - input \$auto$clkbufmap.cc:295:execute$571 ; - wire \$iopadmap$b ; - (* init = 1'h0 *) - (* init = 1'h0 *) - wire \$iopadmap$c1 ; - (* init = 1'h0 *) - (* init = 1'h0 *) - wire \$iopadmap$c2 ; - wire \$iopadmap$clk1 ; - wire \$iopadmap$clk2 ; - wire \$iopadmap$reset ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap572$auto$clkbufmap.cc:262:execute$569.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap572$auto$clkbufmap.cc:262:execute$569.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap573$auto$clkbufmap.cc:262:execute$566.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap573$auto$clkbufmap.cc:262:execute$566.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap574$iopadmap$and2x2.a.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap574$iopadmap$and2x2.a.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap574$iopadmap$and2x2.a.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap575$iopadmap$and2x2.clk2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap575$iopadmap$and2x2.clk2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap575$iopadmap$and2x2.clk2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap576$iopadmap$and2x2.c1.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap576$iopadmap$and2x2.c1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap576$iopadmap$and2x2.c1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap577$iopadmap$and2x2.c2.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap577$iopadmap$and2x2.c2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap577$iopadmap$and2x2.c2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap578$iopadmap$and2x2.clk1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap578$iopadmap$and2x2.clk1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap578$iopadmap$and2x2.clk1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap579$iopadmap$and2x2.reset.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap579$iopadmap$and2x2.reset.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap579$iopadmap$and2x2.reset.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap580$iopadmap$and2x2.b.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap580$iopadmap$and2x2.b.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap580$iopadmap$and2x2.b.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap581$abc$561$auto$blifparse.cc:515:parse_blif$565.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap581$abc$561$auto$blifparse.cc:515:parse_blif$565.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap582$abc$561$auto$blifparse.cc:515:parse_blif$563.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap582$abc$561$auto$blifparse.cc:515:parse_blif$563.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap583$abc$561$auto$blifparse.cc:515:parse_blif$562.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap583$abc$561$auto$blifparse.cc:515:parse_blif$562.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap584$abc$561$auto$blifparse.cc:515:parse_blif$564.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap584$abc$561$auto$blifparse.cc:515:parse_blif$564.Y ; - wire \$iopadmap$a ; - wire \$abc$249$li2_li2 ; - wire \$auto$clkbufmap.cc:295:execute$568 ; - wire \$auto$clkbufmap.cc:295:execute$571 ; - wire \$abc$236$li2_li2 ; - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:18.3-27.8" *) - wire \$abc$212$flatten\u1.$0\b_reg[0:0] ; - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:18.3-27.8" *) - wire \$abc$212$flatten\u1.$0\a_reg[0:0] ; - (* hdlname = "u1 a_reg" *) - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:16.7-16.12" *) - wire \u1.a_reg ; - (* hdlname = "u1 b_reg" *) - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:16.14-16.19" *) - wire \u1.b_reg ; - (* hdlname = "u1 c" *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:42.9-42.34|./Src/and2x2.v:13.14-13.15" *) - wire \u1.c ; - (* hdlname = "u2 a_reg" *) - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:43.9-43.34|./Src/and2x2.v:16.7-16.12" *) - wire \u2.a_reg ; - (* hdlname = "u2 b_reg" *) - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:43.9-43.34|./Src/and2x2.v:16.14-16.19" *) - wire \u2.b_reg ; - (* hdlname = "u2 c" *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2x2.v:43.9-43.34|./Src/and2x2.v:13.14-13.15" *) - wire \u2.c ; - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$561$auto$blifparse.cc:515:parse_blif$565 ( - .A({ \$iopadmap$b , \$iopadmap$reset }), - .Y(\$abc$212$flatten\u1.$0\b_reg[0:0] ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$236$auto$blifparse.cc:362:parse_blif$237 ( - .C(\$auto$clkbufmap.cc:295:execute$568 ), - .D(\$abc$212$flatten\u1.$0\a_reg[0:0] ), - .E(1'h1), - .Q(\u1.a_reg ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$236$auto$blifparse.cc:362:parse_blif$238 ( - .C(\$auto$clkbufmap.cc:295:execute$568 ), - .D(\$abc$212$flatten\u1.$0\b_reg[0:0] ), - .E(1'h1), - .Q(\u1.b_reg ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$236$auto$blifparse.cc:362:parse_blif$239 ( - .C(\$auto$clkbufmap.cc:295:execute$568 ), - .D(\$abc$236$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c1 ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$249$auto$blifparse.cc:362:parse_blif$250 ( - .C(\$auto$clkbufmap.cc:295:execute$571 ), - .D(\$abc$212$flatten\u1.$0\a_reg[0:0] ), - .E(1'h1), - .Q(\u2.a_reg ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$249$auto$blifparse.cc:362:parse_blif$251 ( - .C(\$auto$clkbufmap.cc:295:execute$571 ), - .D(\$abc$212$flatten\u1.$0\b_reg[0:0] ), - .E(1'h1), - .Q(\u2.b_reg ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$249$auto$blifparse.cc:362:parse_blif$252 ( - .C(\$auto$clkbufmap.cc:295:execute$571 ), - .D(\$abc$249$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c2 ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$561$auto$blifparse.cc:515:parse_blif$562 ( - .A({ \u2.a_reg , \u2.b_reg , \$iopadmap$reset }), - .Y(\$abc$249$li2_li2 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$561$auto$blifparse.cc:515:parse_blif$563 ( - .A({ \$iopadmap$a , \$iopadmap$reset }), - .Y(\$abc$212$flatten\u1.$0\a_reg[0:0] ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$561$auto$blifparse.cc:515:parse_blif$564 ( - .A({ \u1.a_reg , \u1.b_reg , \$iopadmap$reset }), - .Y(\$abc$236$li2_li2 ) - ); - assign \u1.c = \$iopadmap$c1 ; - assign \u2.c = \$iopadmap$c2 ; -endmodule diff --git a/design_edit/Tests/and2_2clks/gold/io_config.json b/design_edit/Tests/and2_2clks/gold/io_config.json deleted file mode 100644 index 378ad1157..000000000 --- a/design_edit/Tests/and2_2clks/gold/io_config.json +++ /dev/null @@ -1,246 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\a (index=0, width=1, offset=0)", - " Detect input port \\b (index=0, width=1, offset=0)", - " Detect output port \\c1 (index=0, width=1, offset=0)", - " Detect output port \\c2 (index=0, width=1, offset=0)", - " Detect input port \\clk1 (index=0, width=1, offset=0)", - " Detect input port \\clk2 (index=0, width=1, offset=0)", - " Detect input port \\reset (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$and2x2.a", - " Cell port \\I is connected to input port \\a", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$and2x2.b", - " Cell port \\I is connected to input port \\b", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$and2x2.c1", - " Cell port \\O is connected to output port \\c1", - " Get important connection of cell \\O_BUF $iopadmap$and2x2.c2", - " Cell port \\O is connected to output port \\c2", - " Get important connection of cell \\I_BUF $iopadmap$and2x2.clk1", - " Cell port \\I is connected to input port \\clk1", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$and2x2.clk2", - " Cell port \\I is connected to input port \\clk2", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$and2x2.reset", - " Cell port \\I is connected to input port \\reset", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Trace Clock Buffer", - " Try \\I_BUF $iopadmap$and2x2.clk1 out connection: $iopadmap$clk1", - " Connected $auto$clkbufmap.cc:262:execute$566", - " Additional Connection: $auto$clkbufmap.cc:263:execute$567", - " Try \\I_BUF $iopadmap$and2x2.clk2 out connection: $iopadmap$clk2", - " Connected $auto$clkbufmap.cc:262:execute$569", - " Additional Connection: $auto$clkbufmap.cc:263:execute$570", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$and2x2.a", - "linked_object" : "a", - "linked_objects" : { - "a" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "a", - "O" : "$iopadmap$a" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2x2.b", - "linked_object" : "b", - "linked_objects" : { - "b" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "b", - "O" : "$iopadmap$b" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$and2x2.c1", - "linked_object" : "c1", - "linked_objects" : { - "c1" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$c1", - "O" : "c1" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$and2x2.c2", - "linked_object" : "c2", - "linked_objects" : { - "c2" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$c2", - "O" : "c2" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2x2.clk1", - "linked_object" : "clk1", - "linked_objects" : { - "clk1" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "clk1", - "O" : "$iopadmap$clk1" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk1_#0", - "linked_object" : "clk1", - "linked_objects" : { - "clk1" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk1", - "O" : "$auto$clkbufmap.cc:263:execute$567" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$566", - "linked_object" : "clk1", - "linked_objects" : { - "clk1" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$567", - "O" : "$auto$clkbufmap.cc:295:execute$568" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2x2.clk2", - "linked_object" : "clk2", - "linked_objects" : { - "clk2" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "clk2", - "O" : "$iopadmap$clk2" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk2_#0", - "linked_object" : "clk2", - "linked_objects" : { - "clk2" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk2", - "O" : "$auto$clkbufmap.cc:263:execute$570" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$569", - "linked_object" : "clk2", - "linked_objects" : { - "clk2" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$570", - "O" : "$auto$clkbufmap.cc:295:execute$571" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2x2.reset", - "linked_object" : "reset", - "linked_objects" : { - "reset" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "reset", - "O" : "$iopadmap$reset" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - } - ] -} diff --git a/design_edit/Tests/and2_2clks/gold/wrapper_and2x2_post_synth.eblif b/design_edit/Tests/and2_2clks/gold/wrapper_and2x2_post_synth.eblif deleted file mode 100644 index 53e7afe53..000000000 --- a/design_edit/Tests/and2_2clks/gold/wrapper_and2x2_post_synth.eblif +++ /dev/null @@ -1,53 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model and2x2 -.inputs a b clk1 clk2 reset -.outputs c1 c2 -.names $false -.names $true -1 -.names $undef -.subckt fabric_and2x2 $auto$clkbufmap.cc:295:execute$568=$auto$clkbufmap.cc:295:execute$568 $auto$clkbufmap.cc:295:execute$571=$auto$clkbufmap.cc:295:execute$571 $iopadmap$a=$iopadmap$a $iopadmap$b=$iopadmap$b $iopadmap$c1=$iopadmap$c1 $iopadmap$c2=$iopadmap$c2 $iopadmap$reset=$iopadmap$reset -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk1 O=$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$568 -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk2 O=$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$571 -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$586.a O=$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$a -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$586.b O=$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$b -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c1 O=$auto$rs_design_edit.cc:682:execute$586.c1 -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c2 O=$auto$rs_design_edit.cc:682:execute$586.c2 -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$586.clk1 O=$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk1 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$586.clk2 O=$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk2 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$586.reset O=$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$reset -.param WEAK_KEEPER "NONE" -.names $flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$568 $auto$clkbufmap.cc:295:execute$568 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$571 $auto$clkbufmap.cc:295:execute$571 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$a $iopadmap$a -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$b $iopadmap$b -1 1 -.names $iopadmap$c1 $flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c1 -1 1 -.names $iopadmap$c2 $flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c2 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$reset $iopadmap$reset -1 1 -.names a $auto$rs_design_edit.cc:682:execute$586.a -1 1 -.names b $auto$rs_design_edit.cc:682:execute$586.b -1 1 -.names $auto$rs_design_edit.cc:682:execute$586.c1 c1 -1 1 -.names $auto$rs_design_edit.cc:682:execute$586.c2 c2 -1 1 -.names clk1 $auto$rs_design_edit.cc:682:execute$586.clk1 -1 1 -.names clk2 $auto$rs_design_edit.cc:682:execute$586.clk2 -1 1 -.names reset $auto$rs_design_edit.cc:682:execute$586.reset -1 1 -.end diff --git a/design_edit/Tests/and2_2clks/gold/wrapper_and2x2_post_synth.v b/design_edit/Tests/and2_2clks/gold/wrapper_and2x2_post_synth.v deleted file mode 100644 index 77aa957cd..000000000 --- a/design_edit/Tests/and2_2clks/gold/wrapper_and2x2_post_synth.v +++ /dev/null @@ -1,171 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module and2x2(a, b, clk1, clk2, reset, c1, c2); - input clk1; - input clk2; - input a; - output c2; - input reset; - input b; - output c1; - (* keep = 32'd1 *) - (* src = "./Src/and2x2.v:39.15-39.17" *) - wire \$auto$rs_design_edit.cc:682:execute$586.c2 ; - (* keep = 32'd1 *) - (* src = "./Src/and2x2.v:38.15-38.17" *) - wire \$auto$rs_design_edit.cc:682:execute$586.c1 ; - (* src = "./Src/and2x2.v:36.9-36.13" *) - wire \$auto$rs_design_edit.cc:682:execute$586.clk2 ; - (* src = "./Src/and2x2.v:33.9-33.10" *) - wire \$auto$rs_design_edit.cc:682:execute$586.a ; - (* src = "./Src/and2x2.v:37.9-37.14" *) - wire \$auto$rs_design_edit.cc:682:execute$586.reset ; - (* src = "./Src/and2x2.v:35.9-35.13" *) - wire \$auto$rs_design_edit.cc:682:execute$586.clk1 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$568 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$571 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$a ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$b ; - (* init = 1'h0 *) - wire \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c1 ; - (* init = 1'h0 *) - wire \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c2 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk1 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk2 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$reset ; - (* src = "./Src/and2x2.v:34.9-34.10" *) - wire \$auto$rs_design_edit.cc:682:execute$586.b ; - (* src = "./Src/and2x2.v:35.9-35.13" *) - (* src = "./Src/and2x2.v:35.9-35.13" *) - wire clk1; - (* src = "./Src/and2x2.v:36.9-36.13" *) - (* src = "./Src/and2x2.v:36.9-36.13" *) - wire clk2; - (* init = 1'h0 *) - wire \$iopadmap$c2 ; - (* init = 1'h0 *) - wire \$iopadmap$c1 ; - wire \$iopadmap$b ; - wire \$iopadmap$a ; - wire \$auto$clkbufmap.cc:295:execute$571 ; - wire \$auto$clkbufmap.cc:295:execute$568 ; - wire \$iopadmap$reset ; - (* src = "./Src/and2x2.v:33.9-33.10" *) - (* src = "./Src/and2x2.v:33.9-33.10" *) - wire a; - (* keep = 32'd1 *) - (* src = "./Src/and2x2.v:39.15-39.17" *) - (* keep = 32'd1 *) - (* src = "./Src/and2x2.v:39.15-39.17" *) - wire c2; - (* src = "./Src/and2x2.v:37.9-37.14" *) - (* src = "./Src/and2x2.v:37.9-37.14" *) - wire reset; - (* src = "./Src/and2x2.v:34.9-34.10" *) - (* src = "./Src/and2x2.v:34.9-34.10" *) - wire b; - (* keep = 32'd1 *) - (* src = "./Src/and2x2.v:38.15-38.17" *) - (* keep = 32'd1 *) - (* src = "./Src/and2x2.v:38.15-38.17" *) - wire c1; - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:262:execute$566 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk1 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$568 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:262:execute$569 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk2 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$571 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$and2x2.a ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$586.a ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$a ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$and2x2.b ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$586.b ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$b ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$and2x2.c1 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c1 ), - .O(\$auto$rs_design_edit.cc:682:execute$586.c1 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$and2x2.c2 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c2 ), - .O(\$auto$rs_design_edit.cc:682:execute$586.c2 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$and2x2.clk1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$586.clk1 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk1 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$and2x2.clk2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$586.clk2 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$clk2 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$and2x2.reset ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$586.reset ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$reset ) - ); - fabric_and2x2 \$auto$rs_design_edit.cc:680:execute$585 ( - .\$auto$clkbufmap.cc:295:execute$568 (\$auto$clkbufmap.cc:295:execute$568 ), - .\$auto$clkbufmap.cc:295:execute$571 (\$auto$clkbufmap.cc:295:execute$571 ), - .\$iopadmap$a (\$iopadmap$a ), - .\$iopadmap$b (\$iopadmap$b ), - .\$iopadmap$c1 (\$iopadmap$c1 ), - .\$iopadmap$c2 (\$iopadmap$c2 ), - .\$iopadmap$reset (\$iopadmap$reset ) - ); - assign \$auto$clkbufmap.cc:295:execute$568 = \$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$568 ; - assign \$auto$clkbufmap.cc:295:execute$571 = \$flatten$auto$rs_design_edit.cc:682:execute$586.$auto$clkbufmap.cc:295:execute$571 ; - assign \$iopadmap$a = \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$a ; - assign \$iopadmap$b = \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$b ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c1 = \$iopadmap$c1 ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$c2 = \$iopadmap$c2 ; - assign \$iopadmap$reset = \$flatten$auto$rs_design_edit.cc:682:execute$586.$iopadmap$reset ; - assign \$auto$rs_design_edit.cc:682:execute$586.a = a; - assign \$auto$rs_design_edit.cc:682:execute$586.b = b; - assign c1 = \$auto$rs_design_edit.cc:682:execute$586.c1 ; - assign c2 = \$auto$rs_design_edit.cc:682:execute$586.c2 ; - assign \$auto$rs_design_edit.cc:682:execute$586.clk1 = clk1; - assign \$auto$rs_design_edit.cc:682:execute$586.clk2 = clk2; - assign \$auto$rs_design_edit.cc:682:execute$586.reset = reset; -endmodule diff --git a/design_edit/Tests/and2_2clks/pin_constraints.pin b/design_edit/Tests/and2_2clks/pin_constraints.pin deleted file mode 100644 index c81c8f14b..000000000 --- a/design_edit/Tests/and2_2clks/pin_constraints.pin +++ /dev/null @@ -1,3 +0,0 @@ -set_clock_pin -device_clock clk[1] -design_clock clk1 -set_clock_pin -device_clock clk[2] -design_clock clk2 - diff --git a/design_edit/Tests/input_to_I_DELAY/input_to_I_DELAY.ys b/design_edit/Tests/input_to_I_DELAY/input_to_I_DELAY.ys new file mode 100644 index 000000000..b8ff33a59 --- /dev/null +++ b/design_edit/Tests/input_to_I_DELAY/input_to_I_DELAY.ys @@ -0,0 +1,17 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/input_to_I_DELAY.v + +# Technology mapping +hierarchy -auto-top + +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_input_to_I_DELAY_post_synth.v ./tmp//wrapper_input_to_I_DELAY_post_synth.eblif + +write_verilog -noexpr -nodec -v ./tmp/fabric_input_to_I_DELAY_post_synth.v +write_blif -param ./tmp/fabric_input_to_I_DELAY_post_synth.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/input_to_I_DELAY/rtl/input_to_I_DELAY.v b/design_edit/Tests/input_to_I_DELAY/rtl/input_to_I_DELAY.v new file mode 100644 index 000000000..90802401d --- /dev/null +++ b/design_edit/Tests/input_to_I_DELAY/rtl/input_to_I_DELAY.v @@ -0,0 +1,325 @@ +/* Generated by Yosys 0.38 (git sha1 6c475f1f1, gcc 11.2.1 -fPIC -Os) */ + +module GJC19(clk_i_buf, data_i, dly_incdec_buf, dly_ld_buf, dly_adj_buf, data_o_inv_delayed_buf, dly_tap_val_inv_buf); + input clk_i_buf; + input data_i; + output data_o_inv_delayed_buf; + input dly_adj_buf; + input dly_incdec_buf; + input dly_ld_buf; + output [5:0] dly_tap_val_inv_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.26-21.37" *) + wire \$f2g_trx_dly_adj_dly_adj_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.10-21.24" *) + wire \$f2g_trx_dly_inc_dly_incdec_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.39-21.49" *) + wire \$f2g_trx_dly_ld_dly_ld_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:24.10-24.19" *) + wire clk_buf_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:25.10-25.15" *) + wire clk_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:10.16-10.25" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:10.16-10.25" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:11.16-11.22" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:11.16-11.22" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:19.10-19.16" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:30.10-30.28" *) + wire data_o_inv_delayed; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:15.17-15.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:15.17-15.39" *) + wire data_o_inv_delayed_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:28.10-28.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:14.16-14.27" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:14.16-14.27" *) + wire dly_adj_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.26-21.37" *) + wire dly_adj_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:26.10-26.20" *) + wire dly_incdec; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:12.16-12.30" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:12.16-12.30" *) + wire dly_incdec_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.10-21.24" *) + wire dly_incdec_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:27.10-27.16" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:13.16-13.26" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:13.16-13.26" *) + wire dly_ld_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.39-21.49" *) + wire dly_ld_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:16.23-16.42" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:16.23-16.42" *) + wire [5:0] dly_tap_val_inv_buf; + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_481 ( + .A(data_o), + .Y(data_o_inv_delayed) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_482 ( + .A(dly_incdec), + .Y(dly_incdec_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_483 ( + .A(dly_adj), + .Y(dly_adj_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_484 ( + .A(dly_ld), + .Y(dly_ld_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_485 ( + .A(\dly_tap_val[5] ), + .Y(\dly_tap_val_inv[5] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_486 ( + .A(\dly_tap_val[4] ), + .Y(\dly_tap_val_inv[4] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_487 ( + .A(\dly_tap_val[3] ), + .Y(\dly_tap_val_inv[3] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_488 ( + .A(\dly_tap_val[2] ), + .Y(\dly_tap_val_inv[2] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_489 ( + .A(\dly_tap_val[1] ), + .Y(\dly_tap_val_inv[1] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_490 ( + .A(\dly_tap_val[0] ), + .Y(\dly_tap_val_inv[0] ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_inv_1 ( + .I(dly_adj_inv), + .O(\$f2g_trx_dly_adj_dly_adj_inv ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_incdec_inv_1 ( + .I(dly_incdec_inv), + .O(\$f2g_trx_dly_inc_dly_incdec_inv ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_inv_1 ( + .I(dly_ld_inv), + .O(\$f2g_trx_dly_ld_dly_ld_inv ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[0]_1 ( + .I(\$ifab_dly_tap_val[0] ), + .O(\dly_tap_val[0] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[1]_1 ( + .I(\$ifab_dly_tap_val[1] ), + .O(\dly_tap_val[1] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[2]_1 ( + .I(\$ifab_dly_tap_val[2] ), + .O(\dly_tap_val[2] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[3]_1 ( + .I(\$ifab_dly_tap_val[3] ), + .O(\dly_tap_val[3] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[4]_1 ( + .I(\$ifab_dly_tap_val[4] ), + .O(\dly_tap_val[4] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[5]_1 ( + .I(\$ifab_dly_tap_val[5] ), + .O(\dly_tap_val[5] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:33.39-33.69" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_i) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:34.39-34.79" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(dly_incdec_buf), + .O(dly_incdec) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:35.39-35.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(dly_ld_buf), + .O(dly_ld) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:36.39-36.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_adj_buf), + .O(dly_adj) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:47.13-47.43" *) + CLK_BUF clock_buffer ( + .I(clk_i), + .O(clk_buf_i) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:56.11-56.46" *) + I_BUF data_buf ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:57.13-63.40" *) + I_DELAY #( + .DELAY(32'h00000000) + ) data_i_delay ( + .CLK_IN(clk_buf_i), + .DLY_ADJ(\$f2g_trx_dly_adj_dly_adj_inv ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_incdec_inv ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld_inv ), + .DLY_TAP_VALUE({ \$ifab_dly_tap_val[5] , \$ifab_dly_tap_val[4] , \$ifab_dly_tap_val[3] , \$ifab_dly_tap_val[2] , \$ifab_dly_tap_val[1] , \$ifab_dly_tap_val[0] }), + .I(data_i), + .O(data_o) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:37.11-37.62" *) + O_BUF obuf00_ ( + .I(data_o_inv_delayed), + .O(data_o_inv_delayed_buf) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:38.11-38.62" *) + O_BUF obuf0_ ( + .I(\dly_tap_val_inv[0] ), + .O(dly_tap_val_inv_buf[0]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:39.11-39.62" *) + O_BUF obuf1_ ( + .I(\dly_tap_val_inv[1] ), + .O(dly_tap_val_inv_buf[1]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:40.11-40.62" *) + O_BUF obuf2_ ( + .I(\dly_tap_val_inv[2] ), + .O(dly_tap_val_inv_buf[2]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:41.11-41.62" *) + O_BUF obuf3_ ( + .I(\dly_tap_val_inv[3] ), + .O(dly_tap_val_inv_buf[3]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:42.11-42.62" *) + O_BUF obuf4_ ( + .I(\dly_tap_val_inv[4] ), + .O(dly_tap_val_inv_buf[4]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:43.11-43.62" *) + O_BUF obuf5_ ( + .I(\dly_tap_val_inv[5] ), + .O(dly_tap_val_inv_buf[5]) + ); +endmodule diff --git a/design_edit/Tests/input_to_I_DELAY_ctrl/input_to_I_DELAY_ctrl.ys b/design_edit/Tests/input_to_I_DELAY_ctrl/input_to_I_DELAY_ctrl.ys new file mode 100644 index 000000000..585f1d1dc --- /dev/null +++ b/design_edit/Tests/input_to_I_DELAY_ctrl/input_to_I_DELAY_ctrl.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/input_to_I_DELAY_ctrl.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/input_to_I_DELAY_ctrl.v +#write_blif -param ./tmp/input_to_I_DELAY_ctrl.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_input_to_I_DELAY_ctrl.v ./tmp//wrapper_input_to_I_DELAY_ctrl.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_input_to_I_DELAY_ctrl.v +write_blif -param ./tmp/fabric_input_to_I_DELAY_ctrl.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/input_to_I_DELAY_ctrl/pin_constraints.pin b/design_edit/Tests/input_to_I_DELAY_ctrl/pin_constraints.pin new file mode 100644 index 000000000..901583ed2 --- /dev/null +++ b/design_edit/Tests/input_to_I_DELAY_ctrl/pin_constraints.pin @@ -0,0 +1 @@ +set_pin_loc clk_i_buf HP_1_CC_18_9P diff --git a/design_edit/Tests/input_to_I_DELAY_ctrl/rtl/input_to_I_DELAY_ctrl.v b/design_edit/Tests/input_to_I_DELAY_ctrl/rtl/input_to_I_DELAY_ctrl.v new file mode 100644 index 000000000..800d454f0 --- /dev/null +++ b/design_edit/Tests/input_to_I_DELAY_ctrl/rtl/input_to_I_DELAY_ctrl.v @@ -0,0 +1,325 @@ +/* Generated by Yosys 0.38 (git sha1 6c475f1f1, gcc 11.2.1 -fPIC -Os) */ + +module GJC19(clk_i_buf, data_i, dly_incdec_buf, dly_ld_buf, dly_adj_buf, data_o_inv_delayed_buf, dly_tap_val_inv_buf); + input clk_i_buf; + input data_i; + output data_o_inv_delayed_buf; + input dly_adj_buf; + input dly_incdec_buf; + input dly_ld_buf; + output [5:0] dly_tap_val_inv_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.26-21.37" *) + wire \$f2g_trx_dly_adj_dly_adj_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.10-21.24" *) + wire \$f2g_trx_dly_inc_dly_incdec_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.39-21.49" *) + wire \$f2g_trx_dly_ld_dly_ld_inv ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \$ifab_dly_tap_val[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:24.10-24.19" *) + wire clk_buf_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:25.10-25.15" *) + wire clk_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:10.16-10.25" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:10.16-10.25" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:11.16-11.22" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:11.16-11.22" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:19.10-19.16" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:30.10-30.28" *) + wire data_o_inv_delayed; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:15.17-15.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:15.17-15.39" *) + wire data_o_inv_delayed_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:28.10-28.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:14.16-14.27" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:14.16-14.27" *) + wire dly_adj_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.26-21.37" *) + wire dly_adj_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:26.10-26.20" *) + wire dly_incdec; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:12.16-12.30" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:12.16-12.30" *) + wire dly_incdec_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.10-21.24" *) + wire dly_incdec_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:27.10-27.16" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:13.16-13.26" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:13.16-13.26" *) + wire dly_ld_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:21.39-21.49" *) + wire dly_ld_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:20.16-20.27" *) + wire \dly_tap_val[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:31.16-31.31" *) + wire \dly_tap_val_inv[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:16.23-16.42" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:16.23-16.42" *) + wire [5:0] dly_tap_val_inv_buf; + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_481 ( + .A(data_o), + .Y(data_o_inv_delayed) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_482 ( + .A(dly_incdec), + .Y(dly_incdec_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_483 ( + .A(dly_adj), + .Y(dly_adj_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_484 ( + .A(dly_ld), + .Y(dly_ld_inv) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_485 ( + .A(\dly_tap_val[5] ), + .Y(\dly_tap_val_inv[5] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_486 ( + .A(\dly_tap_val[4] ), + .Y(\dly_tap_val_inv[4] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_487 ( + .A(\dly_tap_val[3] ), + .Y(\dly_tap_val_inv[3] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_488 ( + .A(\dly_tap_val[2] ), + .Y(\dly_tap_val_inv[2] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_489 ( + .A(\dly_tap_val[1] ), + .Y(\dly_tap_val_inv[1] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/07_24_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$480$auto_490 ( + .A(\dly_tap_val[0] ), + .Y(\dly_tap_val_inv[0] ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_inv_1 ( + .I(dly_adj_inv), + .O(\$f2g_trx_dly_adj_dly_adj_inv ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_incdec_inv_1 ( + .I(dly_incdec_inv), + .O(\$f2g_trx_dly_inc_dly_incdec_inv ) + ); + (* keep = 32'h00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_inv_1 ( + .I(dly_ld_inv), + .O(\$f2g_trx_dly_ld_dly_ld_inv ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[0]_1 ( + .I(\$ifab_dly_tap_val[0] ), + .O(\dly_tap_val[0] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[1]_1 ( + .I(\$ifab_dly_tap_val[1] ), + .O(\dly_tap_val[1] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[2]_1 ( + .I(\$ifab_dly_tap_val[2] ), + .O(\dly_tap_val[2] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[3]_1 ( + .I(\$ifab_dly_tap_val[3] ), + .O(\dly_tap_val[3] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[4]_1 ( + .I(\$ifab_dly_tap_val[4] ), + .O(\dly_tap_val[4] ) + ); + (* keep = 32'h00000001 *) + I_FAB \$ifab_dly_tap_val[5]_1 ( + .I(\$ifab_dly_tap_val[5] ), + .O(\dly_tap_val[5] ) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:33.39-33.69" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_i) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:34.39-34.79" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(dly_incdec_buf), + .O(dly_incdec) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:35.39-35.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(dly_ld_buf), + .O(dly_ld) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:36.39-36.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_adj_buf), + .O(dly_adj) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:47.13-47.43" *) + CLK_BUF clock_buffer ( + .I(clk_i), + .O(clk_buf_i) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:56.11-56.46" *) + I_BUF data_buf ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:57.13-63.40" *) + I_DELAY #( + .DELAY(32'h00000000) + ) data_i_delay ( + .CLK_IN(clk_buf_i), + .DLY_ADJ(dly_adj_buf ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_incdec_inv ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld_inv ), + .DLY_TAP_VALUE({ \$ifab_dly_tap_val[5] , \$ifab_dly_tap_val[4] , \$ifab_dly_tap_val[3] , \$ifab_dly_tap_val[2] , \$ifab_dly_tap_val[1] , \$ifab_dly_tap_val[0] }), + .I(data_i_buf), + .O(data_o) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:37.11-37.62" *) + O_BUF obuf00_ ( + .I(data_o_inv_delayed), + .O(data_o_inv_delayed_buf) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:38.11-38.62" *) + O_BUF obuf0_ ( + .I(\dly_tap_val_inv[0] ), + .O(dly_tap_val_inv_buf[0]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:39.11-39.62" *) + O_BUF obuf1_ ( + .I(\dly_tap_val_inv[1] ), + .O(dly_tap_val_inv_buf[1]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:40.11-40.62" *) + O_BUF obuf2_ ( + .I(\dly_tap_val_inv[2] ), + .O(dly_tap_val_inv_buf[2]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:41.11-41.62" *) + O_BUF obuf3_ ( + .I(\dly_tap_val_inv[3] ), + .O(dly_tap_val_inv_buf[3]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:42.11-42.62" *) + O_BUF obuf4_ ( + .I(\dly_tap_val_inv[4] ), + .O(dly_tap_val_inv_buf[4]) + ); + (* module_not_derived = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC19/results_dir/.././rtl/GJC19.v:43.11-43.62" *) + O_BUF obuf5_ ( + .I(\dly_tap_val_inv[5] ), + .O(dly_tap_val_inv_buf[5]) + ); +endmodule diff --git a/design_edit/Tests/input_to_I_SERDES/input_to_I_SERDES.ys b/design_edit/Tests/input_to_I_SERDES/input_to_I_SERDES.ys new file mode 100644 index 000000000..6d5c1d1bf --- /dev/null +++ b/design_edit/Tests/input_to_I_SERDES/input_to_I_SERDES.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/input_to_I_SERDES.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/input_to_I_SERDES.v +#write_blif -param ./tmp/input_to_I_SERDES.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_input_to_I_SERDES.v ./tmp//wrapper_input_to_I_SERDES.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_input_to_I_SERDES.v +write_blif -param ./tmp/fabric_input_to_I_SERDES.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/input_to_I_SERDES/pin_constraints.pin b/design_edit/Tests/input_to_I_SERDES/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/input_to_I_SERDES/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/input_to_I_SERDES/rtl/input_to_I_SERDES.v b/design_edit/Tests/input_to_I_SERDES/rtl/input_to_I_SERDES.v new file mode 100644 index 000000000..051d09823 --- /dev/null +++ b/design_edit/Tests/input_to_I_SERDES/rtl/input_to_I_SERDES.v @@ -0,0 +1,783 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(\$ofab_enable_buf_2 ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/input_to_ictrl_O_SERDES/input_to_ictrl_O_SERDES.ys b/design_edit/Tests/input_to_ictrl_O_SERDES/input_to_ictrl_O_SERDES.ys new file mode 100644 index 000000000..2cd0ae9db --- /dev/null +++ b/design_edit/Tests/input_to_ictrl_O_SERDES/input_to_ictrl_O_SERDES.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/input_to_ictrl_O_SERDES.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/input_to_ictrl_O_SERDES.v +#write_blif -param ./tmp/input_to_ictrl_O_SERDES.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_input_to_ictrl_O_SERDES.v ./tmp//wrapper_input_to_ictrl_O_SERDES.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_input_to_ictrl_O_SERDES.v +write_blif -param ./tmp/fabric_input_to_ictrl_O_SERDES.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/input_to_ictrl_O_SERDES/pin_constraints.pin b/design_edit/Tests/input_to_ictrl_O_SERDES/pin_constraints.pin new file mode 100644 index 000000000..dcc47bbff --- /dev/null +++ b/design_edit/Tests/input_to_ictrl_O_SERDES/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clkGHz HP_1_CC_18_9P + +set_pin_loc reset HP_1_0_0P + +set_pin_loc enable_n HP_1_2_1P + +set_pin_loc data_i HP_1_4_2P + +set_pin_loc bitslip_ctrl_n HP_1_6_3P + +set_pin_loc data_o HP_1_8_4P + +set_pin_loc ready HP_1_28_14P \ No newline at end of file diff --git a/design_edit/Tests/input_to_ictrl_O_SERDES/rtl/input_to_ictrl_O_SERDES.v b/design_edit/Tests/input_to_ictrl_O_SERDES/rtl/input_to_ictrl_O_SERDES.v new file mode 100644 index 000000000..033410bbd --- /dev/null +++ b/design_edit/Tests/input_to_ictrl_O_SERDES/rtl/input_to_ictrl_O_SERDES.v @@ -0,0 +1,783 @@ +/* Generated by Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3) */ + +module GJC46_post_synth(reset, enable_n, data_i, bitslip_ctrl_n, clkGHz, data_o, ready); + input bitslip_ctrl_n; + input clkGHz; + input data_i; + output data_o; + input enable_n; + output ready; + input reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97.17-97.42" *) + wire \$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ; + wire \$abc$1161$abc$702$li0_li0 ; + wire \$abc$1161$abc$702$li1_li1 ; + wire \$abc$1161$abc$702$li2_li2 ; + wire \$abc$1161$abc$702$li3_li3 ; + wire \$abc$1161$abc$702$li4_li4 ; + wire \$abc$1161$abc$702$li5_li5 ; + wire \$abc$1161$abc$702$li6_li6 ; + wire \$abc$1161$abc$702$li7_li7 ; + wire \$abc$1729$new_new_n29__ ; + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.54-89.56" *) + wire \$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$f2g_trx_dvalid_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire \$f2g_trx_reset_n_reset_buf_n_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$f2g_tx_oe_buf_output_enable ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \$f2g_tx_out_data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire \$f2g_tx_out_ready_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire \$ifab_buf_output_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire \$ifab_data_i_valid ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire \$ifab_serdes_dpa_lock ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire \$ofab_bitslip_ctrl ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire \$ofab_enable_buf_2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:36.10-36.22" *) + wire bitslip_ctrl; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:13.18-13.32" *) + wire bitslip_ctrl_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:35.10-35.28" *) + wire bitslip_ctrl_n_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:38.10-38.27" *) + wire buf_output_enable; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:14.18-14.24" *) + wire clkGHz; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:37.10-37.20" *) + wire clkGHz_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:26.10-26.23" *) + wire clkGHz_clkbuf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:23.10-23.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:24.10-24.22" *) + wire data_i_delay; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[2] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[3] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[4] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[5] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[6] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[7] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[8] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:29.26-29.39" *) + wire \data_i_serdes[9] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[7] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[8] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:30.25-30.42" *) + wire \data_i_serdes_reg[9] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:31.10-31.22" *) + wire data_i_valid; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:15.18-15.24" *) + wire data_o; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:39.10-39.18" *) + wire delay_in; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:40.10-40.19" *) + wire delay_out; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:22.10-22.20" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:21.10-21.22" *) + wire enable_buf_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:11.18-11.26" *) + wire enable_n; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:28.10-28.24" *) + wire fabric_clk_div; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:27.10-27.17" *) + wire pll_clk; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:16.17-16.22" *) + wire ready; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:33.10-33.19" *) + wire ready_buf; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:10.18-10.23" *) + wire reset; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:19.10-19.19" *) + wire reset_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:20.10-20.21" *) + wire reset_buf_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:34.10-34.25" *) + wire serdes_dpa_lock; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[1] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[2] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[3] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[4] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[5] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[6] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:32.15-32.23" *) + wire \wait_pll[7] ; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h8000000000000000) + ) \$abc$1729$auto_1730 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[5] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1729$new_new_n29__ ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1731 ( + .A({ \wait_pll[7] , \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li7_li7 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1732 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[6] }), + .Y(\$abc$1161$abc$702$li6_li6 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:37.38-37.69" *) + LUT6 #( + .INIT_VALUE(64'h7fffffff80000000) + ) \$abc$1729$auto_1733 ( + .A({ \wait_pll[5] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[4] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li5_li5 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h7fff8000) + ) \$abc$1729$auto_1734 ( + .A({ \wait_pll[4] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] , \wait_pll[3] }), + .Y(\$abc$1161$abc$702$li4_li4 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h7f80) + ) \$abc$1729$auto_1735 ( + .A({ \wait_pll[3] , \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li3_li3 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h78) + ) \$abc$1729$auto_1736 ( + .A({ \wait_pll[2] , \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li2_li2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h6) + ) \$abc$1729$auto_1737 ( + .A({ \wait_pll[1] , \wait_pll[0] }), + .Y(\$abc$1161$abc$702$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:33.38-33.69" *) + LUT5 #( + .INIT_VALUE(32'h80000000) + ) \$abc$1729$auto_1738 ( + .A({ \$abc$1729$new_new_n29__ , data_i_valid, serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:29.38-29.69" *) + LUT4 #( + .INIT_VALUE(16'h8000) + ) \$abc$1729$auto_1739 ( + .A({ \$abc$1729$new_new_n29__ , serdes_dpa_lock, \wait_pll[7] , \wait_pll[6] }), + .Y(ready_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) + LUT3 #( + .INIT_VALUE(8'h7f) + ) \$abc$1729$auto_1740 ( + .A({ \$abc$1729$new_new_n29__ , \wait_pll[7] , \wait_pll[6] }), + .Y(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1741 ( + .A(bitslip_ctrl_n_buf), + .Y(bitslip_ctrl) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1742 ( + .A(enable_buf_n), + .Y(enable_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1743 ( + .A(\wait_pll[0] ), + .Y(\$abc$1161$abc$702$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$1729$auto_1744 ( + .A(reset_buf), + .Y(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_667 ( + .C(fabric_clk_div), + .D(\data_i_serdes[0] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_668 ( + .C(fabric_clk_div), + .D(\data_i_serdes[1] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_669 ( + .C(fabric_clk_div), + .D(\data_i_serdes[2] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_670 ( + .C(fabric_clk_div), + .D(\data_i_serdes[3] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_671 ( + .C(fabric_clk_div), + .D(\data_i_serdes[4] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_672 ( + .C(fabric_clk_div), + .D(\data_i_serdes[5] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_673 ( + .C(fabric_clk_div), + .D(\data_i_serdes[6] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_674 ( + .C(fabric_clk_div), + .D(\data_i_serdes[7] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[7] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_675 ( + .C(fabric_clk_div), + .D(\data_i_serdes[8] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[8] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$666$auto_676 ( + .C(fabric_clk_div), + .D(\data_i_serdes[9] ), + .E(\$abc$1161$abc$489$logic_and$/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:97$12_Y ), + .Q(\data_i_serdes_reg[9] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_703 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li0_li0 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[0] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_704 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li1_li1 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[1] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_705 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li2_li2 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[2] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_706 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li3_li3 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[3] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_707 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li4_li4 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[4] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_708 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li5_li5 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[5] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_709 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li6_li6 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[6] ), + .R(reset_buf_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89.11-89.66" *) + DFFRE \$abc$702$auto_710 ( + .C(clkGHz_clkbuf), + .D(\$abc$1161$abc$702$li7_li7 ), + .E(\$abc$1729$techmap$techmap1312$abc$702$auto_709.$logic_not$/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:89$1262_Y ), + .Q(\wait_pll[7] ), + .R(reset_buf_n) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dvalid_enable_buf_1 ( + .I(enable_buf), + .O(\$f2g_trx_dvalid_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_1 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_buf_n_3 ( + .I(reset_buf_n), + .O(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_oe_buf_output_enable_1 ( + .I(buf_output_enable), + .O(\$f2g_tx_oe_buf_output_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[0]_1 ( + .I(\data_i_serdes_reg[0] ), + .O(\$f2g_tx_out_data_i_serdes_reg[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[1]_1 ( + .I(\data_i_serdes_reg[1] ), + .O(\$f2g_tx_out_data_i_serdes_reg[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[2]_1 ( + .I(\data_i_serdes_reg[2] ), + .O(\$f2g_tx_out_data_i_serdes_reg[2] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[3]_1 ( + .I(\data_i_serdes_reg[3] ), + .O(\$f2g_tx_out_data_i_serdes_reg[3] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[4]_1 ( + .I(\data_i_serdes_reg[4] ), + .O(\$f2g_tx_out_data_i_serdes_reg[4] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[5]_1 ( + .I(\data_i_serdes_reg[5] ), + .O(\$f2g_tx_out_data_i_serdes_reg[5] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[6]_1 ( + .I(\data_i_serdes_reg[6] ), + .O(\$f2g_tx_out_data_i_serdes_reg[6] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[7]_1 ( + .I(\data_i_serdes_reg[7] ), + .O(\$f2g_tx_out_data_i_serdes_reg[7] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[8]_1 ( + .I(\data_i_serdes_reg[8] ), + .O(\$f2g_tx_out_data_i_serdes_reg[8] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_i_serdes_reg[9]_1 ( + .I(\data_i_serdes_reg[9] ), + .O(\$f2g_tx_out_data_i_serdes_reg[9] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_ready_buf_1 ( + .I(ready_buf), + .O(\$f2g_tx_out_ready_buf ) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_bitslip_ctrl_n ( + .EN(1'h1), + .I(bitslip_ctrl_n), + .O(bitslip_ctrl_n_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_clkGHz ( + .EN(1'h1), + .I(clkGHz), + .O(clkGHz_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_data_i ( + .EN(1'h1), + .I(data_i), + .O(data_i_buf) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_enable_n ( + .EN(1'h1), + .I(enable_n), + .O(enable_buf_n) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) + I_BUF #( + .WEAK_KEEPER("NONE") + ) \$ibuf$GJC46.$ibuf_reset ( + .EN(1'h1), + .I(reset), + .O(reset_buf) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_buf_output_enable_1 ( + .I(\$ifab_buf_output_enable ), + .O(buf_output_enable) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_data_i_valid_1 ( + .I(\$ifab_data_i_valid ), + .O(data_i_valid) + ); + (* keep = 32'sh00000001 *) + I_FAB \$ifab_serdes_dpa_lock_1 ( + .I(\$ifab_serdes_dpa_lock ), + .O(serdes_dpa_lock) + ); + (* keep = 32'sh00000001 *) + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) + O_BUFT \$obuf$GJC46.$obuf_ready ( + .I(\$f2g_tx_out_ready_buf ), + .O(ready), + .T(1'h1) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_bitslip_ctrl_1 ( + .I(bitslip_ctrl), + .O(\$ofab_bitslip_ctrl ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_1 ( + .I(enable_buf), + .O(\$ofab_enable_buf ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_buf_3 ( + .I(enable_buf), + .O(\$ofab_enable_buf_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:61.58-65.6" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000001), + .PLL_MULT(32'sh00000032), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen0 ( + .CLK_IN(clkGHz_clkbuf), + .FAST_CLK(pll_clk), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:56.13-56.53" *) + CLK_BUF clock_buffer ( + .I(clkGHz_buf), + .O(clkGHz_clkbuf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:134.12-138.6" *) + O_BUFT counter_o_buft ( + .I(delay_out), + .O(data_o), + .T(\$f2g_tx_oe_buf_output_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:125.7-132.6" *) + O_DELAY #( + .DELAY(32'sh00000000) + ) counter_o_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(delay_in), + .O(delay_out) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:111.7-121.6" *) + O_SERDES #( + .DATA_RATE("SDR"), + .WIDTH(32'sh0000000a) + ) counter_o_serdes ( + .CLK_IN(clkGHz_clkbuf), + .D({ \$f2g_tx_out_data_i_serdes_reg[9] , \$f2g_tx_out_data_i_serdes_reg[8] , \$f2g_tx_out_data_i_serdes_reg[7] , \$f2g_tx_out_data_i_serdes_reg[6] , \$f2g_tx_out_data_i_serdes_reg[5] , \$f2g_tx_out_data_i_serdes_reg[4] , \$f2g_tx_out_data_i_serdes_reg[3] , \$f2g_tx_out_data_i_serdes_reg[2] , \$f2g_tx_out_data_i_serdes_reg[1] , \$f2g_tx_out_data_i_serdes_reg[0] }), + .DATA_VALID(\$f2g_trx_dvalid_enable_buf ), + .OE_IN(enable_n ), + .OE_OUT(\$ifab_buf_output_enable ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q(delay_in), + .RST(\$f2g_trx_reset_n_reset_buf_n_2 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:67.13-74.6" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) input_data_delay ( + .CLK_IN(clkGHz_clkbuf), + .DLY_ADJ(1'h0), + .DLY_INCDEC(1'h0), + .DLY_LOAD(1'h0), + .I(data_i_buf), + .O(data_i_delay) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC46/results_dir/.././rtl/GJC46.v:80.7-92.6" *) + I_SERDES #( + .DATA_RATE("SDR"), + .DPA_MODE("DPA"), + .WIDTH(32'sh0000000a) + ) input_data_serdes ( + .BITSLIP_ADJ(\$ofab_bitslip_ctrl ), + .CLK_IN(clkGHz_clkbuf), + .CLK_OUT(fabric_clk_div), + .D(data_i_delay), + .DATA_VALID(\$ifab_data_i_valid ), + .DPA_LOCK(\$ifab_serdes_dpa_lock ), + .EN(\$ofab_enable_buf ), + .PLL_CLK(pll_clk), + .PLL_LOCK(1'h1), + .Q({ \data_i_serdes[9] , \data_i_serdes[8] , \data_i_serdes[7] , \data_i_serdes[6] , \data_i_serdes[5] , \data_i_serdes[4] , \data_i_serdes[3] , \data_i_serdes[2] , \data_i_serdes[1] , \data_i_serdes[0] }), + .RST(\$f2g_trx_reset_n_reset_buf_n ) + ); +endmodule + diff --git a/design_edit/Tests/input_to_iddr/input_to_iddr.ys b/design_edit/Tests/input_to_iddr/input_to_iddr.ys new file mode 100644 index 000000000..124ebc672 --- /dev/null +++ b/design_edit/Tests/input_to_iddr/input_to_iddr.ys @@ -0,0 +1,25 @@ + +# Yosys synthesis script for ${TOP_MODULE} +# Read source files +read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v +verilog_defines +read_verilog ./rtl/input_to_iddr.v + +# Technology mapping +hierarchy -auto-top + + + +#plugin -i synth-rs +# +#synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 +#write_rtlil design.rtlil +#write_verilog -noexpr -nodec -v ./tmp/input_to_iddr.v +#write_blif -param ./tmp/input_to_iddr.eblif +plugin -i design-edit +design_edit -tech genesis3 -sdc pin_constraints.pin -json ./tmp/io_config.json -w ./tmp//wrapper_input_to_iddr.v ./tmp//wrapper_input_to_iddr.eblif + +write_verilog -noexpr -nodec -norename -v ./tmp/fabric_input_to_iddr.v +write_blif -param ./tmp/fabric_input_to_iddr.eblif + + \ No newline at end of file diff --git a/design_edit/Tests/input_to_iddr/pin_constraints.pin b/design_edit/Tests/input_to_iddr/pin_constraints.pin new file mode 100644 index 000000000..990c57c03 --- /dev/null +++ b/design_edit/Tests/input_to_iddr/pin_constraints.pin @@ -0,0 +1,13 @@ +set_pin_loc clk_i_buf HP_1_CC_18_9P + +set_pin_loc dly_inc_pulse_inv_buf HP_1_0_0P + +set_pin_loc data_i HP_1_1_0N + +set_pin_loc enable_buf HP_1_4_2P + +set_pin_loc reset_n_buf HP_1_3_1N + +set_pin_loc data_o_buf[0] HP_1_6_3P + +set_pin_loc data_o_buf[1] HP_1_8_4P \ No newline at end of file diff --git a/design_edit/Tests/input_to_iddr/rtl/input_to_iddr.v b/design_edit/Tests/input_to_iddr/rtl/input_to_iddr.v new file mode 100644 index 000000000..12d7ec575 --- /dev/null +++ b/design_edit/Tests/input_to_iddr/rtl/input_to_iddr.v @@ -0,0 +1,296 @@ +/* Generated by Yosys 0.44 (git sha1 86a09ee26, g++ 11.2.1 -fPIC -O3) */ + +module GJC31(data_i, reset_n_buf, enable_buf, clk_i_buf, dly_inc_pulse_inv_buf, data_o_buf); + input clk_i_buf; + input data_i; + output [1:0] data_o_buf; + input dly_inc_pulse_inv_buf; + input enable_buf; + input reset_n_buf; + wire \$abc$238$auto_53 ; + wire \$abc$250$li0_li0 ; + wire \$abc$250$li1_li1 ; + wire \$abc$250$li2_li2 ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire \$f2g_in_en_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire \$f2g_trx_dly_adj_dly_adj ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire \$f2g_trx_dly_inc_dly_adj ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:22.9-22.15" *) + wire \$f2g_trx_dly_ld_dly_ld ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:24.10-24.17" *) + wire \$f2g_trx_reset_n_reset_n ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \$f2g_tx_out_data_o[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \$f2g_tx_out_data_o[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire \$ofab_enable ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.16-26.25" *) + wire clk_buf_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.10-26.15" *) + wire clk_i; + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:15.18-15.27" *) + (* keep = 32'h00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:15.18-15.27" *) + wire clk_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:26.26-26.33" *) + wire clk_pll; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:12.18-12.24" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:12.18-12.24" *) + wire data_i; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:21.10-21.20" *) + wire data_i_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:21.22-21.40" *) + wire data_i_buf_delayed; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \data_o[0] ; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:28.16-28.22" *) + wire \data_o[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:17.24-17.34" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:17.24-17.34" *) + wire [1:0] data_o_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:20.16-20.24" *) + wire \data_reg[0] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:20.16-20.24" *) + wire \data_reg[1] ; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:23.10-23.17" *) + wire dly_adj; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:27.10-27.27" *) + wire dly_inc_pulse_inv; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:16.18-16.39" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:16.18-16.39" *) + wire dly_inc_pulse_inv_buf; + (* init = 1'h0 *) + (* keep = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:22.9-22.15" *) + wire dly_ld; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:25.10-25.16" *) + wire enable; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:14.18-14.28" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:14.18-14.28" *) + wire enable_buf; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:24.10-24.17" *) + wire reset_n; + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:13.18-13.29" *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:13.18-13.29" *) + wire reset_n_buf; + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_251 ( + .C(clk_i), + .D(\$abc$250$li0_li0 ), + .E(\$abc$238$auto_53 ), + .Q(\data_o[0] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_252 ( + .C(clk_i), + .D(\$abc$250$li1_li1 ), + .E(\$abc$238$auto_53 ), + .Q(\data_o[1] ), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:80.11-80.65" *) + DFFRE \$abc$250$auto_253 ( + .C(clk_i), + .D(\$abc$250$li2_li2 ), + .E(\$abc$238$auto_53 ), + .Q(dly_ld), + .R(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$596$auto_597 ( + .A({ \data_reg[1] , reset_n }), + .Y(\$abc$250$li1_li1 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'h8) + ) \$abc$596$auto_598 ( + .A({ \data_reg[0] , reset_n }), + .Y(\$abc$250$li0_li0 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) + LUT2 #( + .INIT_VALUE(4'hb) + ) \$abc$596$auto_599 ( + .A({ reset_n, enable }), + .Y(\$abc$238$auto_53 ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$596$auto_600 ( + .A(dly_inc_pulse_inv), + .Y(dly_adj) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_eda_sw/softwares/Raptor/instl_dir/10_16_2024_09_15_01/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) + LUT1 #( + .INIT_VALUE(2'h1) + ) \$abc$596$auto_601 ( + .A(reset_n), + .Y(\$abc$250$li2_li2 ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_in_en_enable_1 ( + .I(enable), + .O(\$f2g_in_en_enable ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_adj_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_adj_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_inc_dly_adj_1 ( + .I(dly_adj), + .O(\$f2g_trx_dly_inc_dly_adj ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_dly_ld_dly_ld_1 ( + .I(dly_ld), + .O(\$f2g_trx_dly_ld_dly_ld ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_trx_reset_n_reset_n_1 ( + .I(reset_n), + .O(\$f2g_trx_reset_n_reset_n ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_o[0]_1 ( + .I(\data_o[0] ), + .O(\$f2g_tx_out_data_o[0] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$f2g_tx_out_data_o[1]_1 ( + .I(\data_o[1] ), + .O(\$f2g_tx_out_data_o[1] ) + ); + (* keep = 32'sh00000001 *) + O_FAB \$ofab_enable_1 ( + .I(enable), + .O(\$ofab_enable ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:31.39-31.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf0_ ( + .EN(1'h1), + .I(reset_n_buf), + .O(reset_n) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:32.39-32.71" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf1_ ( + .EN(1'h1), + .I(enable_buf), + .O(enable) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:33.39-33.73" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf2_ ( + .EN(1'h1), + .I(clk_i_buf), + .O(clk_buf_i) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:34.39-34.93" *) + I_BUF #( + .WEAK_KEEPER("PULLDOWN") + ) buf3_ ( + .EN(1'h1), + .I(dly_inc_pulse_inv_buf), + .O(dly_inc_pulse_inv) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:42.60-46.10" *) + PLL #( + .DEV_FAMILY("VIRGO"), + .DIVIDE_CLK_IN_BY_2("FALSE"), + .PLL_DIV(32'sh00000020), + .PLL_MULT(32'sh00000064), + .PLL_MULT_FRAC(32'sh00000000), + .PLL_POST_DIV(32'sh00000011) + ) clk_pll_gen ( + .CLK_IN(clk_pll), + .CLK_OUT(clk_i), + .PLL_EN(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:40.13-40.45" *) + CLK_BUF clock_buffer ( + .I(clk_buf_i), + .O(clk_pll) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:51.11-51.46" *) + I_BUF data_buf ( + .EN(\$f2g_in_en_enable ), + .I(data_i), + .O(data_i_buf) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:58.11-58.76" *) + I_DDR data_i_ddr ( + .C(clk_i), + .D(data_i), + .E(\$ofab_enable ), + .Q({ \data_reg[1] , \data_reg[0] }), + .R(\$f2g_trx_reset_n_reset_n ) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:52.13-57.52" *) + I_DELAY #( + .DELAY(32'sh00000000) + ) data_i_delay ( + .CLK_IN(clk_i), + .DLY_ADJ(\$f2g_trx_dly_adj_dly_adj ), + .DLY_INCDEC(\$f2g_trx_dly_inc_dly_adj ), + .DLY_LOAD(\$f2g_trx_dly_ld_dly_ld ), + .I(data_i_buf), + .O(data_i_buf_delayed) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:35.11-35.44" *) + O_BUFT obuf0_ ( + .I(\$f2g_tx_out_data_o[0] ), + .O(data_o_buf[0]), + .T(1'h1) + ); + (* module_not_derived = 32'sh00000001 *) + (* src = "/nfs_scratch/scratch/eda/behzad/Validation/RTL_testcases/GJC-IO-Testcases/GJC31/results_dir/.././rtl/GJC31.v:36.11-36.44" *) + O_BUFT obuf1_ ( + .I(\$f2g_tx_out_data_o[1] ), + .O(data_o_buf[1]), + .T(1'h1) + ); +endmodule diff --git a/design_edit/Tests/non_primitive_design/gold/and2_post_synth.eblif b/design_edit/Tests/non_primitive_design/gold/and2_post_synth.eblif deleted file mode 100644 index 0f11cd798..000000000 --- a/design_edit/Tests/non_primitive_design/gold/and2_post_synth.eblif +++ /dev/null @@ -1,15 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_and2 -.inputs $iopadmap$b $auto$clkbufmap.cc:295:execute$425 $iopadmap$a $iopadmap$reset -.outputs $iopadmap$c -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$425 D=$abc$187$li0_li0 E=$true Q=$iopadmap$c R=$abc$420$techmap$techmap336$abc$187$auto$blifparse.cc:362:parse_blif$188.$logic_not$/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19$278_Y -.subckt LUT2 A[0]=$iopadmap$a A[1]=$iopadmap$b Y=$abc$187$li0_li0 -.param INIT_VALUE 1000 -.subckt LUT1 A=$iopadmap$reset Y=$abc$420$techmap$techmap336$abc$187$auto$blifparse.cc:362:parse_blif$188.$logic_not$/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19$278_Y -.param INIT_VALUE 01 -.end diff --git a/design_edit/Tests/non_primitive_design/gold/and2_post_synth.v b/design_edit/Tests/non_primitive_design/gold/and2_post_synth.v deleted file mode 100644 index c50a6dc9b..000000000 --- a/design_edit/Tests/non_primitive_design/gold/and2_post_synth.v +++ /dev/null @@ -1,85 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_and2(\$iopadmap$b , \$iopadmap$c , \$auto$clkbufmap.cc:295:execute$425 , \$iopadmap$a , \$iopadmap$reset ); - output \$iopadmap$c ; - input \$iopadmap$reset ; - input \$auto$clkbufmap.cc:295:execute$425 ; - input \$iopadmap$b ; - input \$iopadmap$a ; - wire \$iopadmap$c ; - wire \$iopadmap$clk ; - wire \$iopadmap$reset ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap426$auto$clkbufmap.cc:262:execute$423.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap426$auto$clkbufmap.cc:262:execute$423.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap427$iopadmap$and2.reset.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap427$iopadmap$and2.reset.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap427$iopadmap$and2.reset.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap428$iopadmap$and2.c.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap428$iopadmap$and2.c.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap428$iopadmap$and2.c.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap429$iopadmap$and2.b.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap429$iopadmap$and2.b.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap429$iopadmap$and2.b.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap430$iopadmap$and2.clk.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap430$iopadmap$and2.clk.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap430$iopadmap$and2.clk.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap431$iopadmap$and2.a.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap431$iopadmap$and2.a.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap431$iopadmap$and2.a.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire \$techmap432$abc$420$auto$blifparse.cc:515:parse_blif$422.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap432$abc$420$auto$blifparse.cc:515:parse_blif$422.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap433$abc$420$auto$blifparse.cc:515:parse_blif$421.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap433$abc$420$auto$blifparse.cc:515:parse_blif$421.Y ; - wire \$auto$clkbufmap.cc:295:execute$425 ; - wire \$iopadmap$b ; - wire \$iopadmap$a ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19.64-19.66" *) - wire \$abc$420$techmap$techmap336$abc$187$auto$blifparse.cc:362:parse_blif$188.$logic_not$/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19$278_Y ; - wire \$abc$187$li0_li0 ; - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19.11-19.68" *) - DFFRE \$abc$187$auto$blifparse.cc:362:parse_blif$188 ( - .C(\$auto$clkbufmap.cc:295:execute$425 ), - .D(\$abc$187$li0_li0 ), - .E(1'h1), - .Q(\$iopadmap$c ), - .R(\$abc$420$techmap$techmap336$abc$187$auto$blifparse.cc:362:parse_blif$188.$logic_not$/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19$278_Y ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h8) - ) \$abc$420$auto$blifparse.cc:515:parse_blif$421 ( - .A({ \$iopadmap$b , \$iopadmap$a }), - .Y(\$abc$187$li0_li0 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) - LUT1 #( - .INIT_VALUE(2'h1) - ) \$abc$420$auto$blifparse.cc:515:parse_blif$422 ( - .A(\$iopadmap$reset ), - .Y(\$abc$420$techmap$techmap336$abc$187$auto$blifparse.cc:362:parse_blif$188.$logic_not$/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19$278_Y ) - ); -endmodule diff --git a/design_edit/Tests/non_primitive_design/gold/io_config.json b/design_edit/Tests/non_primitive_design/gold/io_config.json deleted file mode 100644 index accf59056..000000000 --- a/design_edit/Tests/non_primitive_design/gold/io_config.json +++ /dev/null @@ -1,163 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\a (index=0, width=1, offset=0)", - " Detect input port \\b (index=0, width=1, offset=0)", - " Detect output port \\c (index=0, width=1, offset=0)", - " Detect input port \\clk (index=0, width=1, offset=0)", - " Detect input port \\reset (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$and2.a", - " Cell port \\I is connected to input port \\a", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$and2.b", - " Cell port \\I is connected to input port \\b", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$and2.c", - " Cell port \\O is connected to output port \\c", - " Get important connection of cell \\I_BUF $iopadmap$and2.clk", - " Cell port \\I is connected to input port \\clk", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$and2.reset", - " Cell port \\I is connected to input port \\reset", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Trace Clock Buffer", - " Try \\I_BUF $iopadmap$and2.clk out connection: $iopadmap$clk", - " Connected $auto$clkbufmap.cc:262:execute$423", - " Additional Connection: $auto$clkbufmap.cc:263:execute$424", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.a", - "linked_object" : "a", - "linked_objects" : { - "a" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "a", - "O" : "$iopadmap$a" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.b", - "linked_object" : "b", - "linked_objects" : { - "b" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "b", - "O" : "$iopadmap$b" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$and2.c", - "linked_object" : "c", - "linked_objects" : { - "c" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$c", - "O" : "c" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.clk", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "clk", - "O" : "$iopadmap$clk" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk_#0", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk", - "O" : "$auto$clkbufmap.cc:263:execute$424" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$423", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$424", - "O" : "$auto$clkbufmap.cc:295:execute$425" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.reset", - "linked_object" : "reset", - "linked_objects" : { - "reset" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "reset", - "O" : "$iopadmap$reset" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - } - ] -} diff --git a/design_edit/Tests/non_primitive_design/gold/wrapper_and2_post_synth.eblif b/design_edit/Tests/non_primitive_design/gold/wrapper_and2_post_synth.eblif deleted file mode 100644 index 09b028a29..000000000 --- a/design_edit/Tests/non_primitive_design/gold/wrapper_and2_post_synth.eblif +++ /dev/null @@ -1,41 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model and2 -.inputs a b clk reset -.outputs c -.names $false -.names $true -1 -.names $undef -.subckt fabric_and2 $auto$clkbufmap.cc:295:execute$425=$auto$clkbufmap.cc:295:execute$425 $iopadmap$a=$iopadmap$a $iopadmap$b=$iopadmap$b $iopadmap$c=$iopadmap$c $iopadmap$reset=$iopadmap$reset -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$clk O=$flatten$auto$rs_design_edit.cc:682:execute$435.$auto$clkbufmap.cc:295:execute$425 -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$435.a O=$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$a -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$435.b O=$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$b -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$c O=$auto$rs_design_edit.cc:682:execute$435.c -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$435.clk O=$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$435.reset O=$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$reset -.param WEAK_KEEPER "NONE" -.names $flatten$auto$rs_design_edit.cc:682:execute$435.$auto$clkbufmap.cc:295:execute$425 $auto$clkbufmap.cc:295:execute$425 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$a $iopadmap$a -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$b $iopadmap$b -1 1 -.names $iopadmap$c $flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$c -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$reset $iopadmap$reset -1 1 -.names a $auto$rs_design_edit.cc:682:execute$435.a -1 1 -.names b $auto$rs_design_edit.cc:682:execute$435.b -1 1 -.names $auto$rs_design_edit.cc:682:execute$435.c c -1 1 -.names clk $auto$rs_design_edit.cc:682:execute$435.clk -1 1 -.names reset $auto$rs_design_edit.cc:682:execute$435.reset -1 1 -.end diff --git a/design_edit/Tests/non_primitive_design/gold/wrapper_and2_post_synth.v b/design_edit/Tests/non_primitive_design/gold/wrapper_and2_post_synth.v deleted file mode 100644 index 4b62fdb20..000000000 --- a/design_edit/Tests/non_primitive_design/gold/wrapper_and2_post_synth.v +++ /dev/null @@ -1,118 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module and2(a, b, c, clk, reset); - input a; - input clk; - output c; - input reset; - input b; - (* keep = 32'd1 *) - (* src = "./rtl/and2.v:18.8-18.9" *) - wire \$auto$rs_design_edit.cc:682:execute$435.c ; - (* src = "./rtl/and2.v:14.12-14.13" *) - wire \$auto$rs_design_edit.cc:682:execute$435.a ; - (* src = "./rtl/and2.v:16.12-16.15" *) - wire \$auto$rs_design_edit.cc:682:execute$435.clk ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$435.$auto$clkbufmap.cc:295:execute$425 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$a ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$b ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$c ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$clk ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$reset ; - (* src = "./rtl/and2.v:15.12-15.13" *) - wire \$auto$rs_design_edit.cc:682:execute$435.b ; - (* src = "./rtl/and2.v:17.12-17.17" *) - wire \$auto$rs_design_edit.cc:682:execute$435.reset ; - (* src = "./rtl/and2.v:14.12-14.13" *) - (* src = "./rtl/and2.v:14.12-14.13" *) - wire a; - wire \$iopadmap$reset ; - (* src = "./rtl/and2.v:16.12-16.15" *) - (* src = "./rtl/and2.v:16.12-16.15" *) - wire clk; - wire \$iopadmap$c ; - wire \$iopadmap$b ; - wire \$iopadmap$a ; - wire \$auto$clkbufmap.cc:295:execute$425 ; - (* keep = 32'd1 *) - (* src = "./rtl/and2.v:18.8-18.9" *) - (* keep = 32'd1 *) - (* src = "./rtl/and2.v:18.8-18.9" *) - wire c; - (* src = "./rtl/and2.v:17.12-17.17" *) - (* src = "./rtl/and2.v:17.12-17.17" *) - wire reset; - (* src = "./rtl/and2.v:15.12-15.13" *) - (* src = "./rtl/and2.v:15.12-15.13" *) - wire b; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$and2.clk ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$435.clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$clk ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$and2.reset ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$435.reset ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$reset ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$435.$auto$clkbufmap.cc:262:execute$423 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$435.$auto$clkbufmap.cc:295:execute$425 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$and2.a ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$435.a ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$a ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$and2.b ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$435.b ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$b ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$and2.c ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$c ), - .O(\$auto$rs_design_edit.cc:682:execute$435.c ) - ); - fabric_and2 \$auto$rs_design_edit.cc:680:execute$434 ( - .\$auto$clkbufmap.cc:295:execute$425 (\$auto$clkbufmap.cc:295:execute$425 ), - .\$iopadmap$a (\$iopadmap$a ), - .\$iopadmap$b (\$iopadmap$b ), - .\$iopadmap$c (\$iopadmap$c ), - .\$iopadmap$reset (\$iopadmap$reset ) - ); - assign \$auto$clkbufmap.cc:295:execute$425 = \$flatten$auto$rs_design_edit.cc:682:execute$435.$auto$clkbufmap.cc:295:execute$425 ; - assign \$iopadmap$a = \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$a ; - assign \$iopadmap$b = \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$b ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$c = \$iopadmap$c ; - assign \$iopadmap$reset = \$flatten$auto$rs_design_edit.cc:682:execute$435.$iopadmap$reset ; - assign \$auto$rs_design_edit.cc:682:execute$435.a = a; - assign \$auto$rs_design_edit.cc:682:execute$435.b = b; - assign c = \$auto$rs_design_edit.cc:682:execute$435.c ; - assign \$auto$rs_design_edit.cc:682:execute$435.clk = clk; - assign \$auto$rs_design_edit.cc:682:execute$435.reset = reset; -endmodule diff --git a/design_edit/Tests/non_primitive_design/non_primitive_design.ys b/design_edit/Tests/non_primitive_design/non_primitive_design.ys deleted file mode 100644 index 9c626ef04..000000000 --- a/design_edit/Tests/non_primitive_design/non_primitive_design.ys +++ /dev/null @@ -1,19 +0,0 @@ -# Yosys synthesis script for O_SERDES_primitive_inst -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./rtl/and2.v - - -# Technology mapping -hierarchy -top and2 - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal delay -effort high -carry auto -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -json ./tmp/io_config.json -w ./tmp/wrapper_and2_post_synth.v ./tmp/wrapper_and2_post_synth.eblif -write_verilog -noexpr -nodec -norename -v ./tmp/and2_post_synth.v -write_blif -param ./tmp/and2_post_synth.eblif \ No newline at end of file diff --git a/design_edit/Tests/non_primitive_design/rtl/and2.v b/design_edit/Tests/non_primitive_design/rtl/and2.v deleted file mode 100644 index 9a40080bf..000000000 --- a/design_edit/Tests/non_primitive_design/rtl/and2.v +++ /dev/null @@ -1,32 +0,0 @@ -///////////////////////////////////////// -// Functionality: 2-input AND -// Author: Xifan Tang -//////////////////////////////////////// -// `timescale 1ns / 1ps - -module and2( - a, - b, - c, - clk, - reset); - -input wire a; -input wire b; -input wire clk; -input wire reset; -output c; - -wire d; -reg c; - -assign d = a & b; - -always@(posedge clk or posedge reset) begin - if (reset) - c = 0; - else - c = d; -end - -endmodule diff --git a/design_edit/Tests/non_primitive_design/synthesis/and2_post_synth.eblif b/design_edit/Tests/non_primitive_design/synthesis/and2_post_synth.eblif deleted file mode 100644 index ac8249494..000000000 --- a/design_edit/Tests/non_primitive_design/synthesis/and2_post_synth.eblif +++ /dev/null @@ -1,15 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model and2 -.inputs a b clk reset -.outputs c -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=clk D=$abc$187$li0_li0 E=$true Q=c R=$abc$420$techmap$techmap341$abc$187$auto$blifparse.cc:362:parse_blif$188.$logic_not$/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19$278_Y -.subckt LUT2 A[0]=a A[1]=b Y=$abc$187$li0_li0 -.param INIT_VALUE 1000 -.subckt LUT1 A=reset Y=$abc$420$techmap$techmap341$abc$187$auto$blifparse.cc:362:parse_blif$188.$logic_not$/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19$278_Y -.param INIT_VALUE 01 -.end diff --git a/design_edit/Tests/non_primitive_design/synthesis/and2_post_synth.v b/design_edit/Tests/non_primitive_design/synthesis/and2_post_synth.v deleted file mode 100644 index e461cdd9e..000000000 --- a/design_edit/Tests/non_primitive_design/synthesis/and2_post_synth.v +++ /dev/null @@ -1,62 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 9ae216287, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module and2(a, b, c, clk, reset); - input a; - input b; - output c; - input clk; - input reset; - (* src = "/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] _0_; - (* src = "/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _1_; - (* src = "/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire _2_; - (* src = "/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _3_; - wire _4_; - (* src = "/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19.64-19.66" *) - wire _5_; - (* src = "./rtl/and2.v:14.12-14.13" *) - (* src = "./rtl/and2.v:14.12-14.13" *) - wire a; - (* src = "./rtl/and2.v:15.12-15.13" *) - (* src = "./rtl/and2.v:15.12-15.13" *) - wire b; - (* keep = 32'h00000001 *) - (* src = "./rtl/and2.v:18.8-18.9" *) - (* keep = 32'h00000001 *) - (* src = "./rtl/and2.v:18.8-18.9" *) - wire c; - (* src = "./rtl/and2.v:16.12-16.15" *) - (* src = "./rtl/and2.v:16.12-16.15" *) - wire clk; - (* src = "./rtl/and2.v:17.12-17.17" *) - (* src = "./rtl/and2.v:17.12-17.17" *) - wire reset; - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h8) - ) _6_ ( - .Y(_4_), - .A({ b, a }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) - LUT1 #( - .INIT_VALUE(2'h1) - ) _7_ ( - .Y(_5_), - .A(reset) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/gg/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:19.11-19.68" *) - DFFRE _8_ ( - .C(clk), - .D(_4_), - .E(1'h1), - .Q(c), - .R(_5_) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_1/gold/interface.json b/design_edit/Tests/primitive_example_design_1/gold/interface.json deleted file mode 100644 index 2abb29f96..000000000 --- a/design_edit/Tests/primitive_example_design_1/gold/interface.json +++ /dev/null @@ -1,545 +0,0 @@ -{ - "IO_Instances": { - "clk_buf_inst": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf0_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "clk", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "clk_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst1": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf1_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst10": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf10_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst11": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf11_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ] - } - }, - "ibuf_inst12": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf12_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ] - } - }, - "ibuf_inst13": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf13_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 3, - "msb": 3 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 3, - "msb": 3 - } - ] - } - }, - "ibuf_inst14": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf14_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 4, - "msb": 4 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 4, - "msb": 4 - } - ] - } - }, - "ibuf_inst15": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf15_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 5, - "msb": 5 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 5, - "msb": 5 - } - ] - } - }, - "ibuf_inst16": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf16_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "obuft_oe", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "ibuf_obuft_oe", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst2": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf2_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ] - } - }, - "ibuf_inst3": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf3_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ] - } - }, - "ibuf_inst4": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf4_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "rst", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "rst_i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst5": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf5_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "mux1_sel", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_mux1_sel", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst6": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf6_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "mux2_sel", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_mux2_sel", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst7": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf7_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "P", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "p_ibuf", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst8": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf8_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "G", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "g_ibuf", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst9": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf9_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_we", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "ram_inst.we", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "o_buff_inst": { - "module": "O_BUF", - "ports": { - "I": [ - { - "Actual": "ram_out", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "Q", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "obuft_inst": { - "module": "O_BUFT", - "ports": { - "I": [ - { - "Actual": "ff_inst1.Q", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "buft_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "T": [ - { - "Actual": "ibuf_obuft_oe", - "lsb": 0, - "msb": 0 - } - ] - } - } - } -} diff --git a/design_edit/Tests/primitive_example_design_1/gold/io_config.json b/design_edit/Tests/primitive_example_design_1/gold/io_config.json deleted file mode 100644 index 9d1b866f4..000000000 --- a/design_edit/Tests/primitive_example_design_1/gold/io_config.json +++ /dev/null @@ -1,678 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " IN: \\clk (offset: 0, width: 1)", - " Connected \\clk to \\I_BUF ($iopadmap$primitive_example_design_1.clk)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\G (offset: 0, width: 1)", - " Connected \\G to \\I_BUF ($iopadmap$primitive_example_design_1.G)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\P (offset: 0, width: 1)", - " Connected \\P to \\I_BUF ($iopadmap$primitive_example_design_1.P)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " OUT: \\Q (offset: 0, width: 1)", - " Connected \\Q to \\O_BUF ($iopadmap$primitive_example_design_1.Q)", - " OUT: \\buft_out (offset: 0, width: 1)", - " Connected \\buft_out to \\O_BUF ($iopadmap$primitive_example_design_1.buft_out)", - " IN: \\ibuf0_en (offset: 0, width: 1)", - " Connected \\ibuf0_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf0_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf10_en (offset: 0, width: 1)", - " Connected \\ibuf10_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf10_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf11_en (offset: 0, width: 1)", - " Connected \\ibuf11_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf11_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf12_en (offset: 0, width: 1)", - " Connected \\ibuf12_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf12_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf13_en (offset: 0, width: 1)", - " Connected \\ibuf13_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf13_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf14_en (offset: 0, width: 1)", - " Connected \\ibuf14_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf14_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf15_en (offset: 0, width: 1)", - " Connected \\ibuf15_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf15_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf16_en (offset: 0, width: 1)", - " Connected \\ibuf16_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf16_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf1_en (offset: 0, width: 1)", - " Connected \\ibuf1_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf1_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf2_en (offset: 0, width: 1)", - " Connected \\ibuf2_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf2_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf3_en (offset: 0, width: 1)", - " Connected \\ibuf3_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf3_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf4_en (offset: 0, width: 1)", - " Connected \\ibuf4_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf4_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf5_en (offset: 0, width: 1)", - " Connected \\ibuf5_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf5_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf6_en (offset: 0, width: 1)", - " Connected \\ibuf6_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf6_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf7_en (offset: 0, width: 1)", - " Connected \\ibuf7_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf7_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf8_en (offset: 0, width: 1)", - " Connected \\ibuf8_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf8_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf9_en (offset: 0, width: 1)", - " Connected \\ibuf9_en to \\I_BUF ($iopadmap$primitive_example_design_1.ibuf9_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\in (offset: 0, width: 3)", - " Connected \\in [0] to \\I_BUF ($iopadmap$primitive_example_design_1.in)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\in [1] to \\I_BUF ($iopadmap$primitive_example_design_1.in_1)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\in [2] to \\I_BUF ($iopadmap$primitive_example_design_1.in_2)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\mux1_sel (offset: 0, width: 1)", - " Connected \\mux1_sel to \\I_BUF ($iopadmap$primitive_example_design_1.mux1_sel)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\mux2_sel (offset: 0, width: 1)", - " Connected \\mux2_sel to \\I_BUF ($iopadmap$primitive_example_design_1.mux2_sel)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\obuft_oe (offset: 0, width: 1)", - " Connected \\obuft_oe to \\I_BUF ($iopadmap$primitive_example_design_1.obuft_oe)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ram_addr (offset: 0, width: 6)", - " Connected \\ram_addr [0] to \\I_BUF ($iopadmap$primitive_example_design_1.ram_addr)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [1] to \\I_BUF ($iopadmap$primitive_example_design_1.ram_addr_1)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [2] to \\I_BUF ($iopadmap$primitive_example_design_1.ram_addr_2)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [3] to \\I_BUF ($iopadmap$primitive_example_design_1.ram_addr_3)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [4] to \\I_BUF ($iopadmap$primitive_example_design_1.ram_addr_4)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [5] to \\I_BUF ($iopadmap$primitive_example_design_1.ram_addr_5)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ram_we (offset: 0, width: 1)", - " Connected \\ram_we to \\I_BUF ($iopadmap$primitive_example_design_1.ram_we)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\rst (offset: 0, width: 1)", - " Connected \\rst to \\I_BUF ($iopadmap$primitive_example_design_1.rst)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Trace Clock Buffer", - " IN Port: \\clk", - " Connected $auto$clkbufmap.cc:261:execute$663", - " Additional Connection: $auto$clkbufmap.cc:262:execute$664", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.clk", - "linked_object" : "clk", - "location" : "", - "connectivity" : { - "I" : "clk", - "O" : "$iopadmap$clk" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk_#0", - "linked_object" : "clk", - "location" : "", - "connectivity" : { - "I" : "$iopadmap$clk", - "O" : "$auto$clkbufmap.cc:262:execute$664" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:261:execute$663", - "linked_object" : "clk", - "location" : "", - "connectivity" : { - "I" : "$auto$clkbufmap.cc:262:execute$664", - "O" : "$auto$clkbufmap.cc:294:execute$665" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.G", - "linked_object" : "G", - "location" : "", - "connectivity" : { - "I" : "G", - "O" : "$iopadmap$G" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.P", - "linked_object" : "P", - "location" : "", - "connectivity" : { - "I" : "P", - "O" : "$iopadmap$P" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_1.Q", - "linked_object" : "Q", - "location" : "", - "connectivity" : { - "I" : "$iopadmap$Q", - "O" : "Q" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_1.buft_out", - "linked_object" : "buft_out", - "location" : "", - "connectivity" : { - "I" : "$iopadmap$buft_out", - "O" : "buft_out" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf0_en", - "linked_object" : "ibuf0_en", - "location" : "", - "connectivity" : { - "I" : "ibuf0_en", - "O" : "$iopadmap$ibuf0_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf10_en", - "linked_object" : "ibuf10_en", - "location" : "", - "connectivity" : { - "I" : "ibuf10_en", - "O" : "$iopadmap$ibuf10_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf11_en", - "linked_object" : "ibuf11_en", - "location" : "", - "connectivity" : { - "I" : "ibuf11_en", - "O" : "$iopadmap$ibuf11_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf12_en", - "linked_object" : "ibuf12_en", - "location" : "", - "connectivity" : { - "I" : "ibuf12_en", - "O" : "$iopadmap$ibuf12_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf13_en", - "linked_object" : "ibuf13_en", - "location" : "", - "connectivity" : { - "I" : "ibuf13_en", - "O" : "$iopadmap$ibuf13_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf14_en", - "linked_object" : "ibuf14_en", - "location" : "", - "connectivity" : { - "I" : "ibuf14_en", - "O" : "$iopadmap$ibuf14_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf15_en", - "linked_object" : "ibuf15_en", - "location" : "", - "connectivity" : { - "I" : "ibuf15_en", - "O" : "$iopadmap$ibuf15_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf16_en", - "linked_object" : "ibuf16_en", - "location" : "", - "connectivity" : { - "I" : "ibuf16_en", - "O" : "$iopadmap$ibuf16_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf1_en", - "linked_object" : "ibuf1_en", - "location" : "", - "connectivity" : { - "I" : "ibuf1_en", - "O" : "$iopadmap$ibuf1_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf2_en", - "linked_object" : "ibuf2_en", - "location" : "", - "connectivity" : { - "I" : "ibuf2_en", - "O" : "$iopadmap$ibuf2_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf3_en", - "linked_object" : "ibuf3_en", - "location" : "", - "connectivity" : { - "I" : "ibuf3_en", - "O" : "$iopadmap$ibuf3_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf4_en", - "linked_object" : "ibuf4_en", - "location" : "", - "connectivity" : { - "I" : "ibuf4_en", - "O" : "$iopadmap$ibuf4_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf5_en", - "linked_object" : "ibuf5_en", - "location" : "", - "connectivity" : { - "I" : "ibuf5_en", - "O" : "$iopadmap$ibuf5_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf6_en", - "linked_object" : "ibuf6_en", - "location" : "", - "connectivity" : { - "I" : "ibuf6_en", - "O" : "$iopadmap$ibuf6_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf7_en", - "linked_object" : "ibuf7_en", - "location" : "", - "connectivity" : { - "I" : "ibuf7_en", - "O" : "$iopadmap$ibuf7_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf8_en", - "linked_object" : "ibuf8_en", - "location" : "", - "connectivity" : { - "I" : "ibuf8_en", - "O" : "$iopadmap$ibuf8_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ibuf9_en", - "linked_object" : "ibuf9_en", - "location" : "", - "connectivity" : { - "I" : "ibuf9_en", - "O" : "$iopadmap$ibuf9_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.in", - "linked_object" : "in [0]", - "location" : "", - "connectivity" : { - "I" : "in [0]", - "O" : "$iopadmap$in [0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.in_1", - "linked_object" : "in [1]", - "location" : "", - "connectivity" : { - "I" : "in [1]", - "O" : "$iopadmap$in [1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.in_2", - "linked_object" : "in [2]", - "location" : "", - "connectivity" : { - "I" : "in [2]", - "O" : "$iopadmap$in [2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.mux1_sel", - "linked_object" : "mux1_sel", - "location" : "", - "connectivity" : { - "I" : "mux1_sel", - "O" : "$iopadmap$mux1_sel" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.mux2_sel", - "linked_object" : "mux2_sel", - "location" : "", - "connectivity" : { - "I" : "mux2_sel", - "O" : "$iopadmap$mux2_sel" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.obuft_oe", - "linked_object" : "obuft_oe", - "location" : "", - "connectivity" : { - "I" : "obuft_oe", - "O" : "$iopadmap$obuft_oe" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ram_addr", - "linked_object" : "ram_addr [0]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [0]", - "O" : "$iopadmap$ram_addr [0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ram_addr_1", - "linked_object" : "ram_addr [1]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [1]", - "O" : "$iopadmap$ram_addr [1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ram_addr_2", - "linked_object" : "ram_addr [2]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [2]", - "O" : "$iopadmap$ram_addr [2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ram_addr_3", - "linked_object" : "ram_addr [3]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [3]", - "O" : "$iopadmap$ram_addr [3]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ram_addr_4", - "linked_object" : "ram_addr [4]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [4]", - "O" : "$iopadmap$ram_addr [4]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ram_addr_5", - "linked_object" : "ram_addr [5]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [5]", - "O" : "$iopadmap$ram_addr [5]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.ram_we", - "linked_object" : "ram_we", - "location" : "", - "connectivity" : { - "I" : "ram_we", - "O" : "$iopadmap$ram_we" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_1.rst", - "linked_object" : "rst", - "location" : "", - "connectivity" : { - "I" : "rst", - "O" : "$iopadmap$rst" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - } - ] -} diff --git a/design_edit/Tests/primitive_example_design_1/gold/primitive_example_design_1_post_synth.eblif b/design_edit/Tests/primitive_example_design_1/gold/primitive_example_design_1_post_synth.eblif deleted file mode 100644 index c61c0aee9..000000000 --- a/design_edit/Tests/primitive_example_design_1/gold/primitive_example_design_1_post_synth.eblif +++ /dev/null @@ -1,93 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_primitive_example_design_1 -.inputs i_buf_out[0] i_buf_out[1] i_buf_out[2] clk_buf_out rst_i_buf_out i_buf_mux1_sel i_buf_mux2_sel p_ibuf g_ibuf ram_inst.addr[0] ram_inst.addr[1] ram_inst.addr[2] ram_inst.addr[3] ram_inst.addr[4] ram_inst.addr[5] $iopadmap$clk ram_inst.we -.outputs ram_out $auto$clkbufmap.cc:262:execute$664 ff_inst1.Q -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:294:execute$665 D=ram_inst.we E=$true Q=$auto$memory_dff.cc:778:handle_rd_port_addr$44 R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:294:execute$665 D=Q_buff_in E=$true Q=$auto$memory_dff.cc:780:handle_rd_port_addr$46[0] R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:294:execute$665 D=$abc$341$li2_li2 E=$true Q=ff_inst1.Q R=$true -.subckt LUT3 A[0]=i_buf_out[2] A[1]=i_buf_out[0] A[2]=i_buf_out[1] Y=lut_out -.param INIT_VALUE 00111110 -.subckt LUT2 A[0]=dffnre_out A[1]=i_buf_mux1_sel Y=out -.param INIT_VALUE 1001 -.subckt LUT2 A[0]=$iopadmap$rst A[1]=ff_inst1.D Y=$abc$341$li2_li2 -.param INIT_VALUE 0100 -.subckt LUT3 A[0]=acc_out A[1]=ff_inst1.D A[2]=i_buf_mux2_sel Y=mux2_out -.param INIT_VALUE 11001010 -.subckt LUT3 A[0]=$auto$memory_dff.cc:780:handle_rd_port_addr$46[0] A[1]=$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] A[2]=$auto$memory_dff.cc:778:handle_rd_port_addr$44 Y=ram_out -.param INIT_VALUE 10101100 -.subckt LUT1 A=ram_inst.we Y=$abc$324$auto$rtlil.cc:2384:Not$55 -.param INIT_VALUE 01 -.subckt CARRY_CHAIN CIN=out COUT=acc_out G=g_ibuf O=ff_inst1.D P=p_ibuf -.subckt DFFRE C=clk_buf_out D=mux2_out E=$true Q=Q_buff_in R=rst_i_buf_out -.subckt DFFNRE C=clk_buf_out D=lut_out E=$true Q=dffnre_out R=rst_i_buf_out -.subckt TDP_RAM18KX2 ADDR_A1[0]=$false ADDR_A1[1]=$false ADDR_A1[2]=$false ADDR_A1[3]=ram_inst.addr[0] ADDR_A1[4]=ram_inst.addr[1] ADDR_A1[5]=ram_inst.addr[2] ADDR_A1[6]=ram_inst.addr[3] ADDR_A1[7]=ram_inst.addr[4] ADDR_A1[8]=ram_inst.addr[5] ADDR_A1[9]=$false ADDR_A1[10]=$false ADDR_A1[11]=$false ADDR_A1[12]=$false ADDR_A1[13]=$false ADDR_A2[0]=$undef ADDR_A2[1]=$undef ADDR_A2[2]=$undef ADDR_A2[3]=$undef ADDR_A2[4]=$undef ADDR_A2[5]=$undef ADDR_A2[6]=$undef ADDR_A2[7]=$undef ADDR_A2[8]=$undef ADDR_A2[9]=$undef ADDR_A2[10]=$undef ADDR_A2[11]=$undef ADDR_A2[12]=$undef ADDR_A2[13]=$undef ADDR_B1[0]=$false ADDR_B1[1]=$false ADDR_B1[2]=$false ADDR_B1[3]=ram_inst.addr[0] ADDR_B1[4]=ram_inst.addr[1] ADDR_B1[5]=ram_inst.addr[2] ADDR_B1[6]=ram_inst.addr[3] ADDR_B1[7]=ram_inst.addr[4] ADDR_B1[8]=ram_inst.addr[5] ADDR_B1[9]=$false ADDR_B1[10]=$false ADDR_B1[11]=$false ADDR_B1[12]=$false ADDR_B1[13]=$false ADDR_B2[0]=$undef ADDR_B2[1]=$undef ADDR_B2[2]=$undef ADDR_B2[3]=$undef ADDR_B2[4]=$undef ADDR_B2[5]=$undef ADDR_B2[6]=$undef ADDR_B2[7]=$undef ADDR_B2[8]=$undef ADDR_B2[9]=$undef ADDR_B2[10]=$undef ADDR_B2[11]=$undef ADDR_B2[12]=$undef ADDR_B2[13]=$undef BE_A1[0]=$false BE_A1[1]=$false BE_A2[0]=$false BE_A2[1]=$false BE_B1[0]=ram_inst.we BE_B1[1]=$false BE_B2[0]=$undef BE_B2[1]=$undef CLK_A1=$auto$clkbufmap.cc:294:execute$665 CLK_A2=$undef CLK_B1=$auto$clkbufmap.cc:294:execute$665 CLK_B2=$undef RDATA_A1[0]=$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] RDATA_A1[1]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[1] RDATA_A1[2]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[2] RDATA_A1[3]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[3] RDATA_A1[4]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[4] RDATA_A1[5]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[5] RDATA_A1[6]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[6] RDATA_A1[7]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[7] RDATA_A1[8]=$auto$memory_libmap.cc:1890:emit_port$56[8] RDATA_A1[9]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[9] RDATA_A1[10]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[10] RDATA_A1[11]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[11] RDATA_A1[12]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[12] RDATA_A1[13]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[13] RDATA_A1[14]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[14] RDATA_A1[15]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[15] RDATA_A2[0]=$techmap76\ram_inst.ram.0.0.C1DATA RDATA_A2[1]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[1] RDATA_A2[2]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[2] RDATA_A2[3]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[3] RDATA_A2[4]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[4] RDATA_A2[5]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[5] RDATA_A2[6]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[6] RDATA_A2[7]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[7] RDATA_A2[8]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[8] RDATA_A2[9]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[9] RDATA_A2[10]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[10] RDATA_A2[11]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[11] RDATA_A2[12]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[12] RDATA_A2[13]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[13] RDATA_A2[14]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[14] RDATA_A2[15]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[15] RDATA_B1[0]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[0] RDATA_B1[1]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[1] RDATA_B1[2]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[2] RDATA_B1[3]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[3] RDATA_B1[4]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[4] RDATA_B1[5]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[5] RDATA_B1[6]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[6] RDATA_B1[7]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[7] RDATA_B1[8]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[8] RDATA_B1[9]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[9] RDATA_B1[10]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[10] RDATA_B1[11]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[11] RDATA_B1[12]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[12] RDATA_B1[13]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[13] RDATA_B1[14]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[14] RDATA_B1[15]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[15] RDATA_B2[0]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[0] RDATA_B2[1]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[1] RDATA_B2[2]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[2] RDATA_B2[3]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[3] RDATA_B2[4]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[4] RDATA_B2[5]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[5] RDATA_B2[6]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[6] RDATA_B2[7]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[7] RDATA_B2[8]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[8] RDATA_B2[9]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[9] RDATA_B2[10]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[10] RDATA_B2[11]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[11] RDATA_B2[12]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[12] RDATA_B2[13]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[13] RDATA_B2[14]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[14] RDATA_B2[15]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[15] REN_A1=$abc$324$auto$rtlil.cc:2384:Not$55 REN_A2=$undef REN_B1=$false REN_B2=$false RPARITY_A1[0]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[16] RPARITY_A1[1]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[17] RPARITY_A2[0]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[16] RPARITY_A2[1]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[17] RPARITY_B1[0]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[16] RPARITY_B1[1]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[17] RPARITY_B2[0]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[16] RPARITY_B2[1]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[17] WDATA_A1[0]=$undef WDATA_A1[1]=$undef WDATA_A1[2]=$undef WDATA_A1[3]=$undef WDATA_A1[4]=$undef WDATA_A1[5]=$undef WDATA_A1[6]=$undef WDATA_A1[7]=$undef WDATA_A1[8]=$undef WDATA_A1[9]=$undef WDATA_A1[10]=$undef WDATA_A1[11]=$undef WDATA_A1[12]=$undef WDATA_A1[13]=$undef WDATA_A1[14]=$undef WDATA_A1[15]=$undef WDATA_A2[0]=$undef WDATA_A2[1]=$undef WDATA_A2[2]=$undef WDATA_A2[3]=$undef WDATA_A2[4]=$undef WDATA_A2[5]=$undef WDATA_A2[6]=$undef WDATA_A2[7]=$undef WDATA_A2[8]=$undef WDATA_A2[9]=$undef WDATA_A2[10]=$undef WDATA_A2[11]=$undef WDATA_A2[12]=$undef WDATA_A2[13]=$undef WDATA_A2[14]=$undef WDATA_A2[15]=$undef WDATA_B1[0]=Q_buff_in WDATA_B1[1]=$false WDATA_B1[2]=$false WDATA_B1[3]=$false WDATA_B1[4]=$false WDATA_B1[5]=$false WDATA_B1[6]=$false WDATA_B1[7]=$false WDATA_B1[8]=$undef WDATA_B1[9]=$undef WDATA_B1[10]=$undef WDATA_B1[11]=$undef WDATA_B1[12]=$undef WDATA_B1[13]=$undef WDATA_B1[14]=$undef WDATA_B1[15]=$undef WDATA_B2[0]=$undef WDATA_B2[1]=$undef WDATA_B2[2]=$undef WDATA_B2[3]=$undef WDATA_B2[4]=$undef WDATA_B2[5]=$undef WDATA_B2[6]=$undef WDATA_B2[7]=$undef WDATA_B2[8]=$undef WDATA_B2[9]=$undef WDATA_B2[10]=$undef WDATA_B2[11]=$undef WDATA_B2[12]=$undef WDATA_B2[13]=$undef WDATA_B2[14]=$undef WDATA_B2[15]=$undef WEN_A1=$false WEN_A2=$false WEN_B1=ram_inst.we WEN_B2=$undef WPARITY_A1[0]=$undef WPARITY_A1[1]=$undef WPARITY_A2[0]=$undef WPARITY_A2[1]=$undef WPARITY_B1[0]=$undef WPARITY_B1[1]=$undef WPARITY_B2[0]=$undef WPARITY_B2[1]=$undef -.param INIT1 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-.param READ_WIDTH_A1 00000000000000000000000000001001 -.param READ_WIDTH_A2 00000000000000000000000000000001 -.param READ_WIDTH_B1 00000000000000000000000000001001 -.param READ_WIDTH_B2 00000000000000000000000000000001 -.param WRITE_WIDTH_A1 00000000000000000000000000001001 -.param WRITE_WIDTH_A2 00000000000000000000000000000001 -.param WRITE_WIDTH_B1 00000000000000000000000000001001 -.param WRITE_WIDTH_B2 00000000000000000000000000000001 -.names $techmap76\ram_inst.ram.0.0.C1DATA $techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[0] -1 1 -.names $abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[0] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[1] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[1] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[2] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[2] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[3] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[3] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[4] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[4] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[5] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[5] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[6] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[6] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[7] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[7] -1 1 -.names $auto$memory_libmap.cc:1890:emit_port$56[8] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[8] -1 1 -.names $abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] $auto$memory_libmap.cc:1890:emit_port$56[0] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[1] $auto$memory_libmap.cc:1890:emit_port$56[1] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[2] $auto$memory_libmap.cc:1890:emit_port$56[2] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[3] $auto$memory_libmap.cc:1890:emit_port$56[3] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[4] $auto$memory_libmap.cc:1890:emit_port$56[4] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[5] $auto$memory_libmap.cc:1890:emit_port$56[5] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[6] $auto$memory_libmap.cc:1890:emit_port$56[6] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[7] $auto$memory_libmap.cc:1890:emit_port$56[7] -1 1 -.names $abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] $auto$memory_dff.cc:785:handle_rd_port_addr$50[0] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[1] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[2] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[3] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[4] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[5] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[6] -1 1 -.names $iopadmap$clk $auto$clkbufmap.cc:262:execute$664 -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_1/gold/primitive_example_design_1_post_synth.v b/design_edit/Tests/primitive_example_design_1/gold/primitive_example_design_1_post_synth.v deleted file mode 100644 index 14059e16a..000000000 --- a/design_edit/Tests/primitive_example_design_1/gold/primitive_example_design_1_post_synth.v +++ /dev/null @@ -1,513 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_primitive_example_design_1(i_buf_out, clk_buf_out, rst_i_buf_out, i_buf_mux1_sel, i_buf_mux2_sel, p_ibuf, g_ibuf, ram_out, _097_, \ram_inst.addr , _062_, \ram_inst.we , \ff_inst1.Q ); - input _062_; - output _097_; - input clk_buf_out; - output \ff_inst1.Q ; - input g_ibuf; - input i_buf_mux1_sel; - input i_buf_mux2_sel; - input [2:0] i_buf_out; - input p_ibuf; - input [5:0] \ram_inst.addr ; - input \ram_inst.we ; - output ram_out; - input rst_i_buf_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _000_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _001_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _002_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _003_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _004_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _005_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _006_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _007_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _008_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _009_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _010_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _011_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _012_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _013_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _014_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _015_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _016_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _017_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _018_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _019_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire _020_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire _021_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire _022_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _023_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _024_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _025_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _026_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _027_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _028_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _029_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _030_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _031_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _032_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _033_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _034_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _035_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _036_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _037_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _038_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _039_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _040_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _041_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _042_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _043_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _044_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _045_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _046_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _047_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _048_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _049_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _050_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _051_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _052_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _053_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _054_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _055_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _056_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _057_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _058_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire _059_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire _060_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire _061_; - wire _062_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _063_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _064_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _065_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _066_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _067_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _068_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _069_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _070_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _071_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _072_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _073_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _074_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _075_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _076_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _077_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _078_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _079_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _080_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _081_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _082_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _083_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _084_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _085_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _086_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _087_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _088_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _089_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _090_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _091_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire _092_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire _093_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire _094_; - wire _095_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _096_; - wire _097_; - wire _098_; - wire _099_; - wire _100_; - (* keep = 32'h00000001 *) - wire _101_; - (* keep = 32'h00000001 *) - (* unused_bits = "1 2 3 4 5 6 7" *) - wire [7:0] _102_; - (* unused_bits = "1 2 3 4 5 6 7" *) - wire [7:0] _103_; - (* unused_bits = "1 2 3 4 5 6 7 8" *) - wire [8:0] _104_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:461.28-461.34" *) - (* unused_bits = "0" *) - wire _105_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:498.14-498.27" *) - (* unused_bits = "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _106_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:500.14-500.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _107_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:499.14-499.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _108_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:501.14-501.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _109_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _110_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] _111_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire _112_; - (* src = "./rtl/primitive_example_design_1.v:21.10-21.19" *) - wire Q_buff_in; - (* src = "./rtl/primitive_example_design_1.v:19.18-19.25" *) - wire acc_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _113_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] _114_; - (* src = "./rtl/primitive_example_design_1.v:14.21-14.32" *) - (* src = "./rtl/primitive_example_design_1.v:14.21-14.32" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_1.v:18.10-18.20" *) - wire dffnre_out; - (* hdlname = "ff_inst1 D" *) - (* src = "./rtl/primitive_example_design_1.v:48.15-48.66|./rtl/primitive_example_design_1.v:79.11-79.12" *) - wire \ff_inst1.D ; - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:48.15-48.66|./rtl/primitive_example_design_1.v:80.16-80.17" *) - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:48.15-48.66|./rtl/primitive_example_design_1.v:80.16-80.17" *) - wire \ff_inst1.Q ; - (* src = "./rtl/primitive_example_design_1.v:17.21-17.27" *) - (* src = "./rtl/primitive_example_design_1.v:17.21-17.27" *) - wire g_ibuf; - (* src = "./rtl/primitive_example_design_1.v:16.24-16.38" *) - (* src = "./rtl/primitive_example_design_1.v:16.24-16.38" *) - wire i_buf_mux1_sel; - (* src = "./rtl/primitive_example_design_1.v:16.39-16.53" *) - (* src = "./rtl/primitive_example_design_1.v:16.39-16.53" *) - wire i_buf_mux2_sel; - (* src = "./rtl/primitive_example_design_1.v:12.16-12.25" *) - (* src = "./rtl/primitive_example_design_1.v:12.16-12.25" *) - wire [2:0] i_buf_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _115_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _116_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] _117_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _118_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] _119_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _120_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _121_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] _122_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _123_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _124_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _125_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _126_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _127_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _128_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _129_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _130_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _131_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _132_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire _133_; - (* src = "./rtl/primitive_example_design_1.v:15.10-15.17" *) - wire lut_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire _134_; - (* src = "./rtl/primitive_example_design_1.v:20.10-20.18" *) - wire mux2_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _135_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire _136_; - (* src = "./rtl/primitive_example_design_1.v:17.10-17.13" *) - wire out; - (* src = "./rtl/primitive_example_design_1.v:17.14-17.20" *) - (* src = "./rtl/primitive_example_design_1.v:17.14-17.20" *) - wire p_ibuf; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _137_; - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:94.27-94.31" *) - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:94.27-94.31" *) - wire [5:0] \ram_inst.addr ; - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:95.8-95.10" *) - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:95.8-95.10" *) - wire \ram_inst.we ; - (* src = "./rtl/primitive_example_design_1.v:22.10-22.17" *) - (* src = "./rtl/primitive_example_design_1.v:22.10-22.17" *) - wire ram_out; - wire _138_; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire _139_; - (* src = "./rtl/primitive_example_design_1.v:16.10-16.23" *) - (* src = "./rtl/primitive_example_design_1.v:16.10-16.23" *) - wire rst_i_buf_out; - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) - LUT1 #( - .INIT_VALUE(2'h1) - ) _140_ ( - .Y(_099_), - .A(\ram_inst.we ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h9) - ) _141_ ( - .Y(out), - .A({ i_buf_mux1_sel, dffnre_out }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:58.17-58.93" *) - CARRY_CHAIN carry_chain_inst ( - .CIN(out), - .COUT(acc_out), - .G(g_ibuf), - .O(\ff_inst1.D ), - .P(p_ibuf) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _142_ ( - .C(_095_), - .D(\ram_inst.we ), - .E(1'h1), - .Q(_101_), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:54.11-54.90" *) - DFFRE ff_inst ( - .C(clk_buf_out), - .D(mux2_out), - .E(1'h1), - .Q(Q_buff_in), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:44.12-44.92" *) - DFFNRE ffn_inst ( - .C(clk_buf_out), - .D(lut_out), - .E(1'h1), - .Q(dffnre_out), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _143_ ( - .C(_095_), - .D(Q_buff_in), - .E(1'h1), - .Q(_102_[0]), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _144_ ( - .C(_095_), - .D(_100_), - .E(1'h1), - .Q(\ff_inst1.Q ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) _145_ ( - .Y(_100_), - .A({ \ff_inst1.D , _138_ }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'hca) - ) _146_ ( - .Y(mux2_out), - .A({ i_buf_mux2_sel, \ff_inst1.D , acc_out }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'hac) - ) _147_ ( - .Y(ram_out), - .A({ _101_, _098_, _102_[0] }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h3e) - ) _148_ ( - .Y(lut_out), - .A({ i_buf_out[1:0], i_buf_out[2] }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:645.7-684.2" *) - TDP_RAM18KX2 #( - .INIT1(16384'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT1_PARITY(2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT2(16384'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT2_PARITY(2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .READ_WIDTH_A1(32'h00000009), - .READ_WIDTH_A2(32'sh00000001), - .READ_WIDTH_B1(32'h00000009), - .READ_WIDTH_B2(32'sh00000001), - .WRITE_WIDTH_A1(32'h00000009), - .WRITE_WIDTH_A2(32'sh00000001), - .WRITE_WIDTH_B1(32'h00000009), - .WRITE_WIDTH_B2(32'sh00000001) - ) \ram_inst.ram.0.0 ( - .ADDR_A1({ 5'h00, \ram_inst.addr , 3'h0 }), - .ADDR_A2(14'hxxxx), - .ADDR_B1({ 5'h00, \ram_inst.addr , 3'h0 }), - .ADDR_B2(14'hxxxx), - .BE_A1(2'h0), - .BE_A2(2'h0), - .BE_B1({ 1'h0, \ram_inst.we }), - .BE_B2(2'hx), - .CLK_A1(_095_), - .CLK_A2(1'hx), - .CLK_B1(_095_), - .CLK_B2(1'hx), - .RDATA_A1({ _106_[15:9], _104_[8], _103_[7:1], _098_ }), - .RDATA_A2({ _107_[15:1], _105_ }), - .RDATA_B1(_108_[15:0]), - .RDATA_B2(_109_[15:0]), - .REN_A1(_099_), - .REN_A2(1'hx), - .REN_B1(1'h0), - .REN_B2(1'h0), - .RPARITY_A1(_106_[17:16]), - .RPARITY_A2(_107_[17:16]), - .RPARITY_B1(_108_[17:16]), - .RPARITY_B2(_109_[17:16]), - .WDATA_A1(16'hxxxx), - .WDATA_A2(16'hxxxx), - .WDATA_B1({ 15'bxxxxxxxx0000000, Q_buff_in }), - .WDATA_B2(16'hxxxx), - .WEN_A1(1'h0), - .WEN_A2(1'h0), - .WEN_B1(\ram_inst.we ), - .WEN_B2(1'hx), - .WPARITY_A1(2'hx), - .WPARITY_A2(2'hx), - .WPARITY_B1(2'hx), - .WPARITY_B2(2'hx) - ); - assign _107_[0] = _105_; - assign _106_[8:0] = { _104_[8], _103_[7:1], _098_ }; - assign _104_[7:0] = { _103_[7:1], _098_ }; - assign _103_[0] = _098_; - assign _102_[6:1] = { _102_[7], _102_[7], _102_[7], _102_[7], _102_[7], _102_[7] }; - assign _097_ = _062_; -endmodule diff --git a/design_edit/Tests/primitive_example_design_1/gold/wrapper_primitive_example_design_1_post_synth.eblif b/design_edit/Tests/primitive_example_design_1/gold/wrapper_primitive_example_design_1_post_synth.eblif deleted file mode 100644 index fcc8ba77d..000000000 --- a/design_edit/Tests/primitive_example_design_1/gold/wrapper_primitive_example_design_1_post_synth.eblif +++ /dev/null @@ -1,112 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model interface_primitive_example_design_1 -.inputs clk in[0] in[1] in[2] rst mux1_sel mux2_sel P G ram_addr[0] ram_addr[1] ram_addr[2] ram_addr[3] ram_addr[4] ram_addr[5] ram_we obuft_oe ibuf0_en ibuf1_en ibuf2_en ibuf3_en ibuf4_en ibuf5_en ibuf6_en ibuf7_en ibuf8_en ibuf9_en ibuf10_en ibuf11_en ibuf12_en ibuf13_en ibuf14_en ibuf15_en ibuf16_en ram_out $auto$clkbufmap.cc:262:execute$664 ff_inst1.Q -.outputs Q buft_out i_buf_out[0] i_buf_out[1] i_buf_out[2] clk_buf_out rst_i_buf_out i_buf_mux1_sel i_buf_mux2_sel p_ibuf g_ibuf ram_inst.addr[0] ram_inst.addr[1] ram_inst.addr[2] ram_inst.addr[3] ram_inst.addr[4] ram_inst.addr[5] $iopadmap$clk ram_inst.we -.names $false -.names $true -1 -.names $undef -.subckt CLK_BUF I=$auto$clkbufmap.cc:262:execute$664 O=$auto$clkbufmap.cc:294:execute$665 -.subckt CLK_BUF I=$auto$clkbufmap.cc:262:execute$667 O=clk_buf_out -.subckt I_BUF EN=$true I=G O=$iopadmap$G -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=P O=$iopadmap$P -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$iopadmap$Q O=Q -.subckt O_BUF I=$iopadmap$buft_out O=buft_out -.subckt I_BUF EN=$true I=clk O=$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf0_en O=$iopadmap$ibuf0_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf10_en O=$iopadmap$ibuf10_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf11_en O=$iopadmap$ibuf11_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf12_en O=$iopadmap$ibuf12_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf13_en O=$iopadmap$ibuf13_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf14_en O=$iopadmap$ibuf14_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf15_en O=$iopadmap$ibuf15_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf16_en O=$iopadmap$ibuf16_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf1_en O=$iopadmap$ibuf1_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf2_en O=$iopadmap$ibuf2_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf3_en O=$iopadmap$ibuf3_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf4_en O=$iopadmap$ibuf4_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf5_en O=$iopadmap$ibuf5_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf6_en O=$iopadmap$ibuf6_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf7_en O=$iopadmap$ibuf7_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf8_en O=$iopadmap$ibuf8_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf9_en O=$iopadmap$ibuf9_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=in[0] O=$iopadmap$in[0] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=in[1] O=$iopadmap$in[1] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=in[2] O=$iopadmap$in[2] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=mux1_sel O=$iopadmap$mux1_sel -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=mux2_sel O=$iopadmap$mux2_sel -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=obuft_oe O=$iopadmap$obuft_oe -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[0] O=$iopadmap$ram_addr[0] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[1] O=$iopadmap$ram_addr[1] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[2] O=$iopadmap$ram_addr[2] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[3] O=$iopadmap$ram_addr[3] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[4] O=$iopadmap$ram_addr[4] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[5] O=$iopadmap$ram_addr[5] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_we O=$iopadmap$ram_we -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=rst O=$iopadmap$rst -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$iopadmap$ibuf0_en I=$auto$clkbufmap.cc:294:execute$665 O=$auto$clkbufmap.cc:262:execute$667 -.subckt I_BUF EN=$iopadmap$ibuf1_en I=$iopadmap$in[0] O=i_buf_out[0] -.subckt I_BUF EN=$iopadmap$ibuf10_en I=$iopadmap$ram_addr[0] O=ram_inst.addr[0] -.subckt I_BUF EN=$iopadmap$ibuf11_en I=$iopadmap$ram_addr[1] O=ram_inst.addr[1] -.subckt I_BUF EN=$iopadmap$ibuf12_en I=$iopadmap$ram_addr[2] O=ram_inst.addr[2] -.subckt I_BUF EN=$iopadmap$ibuf13_en I=$iopadmap$ram_addr[3] O=ram_inst.addr[3] -.subckt I_BUF EN=$iopadmap$ibuf14_en I=$iopadmap$ram_addr[4] O=ram_inst.addr[4] -.subckt I_BUF EN=$iopadmap$ibuf15_en I=$iopadmap$ram_addr[5] O=ram_inst.addr[5] -.subckt I_BUF EN=$iopadmap$ibuf16_en I=$iopadmap$obuft_oe O=ibuf_obuft_oe -.subckt I_BUF EN=$iopadmap$ibuf2_en I=$iopadmap$in[1] O=i_buf_out[1] -.subckt I_BUF EN=$iopadmap$ibuf3_en I=$iopadmap$in[2] O=i_buf_out[2] -.subckt I_BUF EN=$iopadmap$ibuf4_en I=$iopadmap$rst O=rst_i_buf_out -.subckt I_BUF EN=$iopadmap$ibuf5_en I=$iopadmap$mux1_sel O=i_buf_mux1_sel -.subckt I_BUF EN=$iopadmap$ibuf6_en I=$iopadmap$mux2_sel O=i_buf_mux2_sel -.subckt I_BUF EN=$iopadmap$ibuf7_en I=$iopadmap$P O=p_ibuf -.subckt I_BUF EN=$iopadmap$ibuf8_en I=$iopadmap$G O=g_ibuf -.subckt I_BUF EN=$iopadmap$ibuf9_en I=$iopadmap$ram_we O=ram_inst.we -.subckt O_BUF I=ram_out O=$iopadmap$Q -.subckt O_BUFT I=ff_inst1.Q O=$iopadmap$buft_out T=ibuf_obuft_oe -.end - -.model primitive_example_design_1 -.inputs clk in[0] in[1] in[2] rst mux1_sel mux2_sel P G ram_addr[0] ram_addr[1] ram_addr[2] ram_addr[3] ram_addr[4] ram_addr[5] ram_we obuft_oe ibuf0_en ibuf1_en ibuf2_en ibuf3_en ibuf4_en ibuf5_en ibuf6_en ibuf7_en ibuf8_en ibuf9_en ibuf10_en ibuf11_en ibuf12_en ibuf13_en ibuf14_en ibuf15_en ibuf16_en -.outputs Q buft_out -.names $false -.names $true -1 -.names $undef -.subckt fabric_primitive_example_design_1 $auto$clkbufmap.cc:262:execute$664=$auto$clkbufmap.cc:262:execute$664 $iopadmap$clk=$iopadmap$clk clk_buf_out=clk_buf_out ff_inst1.Q=ff_inst1.Q g_ibuf=g_ibuf i_buf_mux1_sel=i_buf_mux1_sel i_buf_mux2_sel=i_buf_mux2_sel i_buf_out[0]=i_buf_out[0] i_buf_out[1]=i_buf_out[1] i_buf_out[2]=i_buf_out[2] p_ibuf=p_ibuf ram_inst.addr[0]=ram_inst.addr[0] ram_inst.addr[1]=ram_inst.addr[1] ram_inst.addr[2]=ram_inst.addr[2] ram_inst.addr[3]=ram_inst.addr[3] ram_inst.addr[4]=ram_inst.addr[4] ram_inst.addr[5]=ram_inst.addr[5] ram_inst.we=ram_inst.we ram_out=ram_out rst_i_buf_out=rst_i_buf_out -.subckt interface_primitive_example_design_1 $auto$clkbufmap.cc:262:execute$664=$auto$clkbufmap.cc:262:execute$664 $iopadmap$clk=$iopadmap$clk G=G P=P Q=Q buft_out=buft_out clk=clk clk_buf_out=clk_buf_out ff_inst1.Q=ff_inst1.Q g_ibuf=g_ibuf i_buf_mux1_sel=i_buf_mux1_sel i_buf_mux2_sel=i_buf_mux2_sel i_buf_out[0]=i_buf_out[0] i_buf_out[1]=i_buf_out[1] i_buf_out[2]=i_buf_out[2] ibuf0_en=ibuf0_en ibuf10_en=ibuf10_en ibuf11_en=ibuf11_en ibuf12_en=ibuf12_en ibuf13_en=ibuf13_en ibuf14_en=ibuf14_en ibuf15_en=ibuf15_en ibuf16_en=ibuf16_en ibuf1_en=ibuf1_en ibuf2_en=ibuf2_en ibuf3_en=ibuf3_en ibuf4_en=ibuf4_en ibuf5_en=ibuf5_en ibuf6_en=ibuf6_en ibuf7_en=ibuf7_en ibuf8_en=ibuf8_en ibuf9_en=ibuf9_en in[0]=in[0] in[1]=in[1] in[2]=in[2] mux1_sel=mux1_sel mux2_sel=mux2_sel obuft_oe=obuft_oe p_ibuf=p_ibuf ram_addr[0]=ram_addr[0] ram_addr[1]=ram_addr[1] ram_addr[2]=ram_addr[2] ram_addr[3]=ram_addr[3] ram_addr[4]=ram_addr[4] ram_addr[5]=ram_addr[5] ram_inst.addr[0]=ram_inst.addr[0] ram_inst.addr[1]=ram_inst.addr[1] ram_inst.addr[2]=ram_inst.addr[2] ram_inst.addr[3]=ram_inst.addr[3] ram_inst.addr[4]=ram_inst.addr[4] ram_inst.addr[5]=ram_inst.addr[5] ram_inst.we=ram_inst.we ram_out=ram_out ram_we=ram_we rst=rst rst_i_buf_out=rst_i_buf_out -.end diff --git a/design_edit/Tests/primitive_example_design_1/gold/wrapper_primitive_example_design_1_post_synth.v b/design_edit/Tests/primitive_example_design_1/gold/wrapper_primitive_example_design_1_post_synth.v deleted file mode 100644 index 53ca17a65..000000000 --- a/design_edit/Tests/primitive_example_design_1/gold/wrapper_primitive_example_design_1_post_synth.v +++ /dev/null @@ -1,947 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module primitive_example_design_1(clk, in, rst, Q, mux1_sel, mux2_sel, P, G, ram_addr, ram_we, buft_out, obuft_oe, ibuf0_en, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en, ibuf5_en, ibuf6_en, ibuf7_en, ibuf8_en -, ibuf9_en, ibuf10_en, ibuf11_en, ibuf12_en, ibuf13_en, ibuf14_en, ibuf15_en, ibuf16_en); - input mux1_sel; - input ibuf1_en; - input [5:0] ram_addr; - output Q; - input ibuf2_en; - input P; - input [2:0] in; - input rst; - input ibuf15_en; - input ibuf8_en; - input G; - input clk; - input ibuf4_en; - input ibuf14_en; - input ibuf16_en; - input ibuf5_en; - input ibuf6_en; - input ram_we; - input ibuf13_en; - input ibuf3_en; - output buft_out; - input ibuf9_en; - input ibuf0_en; - input mux2_sel; - input ibuf7_en; - input obuft_oe; - input ibuf12_en; - input ibuf11_en; - input ibuf10_en; - wire \$iopadmap$ibuf5_en ; - (* src = "./rtl/primitive_example_design_1.v:16.10-16.23" *) - wire rst_i_buf_out; - (* src = "./rtl/primitive_example_design_1.v:4.11-4.19" *) - (* src = "./rtl/primitive_example_design_1.v:4.11-4.19" *) - wire mux1_sel; - (* src = "./rtl/primitive_example_design_1.v:5.20-5.28" *) - (* src = "./rtl/primitive_example_design_1.v:5.20-5.28" *) - wire ibuf1_en; - wire \$iopadmap$rst ; - (* src = "./rtl/primitive_example_design_1.v:22.10-22.17" *) - wire ram_out; - wire \$iopadmap$ibuf7_en ; - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:95.8-95.10" *) - wire \ram_inst.we ; - wire \$iopadmap$Q ; - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:94.27-94.31" *) - wire [5:0] \ram_inst.addr ; - wire \$iopadmap$ibuf14_en ; - wire \$iopadmap$mux1_sel ; - (* src = "./rtl/primitive_example_design_1.v:7.17-7.25" *) - (* src = "./rtl/primitive_example_design_1.v:7.17-7.25" *) - wire [5:0] ram_addr; - wire \$iopadmap$ram_we ; - (* src = "./rtl/primitive_example_design_1.v:17.14-17.20" *) - wire p_ibuf; - (* src = "./rtl/primitive_example_design_1.v:10.12-10.13" *) - (* src = "./rtl/primitive_example_design_1.v:10.12-10.13" *) - wire Q; - (* src = "./rtl/primitive_example_design_1.v:5.29-5.37" *) - (* src = "./rtl/primitive_example_design_1.v:5.29-5.37" *) - wire ibuf2_en; - (* src = "./rtl/primitive_example_design_1.v:6.11-6.12" *) - (* src = "./rtl/primitive_example_design_1.v:6.11-6.12" *) - wire P; - wire \$auto$clkbufmap.cc:262:execute$667 ; - wire \$iopadmap$ibuf3_en ; - wire \$auto$clkbufmap.cc:294:execute$665 ; - wire \$iopadmap$ibuf9_en ; - wire [5:0] \$iopadmap$ram_addr ; - wire \$iopadmap$ibuf13_en ; - (* src = "./rtl/primitive_example_design_1.v:16.24-16.38" *) - wire i_buf_mux1_sel; - wire \$iopadmap$ibuf10_en ; - (* src = "./rtl/primitive_example_design_1.v:2.17-2.19" *) - (* src = "./rtl/primitive_example_design_1.v:2.17-2.19" *) - wire [2:0] in; - (* src = "./rtl/primitive_example_design_1.v:3.16-3.19" *) - (* src = "./rtl/primitive_example_design_1.v:3.16-3.19" *) - wire rst; - (* src = "./rtl/primitive_example_design_1.v:14.21-14.32" *) - wire clk_buf_out; - wire \$iopadmap$ibuf12_en ; - wire \$iopadmap$P ; - (* src = "./rtl/primitive_example_design_1.v:5.151-5.160" *) - (* src = "./rtl/primitive_example_design_1.v:5.151-5.160" *) - wire ibuf15_en; - (* src = "./rtl/primitive_example_design_1.v:5.83-5.91" *) - (* src = "./rtl/primitive_example_design_1.v:5.83-5.91" *) - wire ibuf8_en; - (* src = "./rtl/primitive_example_design_1.v:6.13-6.14" *) - (* src = "./rtl/primitive_example_design_1.v:6.13-6.14" *) - wire G; - (* src = "./rtl/primitive_example_design_1.v:3.11-3.14" *) - (* src = "./rtl/primitive_example_design_1.v:3.11-3.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_1.v:5.47-5.55" *) - (* src = "./rtl/primitive_example_design_1.v:5.47-5.55" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_1.v:5.141-5.150" *) - (* src = "./rtl/primitive_example_design_1.v:5.141-5.150" *) - wire ibuf14_en; - (* src = "./rtl/primitive_example_design_1.v:5.161-5.170" *) - (* src = "./rtl/primitive_example_design_1.v:5.161-5.170" *) - wire ibuf16_en; - (* src = "./rtl/primitive_example_design_1.v:5.56-5.64" *) - (* src = "./rtl/primitive_example_design_1.v:5.56-5.64" *) - wire ibuf5_en; - (* src = "./rtl/primitive_example_design_1.v:23.16-23.29" *) - wire ibuf_obuft_oe; - wire [2:0] \$iopadmap$in ; - wire \$iopadmap$ibuf11_en ; - wire \$iopadmap$ibuf8_en ; - (* src = "./rtl/primitive_example_design_1.v:5.65-5.73" *) - (* src = "./rtl/primitive_example_design_1.v:5.65-5.73" *) - wire ibuf6_en; - (* src = "./rtl/primitive_example_design_1.v:8.11-8.17" *) - (* src = "./rtl/primitive_example_design_1.v:8.11-8.17" *) - wire ram_we; - (* src = "./rtl/primitive_example_design_1.v:5.131-5.140" *) - (* src = "./rtl/primitive_example_design_1.v:5.131-5.140" *) - wire ibuf13_en; - wire \$iopadmap$obuft_oe ; - wire \$iopadmap$mux2_sel ; - (* src = "./rtl/primitive_example_design_1.v:5.38-5.46" *) - (* src = "./rtl/primitive_example_design_1.v:5.38-5.46" *) - wire ibuf3_en; - wire \$iopadmap$clk ; - (* src = "./rtl/primitive_example_design_1.v:10.14-10.22" *) - (* src = "./rtl/primitive_example_design_1.v:10.14-10.22" *) - wire buft_out; - (* src = "./rtl/primitive_example_design_1.v:5.92-5.100" *) - (* src = "./rtl/primitive_example_design_1.v:5.92-5.100" *) - wire ibuf9_en; - wire \$iopadmap$ibuf6_en ; - wire \$iopadmap$ibuf2_en ; - wire \$iopadmap$ibuf16_en ; - wire \$iopadmap$G ; - (* src = "./rtl/primitive_example_design_1.v:5.11-5.19" *) - (* src = "./rtl/primitive_example_design_1.v:5.11-5.19" *) - wire ibuf0_en; - wire \$iopadmap$buft_out ; - (* src = "./rtl/primitive_example_design_1.v:4.20-4.28" *) - (* src = "./rtl/primitive_example_design_1.v:4.20-4.28" *) - wire mux2_sel; - (* src = "./rtl/primitive_example_design_1.v:5.74-5.82" *) - (* src = "./rtl/primitive_example_design_1.v:5.74-5.82" *) - wire ibuf7_en; - (* src = "./rtl/primitive_example_design_1.v:9.11-9.19" *) - (* src = "./rtl/primitive_example_design_1.v:9.11-9.19" *) - wire obuft_oe; - wire \$iopadmap$ibuf4_en ; - wire \$iopadmap$ibuf15_en ; - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:48.15-48.66|./rtl/primitive_example_design_1.v:80.16-80.17" *) - wire \ff_inst1.Q ; - wire \$iopadmap$ibuf1_en ; - (* src = "./rtl/primitive_example_design_1.v:5.121-5.130" *) - (* src = "./rtl/primitive_example_design_1.v:5.121-5.130" *) - wire ibuf12_en; - wire \$iopadmap$ibuf0_en ; - (* src = "./rtl/primitive_example_design_1.v:17.21-17.27" *) - wire g_ibuf; - (* src = "./rtl/primitive_example_design_1.v:16.39-16.53" *) - wire i_buf_mux2_sel; - (* src = "./rtl/primitive_example_design_1.v:12.16-12.25" *) - wire [2:0] i_buf_out; - (* src = "./rtl/primitive_example_design_1.v:5.111-5.120" *) - (* src = "./rtl/primitive_example_design_1.v:5.111-5.120" *) - wire ibuf11_en; - (* src = "./rtl/primitive_example_design_1.v:5.101-5.110" *) - (* src = "./rtl/primitive_example_design_1.v:5.101-5.110" *) - wire ibuf10_en; - wire \$auto$clkbufmap.cc:262:execute$664 ; - fabric_primitive_example_design_1 \$auto$rs_design_edit.cc:578:execute$712 ( - .\$iopadmap$clk (\$iopadmap$clk ), - .\$auto$clkbufmap.cc:262:execute$664 (\$auto$clkbufmap.cc:262:execute$664 ), - .clk_buf_out(clk_buf_out), - .\ff_inst1.Q (\ff_inst1.Q ), - .g_ibuf(g_ibuf), - .i_buf_mux1_sel(i_buf_mux1_sel), - .i_buf_mux2_sel(i_buf_mux2_sel), - .i_buf_out(i_buf_out), - .p_ibuf(p_ibuf), - .\ram_inst.addr (\ram_inst.addr ), - .\ram_inst.we (\ram_inst.we ), - .ram_out(ram_out), - .rst_i_buf_out(rst_i_buf_out) - ); - interface_primitive_example_design_1 \$auto$rs_design_edit.cc:580:execute$713 ( - .\$iopadmap$clk (\$iopadmap$clk ), - .clk(clk), - .G(G), - .P(P), - .Q(Q), - .buft_out(buft_out), - .ibuf0_en(ibuf0_en), - .ibuf10_en(ibuf10_en), - .ibuf11_en(ibuf11_en), - .ibuf12_en(ibuf12_en), - .ibuf13_en(ibuf13_en), - .ibuf14_en(ibuf14_en), - .ibuf15_en(ibuf15_en), - .ibuf16_en(ibuf16_en), - .ibuf1_en(ibuf1_en), - .ibuf2_en(ibuf2_en), - .ibuf3_en(ibuf3_en), - .ibuf4_en(ibuf4_en), - .ibuf5_en(ibuf5_en), - .ibuf6_en(ibuf6_en), - .ibuf7_en(ibuf7_en), - .ibuf8_en(ibuf8_en), - .ibuf9_en(ibuf9_en), - .in(in), - .mux1_sel(mux1_sel), - .mux2_sel(mux2_sel), - .obuft_oe(obuft_oe), - .ram_addr(ram_addr), - .ram_we(ram_we), - .rst(rst), - .\$auto$clkbufmap.cc:262:execute$664 (\$auto$clkbufmap.cc:262:execute$664 ), - .clk_buf_out(clk_buf_out), - .\ff_inst1.Q (\ff_inst1.Q ), - .g_ibuf(g_ibuf), - .i_buf_mux1_sel(i_buf_mux1_sel), - .i_buf_mux2_sel(i_buf_mux2_sel), - .i_buf_out(i_buf_out), - .p_ibuf(p_ibuf), - .\ram_inst.addr (\ram_inst.addr ), - .\ram_inst.we (\ram_inst.we ), - .ram_out(ram_out), - .rst_i_buf_out(rst_i_buf_out) - ); -endmodule - -module interface_primitive_example_design_1(clk, in, rst, Q, mux1_sel, mux2_sel, P, G, ram_addr, ram_we, buft_out, obuft_oe, ibuf0_en, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en, ibuf5_en, ibuf6_en, ibuf7_en, ibuf8_en -, ibuf9_en, ibuf10_en, ibuf11_en, ibuf12_en, ibuf13_en, ibuf14_en, ibuf15_en, ibuf16_en, i_buf_out, clk_buf_out, rst_i_buf_out, i_buf_mux1_sel, i_buf_mux2_sel, p_ibuf, g_ibuf, ram_out, \$auto$clkbufmap.cc:262:execute$664 , \ram_inst.addr , \$iopadmap$clk , \ram_inst.we , \ff_inst1.Q -); - output rst_i_buf_out; - input ram_out; - input ibuf3_en; - output \ram_inst.we ; - output [5:0] \ram_inst.addr ; - output p_ibuf; - input \$auto$clkbufmap.cc:262:execute$664 ; - input ibuf5_en; - input ibuf2_en; - output [2:0] i_buf_out; - output \$iopadmap$clk ; - output clk_buf_out; - input [2:0] in; - output Q; - input ibuf14_en; - output i_buf_mux1_sel; - input G; - input ibuf13_en; - input ibuf0_en; - input ibuf1_en; - input clk; - output g_ibuf; - input rst; - input ibuf4_en; - output buft_out; - input ibuf7_en; - input ibuf10_en; - input ibuf16_en; - input ibuf11_en; - input obuft_oe; - output i_buf_mux2_sel; - input ibuf6_en; - input ibuf12_en; - input ibuf15_en; - input P; - input mux2_sel; - input [5:0] ram_addr; - input mux1_sel; - input ibuf9_en; - input ibuf8_en; - input \ff_inst1.Q ; - input ram_we; - (* src = "./rtl/primitive_example_design_1.v:16.10-16.23" *) - (* src = "./rtl/primitive_example_design_1.v:16.10-16.23" *) - wire rst_i_buf_out; - wire \$iopadmap$ibuf1_en ; - wire \$iopadmap$rst ; - (* src = "./rtl/primitive_example_design_1.v:22.10-22.17" *) - (* src = "./rtl/primitive_example_design_1.v:22.10-22.17" *) - wire ram_out; - (* src = "./rtl/primitive_example_design_1.v:5.38-5.46" *) - (* src = "./rtl/primitive_example_design_1.v:5.38-5.46" *) - wire ibuf3_en; - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:95.8-95.10" *) - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:95.8-95.10" *) - wire \ram_inst.we ; - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:94.27-94.31" *) - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:94.27-94.31" *) - wire [5:0] \ram_inst.addr ; - wire \$iopadmap$ram_we ; - (* src = "./rtl/primitive_example_design_1.v:17.14-17.20" *) - (* src = "./rtl/primitive_example_design_1.v:17.14-17.20" *) - wire p_ibuf; - wire \$auto$clkbufmap.cc:262:execute$664 ; - wire [5:0] \$iopadmap$ram_addr ; - wire \$iopadmap$obuft_oe ; - (* src = "./rtl/primitive_example_design_1.v:5.56-5.64" *) - (* src = "./rtl/primitive_example_design_1.v:5.56-5.64" *) - wire ibuf5_en; - wire \$iopadmap$mux2_sel ; - (* src = "./rtl/primitive_example_design_1.v:5.29-5.37" *) - (* src = "./rtl/primitive_example_design_1.v:5.29-5.37" *) - wire ibuf2_en; - wire \$iopadmap$ibuf2_en ; - (* src = "./rtl/primitive_example_design_1.v:12.16-12.25" *) - (* src = "./rtl/primitive_example_design_1.v:12.16-12.25" *) - wire [2:0] i_buf_out; - wire \$iopadmap$clk ; - (* src = "./rtl/primitive_example_design_1.v:14.21-14.32" *) - (* src = "./rtl/primitive_example_design_1.v:14.21-14.32" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_1.v:2.17-2.19" *) - (* src = "./rtl/primitive_example_design_1.v:2.17-2.19" *) - wire [2:0] in; - (* src = "./rtl/primitive_example_design_1.v:10.12-10.13" *) - (* src = "./rtl/primitive_example_design_1.v:10.12-10.13" *) - wire Q; - wire \$iopadmap$ibuf5_en ; - (* src = "./rtl/primitive_example_design_1.v:5.141-5.150" *) - (* src = "./rtl/primitive_example_design_1.v:5.141-5.150" *) - wire ibuf14_en; - (* src = "./rtl/primitive_example_design_1.v:16.24-16.38" *) - (* src = "./rtl/primitive_example_design_1.v:16.24-16.38" *) - wire i_buf_mux1_sel; - (* src = "./rtl/primitive_example_design_1.v:6.13-6.14" *) - (* src = "./rtl/primitive_example_design_1.v:6.13-6.14" *) - wire G; - (* src = "./rtl/primitive_example_design_1.v:5.131-5.140" *) - (* src = "./rtl/primitive_example_design_1.v:5.131-5.140" *) - wire ibuf13_en; - (* src = "./rtl/primitive_example_design_1.v:5.11-5.19" *) - (* src = "./rtl/primitive_example_design_1.v:5.11-5.19" *) - wire ibuf0_en; - (* src = "./rtl/primitive_example_design_1.v:5.20-5.28" *) - (* src = "./rtl/primitive_example_design_1.v:5.20-5.28" *) - wire ibuf1_en; - (* src = "./rtl/primitive_example_design_1.v:3.11-3.14" *) - (* src = "./rtl/primitive_example_design_1.v:3.11-3.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_1.v:17.21-17.27" *) - (* src = "./rtl/primitive_example_design_1.v:17.21-17.27" *) - wire g_ibuf; - (* src = "./rtl/primitive_example_design_1.v:3.16-3.19" *) - (* src = "./rtl/primitive_example_design_1.v:3.16-3.19" *) - wire rst; - (* src = "./rtl/primitive_example_design_1.v:5.47-5.55" *) - (* src = "./rtl/primitive_example_design_1.v:5.47-5.55" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_1.v:10.14-10.22" *) - (* src = "./rtl/primitive_example_design_1.v:10.14-10.22" *) - wire buft_out; - wire \$auto$clkbufmap.cc:262:execute$667 ; - (* src = "./rtl/primitive_example_design_1.v:5.74-5.82" *) - (* src = "./rtl/primitive_example_design_1.v:5.74-5.82" *) - wire ibuf7_en; - (* src = "./rtl/primitive_example_design_1.v:5.101-5.110" *) - (* src = "./rtl/primitive_example_design_1.v:5.101-5.110" *) - wire ibuf10_en; - wire \$iopadmap$G ; - wire \$iopadmap$Q ; - (* src = "./rtl/primitive_example_design_1.v:5.161-5.170" *) - (* src = "./rtl/primitive_example_design_1.v:5.161-5.170" *) - wire ibuf16_en; - (* src = "./rtl/primitive_example_design_1.v:5.111-5.120" *) - (* src = "./rtl/primitive_example_design_1.v:5.111-5.120" *) - wire ibuf11_en; - wire \$iopadmap$mux1_sel ; - wire \$iopadmap$ibuf0_en ; - wire \$iopadmap$buft_out ; - (* src = "./rtl/primitive_example_design_1.v:9.11-9.19" *) - (* src = "./rtl/primitive_example_design_1.v:9.11-9.19" *) - wire obuft_oe; - wire \$iopadmap$ibuf7_en ; - (* src = "./rtl/primitive_example_design_1.v:16.39-16.53" *) - (* src = "./rtl/primitive_example_design_1.v:16.39-16.53" *) - wire i_buf_mux2_sel; - wire \$iopadmap$ibuf8_en ; - (* src = "./rtl/primitive_example_design_1.v:5.65-5.73" *) - (* src = "./rtl/primitive_example_design_1.v:5.65-5.73" *) - wire ibuf6_en; - (* src = "./rtl/primitive_example_design_1.v:5.121-5.130" *) - (* src = "./rtl/primitive_example_design_1.v:5.121-5.130" *) - wire ibuf12_en; - (* src = "./rtl/primitive_example_design_1.v:5.151-5.160" *) - (* src = "./rtl/primitive_example_design_1.v:5.151-5.160" *) - wire ibuf15_en; - (* src = "./rtl/primitive_example_design_1.v:6.11-6.12" *) - (* src = "./rtl/primitive_example_design_1.v:6.11-6.12" *) - wire P; - wire [2:0] \$iopadmap$in ; - wire \$iopadmap$ibuf12_en ; - (* src = "./rtl/primitive_example_design_1.v:4.20-4.28" *) - (* src = "./rtl/primitive_example_design_1.v:4.20-4.28" *) - wire mux2_sel; - (* src = "./rtl/primitive_example_design_1.v:7.17-7.25" *) - (* src = "./rtl/primitive_example_design_1.v:7.17-7.25" *) - wire [5:0] ram_addr; - wire \$iopadmap$ibuf9_en ; - (* src = "./rtl/primitive_example_design_1.v:4.11-4.19" *) - (* src = "./rtl/primitive_example_design_1.v:4.11-4.19" *) - wire mux1_sel; - (* src = "./rtl/primitive_example_design_1.v:5.92-5.100" *) - (* src = "./rtl/primitive_example_design_1.v:5.92-5.100" *) - wire ibuf9_en; - (* src = "./rtl/primitive_example_design_1.v:5.83-5.91" *) - (* src = "./rtl/primitive_example_design_1.v:5.83-5.91" *) - wire ibuf8_en; - wire \$iopadmap$ibuf6_en ; - wire \$iopadmap$ibuf16_en ; - wire \$iopadmap$ibuf3_en ; - wire \$iopadmap$ibuf11_en ; - wire \$iopadmap$ibuf14_en ; - wire \$iopadmap$ibuf13_en ; - (* src = "./rtl/primitive_example_design_1.v:23.16-23.29" *) - wire ibuf_obuft_oe; - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:48.15-48.66|./rtl/primitive_example_design_1.v:80.16-80.17" *) - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:48.15-48.66|./rtl/primitive_example_design_1.v:80.16-80.17" *) - wire \ff_inst1.Q ; - wire \$iopadmap$ibuf10_en ; - wire \$auto$clkbufmap.cc:294:execute$665 ; - wire \$iopadmap$P ; - wire \$iopadmap$ibuf4_en ; - wire \$iopadmap$ibuf15_en ; - (* src = "./rtl/primitive_example_design_1.v:8.11-8.17" *) - (* src = "./rtl/primitive_example_design_1.v:8.11-8.17" *) - wire ram_we; - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:41.11-41.77" *) - I_BUF ibuf_inst15 ( - .EN(\$iopadmap$ibuf15_en ), - .I(\$iopadmap$ram_addr [5]), - .O(\ram_inst.addr [5]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ram_addr_5 ( - .O(\$iopadmap$ram_addr [5]), - .EN(1'h1), - .I(ram_addr[5]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.in_2 ( - .O(\$iopadmap$in [2]), - .EN(1'h1), - .I(in[2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.rst ( - .O(\$iopadmap$rst ), - .EN(1'h1), - .I(rst) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.P ( - .O(\$iopadmap$P ), - .EN(1'h1), - .I(P) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf0_en ( - .O(\$iopadmap$ibuf0_en ), - .EN(1'h1), - .I(ibuf0_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.clk ( - .O(\$iopadmap$clk ), - .EN(1'h1), - .I(clk) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ram_addr_1 ( - .O(\$iopadmap$ram_addr [1]), - .EN(1'h1), - .I(ram_addr[1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ram_addr_2 ( - .O(\$iopadmap$ram_addr [2]), - .EN(1'h1), - .I(ram_addr[2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ram_addr ( - .O(\$iopadmap$ram_addr [0]), - .EN(1'h1), - .I(ram_addr[0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf3_en ( - .O(\$iopadmap$ibuf3_en ), - .EN(1'h1), - .I(ibuf3_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf16_en ( - .O(\$iopadmap$ibuf16_en ), - .EN(1'h1), - .I(ibuf16_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.in ( - .O(\$iopadmap$in [0]), - .EN(1'h1), - .I(in[0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf9_en ( - .O(\$iopadmap$ibuf9_en ), - .EN(1'h1), - .I(ibuf9_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf8_en ( - .O(\$iopadmap$ibuf8_en ), - .EN(1'h1), - .I(ibuf8_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf7_en ( - .O(\$iopadmap$ibuf7_en ), - .EN(1'h1), - .I(ibuf7_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf6_en ( - .O(\$iopadmap$ibuf6_en ), - .EN(1'h1), - .I(ibuf6_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.G ( - .O(\$iopadmap$G ), - .EN(1'h1), - .I(G) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf4_en ( - .O(\$iopadmap$ibuf4_en ), - .EN(1'h1), - .I(ibuf4_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$primitive_example_design_1.buft_out ( - .O(buft_out), - .I(\$iopadmap$buft_out ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ram_addr_4 ( - .O(\$iopadmap$ram_addr [4]), - .EN(1'h1), - .I(ram_addr[4]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ram_we ( - .O(\$iopadmap$ram_we ), - .EN(1'h1), - .I(ram_we) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ram_addr_3 ( - .O(\$iopadmap$ram_addr [3]), - .EN(1'h1), - .I(ram_addr[3]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf11_en ( - .O(\$iopadmap$ibuf11_en ), - .EN(1'h1), - .I(ibuf11_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf13_en ( - .O(\$iopadmap$ibuf13_en ), - .EN(1'h1), - .I(ibuf13_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.in_1 ( - .O(\$iopadmap$in [1]), - .EN(1'h1), - .I(in[1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf14_en ( - .O(\$iopadmap$ibuf14_en ), - .EN(1'h1), - .I(ibuf14_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.mux2_sel ( - .O(\$iopadmap$mux2_sel ), - .EN(1'h1), - .I(mux2_sel) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf15_en ( - .O(\$iopadmap$ibuf15_en ), - .EN(1'h1), - .I(ibuf15_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.obuft_oe ( - .O(\$iopadmap$obuft_oe ), - .EN(1'h1), - .I(obuft_oe) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$primitive_example_design_1.Q ( - .O(Q), - .I(\$iopadmap$Q ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf12_en ( - .O(\$iopadmap$ibuf12_en ), - .EN(1'h1), - .I(ibuf12_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf2_en ( - .O(\$iopadmap$ibuf2_en ), - .EN(1'h1), - .I(ibuf2_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf10_en ( - .O(\$iopadmap$ibuf10_en ), - .EN(1'h1), - .I(ibuf10_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf5_en ( - .O(\$iopadmap$ibuf5_en ), - .EN(1'h1), - .I(ibuf5_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.ibuf1_en ( - .O(\$iopadmap$ibuf1_en ), - .EN(1'h1), - .I(ibuf1_en) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$clkbufmap.cc:261:execute$663 ( - .O(\$auto$clkbufmap.cc:294:execute$665 ), - .I(\$auto$clkbufmap.cc:262:execute$664 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$clkbufmap.cc:261:execute$666 ( - .O(clk_buf_out), - .I(\$auto$clkbufmap.cc:262:execute$667 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:42.11-42.70" *) - I_BUF ibuf_inst16 ( - .EN(\$iopadmap$ibuf16_en ), - .I(\$iopadmap$obuft_oe ), - .O(ibuf_obuft_oe) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:28.11-28.64" *) - I_BUF ibuf_inst2 ( - .EN(\$iopadmap$ibuf2_en ), - .I(\$iopadmap$in [1]), - .O(i_buf_out[1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:29.11-29.64" *) - I_BUF ibuf_inst3 ( - .EN(\$iopadmap$ibuf3_en ), - .I(\$iopadmap$in [2]), - .O(i_buf_out[2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:30.11-30.63" *) - I_BUF ibuf_inst4 ( - .EN(\$iopadmap$ibuf4_en ), - .I(\$iopadmap$rst ), - .O(rst_i_buf_out) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:31.11-31.69" *) - I_BUF ibuf_inst5 ( - .EN(\$iopadmap$ibuf5_en ), - .I(\$iopadmap$mux1_sel ), - .O(i_buf_mux1_sel) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:32.11-32.69" *) - I_BUF ibuf_inst6 ( - .EN(\$iopadmap$ibuf6_en ), - .I(\$iopadmap$mux2_sel ), - .O(i_buf_mux2_sel) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_1.mux1_sel ( - .O(\$iopadmap$mux1_sel ), - .EN(1'h1), - .I(mux1_sel) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:33.11-33.54" *) - I_BUF ibuf_inst7 ( - .EN(\$iopadmap$ibuf7_en ), - .I(\$iopadmap$P ), - .O(p_ibuf) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:34.11-34.54" *) - I_BUF ibuf_inst8 ( - .EN(\$iopadmap$ibuf8_en ), - .I(\$iopadmap$G ), - .O(g_ibuf) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:35.11-35.65" *) - I_BUF ibuf_inst9 ( - .EN(\$iopadmap$ibuf9_en ), - .I(\$iopadmap$ram_we ), - .O(\ram_inst.we ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:25.11-25.63" *) - I_BUF clk_buf_inst ( - .EN(\$iopadmap$ibuf0_en ), - .I(\$auto$clkbufmap.cc:294:execute$665 ), - .O(\$auto$clkbufmap.cc:262:execute$667 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:52.11-52.42" *) - O_BUF o_buff_inst ( - .I(ram_out), - .O(\$iopadmap$Q ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:50.12-50.65" *) - O_BUFT obuft_inst ( - .I(\ff_inst1.Q ), - .O(\$iopadmap$buft_out ), - .T(ibuf_obuft_oe) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:27.11-27.64" *) - I_BUF ibuf_inst1 ( - .EN(\$iopadmap$ibuf1_en ), - .I(\$iopadmap$in [0]), - .O(i_buf_out[0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:36.11-36.77" *) - I_BUF ibuf_inst10 ( - .EN(\$iopadmap$ibuf10_en ), - .I(\$iopadmap$ram_addr [0]), - .O(\ram_inst.addr [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:37.11-37.77" *) - I_BUF ibuf_inst11 ( - .EN(\$iopadmap$ibuf11_en ), - .I(\$iopadmap$ram_addr [1]), - .O(\ram_inst.addr [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:38.11-38.77" *) - I_BUF ibuf_inst12 ( - .EN(\$iopadmap$ibuf12_en ), - .I(\$iopadmap$ram_addr [2]), - .O(\ram_inst.addr [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:39.11-39.77" *) - I_BUF ibuf_inst13 ( - .EN(\$iopadmap$ibuf13_en ), - .I(\$iopadmap$ram_addr [3]), - .O(\ram_inst.addr [3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_1.v:40.11-40.77" *) - I_BUF ibuf_inst14 ( - .EN(\$iopadmap$ibuf14_en ), - .I(\$iopadmap$ram_addr [4]), - .O(\ram_inst.addr [4]) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_1/primitive_example_design_1.pin b/design_edit/Tests/primitive_example_design_1/primitive_example_design_1.pin deleted file mode 100644 index 7256b139a..000000000 --- a/design_edit/Tests/primitive_example_design_1/primitive_example_design_1.pin +++ /dev/null @@ -1,37 +0,0 @@ -#Pin Constraints -set_property PIN_LOC AB5 [get_ports clk] -set_property PIN_LOC AH18 [get_ports P] -set_property PIN_LOC AH8 [get_ports Q] -set_property PIN_LOC P21 [get_ports buft_out] -set_property PIN_LOC AD14 [get_ports ibuf0_en] -set_property PIN_LOC P23 [get_ports ibuf10_en] -set_property PIN_LOC P23 [get_ports ibuf10_en] -set_property PIN_LOC J23 [get_ports ibuf11_en] -set_property PIN_LOC P26 [get_ports ibuf12_en] -set_property PIN_LOC P21 [get_ports ibuf13_en] -set_property PIN_LOC P25 [get_ports ibuf14_en] -set_property PIN_LOC K21 [get_ports ibuf15_en] -set_property PIN_LOC M21 [get_ports ibuf16_en] -set_property PIN_LOC P27 [get_ports ibuf1_en] -set_property PIN_LOC L22 [get_ports ibuf2_en] -set_property PIN_LOC N23 [get_ports ibuf3_en] -set_property PIN_LOC M23 [get_ports ibuf4_en] -set_property PIN_LOC K24 [get_ports ibuf4_en] -set_property PIN_LOC N24 [get_ports ibuf5_en] -set_property PIN_LOC L24 [get_ports ibuf6_en] -set_property PIN_LOC J26 [get_ports ibuf7_en] -set_property PIN_LOC L25 [get_ports ibuf8_en] -set_property PIN_LOC M28 [get_ports ibuf9_en] -set_property PIN_LOC N26 [get_ports in[0]] -set_property PIN_LOC J24 [get_ports in[1]] -set_property PIN_LOC L26 [get_ports mux1_sel] -set_property PIN_LOC T24 [get_ports mux2_sel] -set_property PIN_LOC U25 [get_ports obuft_oe] -set_property PIN_LOC W27 [get_ports ram_addr[0]] -set_property PIN_LOC U27 [get_ports ram_addr[1]] -set_property PIN_LOC R26 [get_ports ram_addr[2]] -set_property PIN_LOC U21 [get_ports ram_addr[3]] -set_property PIN_LOC T21 [get_ports ram_addr[4]] -set_property PIN_LOC U22 [get_ports ram_addr[5]] -set_property PIN_LOC W21 [get_ports ram_we] -set_property PIN_LOC V23 [get_ports rst] diff --git a/design_edit/Tests/primitive_example_design_1/primitive_example_design_1.ys b/design_edit/Tests/primitive_example_design_1/primitive_example_design_1.ys deleted file mode 100644 index 9d96ce75b..000000000 --- a/design_edit/Tests/primitive_example_design_1/primitive_example_design_1.ys +++ /dev/null @@ -1,19 +0,0 @@ -# Yosys synthesis script for O_SERDES_primitive_inst -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./rtl/primitive_example_design_1.v - - -# Technology mapping -hierarchy -top primitive_example_design_1 - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal delay -effort high -carry auto -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -json ./tmp/io_config.json -w ./tmp/wrapper_primitive_example_design_1_post_synth.v ./tmp/wrapper_primitive_example_design_1_post_synth.eblif -write_verilog -noexpr -nodec -v ./tmp/primitive_example_design_1_post_synth.v -write_blif -param ./tmp/primitive_example_design_1_post_synth.eblif \ No newline at end of file diff --git a/design_edit/Tests/primitive_example_design_1/rtl/primitive_example_design_1.v b/design_edit/Tests/primitive_example_design_1/rtl/primitive_example_design_1.v deleted file mode 100644 index df0722a56..000000000 --- a/design_edit/Tests/primitive_example_design_1/rtl/primitive_example_design_1.v +++ /dev/null @@ -1,113 +0,0 @@ -module primitive_example_design_1(clk,in,rst,Q,mux1_sel,mux2_sel,P,G,ram_addr,ram_we,buft_out,obuft_oe,ibuf0_en,ibuf1_en,ibuf2_en,ibuf3_en,ibuf4_en,ibuf5_en,ibuf6_en,ibuf7_en,ibuf8_en,ibuf9_en,ibuf10_en,ibuf11_en,ibuf12_en,ibuf13_en,ibuf14_en,ibuf15_en,ibuf16_en); - input [2:0] in; - input clk, rst; - input mux1_sel,mux2_sel; - input ibuf0_en,ibuf1_en,ibuf2_en,ibuf3_en,ibuf4_en,ibuf5_en,ibuf6_en,ibuf7_en,ibuf8_en,ibuf9_en,ibuf10_en,ibuf11_en,ibuf12_en,ibuf13_en,ibuf14_en,ibuf15_en,ibuf16_en; - input P,G; - input [5:0] ram_addr; - input ram_we; - input obuft_oe; - output Q,buft_out; - - wire [2:0] i_buf_out; - wire [5:0] i_buf_ram_addr; - wire in_buf_out,clk_buf_out; - wire lut_out; - wire rst_i_buf_out,i_buf_mux1_sel,i_buf_mux2_sel; - wire out,p_ibuf,g_ibuf; - wire dffnre_out; - wire ac_out, acc_out; - wire mux2_out; - wire Q_buff_in; - wire ram_out,i_buf_ram_we; - wire inf_q,ibuf_obuft_oe; - - I_BUF clk_buf_inst (.I(clk),.EN(ibuf0_en),.O(clk_buf_out)); - - I_BUF ibuf_inst1 (.I(in[0]),.EN(ibuf1_en),.O(i_buf_out[0])); - I_BUF ibuf_inst2 (.I(in[1]),.EN(ibuf2_en),.O(i_buf_out[1])); - I_BUF ibuf_inst3 (.I(in[2]),.EN(ibuf3_en),.O(i_buf_out[2])); - I_BUF ibuf_inst4 (.I(rst),.EN(ibuf4_en),.O(rst_i_buf_out)); - I_BUF ibuf_inst5 (.I(mux1_sel),.EN(ibuf5_en),.O(i_buf_mux1_sel)); - I_BUF ibuf_inst6 (.I(mux2_sel),.EN(ibuf6_en),.O(i_buf_mux2_sel)); - I_BUF ibuf_inst7 (.I(P),.EN(ibuf7_en),.O(p_ibuf)); - I_BUF ibuf_inst8 (.I(G),.EN(ibuf8_en),.O(g_ibuf)); - I_BUF ibuf_inst9 (.I(ram_we),.EN(ibuf9_en),.O(i_buf_ram_we)); - I_BUF ibuf_inst10 (.I(ram_addr[0]),.EN(ibuf10_en),.O(i_buf_ram_addr[0])); - I_BUF ibuf_inst11 (.I(ram_addr[1]),.EN(ibuf11_en),.O(i_buf_ram_addr[1])); - I_BUF ibuf_inst12 (.I(ram_addr[2]),.EN(ibuf12_en),.O(i_buf_ram_addr[2])); - I_BUF ibuf_inst13 (.I(ram_addr[3]),.EN(ibuf13_en),.O(i_buf_ram_addr[3])); - I_BUF ibuf_inst14 (.I(ram_addr[4]),.EN(ibuf14_en),.O(i_buf_ram_addr[4])); - I_BUF ibuf_inst15 (.I(ram_addr[5]),.EN(ibuf15_en),.O(i_buf_ram_addr[5])); - I_BUF ibuf_inst16 (.I(obuft_oe),.EN(ibuf16_en),.O(ibuf_obuft_oe)); - - DFFNRE ffn_inst (.D(lut_out),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffnre_out)); - - assign out = i_buf_mux1_sel ? dffnre_out : !dffnre_out; - - flip_flop ff_inst1 (.clk(clk),.rst(rst),.D(ac_out),.Q(inf_q)); - - O_BUFT obuft_inst (.I(inf_q),.T(ibuf_obuft_oe),.O(buft_out)); - - O_BUF o_buff_inst (.I(ram_out),.O(Q)); - - DFFRE ff_inst (.D(mux2_out),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(Q_buff_in)); - - assign mux2_out = i_buf_mux2_sel ? ac_out : acc_out; - - CARRY_CHAIN carry_chain_inst (.P(p_ibuf),.G(g_ibuf),.CIN(out),.O(ac_out),.COUT(acc_out)); - - infer_single_port_ram ram_inst (.data(Q_buff_in),.addr(i_buf_ram_addr),.we(i_buf_ram_we),.clk(clk),.q(ram_out)); - - always @(*) begin - case(i_buf_out) - 3'b000 : lut_out = 0; - 3'b001 : lut_out = 1; - 3'b010 : lut_out = 1; - 3'b011 : lut_out = 0; - 3'b100 : lut_out = 1; - 3'b101 : lut_out = 1; - 3'b110 : lut_out = 1; - 3'b111 : lut_out = 0; - default: lut_out = 1; - endcase - end -endmodule - -module flip_flop( - input rst,clk, - input D, - output reg Q -); - always @ (posedge clk) begin - if (rst) - Q <= 0; - else - Q <= D; - end -endmodule - -module infer_single_port_ram -#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) -( - input [(DATA_WIDTH-1):0] data, - input [(ADDR_WIDTH-1):0] addr, - input we, clk, - output [(DATA_WIDTH-1):0] q -); - - reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; - - reg [ADDR_WIDTH-1:0] addr_reg; - - always @ (posedge clk) - begin - if (we) - ram[addr] <= data; - - addr_reg <= addr; - end - - assign q = ram[addr_reg]; - -endmodule diff --git a/design_edit/Tests/primitive_example_design_1/synthesis/primitive_example_design_1_post_synth.eblif b/design_edit/Tests/primitive_example_design_1/synthesis/primitive_example_design_1_post_synth.eblif deleted file mode 100644 index 838480fec..000000000 --- a/design_edit/Tests/primitive_example_design_1/synthesis/primitive_example_design_1_post_synth.eblif +++ /dev/null @@ -1,108 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model primitive_example_design_1 -.inputs clk in[0] in[1] in[2] rst mux1_sel mux2_sel P G ram_addr[0] ram_addr[1] ram_addr[2] ram_addr[3] ram_addr[4] ram_addr[5] ram_we obuft_oe ibuf0_en ibuf1_en ibuf2_en ibuf3_en ibuf4_en ibuf5_en ibuf6_en ibuf7_en ibuf8_en ibuf9_en ibuf10_en ibuf11_en ibuf12_en ibuf13_en ibuf14_en ibuf15_en ibuf16_en -.outputs Q buft_out -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=clk D=ram_inst.we E=$true Q=$auto$memory_dff.cc:774:handle_rd_port_addr$44 R=$true -.subckt DFFRE C=clk D=Q_buff_in E=$true Q=$auto$memory_dff.cc:776:handle_rd_port_addr$46[0] R=$true -.subckt DFFRE C=clk D=$abc$369$li2_li2 E=$true Q=ff_inst1.Q R=$true -.subckt LUT3 A[0]=$auto$memory_dff.cc:776:handle_rd_port_addr$46[0] A[1]=$abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] A[2]=$auto$memory_dff.cc:774:handle_rd_port_addr$44 Y=ram_out -.param INIT_VALUE 10101100 -.subckt LUT2 A[0]=dffnre_out A[1]=i_buf_mux1_sel Y=out -.param INIT_VALUE 1001 -.subckt LUT2 A[0]=rst A[1]=ff_inst1.D Y=$abc$369$li2_li2 -.param INIT_VALUE 0100 -.subckt LUT3 A[0]=acc_out A[1]=ff_inst1.D A[2]=i_buf_mux2_sel Y=mux2_out -.param INIT_VALUE 11001010 -.subckt LUT3 A[0]=i_buf_out[2] A[1]=i_buf_out[0] A[2]=i_buf_out[1] Y=lut_out -.param INIT_VALUE 00111110 -.subckt CARRY_CHAIN CIN=out COUT=acc_out G=g_ibuf O=ff_inst1.D P=p_ibuf -.subckt I_BUF EN=ibuf0_en I=clk O=clk_buf_out -.subckt DFFRE C=clk_buf_out D=mux2_out E=$true Q=Q_buff_in R=rst_i_buf_out -.subckt DFFNRE C=clk_buf_out D=lut_out E=$true Q=dffnre_out R=rst_i_buf_out -.subckt I_BUF EN=ibuf1_en I=in[0] O=i_buf_out[0] -.subckt I_BUF EN=ibuf10_en I=ram_addr[0] O=ram_inst.addr[0] -.subckt I_BUF EN=ibuf11_en I=ram_addr[1] O=ram_inst.addr[1] -.subckt I_BUF EN=ibuf12_en I=ram_addr[2] O=ram_inst.addr[2] -.subckt I_BUF EN=ibuf13_en I=ram_addr[3] O=ram_inst.addr[3] -.subckt I_BUF EN=ibuf14_en I=ram_addr[4] O=ram_inst.addr[4] -.subckt I_BUF EN=ibuf15_en I=ram_addr[5] O=ram_inst.addr[5] -.subckt I_BUF EN=ibuf16_en I=obuft_oe O=ibuf_obuft_oe -.subckt I_BUF EN=ibuf2_en I=in[1] O=i_buf_out[1] -.subckt I_BUF EN=ibuf3_en I=in[2] O=i_buf_out[2] -.subckt I_BUF EN=ibuf4_en I=rst O=rst_i_buf_out -.subckt I_BUF EN=ibuf5_en I=mux1_sel O=i_buf_mux1_sel -.subckt I_BUF EN=ibuf6_en I=mux2_sel O=i_buf_mux2_sel -.subckt I_BUF EN=ibuf7_en I=P O=p_ibuf -.subckt I_BUF EN=ibuf8_en I=G O=g_ibuf -.subckt I_BUF EN=ibuf9_en I=ram_we O=ram_inst.we -.subckt O_BUF I=ram_out O=Q -.subckt O_BUFT I=ff_inst1.Q O=buft_out T=ibuf_obuft_oe -.subckt TDP_RAM18KX2 ADDR_A1[0]=$false ADDR_A1[1]=$false ADDR_A1[2]=$false ADDR_A1[3]=ram_inst.addr[0] ADDR_A1[4]=ram_inst.addr[1] ADDR_A1[5]=ram_inst.addr[2] ADDR_A1[6]=ram_inst.addr[3] ADDR_A1[7]=ram_inst.addr[4] ADDR_A1[8]=ram_inst.addr[5] ADDR_A1[9]=$false ADDR_A1[10]=$false ADDR_A1[11]=$false ADDR_A1[12]=$false ADDR_A1[13]=$false ADDR_A2[0]=$undef ADDR_A2[1]=$undef ADDR_A2[2]=$undef ADDR_A2[3]=$undef ADDR_A2[4]=$undef ADDR_A2[5]=$undef ADDR_A2[6]=$undef ADDR_A2[7]=$undef ADDR_A2[8]=$undef ADDR_A2[9]=$undef ADDR_A2[10]=$undef ADDR_A2[11]=$undef ADDR_A2[12]=$undef ADDR_A2[13]=$undef ADDR_B1[0]=$false ADDR_B1[1]=$false ADDR_B1[2]=$false ADDR_B1[3]=ram_inst.addr[0] ADDR_B1[4]=ram_inst.addr[1] ADDR_B1[5]=ram_inst.addr[2] ADDR_B1[6]=ram_inst.addr[3] ADDR_B1[7]=ram_inst.addr[4] ADDR_B1[8]=ram_inst.addr[5] ADDR_B1[9]=$false ADDR_B1[10]=$false ADDR_B1[11]=$false ADDR_B1[12]=$false ADDR_B1[13]=$false ADDR_B2[0]=$undef ADDR_B2[1]=$undef ADDR_B2[2]=$undef ADDR_B2[3]=$undef ADDR_B2[4]=$undef ADDR_B2[5]=$undef ADDR_B2[6]=$undef ADDR_B2[7]=$undef ADDR_B2[8]=$undef ADDR_B2[9]=$undef ADDR_B2[10]=$undef ADDR_B2[11]=$undef ADDR_B2[12]=$undef ADDR_B2[13]=$undef BE_A1[0]=$false BE_A1[1]=$false BE_A2[0]=$false BE_A2[1]=$false BE_B1[0]=ram_inst.we BE_B1[1]=$false BE_B2[0]=$undef BE_B2[1]=$undef CLK_A1=clk CLK_A2=$undef CLK_B1=clk CLK_B2=$undef RDATA_A1[0]=$abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] RDATA_A1[1]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[1] RDATA_A1[2]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[2] RDATA_A1[3]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[3] RDATA_A1[4]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[4] RDATA_A1[5]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[5] RDATA_A1[6]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[6] RDATA_A1[7]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[7] RDATA_A1[8]=$auto$memory_libmap.cc:1863:emit_port$52[8] RDATA_A1[9]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[9] RDATA_A1[10]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[10] RDATA_A1[11]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[11] RDATA_A1[12]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[12] RDATA_A1[13]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[13] RDATA_A1[14]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[14] RDATA_A1[15]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[15] RDATA_A2[0]=$techmap72\ram_inst.ram.0.0.C1DATA RDATA_A2[1]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[1] RDATA_A2[2]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[2] RDATA_A2[3]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[3] RDATA_A2[4]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[4] RDATA_A2[5]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[5] RDATA_A2[6]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[6] RDATA_A2[7]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[7] RDATA_A2[8]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[8] RDATA_A2[9]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[9] RDATA_A2[10]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[10] RDATA_A2[11]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[11] RDATA_A2[12]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[12] RDATA_A2[13]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[13] RDATA_A2[14]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[14] RDATA_A2[15]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[15] RDATA_B1[0]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[0] RDATA_B1[1]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[1] RDATA_B1[2]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[2] RDATA_B1[3]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[3] RDATA_B1[4]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[4] RDATA_B1[5]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[5] RDATA_B1[6]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[6] RDATA_B1[7]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[7] RDATA_B1[8]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[8] RDATA_B1[9]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[9] RDATA_B1[10]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[10] RDATA_B1[11]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[11] RDATA_B1[12]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[12] RDATA_B1[13]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[13] RDATA_B1[14]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[14] RDATA_B1[15]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[15] RDATA_B2[0]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[0] RDATA_B2[1]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[1] RDATA_B2[2]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[2] RDATA_B2[3]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[3] RDATA_B2[4]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[4] RDATA_B2[5]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[5] RDATA_B2[6]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[6] RDATA_B2[7]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[7] RDATA_B2[8]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[8] RDATA_B2[9]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[9] RDATA_B2[10]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[10] RDATA_B2[11]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[11] RDATA_B2[12]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[12] RDATA_B2[13]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[13] RDATA_B2[14]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[14] RDATA_B2[15]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[15] REN_A1=$true REN_A2=$undef REN_B1=$false REN_B2=$false RPARITY_A1[0]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[16] RPARITY_A1[1]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[17] RPARITY_A2[0]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[16] RPARITY_A2[1]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[17] RPARITY_B1[0]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[16] RPARITY_B1[1]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[17] RPARITY_B2[0]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[16] RPARITY_B2[1]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[17] WDATA_A1[0]=$undef WDATA_A1[1]=$undef WDATA_A1[2]=$undef WDATA_A1[3]=$undef WDATA_A1[4]=$undef WDATA_A1[5]=$undef WDATA_A1[6]=$undef WDATA_A1[7]=$undef WDATA_A1[8]=$undef WDATA_A1[9]=$undef WDATA_A1[10]=$undef WDATA_A1[11]=$undef WDATA_A1[12]=$undef WDATA_A1[13]=$undef WDATA_A1[14]=$undef WDATA_A1[15]=$undef WDATA_A2[0]=$undef WDATA_A2[1]=$undef WDATA_A2[2]=$undef WDATA_A2[3]=$undef WDATA_A2[4]=$undef WDATA_A2[5]=$undef WDATA_A2[6]=$undef WDATA_A2[7]=$undef WDATA_A2[8]=$undef WDATA_A2[9]=$undef WDATA_A2[10]=$undef WDATA_A2[11]=$undef WDATA_A2[12]=$undef WDATA_A2[13]=$undef WDATA_A2[14]=$undef WDATA_A2[15]=$undef WDATA_B1[0]=Q_buff_in WDATA_B1[1]=$false WDATA_B1[2]=$false WDATA_B1[3]=$false WDATA_B1[4]=$false WDATA_B1[5]=$false WDATA_B1[6]=$false WDATA_B1[7]=$false WDATA_B1[8]=$undef WDATA_B1[9]=$undef WDATA_B1[10]=$undef WDATA_B1[11]=$undef WDATA_B1[12]=$undef WDATA_B1[13]=$undef WDATA_B1[14]=$undef WDATA_B1[15]=$undef WDATA_B2[0]=$undef WDATA_B2[1]=$undef WDATA_B2[2]=$undef WDATA_B2[3]=$undef WDATA_B2[4]=$undef WDATA_B2[5]=$undef WDATA_B2[6]=$undef WDATA_B2[7]=$undef WDATA_B2[8]=$undef WDATA_B2[9]=$undef WDATA_B2[10]=$undef WDATA_B2[11]=$undef WDATA_B2[12]=$undef WDATA_B2[13]=$undef WDATA_B2[14]=$undef WDATA_B2[15]=$undef WEN_A1=$false WEN_A2=$false WEN_B1=ram_inst.we WEN_B2=$undef WPARITY_A1[0]=$undef WPARITY_A1[1]=$undef WPARITY_A2[0]=$undef WPARITY_A2[1]=$undef WPARITY_B1[0]=$undef WPARITY_B1[1]=$undef WPARITY_B2[0]=$undef WPARITY_B2[1]=$undef -.param INIT1 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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-.param INIT1_PARITY 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -.param INIT2 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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-.param INIT2_PARITY 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -.param READ_WIDTH_A1 00000000000000000000000000001001 -.param READ_WIDTH_A2 00000000000000000000000000000001 -.param READ_WIDTH_B1 00000000000000000000000000001001 -.param READ_WIDTH_B2 00000000000000000000000000000001 -.param WRITE_WIDTH_A1 00000000000000000000000000001001 -.param WRITE_WIDTH_A2 00000000000000000000000000000001 -.param WRITE_WIDTH_B1 00000000000000000000000000001001 -.param WRITE_WIDTH_B2 00000000000000000000000000000001 -.names $techmap72\ram_inst.ram.0.0.C1DATA $techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[0] -1 1 -.names $abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[0] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[1] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[1] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[2] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[2] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[3] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[3] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[4] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[4] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[5] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[5] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[6] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[6] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[7] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[7] -1 1 -.names $auto$memory_libmap.cc:1863:emit_port$52[8] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[8] -1 1 -.names $abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] $auto$memory_libmap.cc:1863:emit_port$52[0] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[1] $auto$memory_libmap.cc:1863:emit_port$52[1] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[2] $auto$memory_libmap.cc:1863:emit_port$52[2] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[3] $auto$memory_libmap.cc:1863:emit_port$52[3] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[4] $auto$memory_libmap.cc:1863:emit_port$52[4] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[5] $auto$memory_libmap.cc:1863:emit_port$52[5] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[6] $auto$memory_libmap.cc:1863:emit_port$52[6] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[7] $auto$memory_libmap.cc:1863:emit_port$52[7] -1 1 -.names $abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] $auto$memory_dff.cc:781:handle_rd_port_addr$50[0] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[1] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[2] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[3] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[4] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[5] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[6] -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_1/synthesis/primitive_example_design_1_post_synth.v b/design_edit/Tests/primitive_example_design_1/synthesis/primitive_example_design_1_post_synth.v deleted file mode 100644 index 7859327cc..000000000 --- a/design_edit/Tests/primitive_example_design_1/synthesis/primitive_example_design_1_post_synth.v +++ /dev/null @@ -1,494 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module primitive_example_design_1(clk, in, rst, Q, mux1_sel, mux2_sel, P, G, ram_addr, ram_we, buft_out, obuft_oe, ibuf0_en, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en, ibuf5_en, ibuf6_en, ibuf7_en, ibuf8_en -, ibuf9_en, ibuf10_en, ibuf11_en, ibuf12_en, ibuf13_en, ibuf14_en, ibuf15_en, ibuf16_en); - input G; - input P; - output Q; - output buft_out; - input clk; - input ibuf0_en; - input ibuf10_en; - input ibuf11_en; - input ibuf12_en; - input ibuf13_en; - input ibuf14_en; - input ibuf15_en; - input ibuf16_en; - input ibuf1_en; - input ibuf2_en; - input ibuf3_en; - input ibuf4_en; - input ibuf5_en; - input ibuf6_en; - input ibuf7_en; - input ibuf8_en; - input ibuf9_en; - input [2:0] in; - input mux1_sel; - input mux2_sel; - input obuft_oe; - input [5:0] ram_addr; - input ram_we; - input rst; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] _00_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _01_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] _02_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _03_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] _04_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _05_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] _06_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _07_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] _08_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _09_; - wire _10_; - wire _11_; - (* keep = 32'h00000001 *) - wire _12_; - (* keep = 32'h00000001 *) - (* unused_bits = "1 2 3 4 5 6 7" *) - wire [7:0] _13_; - (* unused_bits = "1 2 3 4 5 6 7" *) - wire [7:0] _14_; - (* unused_bits = "1 2 3 4 5 6 7 8" *) - wire [8:0] _15_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:461.28-461.34" *) - (* unused_bits = "0" *) - wire _16_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:498.14-498.27" *) - (* unused_bits = "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _17_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:500.14-500.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _18_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:499.14-499.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _19_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:501.14-501.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _20_; - (* src = "./rtl/primitive_example_design_1.v:6.13-6.14" *) - (* src = "./rtl/primitive_example_design_1.v:6.13-6.14" *) - wire G; - (* src = "./rtl/primitive_example_design_1.v:6.11-6.12" *) - (* src = "./rtl/primitive_example_design_1.v:6.11-6.12" *) - wire P; - (* src = "./rtl/primitive_example_design_1.v:10.12-10.13" *) - (* src = "./rtl/primitive_example_design_1.v:10.12-10.13" *) - wire Q; - (* src = "./rtl/primitive_example_design_1.v:21.10-21.19" *) - wire Q_buff_in; - (* src = "./rtl/primitive_example_design_1.v:19.18-19.25" *) - wire acc_out; - (* src = "./rtl/primitive_example_design_1.v:10.14-10.22" *) - (* src = "./rtl/primitive_example_design_1.v:10.14-10.22" *) - wire buft_out; - (* src = "./rtl/primitive_example_design_1.v:3.11-3.14" *) - (* src = "./rtl/primitive_example_design_1.v:3.11-3.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_1.v:14.21-14.32" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_1.v:18.10-18.20" *) - wire dffnre_out; - (* hdlname = "ff_inst1 D" *) - (* src = "./rtl/primitive_example_design_1.v:48.15-48.66|./rtl/primitive_example_design_1.v:79.11-79.12" *) - wire \ff_inst1.D ; - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:48.15-48.66|./rtl/primitive_example_design_1.v:80.16-80.17" *) - wire \ff_inst1.Q ; - (* src = "./rtl/primitive_example_design_1.v:17.21-17.27" *) - wire g_ibuf; - (* src = "./rtl/primitive_example_design_1.v:16.24-16.38" *) - wire i_buf_mux1_sel; - (* src = "./rtl/primitive_example_design_1.v:16.39-16.53" *) - wire i_buf_mux2_sel; - (* src = "./rtl/primitive_example_design_1.v:12.16-12.25" *) - wire [2:0] i_buf_out; - (* src = "./rtl/primitive_example_design_1.v:5.11-5.19" *) - (* src = "./rtl/primitive_example_design_1.v:5.11-5.19" *) - wire ibuf0_en; - (* src = "./rtl/primitive_example_design_1.v:5.101-5.110" *) - (* src = "./rtl/primitive_example_design_1.v:5.101-5.110" *) - wire ibuf10_en; - (* src = "./rtl/primitive_example_design_1.v:5.111-5.120" *) - (* src = "./rtl/primitive_example_design_1.v:5.111-5.120" *) - wire ibuf11_en; - (* src = "./rtl/primitive_example_design_1.v:5.121-5.130" *) - (* src = "./rtl/primitive_example_design_1.v:5.121-5.130" *) - wire ibuf12_en; - (* src = "./rtl/primitive_example_design_1.v:5.131-5.140" *) - (* src = "./rtl/primitive_example_design_1.v:5.131-5.140" *) - wire ibuf13_en; - (* src = "./rtl/primitive_example_design_1.v:5.141-5.150" *) - (* src = "./rtl/primitive_example_design_1.v:5.141-5.150" *) - wire ibuf14_en; - (* src = "./rtl/primitive_example_design_1.v:5.151-5.160" *) - (* src = "./rtl/primitive_example_design_1.v:5.151-5.160" *) - wire ibuf15_en; - (* src = "./rtl/primitive_example_design_1.v:5.161-5.170" *) - (* src = "./rtl/primitive_example_design_1.v:5.161-5.170" *) - wire ibuf16_en; - (* src = "./rtl/primitive_example_design_1.v:5.20-5.28" *) - (* src = "./rtl/primitive_example_design_1.v:5.20-5.28" *) - wire ibuf1_en; - (* src = "./rtl/primitive_example_design_1.v:5.29-5.37" *) - (* src = "./rtl/primitive_example_design_1.v:5.29-5.37" *) - wire ibuf2_en; - (* src = "./rtl/primitive_example_design_1.v:5.38-5.46" *) - (* src = "./rtl/primitive_example_design_1.v:5.38-5.46" *) - wire ibuf3_en; - (* src = "./rtl/primitive_example_design_1.v:5.47-5.55" *) - (* src = "./rtl/primitive_example_design_1.v:5.47-5.55" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_1.v:5.56-5.64" *) - (* src = "./rtl/primitive_example_design_1.v:5.56-5.64" *) - wire ibuf5_en; - (* src = "./rtl/primitive_example_design_1.v:5.65-5.73" *) - (* src = "./rtl/primitive_example_design_1.v:5.65-5.73" *) - wire ibuf6_en; - (* src = "./rtl/primitive_example_design_1.v:5.74-5.82" *) - (* src = "./rtl/primitive_example_design_1.v:5.74-5.82" *) - wire ibuf7_en; - (* src = "./rtl/primitive_example_design_1.v:5.83-5.91" *) - (* src = "./rtl/primitive_example_design_1.v:5.83-5.91" *) - wire ibuf8_en; - (* src = "./rtl/primitive_example_design_1.v:5.92-5.100" *) - (* src = "./rtl/primitive_example_design_1.v:5.92-5.100" *) - wire ibuf9_en; - (* src = "./rtl/primitive_example_design_1.v:23.16-23.29" *) - wire ibuf_obuft_oe; - (* src = "./rtl/primitive_example_design_1.v:2.17-2.19" *) - (* src = "./rtl/primitive_example_design_1.v:2.17-2.19" *) - wire [2:0] in; - (* src = "./rtl/primitive_example_design_1.v:15.10-15.17" *) - wire lut_out; - (* src = "./rtl/primitive_example_design_1.v:4.11-4.19" *) - (* src = "./rtl/primitive_example_design_1.v:4.11-4.19" *) - wire mux1_sel; - (* src = "./rtl/primitive_example_design_1.v:20.10-20.18" *) - wire mux2_out; - (* src = "./rtl/primitive_example_design_1.v:4.20-4.28" *) - (* src = "./rtl/primitive_example_design_1.v:4.20-4.28" *) - wire mux2_sel; - (* src = "./rtl/primitive_example_design_1.v:9.11-9.19" *) - (* src = "./rtl/primitive_example_design_1.v:9.11-9.19" *) - wire obuft_oe; - (* src = "./rtl/primitive_example_design_1.v:17.10-17.13" *) - wire out; - (* src = "./rtl/primitive_example_design_1.v:17.14-17.20" *) - wire p_ibuf; - (* src = "./rtl/primitive_example_design_1.v:7.17-7.25" *) - (* src = "./rtl/primitive_example_design_1.v:7.17-7.25" *) - wire [5:0] ram_addr; - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:94.27-94.31" *) - wire [5:0] \ram_inst.addr ; - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_1.v:60.27-60.116|./rtl/primitive_example_design_1.v:95.8-95.10" *) - wire \ram_inst.we ; - (* src = "./rtl/primitive_example_design_1.v:22.10-22.17" *) - wire ram_out; - (* src = "./rtl/primitive_example_design_1.v:8.11-8.17" *) - (* src = "./rtl/primitive_example_design_1.v:8.11-8.17" *) - wire ram_we; - (* src = "./rtl/primitive_example_design_1.v:3.16-3.19" *) - (* src = "./rtl/primitive_example_design_1.v:3.16-3.19" *) - wire rst; - (* src = "./rtl/primitive_example_design_1.v:16.10-16.23" *) - wire rst_i_buf_out; - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'hac) - ) _21_ ( - .Y(ram_out), - .A({ _12_, _10_, _13_[0] }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _22_ ( - .C(clk), - .D(Q_buff_in), - .E(1'h1), - .Q(_13_[0]), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _23_ ( - .C(clk), - .D(_11_), - .E(1'h1), - .Q(\ff_inst1.Q ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h9) - ) _24_ ( - .Y(out), - .A({ i_buf_mux1_sel, dffnre_out }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) _25_ ( - .Y(_11_), - .A({ \ff_inst1.D , rst }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'hca) - ) _26_ ( - .Y(mux2_out), - .A({ i_buf_mux2_sel, \ff_inst1.D , acc_out }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h3e) - ) _27_ ( - .Y(lut_out), - .A({ i_buf_out[1:0], i_buf_out[2] }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _28_ ( - .C(clk), - .D(\ram_inst.we ), - .E(1'h1), - .Q(_12_), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:58.17-58.93" *) - CARRY_CHAIN carry_chain_inst ( - .CIN(out), - .COUT(acc_out), - .G(g_ibuf), - .O(\ff_inst1.D ), - .P(p_ibuf) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:25.11-25.63" *) - I_BUF clk_buf_inst ( - .EN(ibuf0_en), - .I(clk), - .O(clk_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:54.11-54.90" *) - DFFRE ff_inst ( - .C(clk_buf_out), - .D(mux2_out), - .E(1'h1), - .Q(Q_buff_in), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:44.12-44.92" *) - DFFNRE ffn_inst ( - .C(clk_buf_out), - .D(lut_out), - .E(1'h1), - .Q(dffnre_out), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:27.11-27.64" *) - I_BUF ibuf_inst1 ( - .EN(ibuf1_en), - .I(in[0]), - .O(i_buf_out[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:36.11-36.77" *) - I_BUF ibuf_inst10 ( - .EN(ibuf10_en), - .I(ram_addr[0]), - .O(\ram_inst.addr [0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:37.11-37.77" *) - I_BUF ibuf_inst11 ( - .EN(ibuf11_en), - .I(ram_addr[1]), - .O(\ram_inst.addr [1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:38.11-38.77" *) - I_BUF ibuf_inst12 ( - .EN(ibuf12_en), - .I(ram_addr[2]), - .O(\ram_inst.addr [2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:39.11-39.77" *) - I_BUF ibuf_inst13 ( - .EN(ibuf13_en), - .I(ram_addr[3]), - .O(\ram_inst.addr [3]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:40.11-40.77" *) - I_BUF ibuf_inst14 ( - .EN(ibuf14_en), - .I(ram_addr[4]), - .O(\ram_inst.addr [4]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:41.11-41.77" *) - I_BUF ibuf_inst15 ( - .EN(ibuf15_en), - .I(ram_addr[5]), - .O(\ram_inst.addr [5]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:42.11-42.70" *) - I_BUF ibuf_inst16 ( - .EN(ibuf16_en), - .I(obuft_oe), - .O(ibuf_obuft_oe) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:28.11-28.64" *) - I_BUF ibuf_inst2 ( - .EN(ibuf2_en), - .I(in[1]), - .O(i_buf_out[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:29.11-29.64" *) - I_BUF ibuf_inst3 ( - .EN(ibuf3_en), - .I(in[2]), - .O(i_buf_out[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:30.11-30.63" *) - I_BUF ibuf_inst4 ( - .EN(ibuf4_en), - .I(rst), - .O(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:31.11-31.69" *) - I_BUF ibuf_inst5 ( - .EN(ibuf5_en), - .I(mux1_sel), - .O(i_buf_mux1_sel) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:32.11-32.69" *) - I_BUF ibuf_inst6 ( - .EN(ibuf6_en), - .I(mux2_sel), - .O(i_buf_mux2_sel) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:33.11-33.54" *) - I_BUF ibuf_inst7 ( - .EN(ibuf7_en), - .I(P), - .O(p_ibuf) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:34.11-34.54" *) - I_BUF ibuf_inst8 ( - .EN(ibuf8_en), - .I(G), - .O(g_ibuf) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:35.11-35.65" *) - I_BUF ibuf_inst9 ( - .EN(ibuf9_en), - .I(ram_we), - .O(\ram_inst.we ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:52.11-52.42" *) - O_BUF o_buff_inst ( - .I(ram_out), - .O(Q) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_1.v:50.12-50.65" *) - O_BUFT obuft_inst ( - .I(\ff_inst1.Q ), - .O(buft_out), - .T(ibuf_obuft_oe) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:645.7-684.2" *) - TDP_RAM18KX2 #( - .INIT1(16384'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT1_PARITY(2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT2(16384'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT2_PARITY(2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .READ_WIDTH_A1(32'h00000009), - .READ_WIDTH_A2(32'sh00000001), - .READ_WIDTH_B1(32'h00000009), - .READ_WIDTH_B2(32'sh00000001), - .WRITE_WIDTH_A1(32'h00000009), - .WRITE_WIDTH_A2(32'sh00000001), - .WRITE_WIDTH_B1(32'h00000009), - .WRITE_WIDTH_B2(32'sh00000001) - ) \ram_inst.ram.0.0 ( - .ADDR_A1({ 5'h00, \ram_inst.addr , 3'h0 }), - .ADDR_A2(14'hxxxx), - .ADDR_B1({ 5'h00, \ram_inst.addr , 3'h0 }), - .ADDR_B2(14'hxxxx), - .BE_A1(2'h0), - .BE_A2(2'h0), - .BE_B1({ 1'h0, \ram_inst.we }), - .BE_B2(2'hx), - .CLK_A1(clk), - .CLK_A2(1'hx), - .CLK_B1(clk), - .CLK_B2(1'hx), - .RDATA_A1({ _17_[15:9], _15_[8], _14_[7:1], _10_ }), - .RDATA_A2({ _18_[15:1], _16_ }), - .RDATA_B1(_19_[15:0]), - .RDATA_B2(_20_[15:0]), - .REN_A1(1'h1), - .REN_A2(1'hx), - .REN_B1(1'h0), - .REN_B2(1'h0), - .RPARITY_A1(_17_[17:16]), - .RPARITY_A2(_18_[17:16]), - .RPARITY_B1(_19_[17:16]), - .RPARITY_B2(_20_[17:16]), - .WDATA_A1(16'hxxxx), - .WDATA_A2(16'hxxxx), - .WDATA_B1({ 15'bxxxxxxxx0000000, Q_buff_in }), - .WDATA_B2(16'hxxxx), - .WEN_A1(1'h0), - .WEN_A2(1'h0), - .WEN_B1(\ram_inst.we ), - .WEN_B2(1'hx), - .WPARITY_A1(2'hx), - .WPARITY_A2(2'hx), - .WPARITY_B1(2'hx), - .WPARITY_B2(2'hx) - ); - assign _18_[0] = _16_; - assign _17_[8:0] = { _15_[8], _14_[7:1], _10_ }; - assign _15_[7:0] = { _14_[7:1], _10_ }; - assign _14_[0] = _10_; - assign _13_[6:1] = { _13_[7], _13_[7], _13_[7], _13_[7], _13_[7], _13_[7] }; -endmodule diff --git a/design_edit/Tests/primitive_example_design_2/gold/interface.json b/design_edit/Tests/primitive_example_design_2/gold/interface.json deleted file mode 100644 index 24557740c..000000000 --- a/design_edit/Tests/primitive_example_design_2/gold/interface.json +++ /dev/null @@ -1,609 +0,0 @@ -{ - "IO_Instances": { - "clk_buf_inst": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf0_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "clk", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "clk_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_ds_inst1": { - "module": "I_BUF_DS", - "ports": { - "EN": [ - { - "Actual": "ibuf1_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_N": [ - { - "Actual": "in_n", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_P": [ - { - "Actual": "in_p", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_ds_inst2": { - "module": "I_BUF_DS", - "ports": { - "EN": [ - { - "Actual": "ibuf2_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_N": [ - { - "Actual": "in_n", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "I_P": [ - { - "Actual": "in_p", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ] - } - }, - "ibuf_ds_inst3": { - "module": "I_BUF_DS", - "ports": { - "EN": [ - { - "Actual": "ibuf3_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_N": [ - { - "Actual": "in_n", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "I_P": [ - { - "Actual": "in_p", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ] - } - }, - "ibuf_ds_inst4": { - "module": "I_BUF_DS", - "ports": { - "EN": [ - { - "Actual": "ibuf4_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_N": [ - { - "Actual": "rst_n", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_P": [ - { - "Actual": "rst_p", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "rst_i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_ds_inst5": { - "module": "I_BUF_DS", - "ports": { - "EN": [ - { - "Actual": "ibuf5_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_N": [ - { - "Actual": "mux1_sel_n", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_P": [ - { - "Actual": "mux1_sel_p", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_mux1_sel", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_ds_inst6": { - "module": "I_BUF_DS", - "ports": { - "EN": [ - { - "Actual": "ibuf6_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_N": [ - { - "Actual": "mux2_sel_n", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I_P": [ - { - "Actual": "mux2_sel_p", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_mux2_sel", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst10": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf10_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst11": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf11_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ] - } - }, - "ibuf_inst12": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf12_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ] - } - }, - "ibuf_inst13": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf13_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 3, - "msb": 3 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 3, - "msb": 3 - } - ] - } - }, - "ibuf_inst14": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf14_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 4, - "msb": 4 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 4, - "msb": 4 - } - ] - } - }, - "ibuf_inst15": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf15_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_addr", - "FUNC": "IN_DIR", - "lsb": 5, - "msb": 5 - } - ], - "O": [ - { - "Actual": "ram_inst.addr", - "FUNC": "OUT_DIR", - "lsb": 5, - "msb": 5 - } - ] - } - }, - "ibuf_inst16": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf16_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "obuft_oe", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "ibuf_obuft_oe", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst7": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf7_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "P", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "p_ibuf", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst8": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf8_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "G", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "g_ibuf", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst9": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf9_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "ram_we", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "ram_inst.we", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "o_buff_ds_inst": { - "module": "O_BUF_DS", - "ports": { - "I": [ - { - "Actual": "ram_out", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_N": [ - { - "Actual": "q_n", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_P": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "obuft_ds_inst": { - "module": "O_BUFT_DS", - "ports": { - "I": [ - { - "Actual": "ff_inst1.Q", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_N": [ - { - "Actual": "buft_out_n", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_P": [ - { - "Actual": "buft_out_p", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "T": [ - { - "Actual": "ibuf_obuft_oe", - "lsb": 0, - "msb": 0 - } - ] - } - } - } -} diff --git a/design_edit/Tests/primitive_example_design_2/gold/io_config.json b/design_edit/Tests/primitive_example_design_2/gold/io_config.json deleted file mode 100644 index 8d2f92929..000000000 --- a/design_edit/Tests/primitive_example_design_2/gold/io_config.json +++ /dev/null @@ -1,816 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " IN: \\clk (offset: 0, width: 1)", - " Connected \\clk to \\I_BUF ($iopadmap$primitive_example_design_2.clk)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\G (offset: 0, width: 1)", - " Connected \\G to \\I_BUF ($iopadmap$primitive_example_design_2.G)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\P (offset: 0, width: 1)", - " Connected \\P to \\I_BUF ($iopadmap$primitive_example_design_2.P)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " OUT: \\buft_out_n (offset: 0, width: 1)", - " Connected \\buft_out_n to \\O_BUF ($iopadmap$primitive_example_design_2.buft_out_n)", - " OUT: \\buft_out_p (offset: 0, width: 1)", - " Connected \\buft_out_p to \\O_BUF ($iopadmap$primitive_example_design_2.buft_out_p)", - " IN: \\ibuf0_en (offset: 0, width: 1)", - " Connected \\ibuf0_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf0_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf10_en (offset: 0, width: 1)", - " Connected \\ibuf10_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf10_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf11_en (offset: 0, width: 1)", - " Connected \\ibuf11_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf11_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf12_en (offset: 0, width: 1)", - " Connected \\ibuf12_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf12_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf13_en (offset: 0, width: 1)", - " Connected \\ibuf13_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf13_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf14_en (offset: 0, width: 1)", - " Connected \\ibuf14_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf14_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf15_en (offset: 0, width: 1)", - " Connected \\ibuf15_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf15_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf16_en (offset: 0, width: 1)", - " Connected \\ibuf16_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf16_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf1_en (offset: 0, width: 1)", - " Connected \\ibuf1_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf1_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf2_en (offset: 0, width: 1)", - " Connected \\ibuf2_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf2_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf3_en (offset: 0, width: 1)", - " Connected \\ibuf3_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf3_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf4_en (offset: 0, width: 1)", - " Connected \\ibuf4_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf4_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf5_en (offset: 0, width: 1)", - " Connected \\ibuf5_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf5_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf6_en (offset: 0, width: 1)", - " Connected \\ibuf6_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf6_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf7_en (offset: 0, width: 1)", - " Connected \\ibuf7_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf7_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf8_en (offset: 0, width: 1)", - " Connected \\ibuf8_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf8_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ibuf9_en (offset: 0, width: 1)", - " Connected \\ibuf9_en to \\I_BUF ($iopadmap$primitive_example_design_2.ibuf9_en)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\in_n (offset: 0, width: 3)", - " Connected \\in_n [0] to \\I_BUF ($iopadmap$primitive_example_design_2.in_n)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\in_n [1] to \\I_BUF ($iopadmap$primitive_example_design_2.in_n_1)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\in_n [2] to \\I_BUF ($iopadmap$primitive_example_design_2.in_n_2)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\in_p (offset: 0, width: 3)", - " Connected \\in_p [0] to \\I_BUF ($iopadmap$primitive_example_design_2.in_p)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\in_p [1] to \\I_BUF ($iopadmap$primitive_example_design_2.in_p_1)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\in_p [2] to \\I_BUF ($iopadmap$primitive_example_design_2.in_p_2)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\mux1_sel_n (offset: 0, width: 1)", - " Connected \\mux1_sel_n to \\I_BUF ($iopadmap$primitive_example_design_2.mux1_sel_n)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\mux1_sel_p (offset: 0, width: 1)", - " Connected \\mux1_sel_p to \\I_BUF ($iopadmap$primitive_example_design_2.mux1_sel_p)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\mux2_sel_n (offset: 0, width: 1)", - " Connected \\mux2_sel_n to \\I_BUF ($iopadmap$primitive_example_design_2.mux2_sel_n)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\mux2_sel_p (offset: 0, width: 1)", - " Connected \\mux2_sel_p to \\I_BUF ($iopadmap$primitive_example_design_2.mux2_sel_p)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\obuft_oe (offset: 0, width: 1)", - " Connected \\obuft_oe to \\I_BUF ($iopadmap$primitive_example_design_2.obuft_oe)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " OUT: \\q_n (offset: 0, width: 1)", - " Connected \\q_n to \\O_BUF ($iopadmap$primitive_example_design_2.q_n)", - " OUT: \\q_p (offset: 0, width: 1)", - " Connected \\q_p to \\O_BUF ($iopadmap$primitive_example_design_2.q_p)", - " IN: \\ram_addr (offset: 0, width: 6)", - " Connected \\ram_addr [0] to \\I_BUF ($iopadmap$primitive_example_design_2.ram_addr)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [1] to \\I_BUF ($iopadmap$primitive_example_design_2.ram_addr_1)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [2] to \\I_BUF ($iopadmap$primitive_example_design_2.ram_addr_2)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [3] to \\I_BUF ($iopadmap$primitive_example_design_2.ram_addr_3)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [4] to \\I_BUF ($iopadmap$primitive_example_design_2.ram_addr_4)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Connected \\ram_addr [5] to \\I_BUF ($iopadmap$primitive_example_design_2.ram_addr_5)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\ram_we (offset: 0, width: 1)", - " Connected \\ram_we to \\I_BUF ($iopadmap$primitive_example_design_2.ram_we)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\rst_n (offset: 0, width: 1)", - " Connected \\rst_n to \\I_BUF ($iopadmap$primitive_example_design_2.rst_n)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " IN: \\rst_p (offset: 0, width: 1)", - " Connected \\rst_p to \\I_BUF ($iopadmap$primitive_example_design_2.rst_p)", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Trace Clock Buffer", - " IN Port: \\clk", - " Connected $auto$clkbufmap.cc:261:execute$656", - " Additional Connection: $auto$clkbufmap.cc:262:execute$657", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.clk", - "linked_object" : "clk", - "location" : "", - "connectivity" : { - "I" : "clk", - "O" : "$iopadmap$clk" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk_#0", - "linked_object" : "clk", - "location" : "", - "connectivity" : { - "I" : "$iopadmap$clk", - "O" : "$auto$clkbufmap.cc:262:execute$657" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:261:execute$656", - "linked_object" : "clk", - "location" : "", - "connectivity" : { - "I" : "$auto$clkbufmap.cc:262:execute$657", - "O" : "$auto$clkbufmap.cc:294:execute$658" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.G", - "linked_object" : "G", - "location" : "", - "connectivity" : { - "I" : "G", - "O" : "$iopadmap$G" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.P", - "linked_object" : "P", - "location" : "", - "connectivity" : { - "I" : "P", - "O" : "$iopadmap$P" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_2.buft_out_n", - "linked_object" : "buft_out_n", - "location" : "", - "connectivity" : { - "I" : "$iopadmap$buft_out_n", - "O" : "buft_out_n" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_2.buft_out_p", - "linked_object" : "buft_out_p", - "location" : "", - "connectivity" : { - "I" : "$iopadmap$buft_out_p", - "O" : "buft_out_p" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf0_en", - "linked_object" : "ibuf0_en", - "location" : "", - "connectivity" : { - "I" : "ibuf0_en", - "O" : "$iopadmap$ibuf0_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf10_en", - "linked_object" : "ibuf10_en", - "location" : "", - "connectivity" : { - "I" : "ibuf10_en", - "O" : "$iopadmap$ibuf10_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf11_en", - "linked_object" : "ibuf11_en", - "location" : "", - "connectivity" : { - "I" : "ibuf11_en", - "O" : "$iopadmap$ibuf11_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf12_en", - "linked_object" : "ibuf12_en", - "location" : "", - "connectivity" : { - "I" : "ibuf12_en", - "O" : "$iopadmap$ibuf12_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf13_en", - "linked_object" : "ibuf13_en", - "location" : "", - "connectivity" : { - "I" : "ibuf13_en", - "O" : "$iopadmap$ibuf13_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf14_en", - "linked_object" : "ibuf14_en", - "location" : "", - "connectivity" : { - "I" : "ibuf14_en", - "O" : "$iopadmap$ibuf14_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf15_en", - "linked_object" : "ibuf15_en", - "location" : "", - "connectivity" : { - "I" : "ibuf15_en", - "O" : "$iopadmap$ibuf15_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf16_en", - "linked_object" : "ibuf16_en", - "location" : "", - "connectivity" : { - "I" : "ibuf16_en", - "O" : "$iopadmap$ibuf16_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf1_en", - "linked_object" : "ibuf1_en", - "location" : "", - "connectivity" : { - "I" : "ibuf1_en", - "O" : "$iopadmap$ibuf1_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf2_en", - "linked_object" : "ibuf2_en", - "location" : "", - "connectivity" : { - "I" : "ibuf2_en", - "O" : "$iopadmap$ibuf2_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf3_en", - "linked_object" : "ibuf3_en", - "location" : "", - "connectivity" : { - "I" : "ibuf3_en", - "O" : "$iopadmap$ibuf3_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf4_en", - "linked_object" : "ibuf4_en", - "location" : "", - "connectivity" : { - "I" : "ibuf4_en", - "O" : "$iopadmap$ibuf4_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf5_en", - "linked_object" : "ibuf5_en", - "location" : "", - "connectivity" : { - "I" : "ibuf5_en", - "O" : "$iopadmap$ibuf5_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf6_en", - "linked_object" : "ibuf6_en", - "location" : "", - "connectivity" : { - "I" : "ibuf6_en", - "O" : "$iopadmap$ibuf6_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf7_en", - "linked_object" : "ibuf7_en", - "location" : "", - "connectivity" : { - "I" : "ibuf7_en", - "O" : "$iopadmap$ibuf7_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf8_en", - "linked_object" : "ibuf8_en", - "location" : "", - "connectivity" : { - "I" : "ibuf8_en", - "O" : "$iopadmap$ibuf8_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ibuf9_en", - "linked_object" : "ibuf9_en", - "location" : "", - "connectivity" : { - "I" : "ibuf9_en", - "O" : "$iopadmap$ibuf9_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.in_n", - "linked_object" : "in_n [0]", - "location" : "", - "connectivity" : { - "I" : "in_n [0]", - "O" : "$iopadmap$in_n [0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.in_n_1", - "linked_object" : "in_n [1]", - "location" : "", - "connectivity" : { - "I" : "in_n [1]", - "O" : "$iopadmap$in_n [1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.in_n_2", - "linked_object" : "in_n [2]", - "location" : "", - "connectivity" : { - "I" : "in_n [2]", - "O" : "$iopadmap$in_n [2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.in_p", - "linked_object" : "in_p [0]", - "location" : "", - "connectivity" : { - "I" : "in_p [0]", - "O" : "$iopadmap$in_p [0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.in_p_1", - "linked_object" : "in_p [1]", - "location" : "", - "connectivity" : { - "I" : "in_p [1]", - "O" : "$iopadmap$in_p [1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.in_p_2", - "linked_object" : "in_p [2]", - "location" : "", - "connectivity" : { - "I" : "in_p [2]", - "O" : "$iopadmap$in_p [2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.mux1_sel_n", - "linked_object" : "mux1_sel_n", - "location" : "", - "connectivity" : { - "I" : "mux1_sel_n", - "O" : "$iopadmap$mux1_sel_n" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.mux1_sel_p", - "linked_object" : "mux1_sel_p", - "location" : "", - "connectivity" : { - "I" : "mux1_sel_p", - "O" : "$iopadmap$mux1_sel_p" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.mux2_sel_n", - "linked_object" : "mux2_sel_n", - "location" : "", - "connectivity" : { - "I" : "mux2_sel_n", - "O" : "$iopadmap$mux2_sel_n" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.mux2_sel_p", - "linked_object" : "mux2_sel_p", - "location" : "", - "connectivity" : { - "I" : "mux2_sel_p", - "O" : "$iopadmap$mux2_sel_p" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.obuft_oe", - "linked_object" : "obuft_oe", - "location" : "", - "connectivity" : { - "I" : "obuft_oe", - "O" : "$iopadmap$obuft_oe" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_2.q_n", - "linked_object" : "q_n", - "location" : "", - "connectivity" : { - "I" : "$iopadmap$q_n", - "O" : "q_n" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_2.q_p", - "linked_object" : "q_p", - "location" : "", - "connectivity" : { - "I" : "$iopadmap$q_p", - "O" : "q_p" - }, - "parameters" : { - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ram_addr", - "linked_object" : "ram_addr [0]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [0]", - "O" : "$iopadmap$ram_addr [0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ram_addr_1", - "linked_object" : "ram_addr [1]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [1]", - "O" : "$iopadmap$ram_addr [1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ram_addr_2", - "linked_object" : "ram_addr [2]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [2]", - "O" : "$iopadmap$ram_addr [2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ram_addr_3", - "linked_object" : "ram_addr [3]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [3]", - "O" : "$iopadmap$ram_addr [3]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ram_addr_4", - "linked_object" : "ram_addr [4]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [4]", - "O" : "$iopadmap$ram_addr [4]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ram_addr_5", - "linked_object" : "ram_addr [5]", - "location" : "", - "connectivity" : { - "I" : "ram_addr [5]", - "O" : "$iopadmap$ram_addr [5]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.ram_we", - "linked_object" : "ram_we", - "location" : "", - "connectivity" : { - "I" : "ram_we", - "O" : "$iopadmap$ram_we" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.rst_n", - "linked_object" : "rst_n", - "location" : "", - "connectivity" : { - "I" : "rst_n", - "O" : "$iopadmap$rst_n" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_2.rst_p", - "linked_object" : "rst_p", - "location" : "", - "connectivity" : { - "I" : "rst_p", - "O" : "$iopadmap$rst_p" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - }, - "properties" : { - } - } - ] -} diff --git a/design_edit/Tests/primitive_example_design_2/gold/primitive_example_design_2_post_synth.eblif b/design_edit/Tests/primitive_example_design_2/gold/primitive_example_design_2_post_synth.eblif deleted file mode 100644 index a87a9d4bb..000000000 --- a/design_edit/Tests/primitive_example_design_2/gold/primitive_example_design_2_post_synth.eblif +++ /dev/null @@ -1,91 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_primitive_example_design_2 -.inputs i_buf_out[0] i_buf_out[1] i_buf_out[2] clk_buf_out rst_i_buf_out i_buf_mux1_sel i_buf_mux2_sel p_ibuf g_ibuf ram_inst.addr[0] ram_inst.addr[1] ram_inst.addr[2] ram_inst.addr[3] ram_inst.addr[4] ram_inst.addr[5] ram_inst.we $iopadmap$clk -.outputs ram_out ff_inst1.Q $auto$clkbufmap.cc:262:execute$657 -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:294:execute$658 D=ram_inst.we E=$true Q=$auto$memory_dff.cc:778:handle_rd_port_addr$44 R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:294:execute$658 D=Q_buff_in E=$true Q=$auto$memory_dff.cc:780:handle_rd_port_addr$46[0] R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:294:execute$658 D=ff_inst1.D E=$true Q=ff_inst1.Q R=$true -.subckt LUT3 A[0]=i_buf_out[2] A[1]=i_buf_out[0] A[2]=i_buf_out[1] Y=lut_out -.param INIT_VALUE 00111110 -.subckt LUT2 A[0]=dffnre_out A[1]=i_buf_mux1_sel Y=out -.param INIT_VALUE 1001 -.subckt LUT3 A[0]=ff_inst1.D A[1]=acc_out A[2]=i_buf_mux2_sel Y=mux2_out -.param INIT_VALUE 10101100 -.subckt LUT3 A[0]=$auto$memory_dff.cc:780:handle_rd_port_addr$46[0] A[1]=$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] A[2]=$auto$memory_dff.cc:778:handle_rd_port_addr$44 Y=ram_out -.param INIT_VALUE 10101100 -.subckt LUT1 A=ram_inst.we Y=$abc$324$auto$rtlil.cc:2384:Not$55 -.param INIT_VALUE 01 -.subckt CARRY_CHAIN CIN=out COUT=acc_out G=g_ibuf O=ff_inst1.D P=p_ibuf -.subckt DFFRE C=clk_buf_out D=mux2_out E=$true Q=Q_buff_in R=rst_i_buf_out -.subckt DFFNRE C=clk_buf_out D=lut_out E=$true Q=dffnre_out R=rst_i_buf_out -.subckt TDP_RAM18KX2 ADDR_A1[0]=$false ADDR_A1[1]=$false ADDR_A1[2]=$false ADDR_A1[3]=ram_inst.addr[0] ADDR_A1[4]=ram_inst.addr[1] ADDR_A1[5]=ram_inst.addr[2] ADDR_A1[6]=ram_inst.addr[3] ADDR_A1[7]=ram_inst.addr[4] ADDR_A1[8]=ram_inst.addr[5] ADDR_A1[9]=$false ADDR_A1[10]=$false ADDR_A1[11]=$false ADDR_A1[12]=$false ADDR_A1[13]=$false ADDR_A2[0]=$undef ADDR_A2[1]=$undef ADDR_A2[2]=$undef ADDR_A2[3]=$undef ADDR_A2[4]=$undef ADDR_A2[5]=$undef ADDR_A2[6]=$undef ADDR_A2[7]=$undef ADDR_A2[8]=$undef ADDR_A2[9]=$undef ADDR_A2[10]=$undef ADDR_A2[11]=$undef ADDR_A2[12]=$undef ADDR_A2[13]=$undef ADDR_B1[0]=$false ADDR_B1[1]=$false ADDR_B1[2]=$false ADDR_B1[3]=ram_inst.addr[0] ADDR_B1[4]=ram_inst.addr[1] ADDR_B1[5]=ram_inst.addr[2] ADDR_B1[6]=ram_inst.addr[3] ADDR_B1[7]=ram_inst.addr[4] ADDR_B1[8]=ram_inst.addr[5] ADDR_B1[9]=$false ADDR_B1[10]=$false ADDR_B1[11]=$false ADDR_B1[12]=$false ADDR_B1[13]=$false ADDR_B2[0]=$undef ADDR_B2[1]=$undef ADDR_B2[2]=$undef ADDR_B2[3]=$undef ADDR_B2[4]=$undef ADDR_B2[5]=$undef ADDR_B2[6]=$undef ADDR_B2[7]=$undef ADDR_B2[8]=$undef ADDR_B2[9]=$undef ADDR_B2[10]=$undef ADDR_B2[11]=$undef ADDR_B2[12]=$undef ADDR_B2[13]=$undef BE_A1[0]=$false BE_A1[1]=$false BE_A2[0]=$false BE_A2[1]=$false BE_B1[0]=ram_inst.we BE_B1[1]=$false BE_B2[0]=$undef BE_B2[1]=$undef CLK_A1=$auto$clkbufmap.cc:294:execute$658 CLK_A2=$undef CLK_B1=$auto$clkbufmap.cc:294:execute$658 CLK_B2=$undef RDATA_A1[0]=$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] RDATA_A1[1]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[1] RDATA_A1[2]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[2] RDATA_A1[3]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[3] RDATA_A1[4]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[4] RDATA_A1[5]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[5] RDATA_A1[6]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[6] RDATA_A1[7]=$auto$memory_dff.cc:785:handle_rd_port_addr$50[7] RDATA_A1[8]=$auto$memory_libmap.cc:1890:emit_port$56[8] RDATA_A1[9]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[9] RDATA_A1[10]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[10] RDATA_A1[11]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[11] RDATA_A1[12]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[12] RDATA_A1[13]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[13] RDATA_A1[14]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[14] RDATA_A1[15]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[15] RDATA_A2[0]=$techmap76\ram_inst.ram.0.0.C1DATA RDATA_A2[1]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[1] RDATA_A2[2]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[2] RDATA_A2[3]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[3] RDATA_A2[4]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[4] RDATA_A2[5]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[5] RDATA_A2[6]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[6] RDATA_A2[7]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[7] RDATA_A2[8]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[8] RDATA_A2[9]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[9] RDATA_A2[10]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[10] RDATA_A2[11]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[11] RDATA_A2[12]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[12] RDATA_A2[13]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[13] RDATA_A2[14]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[14] RDATA_A2[15]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[15] RDATA_B1[0]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[0] RDATA_B1[1]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[1] RDATA_B1[2]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[2] RDATA_B1[3]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[3] RDATA_B1[4]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[4] RDATA_B1[5]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[5] RDATA_B1[6]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[6] RDATA_B1[7]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[7] RDATA_B1[8]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[8] RDATA_B1[9]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[9] RDATA_B1[10]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[10] RDATA_B1[11]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[11] RDATA_B1[12]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[12] RDATA_B1[13]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[13] RDATA_B1[14]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[14] RDATA_B1[15]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[15] RDATA_B2[0]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[0] RDATA_B2[1]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[1] RDATA_B2[2]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[2] RDATA_B2[3]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[3] RDATA_B2[4]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[4] RDATA_B2[5]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[5] RDATA_B2[6]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[6] RDATA_B2[7]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[7] RDATA_B2[8]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[8] RDATA_B2[9]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[9] RDATA_B2[10]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[10] RDATA_B2[11]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[11] RDATA_B2[12]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[12] RDATA_B2[13]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[13] RDATA_B2[14]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[14] RDATA_B2[15]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[15] REN_A1=$abc$324$auto$rtlil.cc:2384:Not$55 REN_A2=$undef REN_B1=$false REN_B2=$false RPARITY_A1[0]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[16] RPARITY_A1[1]=$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[17] RPARITY_A2[0]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[16] RPARITY_A2[1]=$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[17] RPARITY_B1[0]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[16] RPARITY_B1[1]=$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA[17] RPARITY_B2[0]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[16] RPARITY_B2[1]=$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA[17] WDATA_A1[0]=$undef WDATA_A1[1]=$undef WDATA_A1[2]=$undef WDATA_A1[3]=$undef WDATA_A1[4]=$undef WDATA_A1[5]=$undef WDATA_A1[6]=$undef WDATA_A1[7]=$undef WDATA_A1[8]=$undef WDATA_A1[9]=$undef WDATA_A1[10]=$undef WDATA_A1[11]=$undef WDATA_A1[12]=$undef WDATA_A1[13]=$undef WDATA_A1[14]=$undef WDATA_A1[15]=$undef WDATA_A2[0]=$undef WDATA_A2[1]=$undef WDATA_A2[2]=$undef WDATA_A2[3]=$undef WDATA_A2[4]=$undef WDATA_A2[5]=$undef WDATA_A2[6]=$undef WDATA_A2[7]=$undef WDATA_A2[8]=$undef WDATA_A2[9]=$undef WDATA_A2[10]=$undef WDATA_A2[11]=$undef WDATA_A2[12]=$undef WDATA_A2[13]=$undef WDATA_A2[14]=$undef WDATA_A2[15]=$undef WDATA_B1[0]=Q_buff_in WDATA_B1[1]=$false WDATA_B1[2]=$false WDATA_B1[3]=$false WDATA_B1[4]=$false WDATA_B1[5]=$false WDATA_B1[6]=$false WDATA_B1[7]=$false WDATA_B1[8]=$undef WDATA_B1[9]=$undef WDATA_B1[10]=$undef WDATA_B1[11]=$undef WDATA_B1[12]=$undef WDATA_B1[13]=$undef WDATA_B1[14]=$undef WDATA_B1[15]=$undef WDATA_B2[0]=$undef WDATA_B2[1]=$undef WDATA_B2[2]=$undef WDATA_B2[3]=$undef WDATA_B2[4]=$undef WDATA_B2[5]=$undef WDATA_B2[6]=$undef WDATA_B2[7]=$undef WDATA_B2[8]=$undef WDATA_B2[9]=$undef WDATA_B2[10]=$undef WDATA_B2[11]=$undef WDATA_B2[12]=$undef WDATA_B2[13]=$undef WDATA_B2[14]=$undef WDATA_B2[15]=$undef WEN_A1=$false WEN_A2=$false WEN_B1=ram_inst.we WEN_B2=$undef WPARITY_A1[0]=$undef WPARITY_A1[1]=$undef WPARITY_A2[0]=$undef WPARITY_A2[1]=$undef WPARITY_B1[0]=$undef WPARITY_B1[1]=$undef WPARITY_B2[0]=$undef WPARITY_B2[1]=$undef -.param INIT1 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-.param INIT1_PARITY 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -.param INIT2 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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-.param INIT2_PARITY 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -.param READ_WIDTH_A1 00000000000000000000000000001001 -.param READ_WIDTH_A2 00000000000000000000000000000001 -.param READ_WIDTH_B1 00000000000000000000000000001001 -.param READ_WIDTH_B2 00000000000000000000000000000001 -.param WRITE_WIDTH_A1 00000000000000000000000000001001 -.param WRITE_WIDTH_A2 00000000000000000000000000000001 -.param WRITE_WIDTH_B1 00000000000000000000000000001001 -.param WRITE_WIDTH_B2 00000000000000000000000000000001 -.names $techmap76\ram_inst.ram.0.0.C1DATA $techmap76\ram_inst.ram.0.0.PORT_A2_RDATA[0] -1 1 -.names $abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[0] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[1] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[1] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[2] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[2] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[3] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[3] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[4] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[4] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[5] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[5] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[6] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[6] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[7] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[7] -1 1 -.names $auto$memory_libmap.cc:1890:emit_port$56[8] $techmap76\ram_inst.ram.0.0.PORT_A1_RDATA[8] -1 1 -.names $abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] $auto$memory_libmap.cc:1890:emit_port$56[0] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[1] $auto$memory_libmap.cc:1890:emit_port$56[1] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[2] $auto$memory_libmap.cc:1890:emit_port$56[2] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[3] $auto$memory_libmap.cc:1890:emit_port$56[3] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[4] $auto$memory_libmap.cc:1890:emit_port$56[4] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[5] $auto$memory_libmap.cc:1890:emit_port$56[5] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[6] $auto$memory_libmap.cc:1890:emit_port$56[6] -1 1 -.names $auto$memory_dff.cc:785:handle_rd_port_addr$50[7] $auto$memory_libmap.cc:1890:emit_port$56[7] -1 1 -.names $abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] $auto$memory_dff.cc:785:handle_rd_port_addr$50[0] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[1] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[2] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[3] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[4] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[5] -1 1 -.names $auto$memory_dff.cc:780:handle_rd_port_addr$46[7] $auto$memory_dff.cc:780:handle_rd_port_addr$46[6] -1 1 -.names $iopadmap$clk $auto$clkbufmap.cc:262:execute$657 -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_2/gold/primitive_example_design_2_post_synth.v b/design_edit/Tests/primitive_example_design_2/gold/primitive_example_design_2_post_synth.v deleted file mode 100644 index 4ad906006..000000000 --- a/design_edit/Tests/primitive_example_design_2/gold/primitive_example_design_2_post_synth.v +++ /dev/null @@ -1,547 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_primitive_example_design_2(i_buf_out, clk_buf_out, rst_i_buf_out, i_buf_mux1_sel, i_buf_mux2_sel, p_ibuf, g_ibuf, ram_out, \ram_inst.addr , \ram_inst.we , \ff_inst1.Q , \$auto$clkbufmap.cc:262:execute$657 , \$iopadmap$clk ); - input \$iopadmap$clk ; - output \$auto$clkbufmap.cc:262:execute$657 ; - input clk_buf_out; - output \ff_inst1.Q ; - input g_ibuf; - input i_buf_mux1_sel; - input i_buf_mux2_sel; - input [2:0] i_buf_out; - input p_ibuf; - input [5:0] \ram_inst.addr ; - input \ram_inst.we ; - output ram_out; - input rst_i_buf_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap686$iopadmap$primitive_example_design_2.ibuf5_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap686$iopadmap$primitive_example_design_2.ibuf5_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap685$iopadmap$primitive_example_design_2.ibuf4_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap685$iopadmap$primitive_example_design_2.ibuf4_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap685$iopadmap$primitive_example_design_2.ibuf4_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap684$iopadmap$primitive_example_design_2.in_p_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap684$iopadmap$primitive_example_design_2.in_p_2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap684$iopadmap$primitive_example_design_2.in_p_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap683$iopadmap$primitive_example_design_2.ibuf3_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap683$iopadmap$primitive_example_design_2.ibuf3_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap683$iopadmap$primitive_example_design_2.ibuf3_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap682$iopadmap$primitive_example_design_2.ibuf2_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap682$iopadmap$primitive_example_design_2.ibuf2_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap682$iopadmap$primitive_example_design_2.ibuf2_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap681$iopadmap$primitive_example_design_2.ram_addr_3.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap681$iopadmap$primitive_example_design_2.ram_addr_3.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap681$iopadmap$primitive_example_design_2.ram_addr_3.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap680$iopadmap$primitive_example_design_2.ibuf1_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap680$iopadmap$primitive_example_design_2.ibuf1_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap680$iopadmap$primitive_example_design_2.ibuf1_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap679$iopadmap$primitive_example_design_2.mux1_sel_n.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap679$iopadmap$primitive_example_design_2.mux1_sel_n.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap679$iopadmap$primitive_example_design_2.mux1_sel_n.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap678$iopadmap$primitive_example_design_2.ram_addr_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap678$iopadmap$primitive_example_design_2.ram_addr_2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap678$iopadmap$primitive_example_design_2.ram_addr_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap677$iopadmap$primitive_example_design_2.in_n.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap677$iopadmap$primitive_example_design_2.in_n.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap677$iopadmap$primitive_example_design_2.in_n.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap676$iopadmap$primitive_example_design_2.in_n_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap676$iopadmap$primitive_example_design_2.in_n_1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap676$iopadmap$primitive_example_design_2.in_n_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap675$iopadmap$primitive_example_design_2.in_n_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap675$iopadmap$primitive_example_design_2.in_n_2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap675$iopadmap$primitive_example_design_2.in_n_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap674$iopadmap$primitive_example_design_2.ibuf14_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap674$iopadmap$primitive_example_design_2.ibuf14_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap674$iopadmap$primitive_example_design_2.ibuf14_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap673$iopadmap$primitive_example_design_2.ibuf11_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap673$iopadmap$primitive_example_design_2.ibuf11_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap673$iopadmap$primitive_example_design_2.ibuf11_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap672$iopadmap$primitive_example_design_2.in_p.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap672$iopadmap$primitive_example_design_2.in_p.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap672$iopadmap$primitive_example_design_2.in_p.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap671$iopadmap$primitive_example_design_2.ram_addr.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap671$iopadmap$primitive_example_design_2.ram_addr.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap671$iopadmap$primitive_example_design_2.ram_addr.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap670$iopadmap$primitive_example_design_2.buft_out_n.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap670$iopadmap$primitive_example_design_2.buft_out_n.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap670$iopadmap$primitive_example_design_2.buft_out_n.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap669$iopadmap$primitive_example_design_2.ram_addr_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap669$iopadmap$primitive_example_design_2.ram_addr_1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap669$iopadmap$primitive_example_design_2.ram_addr_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap668$iopadmap$primitive_example_design_2.P.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap668$iopadmap$primitive_example_design_2.P.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap668$iopadmap$primitive_example_design_2.P.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap667$iopadmap$primitive_example_design_2.in_p_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap667$iopadmap$primitive_example_design_2.in_p_1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap667$iopadmap$primitive_example_design_2.in_p_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap666$iopadmap$primitive_example_design_2.ibuf9_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap666$iopadmap$primitive_example_design_2.ibuf9_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap666$iopadmap$primitive_example_design_2.ibuf9_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap665$iopadmap$primitive_example_design_2.rst_p.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap665$iopadmap$primitive_example_design_2.rst_p.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap665$iopadmap$primitive_example_design_2.rst_p.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap664$iopadmap$primitive_example_design_2.clk.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap664$iopadmap$primitive_example_design_2.clk.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap664$iopadmap$primitive_example_design_2.clk.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap663$iopadmap$primitive_example_design_2.G.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap663$iopadmap$primitive_example_design_2.G.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap663$iopadmap$primitive_example_design_2.G.O ; - wire \$iopadmap$clk ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap690$iopadmap$primitive_example_design_2.ram_addr_5.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap691$iopadmap$primitive_example_design_2.ram_we.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap690$iopadmap$primitive_example_design_2.ram_addr_5.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap686$iopadmap$primitive_example_design_2.ibuf5_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap687$iopadmap$primitive_example_design_2.ram_addr_4.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap694$iopadmap$primitive_example_design_2.buft_out_p.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap695$iopadmap$primitive_example_design_2.mux1_sel_p.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap697$iopadmap$primitive_example_design_2.ibuf7_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap697$iopadmap$primitive_example_design_2.ibuf7_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap695$iopadmap$primitive_example_design_2.mux1_sel_p.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap696$iopadmap$primitive_example_design_2.ibuf13_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap696$iopadmap$primitive_example_design_2.ibuf13_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap694$iopadmap$primitive_example_design_2.buft_out_p.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap692$iopadmap$primitive_example_design_2.rst_n.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap695$iopadmap$primitive_example_design_2.mux1_sel_p.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap693$iopadmap$primitive_example_design_2.ibuf12_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap692$iopadmap$primitive_example_design_2.rst_n.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap691$iopadmap$primitive_example_design_2.ram_we.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap692$iopadmap$primitive_example_design_2.rst_n.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap689$iopadmap$primitive_example_design_2.ibuf6_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap691$iopadmap$primitive_example_design_2.ram_we.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap689$iopadmap$primitive_example_design_2.ibuf6_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap696$iopadmap$primitive_example_design_2.ibuf13_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap693$iopadmap$primitive_example_design_2.ibuf12_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap690$iopadmap$primitive_example_design_2.ram_addr_5.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap693$iopadmap$primitive_example_design_2.ibuf12_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap697$iopadmap$primitive_example_design_2.ibuf7_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap689$iopadmap$primitive_example_design_2.ibuf6_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap688$iopadmap$primitive_example_design_2.ibuf10_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap687$iopadmap$primitive_example_design_2.ram_addr_4.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap687$iopadmap$primitive_example_design_2.ram_addr_4.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap688$iopadmap$primitive_example_design_2.ibuf10_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap688$iopadmap$primitive_example_design_2.ibuf10_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap698$iopadmap$primitive_example_design_2.mux2_sel_p.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap694$iopadmap$primitive_example_design_2.buft_out_p.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap662$auto$clkbufmap.cc:261:execute$656.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap661$auto$clkbufmap.cc:261:execute$659.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap661$auto$clkbufmap.cc:261:execute$659.O ; - wire \$auto$clkbufmap.cc:294:execute$658 ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap698$iopadmap$primitive_example_design_2.mux2_sel_p.I ; - wire \$auto$clkbufmap.cc:262:execute$657 ; - wire \$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] ; - wire \$abc$324$auto$rtlil.cc:2384:Not$55 ; - (* keep = 32'h00000001 *) - wire \$auto$memory_dff.cc:778:handle_rd_port_addr$44 ; - (* keep = 32'h00000001 *) - (* unused_bits = "1 2 3 4 5 6 7" *) - wire [7:0] \$auto$memory_dff.cc:780:handle_rd_port_addr$46 ; - (* unused_bits = "1 2 3 4 5 6 7" *) - wire [7:0] \$auto$memory_dff.cc:785:handle_rd_port_addr$50 ; - (* unused_bits = "1 2 3 4 5 6 7 8" *) - wire [8:0] \$auto$memory_libmap.cc:1890:emit_port$56 ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:461.28-461.34" *) - (* unused_bits = "0" *) - wire \$techmap76\ram_inst.ram.0.0.C1DATA ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:498.14-498.27" *) - (* unused_bits = "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] \$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:500.14-500.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] \$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:499.14-499.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] \$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:501.14-501.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] \$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap699$iopadmap$primitive_example_design_2.q_p.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap706$iopadmap$primitive_example_design_2.ibuf8_en.I ; - (* src = "./rtl/primitive_example_design_2.v:22.10-22.19" *) - wire Q_buff_in; - (* src = "./rtl/primitive_example_design_2.v:20.18-20.25" *) - wire acc_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap699$iopadmap$primitive_example_design_2.q_p.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap703$iopadmap$primitive_example_design_2.mux2_sel_n.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap705$iopadmap$primitive_example_design_2.ibuf16_en.EN ; - (* src = "./rtl/primitive_example_design_2.v:15.21-15.32" *) - (* src = "./rtl/primitive_example_design_2.v:15.21-15.32" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_2.v:19.10-19.20" *) - wire dffnre_out; - (* hdlname = "ff_inst1 D" *) - (* src = "./rtl/primitive_example_design_2.v:49.15-49.66|./rtl/primitive_example_design_2.v:80.11-80.12" *) - wire \ff_inst1.D ; - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:49.15-49.66|./rtl/primitive_example_design_2.v:81.16-81.17" *) - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:49.15-49.66|./rtl/primitive_example_design_2.v:81.16-81.17" *) - wire \ff_inst1.Q ; - (* src = "./rtl/primitive_example_design_2.v:18.21-18.27" *) - (* src = "./rtl/primitive_example_design_2.v:18.21-18.27" *) - wire g_ibuf; - (* src = "./rtl/primitive_example_design_2.v:17.24-17.38" *) - (* src = "./rtl/primitive_example_design_2.v:17.24-17.38" *) - wire i_buf_mux1_sel; - (* src = "./rtl/primitive_example_design_2.v:17.39-17.53" *) - (* src = "./rtl/primitive_example_design_2.v:17.39-17.53" *) - wire i_buf_mux2_sel; - (* src = "./rtl/primitive_example_design_2.v:13.16-13.25" *) - (* src = "./rtl/primitive_example_design_2.v:13.16-13.25" *) - wire [2:0] i_buf_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap704$iopadmap$primitive_example_design_2.ibuf0_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap705$iopadmap$primitive_example_design_2.ibuf16_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap706$iopadmap$primitive_example_design_2.ibuf8_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap707$abc$650$auto$blifparse.cc:515:parse_blif$655.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap706$iopadmap$primitive_example_design_2.ibuf8_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap708$abc$650$auto$blifparse.cc:515:parse_blif$654.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap705$iopadmap$primitive_example_design_2.ibuf16_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap704$iopadmap$primitive_example_design_2.ibuf0_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap700$iopadmap$primitive_example_design_2.obuft_oe.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap702$iopadmap$primitive_example_design_2.ibuf15_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap701$iopadmap$primitive_example_design_2.q_n.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap702$iopadmap$primitive_example_design_2.ibuf15_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap701$iopadmap$primitive_example_design_2.q_n.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap701$iopadmap$primitive_example_design_2.q_n.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap702$iopadmap$primitive_example_design_2.ibuf15_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap704$iopadmap$primitive_example_design_2.ibuf0_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap700$iopadmap$primitive_example_design_2.obuft_oe.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap700$iopadmap$primitive_example_design_2.obuft_oe.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap703$iopadmap$primitive_example_design_2.mux2_sel_n.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap699$iopadmap$primitive_example_design_2.q_p.C ; - (* src = "./rtl/primitive_example_design_2.v:16.10-16.17" *) - wire lut_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap703$iopadmap$primitive_example_design_2.mux2_sel_n.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap698$iopadmap$primitive_example_design_2.mux2_sel_p.EN ; - (* src = "./rtl/primitive_example_design_2.v:21.10-21.18" *) - wire mux2_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap708$abc$650$auto$blifparse.cc:515:parse_blif$654.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap709$abc$650$auto$blifparse.cc:515:parse_blif$653.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap709$abc$650$auto$blifparse.cc:515:parse_blif$653.A ; - (* src = "./rtl/primitive_example_design_2.v:18.10-18.13" *) - wire out; - (* src = "./rtl/primitive_example_design_2.v:18.14-18.20" *) - (* src = "./rtl/primitive_example_design_2.v:18.14-18.20" *) - wire p_ibuf; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap710$abc$650$auto$blifparse.cc:515:parse_blif$651.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap710$abc$650$auto$blifparse.cc:515:parse_blif$651.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap711$abc$650$auto$blifparse.cc:515:parse_blif$652.A ; - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:95.27-95.31" *) - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:95.27-95.31" *) - wire [5:0] \ram_inst.addr ; - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:96.8-96.10" *) - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:96.8-96.10" *) - wire \ram_inst.we ; - (* src = "./rtl/primitive_example_design_2.v:23.10-23.17" *) - (* src = "./rtl/primitive_example_design_2.v:23.10-23.17" *) - wire ram_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap711$abc$650$auto$blifparse.cc:515:parse_blif$652.Y ; - (* src = "./rtl/primitive_example_design_2.v:17.10-17.23" *) - (* src = "./rtl/primitive_example_design_2.v:17.10-17.23" *) - wire rst_i_buf_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire \$techmap707$abc$650$auto$blifparse.cc:515:parse_blif$655.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap662$auto$clkbufmap.cc:261:execute$656.I ; - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:59.17-59.93" *) - CARRY_CHAIN carry_chain_inst ( - .CIN(out), - .COUT(acc_out), - .G(g_ibuf), - .O(\ff_inst1.D ), - .P(p_ibuf) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$341$auto$blifparse.cc:362:parse_blif$342 ( - .C(\$auto$clkbufmap.cc:294:execute$658 ), - .D(\ram_inst.we ), - .E(1'h1), - .Q(\$auto$memory_dff.cc:778:handle_rd_port_addr$44 ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:55.11-55.90" *) - DFFRE ff_inst ( - .C(clk_buf_out), - .D(mux2_out), - .E(1'h1), - .Q(Q_buff_in), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:45.12-45.92" *) - DFFNRE ffn_inst ( - .C(clk_buf_out), - .D(lut_out), - .E(1'h1), - .Q(dffnre_out), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$341$auto$blifparse.cc:362:parse_blif$343 ( - .C(\$auto$clkbufmap.cc:294:execute$658 ), - .D(Q_buff_in), - .E(1'h1), - .Q(\$auto$memory_dff.cc:780:handle_rd_port_addr$46 [0]), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$341$auto$blifparse.cc:362:parse_blif$344 ( - .C(\$auto$clkbufmap.cc:294:execute$658 ), - .D(\ff_inst1.D ), - .E(1'h1), - .Q(\ff_inst1.Q ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'hac) - ) \$abc$650$auto$blifparse.cc:515:parse_blif$653 ( - .Y(mux2_out), - .A({ i_buf_mux2_sel, acc_out, \ff_inst1.D }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h3e) - ) \$abc$650$auto$blifparse.cc:515:parse_blif$651 ( - .Y(lut_out), - .A({ i_buf_out[1:0], i_buf_out[2] }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'hac) - ) \$abc$650$auto$blifparse.cc:515:parse_blif$654 ( - .Y(ram_out), - .A({ \$auto$memory_dff.cc:778:handle_rd_port_addr$44 , \$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] , \$auto$memory_dff.cc:780:handle_rd_port_addr$46 [0] }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:17.38-17.69" *) - LUT1 #( - .INIT_VALUE(2'h1) - ) \$abc$650$auto$blifparse.cc:515:parse_blif$655 ( - .Y(\$abc$324$auto$rtlil.cc:2384:Not$55 ), - .A(\ram_inst.we ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h9) - ) \$abc$650$auto$blifparse.cc:515:parse_blif$652 ( - .Y(out), - .A({ i_buf_mux1_sel, dffnre_out }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:645.7-684.2" *) - TDP_RAM18KX2 #( - .INIT1(16384'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT1_PARITY(2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT2(16384'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT2_PARITY(2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .READ_WIDTH_A1(32'h00000009), - .READ_WIDTH_A2(32'sh00000001), - .READ_WIDTH_B1(32'h00000009), - .READ_WIDTH_B2(32'sh00000001), - .WRITE_WIDTH_A1(32'h00000009), - .WRITE_WIDTH_A2(32'sh00000001), - .WRITE_WIDTH_B1(32'h00000009), - .WRITE_WIDTH_B2(32'sh00000001) - ) \ram_inst.ram.0.0 ( - .ADDR_A1({ 5'h00, \ram_inst.addr , 3'h0 }), - .ADDR_A2(14'hxxxx), - .ADDR_B1({ 5'h00, \ram_inst.addr , 3'h0 }), - .ADDR_B2(14'hxxxx), - .BE_A1(2'h0), - .BE_A2(2'h0), - .BE_B1({ 1'h0, \ram_inst.we }), - .BE_B2(2'hx), - .CLK_A1(\$auto$clkbufmap.cc:294:execute$658 ), - .CLK_A2(1'hx), - .CLK_B1(\$auto$clkbufmap.cc:294:execute$658 ), - .CLK_B2(1'hx), - .RDATA_A1({ \$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA [15:9], \$auto$memory_libmap.cc:1890:emit_port$56 [8], \$auto$memory_dff.cc:785:handle_rd_port_addr$50 [7:1], \$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] }), - .RDATA_A2({ \$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA [15:1], \$techmap76\ram_inst.ram.0.0.C1DATA }), - .RDATA_B1(\$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA [15:0]), - .RDATA_B2(\$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA [15:0]), - .REN_A1(\$abc$324$auto$rtlil.cc:2384:Not$55 ), - .REN_A2(1'hx), - .REN_B1(1'h0), - .REN_B2(1'h0), - .RPARITY_A1(\$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA [17:16]), - .RPARITY_A2(\$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA [17:16]), - .RPARITY_B1(\$techmap76\ram_inst.ram.0.0.PORT_B1_RDATA [17:16]), - .RPARITY_B2(\$techmap76\ram_inst.ram.0.0.PORT_B2_RDATA [17:16]), - .WDATA_A1(16'hxxxx), - .WDATA_A2(16'hxxxx), - .WDATA_B1({ 15'bxxxxxxxx0000000, Q_buff_in }), - .WDATA_B2(16'hxxxx), - .WEN_A1(1'h0), - .WEN_A2(1'h0), - .WEN_B1(\ram_inst.we ), - .WEN_B2(1'hx), - .WPARITY_A1(2'hx), - .WPARITY_A2(2'hx), - .WPARITY_B1(2'hx), - .WPARITY_B2(2'hx) - ); - assign \$techmap76\ram_inst.ram.0.0.PORT_A2_RDATA [0] = \$techmap76\ram_inst.ram.0.0.C1DATA ; - assign \$techmap76\ram_inst.ram.0.0.PORT_A1_RDATA [8:0] = { \$auto$memory_libmap.cc:1890:emit_port$56 [8], \$auto$memory_dff.cc:785:handle_rd_port_addr$50 [7:1], \$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] }; - assign \$auto$memory_libmap.cc:1890:emit_port$56 [7:0] = { \$auto$memory_dff.cc:785:handle_rd_port_addr$50 [7:1], \$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] }; - assign \$auto$memory_dff.cc:785:handle_rd_port_addr$50 [0] = \$abc$324$auto$memory_dff.cc:785:handle_rd_port_addr$50[0] ; - assign \$auto$memory_dff.cc:780:handle_rd_port_addr$46 [6:1] = { \$auto$memory_dff.cc:780:handle_rd_port_addr$46 [7], \$auto$memory_dff.cc:780:handle_rd_port_addr$46 [7], \$auto$memory_dff.cc:780:handle_rd_port_addr$46 [7], \$auto$memory_dff.cc:780:handle_rd_port_addr$46 [7], \$auto$memory_dff.cc:780:handle_rd_port_addr$46 [7], \$auto$memory_dff.cc:780:handle_rd_port_addr$46 [7] }; - assign \$auto$clkbufmap.cc:262:execute$657 = \$iopadmap$clk ; -endmodule diff --git a/design_edit/Tests/primitive_example_design_2/gold/wrapper_primitive_example_design_2_post_synth.eblif b/design_edit/Tests/primitive_example_design_2/gold/wrapper_primitive_example_design_2_post_synth.eblif deleted file mode 100644 index 861adcfe4..000000000 --- a/design_edit/Tests/primitive_example_design_2/gold/wrapper_primitive_example_design_2_post_synth.eblif +++ /dev/null @@ -1,126 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model interface_primitive_example_design_2 -.inputs in_n[0] in_n[1] in_n[2] in_p[0] in_p[1] in_p[2] clk rst_n rst_p mux1_sel_n mux1_sel_p mux2_sel_n mux2_sel_p ibuf0_en ibuf1_en ibuf2_en ibuf3_en ibuf4_en ibuf5_en ibuf6_en ibuf7_en ibuf8_en ibuf9_en ibuf10_en ibuf11_en ibuf12_en ibuf13_en ibuf14_en ibuf15_en ibuf16_en P G ram_addr[0] ram_addr[1] ram_addr[2] ram_addr[3] ram_addr[4] ram_addr[5] ram_we obuft_oe ram_out ff_inst1.Q $auto$clkbufmap.cc:262:execute$657 -.outputs q_p q_n buft_out_p buft_out_n i_buf_out[0] i_buf_out[1] i_buf_out[2] clk_buf_out rst_i_buf_out i_buf_mux1_sel i_buf_mux2_sel p_ibuf g_ibuf ram_inst.addr[0] ram_inst.addr[1] ram_inst.addr[2] ram_inst.addr[3] ram_inst.addr[4] ram_inst.addr[5] ram_inst.we $iopadmap$clk -.names $false -.names $true -1 -.names $undef -.subckt CLK_BUF I=$auto$clkbufmap.cc:262:execute$657 O=$auto$clkbufmap.cc:294:execute$658 -.subckt CLK_BUF I=$auto$clkbufmap.cc:262:execute$660 O=clk_buf_out -.subckt I_BUF EN=$true I=G O=$iopadmap$G -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=P O=$iopadmap$P -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$iopadmap$buft_out_n O=buft_out_n -.subckt O_BUF I=$iopadmap$buft_out_p O=buft_out_p -.subckt I_BUF EN=$true I=clk O=$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf0_en O=$iopadmap$ibuf0_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf10_en O=$iopadmap$ibuf10_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf11_en O=$iopadmap$ibuf11_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf12_en O=$iopadmap$ibuf12_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf13_en O=$iopadmap$ibuf13_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf14_en O=$iopadmap$ibuf14_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf15_en O=$iopadmap$ibuf15_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf16_en O=$iopadmap$ibuf16_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf1_en O=$iopadmap$ibuf1_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf2_en O=$iopadmap$ibuf2_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf3_en O=$iopadmap$ibuf3_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf4_en O=$iopadmap$ibuf4_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf5_en O=$iopadmap$ibuf5_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf6_en O=$iopadmap$ibuf6_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf7_en O=$iopadmap$ibuf7_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf8_en O=$iopadmap$ibuf8_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ibuf9_en O=$iopadmap$ibuf9_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=in_n[0] O=$iopadmap$in_n[0] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=in_n[1] O=$iopadmap$in_n[1] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=in_n[2] O=$iopadmap$in_n[2] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=in_p[0] O=$iopadmap$in_p[0] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=in_p[1] O=$iopadmap$in_p[1] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=in_p[2] O=$iopadmap$in_p[2] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=mux1_sel_n O=$iopadmap$mux1_sel_n -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=mux1_sel_p O=$iopadmap$mux1_sel_p -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=mux2_sel_n O=$iopadmap$mux2_sel_n -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=mux2_sel_p O=$iopadmap$mux2_sel_p -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=obuft_oe O=$iopadmap$obuft_oe -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$iopadmap$q_n O=q_n -.subckt O_BUF I=$iopadmap$q_p O=q_p -.subckt I_BUF EN=$true I=ram_addr[0] O=$iopadmap$ram_addr[0] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[1] O=$iopadmap$ram_addr[1] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[2] O=$iopadmap$ram_addr[2] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[3] O=$iopadmap$ram_addr[3] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[4] O=$iopadmap$ram_addr[4] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_addr[5] O=$iopadmap$ram_addr[5] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=ram_we O=$iopadmap$ram_we -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=rst_n O=$iopadmap$rst_n -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=rst_p O=$iopadmap$rst_p -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$iopadmap$ibuf0_en I=$auto$clkbufmap.cc:294:execute$658 O=$auto$clkbufmap.cc:262:execute$660 -.subckt I_BUF_DS EN=$iopadmap$ibuf1_en I_N=$iopadmap$in_n[0] I_P=$iopadmap$in_p[0] O=i_buf_out[0] -.subckt I_BUF_DS EN=$iopadmap$ibuf2_en I_N=$iopadmap$in_n[1] I_P=$iopadmap$in_p[1] O=i_buf_out[1] -.subckt I_BUF_DS EN=$iopadmap$ibuf3_en I_N=$iopadmap$in_n[2] I_P=$iopadmap$in_p[2] O=i_buf_out[2] -.subckt I_BUF_DS EN=$iopadmap$ibuf4_en I_N=$iopadmap$rst_n I_P=$iopadmap$rst_p O=rst_i_buf_out -.subckt I_BUF_DS EN=$iopadmap$ibuf5_en I_N=$iopadmap$mux1_sel_n I_P=$iopadmap$mux1_sel_p O=i_buf_mux1_sel -.subckt I_BUF_DS EN=$iopadmap$ibuf6_en I_N=$iopadmap$mux2_sel_n I_P=$iopadmap$mux2_sel_p O=i_buf_mux2_sel -.subckt I_BUF EN=$iopadmap$ibuf10_en I=$iopadmap$ram_addr[0] O=ram_inst.addr[0] -.subckt I_BUF EN=$iopadmap$ibuf11_en I=$iopadmap$ram_addr[1] O=ram_inst.addr[1] -.subckt I_BUF EN=$iopadmap$ibuf12_en I=$iopadmap$ram_addr[2] O=ram_inst.addr[2] -.subckt I_BUF EN=$iopadmap$ibuf13_en I=$iopadmap$ram_addr[3] O=ram_inst.addr[3] -.subckt I_BUF EN=$iopadmap$ibuf14_en I=$iopadmap$ram_addr[4] O=ram_inst.addr[4] -.subckt I_BUF EN=$iopadmap$ibuf15_en I=$iopadmap$ram_addr[5] O=ram_inst.addr[5] -.subckt I_BUF EN=$iopadmap$ibuf16_en I=$iopadmap$obuft_oe O=ibuf_obuft_oe -.subckt I_BUF EN=$iopadmap$ibuf7_en I=$iopadmap$P O=p_ibuf -.subckt I_BUF EN=$iopadmap$ibuf8_en I=$iopadmap$G O=g_ibuf -.subckt I_BUF EN=$iopadmap$ibuf9_en I=$iopadmap$ram_we O=ram_inst.we -.subckt O_BUF_DS I=ram_out O_N=$iopadmap$q_n O_P=$iopadmap$q_p -.subckt O_BUFT_DS I=ff_inst1.Q O_N=$iopadmap$buft_out_n O_P=$iopadmap$buft_out_p T=ibuf_obuft_oe -.end - -.model primitive_example_design_2 -.inputs in_n[0] in_n[1] in_n[2] in_p[0] in_p[1] in_p[2] clk rst_n rst_p mux1_sel_n mux1_sel_p mux2_sel_n mux2_sel_p ibuf0_en ibuf1_en ibuf2_en ibuf3_en ibuf4_en ibuf5_en ibuf6_en ibuf7_en ibuf8_en ibuf9_en ibuf10_en ibuf11_en ibuf12_en ibuf13_en ibuf14_en ibuf15_en ibuf16_en P G ram_addr[0] ram_addr[1] ram_addr[2] ram_addr[3] ram_addr[4] ram_addr[5] ram_we obuft_oe -.outputs q_p q_n buft_out_p buft_out_n -.names $false -.names $true -1 -.names $undef -.subckt fabric_primitive_example_design_2 $auto$clkbufmap.cc:262:execute$657=$auto$clkbufmap.cc:262:execute$657 $iopadmap$clk=$iopadmap$clk clk_buf_out=clk_buf_out ff_inst1.Q=ff_inst1.Q g_ibuf=g_ibuf i_buf_mux1_sel=i_buf_mux1_sel i_buf_mux2_sel=i_buf_mux2_sel i_buf_out[0]=i_buf_out[0] i_buf_out[1]=i_buf_out[1] i_buf_out[2]=i_buf_out[2] p_ibuf=p_ibuf ram_inst.addr[0]=ram_inst.addr[0] ram_inst.addr[1]=ram_inst.addr[1] ram_inst.addr[2]=ram_inst.addr[2] ram_inst.addr[3]=ram_inst.addr[3] ram_inst.addr[4]=ram_inst.addr[4] ram_inst.addr[5]=ram_inst.addr[5] ram_inst.we=ram_inst.we ram_out=ram_out rst_i_buf_out=rst_i_buf_out -.subckt interface_primitive_example_design_2 $auto$clkbufmap.cc:262:execute$657=$auto$clkbufmap.cc:262:execute$657 $iopadmap$clk=$iopadmap$clk G=G P=P buft_out_n=buft_out_n buft_out_p=buft_out_p clk=clk clk_buf_out=clk_buf_out ff_inst1.Q=ff_inst1.Q g_ibuf=g_ibuf i_buf_mux1_sel=i_buf_mux1_sel i_buf_mux2_sel=i_buf_mux2_sel i_buf_out[0]=i_buf_out[0] i_buf_out[1]=i_buf_out[1] i_buf_out[2]=i_buf_out[2] ibuf0_en=ibuf0_en ibuf10_en=ibuf10_en ibuf11_en=ibuf11_en ibuf12_en=ibuf12_en ibuf13_en=ibuf13_en ibuf14_en=ibuf14_en ibuf15_en=ibuf15_en ibuf16_en=ibuf16_en ibuf1_en=ibuf1_en ibuf2_en=ibuf2_en ibuf3_en=ibuf3_en ibuf4_en=ibuf4_en ibuf5_en=ibuf5_en ibuf6_en=ibuf6_en ibuf7_en=ibuf7_en ibuf8_en=ibuf8_en ibuf9_en=ibuf9_en in_n[0]=in_n[0] in_n[1]=in_n[1] in_n[2]=in_n[2] in_p[0]=in_p[0] in_p[1]=in_p[1] in_p[2]=in_p[2] mux1_sel_n=mux1_sel_n mux1_sel_p=mux1_sel_p mux2_sel_n=mux2_sel_n mux2_sel_p=mux2_sel_p obuft_oe=obuft_oe p_ibuf=p_ibuf q_n=q_n q_p=q_p ram_addr[0]=ram_addr[0] ram_addr[1]=ram_addr[1] ram_addr[2]=ram_addr[2] ram_addr[3]=ram_addr[3] ram_addr[4]=ram_addr[4] ram_addr[5]=ram_addr[5] ram_inst.addr[0]=ram_inst.addr[0] ram_inst.addr[1]=ram_inst.addr[1] ram_inst.addr[2]=ram_inst.addr[2] ram_inst.addr[3]=ram_inst.addr[3] ram_inst.addr[4]=ram_inst.addr[4] ram_inst.addr[5]=ram_inst.addr[5] ram_inst.we=ram_inst.we ram_out=ram_out ram_we=ram_we rst_i_buf_out=rst_i_buf_out rst_n=rst_n rst_p=rst_p -.end diff --git a/design_edit/Tests/primitive_example_design_2/gold/wrapper_primitive_example_design_2_post_synth.v b/design_edit/Tests/primitive_example_design_2/gold/wrapper_primitive_example_design_2_post_synth.v deleted file mode 100644 index a4c4430c3..000000000 --- a/design_edit/Tests/primitive_example_design_2/gold/wrapper_primitive_example_design_2_post_synth.v +++ /dev/null @@ -1,1095 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module primitive_example_design_2(in_n, in_p, clk, rst_n, rst_p, mux1_sel_n, mux1_sel_p, mux2_sel_n, mux2_sel_p, ibuf0_en, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en, ibuf5_en, ibuf6_en, ibuf7_en, ibuf8_en, ibuf9_en, ibuf10_en, ibuf11_en -, ibuf12_en, ibuf13_en, ibuf14_en, ibuf15_en, ibuf16_en, P, G, ram_addr, ram_we, obuft_oe, q_p, q_n, buft_out_p, buft_out_n); - input ibuf8_en; - input [2:0] in_p; - input [2:0] in_n; - input ibuf6_en; - input ibuf2_en; - input ibuf13_en; - output q_p; - input ibuf1_en; - input rst_p; - input mux2_sel_p; - input mux1_sel_p; - input ibuf5_en; - output buft_out_p; - input ibuf9_en; - input mux2_sel_n; - input mux1_sel_n; - input ibuf16_en; - input ibuf4_en; - input ibuf7_en; - output q_n; - input clk; - input P; - input ibuf14_en; - input obuft_oe; - input [5:0] ram_addr; - input ram_we; - input ibuf3_en; - input ibuf10_en; - input ibuf15_en; - input ibuf11_en; - input G; - output buft_out_n; - input rst_n; - input ibuf0_en; - input ibuf12_en; - (* src = "./rtl/primitive_example_design_2.v:5.83-5.91" *) - (* src = "./rtl/primitive_example_design_2.v:5.83-5.91" *) - wire ibuf8_en; - wire \$iopadmap$ibuf0_en ; - (* src = "./rtl/primitive_example_design_2.v:2.22-2.26" *) - (* src = "./rtl/primitive_example_design_2.v:2.22-2.26" *) - wire [2:0] in_p; - wire \$iopadmap$rst_p ; - wire \$iopadmap$ibuf15_en ; - (* src = "./rtl/primitive_example_design_2.v:2.17-2.21" *) - (* src = "./rtl/primitive_example_design_2.v:2.17-2.21" *) - wire [2:0] in_n; - (* src = "./rtl/primitive_example_design_2.v:17.10-17.23" *) - wire rst_i_buf_out; - wire \$iopadmap$rst_n ; - (* src = "./rtl/primitive_example_design_2.v:23.10-23.17" *) - wire ram_out; - wire \$iopadmap$ibuf6_en ; - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:96.8-96.10" *) - wire \ram_inst.we ; - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:95.27-95.31" *) - wire [5:0] \ram_inst.addr ; - wire \$iopadmap$ram_we ; - wire [5:0] \$iopadmap$ram_addr ; - wire \$iopadmap$q_p ; - (* src = "./rtl/primitive_example_design_2.v:18.14-18.20" *) - wire p_ibuf; - (* src = "./rtl/primitive_example_design_2.v:5.65-5.73" *) - (* src = "./rtl/primitive_example_design_2.v:5.65-5.73" *) - wire ibuf6_en; - (* src = "./rtl/primitive_example_design_2.v:5.29-5.37" *) - (* src = "./rtl/primitive_example_design_2.v:5.29-5.37" *) - wire ibuf2_en; - wire \$iopadmap$q_n ; - wire \$iopadmap$ibuf5_en ; - wire \$iopadmap$ibuf13_en ; - (* src = "./rtl/primitive_example_design_2.v:5.131-5.140" *) - (* src = "./rtl/primitive_example_design_2.v:5.131-5.140" *) - wire ibuf13_en; - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:49.15-49.66|./rtl/primitive_example_design_2.v:81.16-81.17" *) - wire \ff_inst1.Q ; - (* src = "./rtl/primitive_example_design_2.v:10.12-10.15" *) - (* src = "./rtl/primitive_example_design_2.v:10.12-10.15" *) - wire q_p; - (* src = "./rtl/primitive_example_design_2.v:5.20-5.28" *) - (* src = "./rtl/primitive_example_design_2.v:5.20-5.28" *) - wire ibuf1_en; - wire \$iopadmap$obuft_oe ; - wire \$iopadmap$mux2_sel_p ; - wire \$iopadmap$mux2_sel_n ; - (* src = "./rtl/primitive_example_design_2.v:17.24-17.38" *) - wire i_buf_mux1_sel; - (* src = "./rtl/primitive_example_design_2.v:3.22-3.27" *) - (* src = "./rtl/primitive_example_design_2.v:3.22-3.27" *) - wire rst_p; - (* src = "./rtl/primitive_example_design_2.v:4.44-4.54" *) - (* src = "./rtl/primitive_example_design_2.v:4.44-4.54" *) - wire mux2_sel_p; - (* src = "./rtl/primitive_example_design_2.v:13.16-13.25" *) - wire [2:0] i_buf_out; - (* src = "./rtl/primitive_example_design_2.v:4.22-4.32" *) - (* src = "./rtl/primitive_example_design_2.v:4.22-4.32" *) - wire mux1_sel_p; - wire \$iopadmap$mux1_sel_p ; - (* src = "./rtl/primitive_example_design_2.v:5.56-5.64" *) - (* src = "./rtl/primitive_example_design_2.v:5.56-5.64" *) - wire ibuf5_en; - (* src = "./rtl/primitive_example_design_2.v:10.20-10.30" *) - (* src = "./rtl/primitive_example_design_2.v:10.20-10.30" *) - wire buft_out_p; - wire \$iopadmap$mux1_sel_n ; - wire \$iopadmap$ibuf16_en ; - (* src = "./rtl/primitive_example_design_2.v:5.92-5.100" *) - (* src = "./rtl/primitive_example_design_2.v:5.92-5.100" *) - wire ibuf9_en; - (* src = "./rtl/primitive_example_design_2.v:18.21-18.27" *) - wire g_ibuf; - (* src = "./rtl/primitive_example_design_2.v:4.33-4.43" *) - (* src = "./rtl/primitive_example_design_2.v:4.33-4.43" *) - wire mux2_sel_n; - (* src = "./rtl/primitive_example_design_2.v:4.11-4.21" *) - (* src = "./rtl/primitive_example_design_2.v:4.11-4.21" *) - wire mux1_sel_n; - (* src = "./rtl/primitive_example_design_2.v:5.161-5.170" *) - (* src = "./rtl/primitive_example_design_2.v:5.161-5.170" *) - wire ibuf16_en; - (* src = "./rtl/primitive_example_design_2.v:5.47-5.55" *) - (* src = "./rtl/primitive_example_design_2.v:5.47-5.55" *) - wire ibuf4_en; - wire \$auto$clkbufmap.cc:294:execute$658 ; - wire \$iopadmap$clk ; - wire [2:0] \$iopadmap$in_p ; - (* src = "./rtl/primitive_example_design_2.v:5.74-5.82" *) - (* src = "./rtl/primitive_example_design_2.v:5.74-5.82" *) - wire ibuf7_en; - wire \$auto$clkbufmap.cc:262:execute$660 ; - wire \$iopadmap$ibuf3_en ; - (* src = "./rtl/primitive_example_design_2.v:17.39-17.53" *) - wire i_buf_mux2_sel; - wire \$iopadmap$P ; - wire \$iopadmap$ibuf4_en ; - wire \$iopadmap$ibuf12_en ; - wire \$iopadmap$buft_out_n ; - wire \$auto$clkbufmap.cc:262:execute$657 ; - (* src = "./rtl/primitive_example_design_2.v:10.16-10.19" *) - (* src = "./rtl/primitive_example_design_2.v:10.16-10.19" *) - wire q_n; - (* src = "./rtl/primitive_example_design_2.v:15.21-15.32" *) - wire clk_buf_out; - wire \$iopadmap$ibuf2_en ; - wire \$iopadmap$ibuf1_en ; - wire [2:0] \$iopadmap$in_n ; - wire \$iopadmap$ibuf14_en ; - (* src = "./rtl/primitive_example_design_2.v:3.11-3.14" *) - (* src = "./rtl/primitive_example_design_2.v:3.11-3.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_2.v:6.11-6.12" *) - (* src = "./rtl/primitive_example_design_2.v:6.11-6.12" *) - wire P; - (* src = "./rtl/primitive_example_design_2.v:5.141-5.150" *) - (* src = "./rtl/primitive_example_design_2.v:5.141-5.150" *) - wire ibuf14_en; - wire \$iopadmap$ibuf9_en ; - (* src = "./rtl/primitive_example_design_2.v:9.11-9.19" *) - (* src = "./rtl/primitive_example_design_2.v:9.11-9.19" *) - wire obuft_oe; - (* src = "./rtl/primitive_example_design_2.v:7.17-7.25" *) - (* src = "./rtl/primitive_example_design_2.v:7.17-7.25" *) - wire [5:0] ram_addr; - (* src = "./rtl/primitive_example_design_2.v:8.11-8.17" *) - (* src = "./rtl/primitive_example_design_2.v:8.11-8.17" *) - wire ram_we; - wire \$iopadmap$ibuf11_en ; - (* src = "./rtl/primitive_example_design_2.v:24.16-24.29" *) - wire ibuf_obuft_oe; - wire \$iopadmap$ibuf7_en ; - wire \$iopadmap$ibuf10_en ; - wire \$iopadmap$ibuf8_en ; - (* src = "./rtl/primitive_example_design_2.v:5.38-5.46" *) - (* src = "./rtl/primitive_example_design_2.v:5.38-5.46" *) - wire ibuf3_en; - (* src = "./rtl/primitive_example_design_2.v:5.101-5.110" *) - (* src = "./rtl/primitive_example_design_2.v:5.101-5.110" *) - wire ibuf10_en; - wire \$iopadmap$buft_out_p ; - (* src = "./rtl/primitive_example_design_2.v:5.151-5.160" *) - (* src = "./rtl/primitive_example_design_2.v:5.151-5.160" *) - wire ibuf15_en; - (* src = "./rtl/primitive_example_design_2.v:5.111-5.120" *) - (* src = "./rtl/primitive_example_design_2.v:5.111-5.120" *) - wire ibuf11_en; - (* src = "./rtl/primitive_example_design_2.v:6.13-6.14" *) - (* src = "./rtl/primitive_example_design_2.v:6.13-6.14" *) - wire G; - (* src = "./rtl/primitive_example_design_2.v:10.31-10.41" *) - (* src = "./rtl/primitive_example_design_2.v:10.31-10.41" *) - wire buft_out_n; - (* src = "./rtl/primitive_example_design_2.v:3.16-3.21" *) - (* src = "./rtl/primitive_example_design_2.v:3.16-3.21" *) - wire rst_n; - wire \$iopadmap$G ; - (* src = "./rtl/primitive_example_design_2.v:5.11-5.19" *) - (* src = "./rtl/primitive_example_design_2.v:5.11-5.19" *) - wire ibuf0_en; - (* src = "./rtl/primitive_example_design_2.v:5.121-5.130" *) - (* src = "./rtl/primitive_example_design_2.v:5.121-5.130" *) - wire ibuf12_en; - fabric_primitive_example_design_2 \$auto$rs_design_edit.cc:578:execute$712 ( - .\$iopadmap$clk (\$iopadmap$clk ), - .\$auto$clkbufmap.cc:262:execute$657 (\$auto$clkbufmap.cc:262:execute$657 ), - .clk_buf_out(clk_buf_out), - .\ff_inst1.Q (\ff_inst1.Q ), - .g_ibuf(g_ibuf), - .i_buf_mux1_sel(i_buf_mux1_sel), - .i_buf_mux2_sel(i_buf_mux2_sel), - .i_buf_out(i_buf_out), - .p_ibuf(p_ibuf), - .\ram_inst.addr (\ram_inst.addr ), - .\ram_inst.we (\ram_inst.we ), - .ram_out(ram_out), - .rst_i_buf_out(rst_i_buf_out) - ); - interface_primitive_example_design_2 \$auto$rs_design_edit.cc:580:execute$713 ( - .\$iopadmap$clk (\$iopadmap$clk ), - .clk(clk), - .G(G), - .P(P), - .buft_out_n(buft_out_n), - .buft_out_p(buft_out_p), - .ibuf0_en(ibuf0_en), - .ibuf10_en(ibuf10_en), - .ibuf11_en(ibuf11_en), - .ibuf12_en(ibuf12_en), - .ibuf13_en(ibuf13_en), - .ibuf14_en(ibuf14_en), - .ibuf15_en(ibuf15_en), - .ibuf16_en(ibuf16_en), - .ibuf1_en(ibuf1_en), - .ibuf2_en(ibuf2_en), - .ibuf3_en(ibuf3_en), - .ibuf4_en(ibuf4_en), - .ibuf5_en(ibuf5_en), - .ibuf6_en(ibuf6_en), - .ibuf7_en(ibuf7_en), - .ibuf8_en(ibuf8_en), - .ibuf9_en(ibuf9_en), - .in_n(in_n), - .in_p(in_p), - .mux1_sel_n(mux1_sel_n), - .mux1_sel_p(mux1_sel_p), - .mux2_sel_n(mux2_sel_n), - .mux2_sel_p(mux2_sel_p), - .obuft_oe(obuft_oe), - .q_n(q_n), - .q_p(q_p), - .ram_addr(ram_addr), - .ram_we(ram_we), - .rst_n(rst_n), - .rst_p(rst_p), - .\$auto$clkbufmap.cc:262:execute$657 (\$auto$clkbufmap.cc:262:execute$657 ), - .clk_buf_out(clk_buf_out), - .\ff_inst1.Q (\ff_inst1.Q ), - .g_ibuf(g_ibuf), - .i_buf_mux1_sel(i_buf_mux1_sel), - .i_buf_mux2_sel(i_buf_mux2_sel), - .i_buf_out(i_buf_out), - .p_ibuf(p_ibuf), - .\ram_inst.addr (\ram_inst.addr ), - .\ram_inst.we (\ram_inst.we ), - .ram_out(ram_out), - .rst_i_buf_out(rst_i_buf_out) - ); -endmodule - -module interface_primitive_example_design_2(in_n, in_p, clk, rst_n, rst_p, mux1_sel_n, mux1_sel_p, mux2_sel_n, mux2_sel_p, ibuf0_en, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en, ibuf5_en, ibuf6_en, ibuf7_en, ibuf8_en, ibuf9_en, ibuf10_en, ibuf11_en -, ibuf12_en, ibuf13_en, ibuf14_en, ibuf15_en, ibuf16_en, P, G, ram_addr, ram_we, obuft_oe, q_p, q_n, buft_out_p, buft_out_n, i_buf_out, clk_buf_out, rst_i_buf_out, i_buf_mux1_sel, i_buf_mux2_sel, p_ibuf, g_ibuf -, ram_out, \ram_inst.addr , \ram_inst.we , \ff_inst1.Q , \$auto$clkbufmap.cc:262:execute$657 , \$iopadmap$clk ); - input obuft_oe; - output rst_i_buf_out; - output g_ibuf; - input ibuf7_en; - input ram_out; - output \ram_inst.we ; - output [5:0] \ram_inst.addr ; - input ibuf14_en; - input ibuf0_en; - output buft_out_p; - input ibuf1_en; - output p_ibuf; - output q_n; - input [5:0] ram_addr; - input ibuf12_en; - input ibuf9_en; - output i_buf_mux1_sel; - input G; - input mux1_sel_p; - input [2:0] in_n; - input ibuf4_en; - output i_buf_mux2_sel; - input P; - input ibuf3_en; - input mux2_sel_p; - input clk; - input ibuf5_en; - input rst_p; - input ibuf15_en; - input ibuf11_en; - input ibuf13_en; - input mux1_sel_n; - input ibuf8_en; - input ram_we; - output [2:0] i_buf_out; - output \$iopadmap$clk ; - input ibuf16_en; - output buft_out_n; - input mux2_sel_n; - input ibuf10_en; - input \$auto$clkbufmap.cc:262:execute$657 ; - input ibuf6_en; - input [2:0] in_p; - output clk_buf_out; - input \ff_inst1.Q ; - input rst_n; - input ibuf2_en; - output q_p; - (* src = "./rtl/primitive_example_design_2.v:9.11-9.19" *) - (* src = "./rtl/primitive_example_design_2.v:9.11-9.19" *) - wire obuft_oe; - wire \$iopadmap$rst_p ; - (* src = "./rtl/primitive_example_design_2.v:17.10-17.23" *) - (* src = "./rtl/primitive_example_design_2.v:17.10-17.23" *) - wire rst_i_buf_out; - (* src = "./rtl/primitive_example_design_2.v:18.21-18.27" *) - (* src = "./rtl/primitive_example_design_2.v:18.21-18.27" *) - wire g_ibuf; - (* src = "./rtl/primitive_example_design_2.v:5.74-5.82" *) - (* src = "./rtl/primitive_example_design_2.v:5.74-5.82" *) - wire ibuf7_en; - wire \$iopadmap$rst_n ; - (* src = "./rtl/primitive_example_design_2.v:23.10-23.17" *) - (* src = "./rtl/primitive_example_design_2.v:23.10-23.17" *) - wire ram_out; - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:96.8-96.10" *) - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:96.8-96.10" *) - wire \ram_inst.we ; - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:95.27-95.31" *) - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:95.27-95.31" *) - wire [5:0] \ram_inst.addr ; - (* src = "./rtl/primitive_example_design_2.v:5.141-5.150" *) - (* src = "./rtl/primitive_example_design_2.v:5.141-5.150" *) - wire ibuf14_en; - (* src = "./rtl/primitive_example_design_2.v:5.11-5.19" *) - (* src = "./rtl/primitive_example_design_2.v:5.11-5.19" *) - wire ibuf0_en; - wire \$iopadmap$ram_we ; - (* src = "./rtl/primitive_example_design_2.v:10.20-10.30" *) - (* src = "./rtl/primitive_example_design_2.v:10.20-10.30" *) - wire buft_out_p; - wire \$iopadmap$mux2_sel_n ; - wire [5:0] \$iopadmap$ram_addr ; - (* src = "./rtl/primitive_example_design_2.v:5.20-5.28" *) - (* src = "./rtl/primitive_example_design_2.v:5.20-5.28" *) - wire ibuf1_en; - wire \$iopadmap$q_p ; - (* src = "./rtl/primitive_example_design_2.v:18.14-18.20" *) - (* src = "./rtl/primitive_example_design_2.v:18.14-18.20" *) - wire p_ibuf; - (* src = "./rtl/primitive_example_design_2.v:10.16-10.19" *) - (* src = "./rtl/primitive_example_design_2.v:10.16-10.19" *) - wire q_n; - wire \$iopadmap$ibuf14_en ; - wire \$iopadmap$q_n ; - wire \$iopadmap$obuft_oe ; - wire \$iopadmap$mux2_sel_p ; - (* src = "./rtl/primitive_example_design_2.v:7.17-7.25" *) - (* src = "./rtl/primitive_example_design_2.v:7.17-7.25" *) - wire [5:0] ram_addr; - wire \$auto$clkbufmap.cc:294:execute$658 ; - wire \$iopadmap$mux1_sel_p ; - wire \$iopadmap$G ; - (* src = "./rtl/primitive_example_design_2.v:5.121-5.130" *) - (* src = "./rtl/primitive_example_design_2.v:5.121-5.130" *) - wire ibuf12_en; - wire \$iopadmap$ibuf0_en ; - wire \$iopadmap$buft_out_p ; - (* src = "./rtl/primitive_example_design_2.v:5.92-5.100" *) - (* src = "./rtl/primitive_example_design_2.v:5.92-5.100" *) - wire ibuf9_en; - (* src = "./rtl/primitive_example_design_2.v:17.24-17.38" *) - (* src = "./rtl/primitive_example_design_2.v:17.24-17.38" *) - wire i_buf_mux1_sel; - (* src = "./rtl/primitive_example_design_2.v:6.13-6.14" *) - (* src = "./rtl/primitive_example_design_2.v:6.13-6.14" *) - wire G; - wire \$iopadmap$mux1_sel_n ; - (* src = "./rtl/primitive_example_design_2.v:4.22-4.32" *) - (* src = "./rtl/primitive_example_design_2.v:4.22-4.32" *) - wire mux1_sel_p; - wire [2:0] \$iopadmap$in_p ; - (* src = "./rtl/primitive_example_design_2.v:24.16-24.29" *) - wire ibuf_obuft_oe; - (* src = "./rtl/primitive_example_design_2.v:2.17-2.21" *) - (* src = "./rtl/primitive_example_design_2.v:2.17-2.21" *) - wire [2:0] in_n; - (* src = "./rtl/primitive_example_design_2.v:5.47-5.55" *) - (* src = "./rtl/primitive_example_design_2.v:5.47-5.55" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_2.v:17.39-17.53" *) - (* src = "./rtl/primitive_example_design_2.v:17.39-17.53" *) - wire i_buf_mux2_sel; - (* src = "./rtl/primitive_example_design_2.v:6.11-6.12" *) - (* src = "./rtl/primitive_example_design_2.v:6.11-6.12" *) - wire P; - wire \$iopadmap$ibuf5_en ; - (* src = "./rtl/primitive_example_design_2.v:5.38-5.46" *) - (* src = "./rtl/primitive_example_design_2.v:5.38-5.46" *) - wire ibuf3_en; - (* src = "./rtl/primitive_example_design_2.v:4.44-4.54" *) - (* src = "./rtl/primitive_example_design_2.v:4.44-4.54" *) - wire mux2_sel_p; - wire \$iopadmap$ibuf2_en ; - wire \$iopadmap$ibuf13_en ; - wire \$iopadmap$ibuf1_en ; - (* src = "./rtl/primitive_example_design_2.v:3.11-3.14" *) - (* src = "./rtl/primitive_example_design_2.v:3.11-3.14" *) - wire clk; - wire \$iopadmap$P ; - (* src = "./rtl/primitive_example_design_2.v:5.56-5.64" *) - (* src = "./rtl/primitive_example_design_2.v:5.56-5.64" *) - wire ibuf5_en; - (* src = "./rtl/primitive_example_design_2.v:3.22-3.27" *) - (* src = "./rtl/primitive_example_design_2.v:3.22-3.27" *) - wire rst_p; - wire \$iopadmap$ibuf8_en ; - (* src = "./rtl/primitive_example_design_2.v:5.151-5.160" *) - (* src = "./rtl/primitive_example_design_2.v:5.151-5.160" *) - wire ibuf15_en; - (* src = "./rtl/primitive_example_design_2.v:5.111-5.120" *) - (* src = "./rtl/primitive_example_design_2.v:5.111-5.120" *) - wire ibuf11_en; - (* src = "./rtl/primitive_example_design_2.v:5.131-5.140" *) - (* src = "./rtl/primitive_example_design_2.v:5.131-5.140" *) - wire ibuf13_en; - (* src = "./rtl/primitive_example_design_2.v:4.11-4.21" *) - (* src = "./rtl/primitive_example_design_2.v:4.11-4.21" *) - wire mux1_sel_n; - (* src = "./rtl/primitive_example_design_2.v:5.83-5.91" *) - (* src = "./rtl/primitive_example_design_2.v:5.83-5.91" *) - wire ibuf8_en; - wire \$iopadmap$buft_out_n ; - (* src = "./rtl/primitive_example_design_2.v:8.11-8.17" *) - (* src = "./rtl/primitive_example_design_2.v:8.11-8.17" *) - wire ram_we; - (* src = "./rtl/primitive_example_design_2.v:13.16-13.25" *) - (* src = "./rtl/primitive_example_design_2.v:13.16-13.25" *) - wire [2:0] i_buf_out; - wire \$iopadmap$ibuf11_en ; - wire \$iopadmap$ibuf6_en ; - wire \$iopadmap$clk ; - (* src = "./rtl/primitive_example_design_2.v:5.161-5.170" *) - (* src = "./rtl/primitive_example_design_2.v:5.161-5.170" *) - wire ibuf16_en; - (* src = "./rtl/primitive_example_design_2.v:10.31-10.41" *) - (* src = "./rtl/primitive_example_design_2.v:10.31-10.41" *) - wire buft_out_n; - wire \$iopadmap$ibuf15_en ; - wire \$auto$clkbufmap.cc:262:execute$660 ; - (* src = "./rtl/primitive_example_design_2.v:4.33-4.43" *) - (* src = "./rtl/primitive_example_design_2.v:4.33-4.43" *) - wire mux2_sel_n; - (* src = "./rtl/primitive_example_design_2.v:5.101-5.110" *) - (* src = "./rtl/primitive_example_design_2.v:5.101-5.110" *) - wire ibuf10_en; - wire \$iopadmap$ibuf12_en ; - wire \$auto$clkbufmap.cc:262:execute$657 ; - wire \$iopadmap$ibuf10_en ; - wire \$iopadmap$ibuf4_en ; - wire \$iopadmap$ibuf9_en ; - wire \$iopadmap$ibuf3_en ; - (* src = "./rtl/primitive_example_design_2.v:5.65-5.73" *) - (* src = "./rtl/primitive_example_design_2.v:5.65-5.73" *) - wire ibuf6_en; - (* src = "./rtl/primitive_example_design_2.v:2.22-2.26" *) - (* src = "./rtl/primitive_example_design_2.v:2.22-2.26" *) - wire [2:0] in_p; - wire [2:0] \$iopadmap$in_n ; - (* src = "./rtl/primitive_example_design_2.v:15.21-15.32" *) - (* src = "./rtl/primitive_example_design_2.v:15.21-15.32" *) - wire clk_buf_out; - wire \$iopadmap$ibuf7_en ; - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:49.15-49.66|./rtl/primitive_example_design_2.v:81.16-81.17" *) - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:49.15-49.66|./rtl/primitive_example_design_2.v:81.16-81.17" *) - wire \ff_inst1.Q ; - (* src = "./rtl/primitive_example_design_2.v:3.16-3.21" *) - (* src = "./rtl/primitive_example_design_2.v:3.16-3.21" *) - wire rst_n; - (* src = "./rtl/primitive_example_design_2.v:5.29-5.37" *) - (* src = "./rtl/primitive_example_design_2.v:5.29-5.37" *) - wire ibuf2_en; - (* src = "./rtl/primitive_example_design_2.v:10.12-10.15" *) - (* src = "./rtl/primitive_example_design_2.v:10.12-10.15" *) - wire q_p; - wire \$iopadmap$ibuf16_en ; - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:38.11-38.77" *) - I_BUF ibuf_inst11 ( - .EN(\$iopadmap$ibuf11_en ), - .I(\$iopadmap$ram_addr [1]), - .O(\ram_inst.addr [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ram_we ( - .O(\$iopadmap$ram_we ), - .EN(1'h1), - .I(ram_we) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ram_addr_5 ( - .O(\$iopadmap$ram_addr [5]), - .EN(1'h1), - .I(ram_addr[5]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf6_en ( - .O(\$iopadmap$ibuf6_en ), - .EN(1'h1), - .I(ibuf6_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf5_en ( - .O(\$iopadmap$ibuf5_en ), - .EN(1'h1), - .I(ibuf5_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf1_en ( - .O(\$iopadmap$ibuf1_en ), - .EN(1'h1), - .I(ibuf1_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.in_n ( - .O(\$iopadmap$in_n [0]), - .EN(1'h1), - .I(in_n[0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.P ( - .O(\$iopadmap$P ), - .EN(1'h1), - .I(P) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$primitive_example_design_2.buft_out_n ( - .O(buft_out_n), - .I(\$iopadmap$buft_out_n ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.mux2_sel_p ( - .O(\$iopadmap$mux2_sel_p ), - .EN(1'h1), - .I(mux2_sel_p) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.obuft_oe ( - .O(\$iopadmap$obuft_oe ), - .EN(1'h1), - .I(obuft_oe) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$primitive_example_design_2.q_p ( - .O(q_p), - .I(\$iopadmap$q_p ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf7_en ( - .O(\$iopadmap$ibuf7_en ), - .EN(1'h1), - .I(ibuf7_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf15_en ( - .O(\$iopadmap$ibuf15_en ), - .EN(1'h1), - .I(ibuf15_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$primitive_example_design_2.buft_out_p ( - .O(buft_out_p), - .I(\$iopadmap$buft_out_p ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ram_addr_2 ( - .O(\$iopadmap$ram_addr [2]), - .EN(1'h1), - .I(ram_addr[2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf3_en ( - .O(\$iopadmap$ibuf3_en ), - .EN(1'h1), - .I(ibuf3_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf9_en ( - .O(\$iopadmap$ibuf9_en ), - .EN(1'h1), - .I(ibuf9_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ram_addr ( - .O(\$iopadmap$ram_addr [0]), - .EN(1'h1), - .I(ram_addr[0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf14_en ( - .O(\$iopadmap$ibuf14_en ), - .EN(1'h1), - .I(ibuf14_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.in_n_2 ( - .O(\$iopadmap$in_n [2]), - .EN(1'h1), - .I(in_n[2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.in_n_1 ( - .O(\$iopadmap$in_n [1]), - .EN(1'h1), - .I(in_n[1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.rst_p ( - .O(\$iopadmap$rst_p ), - .EN(1'h1), - .I(rst_p) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf16_en ( - .O(\$iopadmap$ibuf16_en ), - .EN(1'h1), - .I(ibuf16_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf13_en ( - .O(\$iopadmap$ibuf13_en ), - .EN(1'h1), - .I(ibuf13_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf10_en ( - .O(\$iopadmap$ibuf10_en ), - .EN(1'h1), - .I(ibuf10_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf4_en ( - .O(\$iopadmap$ibuf4_en ), - .EN(1'h1), - .I(ibuf4_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.in_p_2 ( - .O(\$iopadmap$in_p [2]), - .EN(1'h1), - .I(in_p[2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf2_en ( - .O(\$iopadmap$ibuf2_en ), - .EN(1'h1), - .I(ibuf2_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ram_addr_3 ( - .O(\$iopadmap$ram_addr [3]), - .EN(1'h1), - .I(ram_addr[3]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.mux1_sel_n ( - .O(\$iopadmap$mux1_sel_n ), - .EN(1'h1), - .I(mux1_sel_n) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf0_en ( - .O(\$iopadmap$ibuf0_en ), - .EN(1'h1), - .I(ibuf0_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$primitive_example_design_2.q_n ( - .O(q_n), - .I(\$iopadmap$q_n ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf11_en ( - .O(\$iopadmap$ibuf11_en ), - .EN(1'h1), - .I(ibuf11_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.mux1_sel_p ( - .O(\$iopadmap$mux1_sel_p ), - .EN(1'h1), - .I(mux1_sel_p) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.rst_n ( - .O(\$iopadmap$rst_n ), - .EN(1'h1), - .I(rst_n) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.in_p ( - .O(\$iopadmap$in_p [0]), - .EN(1'h1), - .I(in_p[0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ram_addr_4 ( - .O(\$iopadmap$ram_addr [4]), - .EN(1'h1), - .I(ram_addr[4]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.mux2_sel_n ( - .O(\$iopadmap$mux2_sel_n ), - .EN(1'h1), - .I(mux2_sel_n) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf12_en ( - .O(\$iopadmap$ibuf12_en ), - .EN(1'h1), - .I(ibuf12_en) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ram_addr_1 ( - .O(\$iopadmap$ram_addr [1]), - .EN(1'h1), - .I(ram_addr[1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.in_p_1 ( - .O(\$iopadmap$in_p [1]), - .EN(1'h1), - .I(in_p[1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.clk ( - .O(\$iopadmap$clk ), - .EN(1'h1), - .I(clk) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.G ( - .O(\$iopadmap$G ), - .EN(1'h1), - .I(G) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$clkbufmap.cc:261:execute$656 ( - .O(\$auto$clkbufmap.cc:294:execute$658 ), - .I(\$auto$clkbufmap.cc:262:execute$657 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$clkbufmap.cc:261:execute$659 ( - .O(clk_buf_out), - .I(\$auto$clkbufmap.cc:262:execute$660 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:39.11-39.77" *) - I_BUF ibuf_inst12 ( - .EN(\$iopadmap$ibuf12_en ), - .I(\$iopadmap$ram_addr [2]), - .O(\ram_inst.addr [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:40.11-40.77" *) - I_BUF ibuf_inst13 ( - .EN(\$iopadmap$ibuf13_en ), - .I(\$iopadmap$ram_addr [3]), - .O(\ram_inst.addr [3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:41.11-41.77" *) - I_BUF ibuf_inst14 ( - .EN(\$iopadmap$ibuf14_en ), - .I(\$iopadmap$ram_addr [4]), - .O(\ram_inst.addr [4]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:42.11-42.77" *) - I_BUF ibuf_inst15 ( - .EN(\$iopadmap$ibuf15_en ), - .I(\$iopadmap$ram_addr [5]), - .O(\ram_inst.addr [5]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:43.11-43.70" *) - I_BUF ibuf_inst16 ( - .EN(\$iopadmap$ibuf16_en ), - .I(\$iopadmap$obuft_oe ), - .O(ibuf_obuft_oe) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:34.11-34.54" *) - I_BUF ibuf_inst7 ( - .EN(\$iopadmap$ibuf7_en ), - .I(\$iopadmap$P ), - .O(p_ibuf) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:35.11-35.54" *) - I_BUF ibuf_inst8 ( - .EN(\$iopadmap$ibuf8_en ), - .I(\$iopadmap$G ), - .O(g_ibuf) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$primitive_example_design_2.ibuf8_en ( - .O(\$iopadmap$ibuf8_en ), - .EN(1'h1), - .I(ibuf8_en) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:36.11-36.65" *) - I_BUF ibuf_inst9 ( - .EN(\$iopadmap$ibuf9_en ), - .I(\$iopadmap$ram_we ), - .O(\ram_inst.we ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:26.11-26.63" *) - I_BUF clk_buf_inst ( - .EN(\$iopadmap$ibuf0_en ), - .I(\$auto$clkbufmap.cc:294:execute$658 ), - .O(\$auto$clkbufmap.cc:262:execute$660 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:53.14-53.62" *) - O_BUF_DS o_buff_ds_inst ( - .I(ram_out), - .O_N(\$iopadmap$q_n ), - .O_P(\$iopadmap$q_p ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:51.15-51.92" *) - O_BUFT_DS obuft_ds_inst ( - .I(\ff_inst1.Q ), - .O_N(\$iopadmap$buft_out_n ), - .O_P(\$iopadmap$buft_out_p ), - .T(ibuf_obuft_oe) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:28.14-28.88" *) - I_BUF_DS ibuf_ds_inst1 ( - .EN(\$iopadmap$ibuf1_en ), - .I_N(\$iopadmap$in_n [0]), - .I_P(\$iopadmap$in_p [0]), - .O(i_buf_out[0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:29.14-29.88" *) - I_BUF_DS ibuf_ds_inst2 ( - .EN(\$iopadmap$ibuf2_en ), - .I_N(\$iopadmap$in_n [1]), - .I_P(\$iopadmap$in_p [1]), - .O(i_buf_out[1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:30.14-30.88" *) - I_BUF_DS ibuf_ds_inst3 ( - .EN(\$iopadmap$ibuf3_en ), - .I_N(\$iopadmap$in_n [2]), - .I_P(\$iopadmap$in_p [2]), - .O(i_buf_out[2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:31.14-31.85" *) - I_BUF_DS ibuf_ds_inst4 ( - .EN(\$iopadmap$ibuf4_en ), - .I_N(\$iopadmap$rst_n ), - .I_P(\$iopadmap$rst_p ), - .O(rst_i_buf_out) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:32.14-32.96" *) - I_BUF_DS ibuf_ds_inst5 ( - .EN(\$iopadmap$ibuf5_en ), - .I_N(\$iopadmap$mux1_sel_n ), - .I_P(\$iopadmap$mux1_sel_p ), - .O(i_buf_mux1_sel) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:33.14-33.96" *) - I_BUF_DS ibuf_ds_inst6 ( - .EN(\$iopadmap$ibuf6_en ), - .I_N(\$iopadmap$mux2_sel_n ), - .I_P(\$iopadmap$mux2_sel_p ), - .O(i_buf_mux2_sel) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_2.v:37.11-37.77" *) - I_BUF ibuf_inst10 ( - .EN(\$iopadmap$ibuf10_en ), - .I(\$iopadmap$ram_addr [0]), - .O(\ram_inst.addr [0]) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_2/primitive_example_design_2.pin b/design_edit/Tests/primitive_example_design_2/primitive_example_design_2.pin deleted file mode 100644 index 2e6f5456b..000000000 --- a/design_edit/Tests/primitive_example_design_2/primitive_example_design_2.pin +++ /dev/null @@ -1,53 +0,0 @@ -#Pin Constraints -set_property PIN_LOC AB5 [get_ports clk] -set_property PIN_LOC AH18 [get_ports G] -set_property PIN_LOC AH8 [get_ports P] -set_property PIN_LOC P21 [get_ports buft_out_n] -set_property PIN_LOC AD14 [get_ports ibuf0_en] -set_property PIN_LOC P23 [get_ports ibuf10_en] -set_property PIN_LOC J23 [get_ports ibuf11_en] -set_property PIN_LOC P26 [get_ports ibuf12_en] -set_property PIN_LOC P21 [get_ports ibuf13_en] -set_property PIN_LOC P25 [get_ports ibuf14_en] -set_property PIN_LOC K21 [get_ports ibuf15_en] -set_property PIN_LOC M21 [get_ports ibuf16_en] -set_property PIN_LOC P27 [get_ports ibuf1_en] -set_property PIN_LOC L22 [get_ports ibuf2_en] -set_property PIN_LOC N23 [get_ports ibuf3_en] -set_property PIN_LOC M23 [get_ports ibuf4_en] -set_property PIN_LOC N24 [get_ports ibuf5_en] -set_property PIN_LOC L24 [get_ports ibuf6_en] -set_property PIN_LOC J26 [get_ports ibuf7_en] -set_property PIN_LOC L25 [get_ports ibuf8_en] -set_property PIN_LOC M28 [get_ports ibuf9_en] -set_property PIN_LOC N26 [get_ports in_n[0]] -set_property PIN_LOC J24 [get_ports in_n[1]] -set_property PIN_LOC L26 [get_ports mux1_sel_n] -set_property PIN_LOC T24 [get_ports mux1_sel_p] -set_property PIN_LOC U25 [get_ports obuft_oe] -set_property PIN_LOC W27 [get_ports ram_addr[0]] -set_property PIN_LOC U27 [get_ports ram_addr[1]] -set_property PIN_LOC R26 [get_ports ram_addr[2]] -set_property PIN_LOC U21 [get_ports ram_addr[3]] -set_property PIN_LOC T21 [get_ports ram_addr[4]] -set_property PIN_LOC U22 [get_ports ram_addr[5]] -set_property PIN_LOC W21 [get_ports ram_we] -set_property PIN_LOC V23 [get_ports rst_n] -set_property PIN_LOC AG17 [get_ports in_p[0]] -set_property PIN_LOC AC15 [get_ports in_p[1]] -set_property PIN_LOC AB12 [get_ports buft_out_p] -set_property PIN_LOC AC12 [get_ports mux2_sel_n] -set_property PIN_LOC AA13 [get_ports mux2_sel_p] -set_property PIN_LOC AF14 [get_ports q_n] -set_property PIN_LOC AD17 [get_ports q_p] -set_property PIN_LOC AG16 [get_ports rst_n] -set_property PIN_LOC AG14 [get_ports rst_p] - - - - - - - - - diff --git a/design_edit/Tests/primitive_example_design_2/primitive_example_design_2.ys b/design_edit/Tests/primitive_example_design_2/primitive_example_design_2.ys deleted file mode 100644 index 71944ff42..000000000 --- a/design_edit/Tests/primitive_example_design_2/primitive_example_design_2.ys +++ /dev/null @@ -1,19 +0,0 @@ -# Yosys synthesis script for O_SERDES_primitive_inst -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./rtl/primitive_example_design_2.v - - -# Technology mapping -hierarchy -top primitive_example_design_2 - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal delay -effort high -carry auto -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -json ./tmp/io_config.json -w ./tmp/wrapper_primitive_example_design_2_post_synth.v ./tmp/wrapper_primitive_example_design_2_post_synth.eblif -write_verilog -noexpr -nodec -norename -v ./tmp/primitive_example_design_2_post_synth.v -write_blif -param ./tmp/primitive_example_design_2_post_synth.eblif \ No newline at end of file diff --git a/design_edit/Tests/primitive_example_design_2/rtl/primitive_example_design_2.v b/design_edit/Tests/primitive_example_design_2/rtl/primitive_example_design_2.v deleted file mode 100644 index f70ee86ab..000000000 --- a/design_edit/Tests/primitive_example_design_2/rtl/primitive_example_design_2.v +++ /dev/null @@ -1,114 +0,0 @@ -module primitive_example_design_2( - input [2:0] in_n,in_p, - input clk, rst_n,rst_p, - input mux1_sel_n,mux1_sel_p,mux2_sel_n,mux2_sel_p, - input ibuf0_en,ibuf1_en,ibuf2_en,ibuf3_en,ibuf4_en,ibuf5_en,ibuf6_en,ibuf7_en,ibuf8_en,ibuf9_en,ibuf10_en,ibuf11_en,ibuf12_en,ibuf13_en,ibuf14_en,ibuf15_en,ibuf16_en, - input P,G, - input [5:0] ram_addr, - input ram_we, - input obuft_oe, - output q_p,q_n,buft_out_p,buft_out_n -); - - wire [2:0] i_buf_out; - wire [5:0] i_buf_ram_addr; - wire in_buf_out,clk_buf_out; - wire lut_out; - wire rst_i_buf_out,i_buf_mux1_sel,i_buf_mux2_sel; - wire out,p_ibuf,g_ibuf; - wire dffnre_out; - wire ac_out, acc_out; - wire mux2_out; - wire Q_buff_in; - wire ram_out,i_buf_ram_we; - wire inf_q,ibuf_obuft_oe; - - I_BUF clk_buf_inst (.I(clk),.EN(ibuf0_en),.O(clk_buf_out)); - - I_BUF_DS ibuf_ds_inst1 (.I_P(in_p[0]),.I_N(in_n[0]),.EN(ibuf1_en),.O(i_buf_out[0])); - I_BUF_DS ibuf_ds_inst2 (.I_P(in_p[1]),.I_N(in_n[1]),.EN(ibuf2_en),.O(i_buf_out[1])); - I_BUF_DS ibuf_ds_inst3 (.I_P(in_p[2]),.I_N(in_n[2]),.EN(ibuf3_en),.O(i_buf_out[2])); - I_BUF_DS ibuf_ds_inst4 (.I_P(rst_p),.I_N(rst_n),.EN(ibuf4_en),.O(rst_i_buf_out)); - I_BUF_DS ibuf_ds_inst5 (.I_P(mux1_sel_p),.I_N(mux1_sel_n),.EN(ibuf5_en),.O(i_buf_mux1_sel)); - I_BUF_DS ibuf_ds_inst6 (.I_P(mux2_sel_p),.I_N(mux2_sel_n),.EN(ibuf6_en),.O(i_buf_mux2_sel)); - I_BUF ibuf_inst7 (.I(P),.EN(ibuf7_en),.O(p_ibuf)); - I_BUF ibuf_inst8 (.I(G),.EN(ibuf8_en),.O(g_ibuf)); - I_BUF ibuf_inst9 (.I(ram_we),.EN(ibuf9_en),.O(i_buf_ram_we)); - I_BUF ibuf_inst10 (.I(ram_addr[0]),.EN(ibuf10_en),.O(i_buf_ram_addr[0])); - I_BUF ibuf_inst11 (.I(ram_addr[1]),.EN(ibuf11_en),.O(i_buf_ram_addr[1])); - I_BUF ibuf_inst12 (.I(ram_addr[2]),.EN(ibuf12_en),.O(i_buf_ram_addr[2])); - I_BUF ibuf_inst13 (.I(ram_addr[3]),.EN(ibuf13_en),.O(i_buf_ram_addr[3])); - I_BUF ibuf_inst14 (.I(ram_addr[4]),.EN(ibuf14_en),.O(i_buf_ram_addr[4])); - I_BUF ibuf_inst15 (.I(ram_addr[5]),.EN(ibuf15_en),.O(i_buf_ram_addr[5])); - I_BUF ibuf_inst16 (.I(obuft_oe),.EN(ibuf16_en),.O(ibuf_obuft_oe)); - - DFFNRE ffn_inst (.D(lut_out),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffnre_out)); - - assign out = i_buf_mux1_sel ? dffnre_out : !dffnre_out; - - flip_flop ff_inst1 (.clk(clk),.rst(rst),.D(ac_out),.Q(inf_q)); - - O_BUFT_DS obuft_ds_inst (.I(inf_q),.T(ibuf_obuft_oe),.O_P(buft_out_p),.O_N(buft_out_n)); - - O_BUF_DS o_buff_ds_inst (.I(ram_out),.O_P(q_p),.O_N(q_n)); - - DFFRE ff_inst (.D(mux2_out),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(Q_buff_in)); - - assign mux2_out = i_buf_mux2_sel ? ac_out : acc_out; - - CARRY_CHAIN carry_chain_inst (.P(p_ibuf),.G(g_ibuf),.CIN(out),.O(ac_out),.COUT(acc_out)); - - infer_single_port_ram ram_inst (.data(Q_buff_in),.addr(i_buf_ram_addr),.we(i_buf_ram_we),.clk(clk),.q(ram_out)); - - always @(*) begin - case(i_buf_out) - 3'b000 : lut_out = 0; - 3'b001 : lut_out = 1; - 3'b010 : lut_out = 1; - 3'b011 : lut_out = 0; - 3'b100 : lut_out = 1; - 3'b101 : lut_out = 1; - 3'b110 : lut_out = 1; - 3'b111 : lut_out = 0; - default: lut_out = 1; - endcase - end -endmodule - -module flip_flop( - input rst,clk, - input D, - output reg Q -); - always @ (posedge clk) begin - if (rst) - Q <= 0; - else - Q <= D; - end -endmodule - -module infer_single_port_ram -#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) -( - input [(DATA_WIDTH-1):0] data, - input [(ADDR_WIDTH-1):0] addr, - input we, clk, - output [(DATA_WIDTH-1):0] q -); - - reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; - - reg [ADDR_WIDTH-1:0] addr_reg; - - always @ (posedge clk) - begin - if (we) - ram[addr] <= data; - - addr_reg <= addr; - end - - assign q = ram[addr_reg]; - -endmodule diff --git a/design_edit/Tests/primitive_example_design_2/synthesis/primitive_example_design_2_post_synth.eblif b/design_edit/Tests/primitive_example_design_2/synthesis/primitive_example_design_2_post_synth.eblif deleted file mode 100644 index 3eeb17fe0..000000000 --- a/design_edit/Tests/primitive_example_design_2/synthesis/primitive_example_design_2_post_synth.eblif +++ /dev/null @@ -1,106 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model primitive_example_design_2 -.inputs in_n[0] in_n[1] in_n[2] in_p[0] in_p[1] in_p[2] clk rst_n rst_p mux1_sel_n mux1_sel_p mux2_sel_n mux2_sel_p ibuf0_en ibuf1_en ibuf2_en ibuf3_en ibuf4_en ibuf5_en ibuf6_en ibuf7_en ibuf8_en ibuf9_en ibuf10_en ibuf11_en ibuf12_en ibuf13_en ibuf14_en ibuf15_en ibuf16_en P G ram_addr[0] ram_addr[1] ram_addr[2] ram_addr[3] ram_addr[4] ram_addr[5] ram_we obuft_oe -.outputs q_p q_n buft_out_p buft_out_n -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=clk D=ram_inst.we E=$true Q=$auto$memory_dff.cc:774:handle_rd_port_addr$44 R=$true -.subckt DFFRE C=clk D=Q_buff_in E=$true Q=$auto$memory_dff.cc:776:handle_rd_port_addr$46[0] R=$true -.subckt DFFRE C=clk D=ff_inst1.D E=$true Q=ff_inst1.Q R=$true -.subckt LUT3 A[0]=$auto$memory_dff.cc:776:handle_rd_port_addr$46[0] A[1]=$abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] A[2]=$auto$memory_dff.cc:774:handle_rd_port_addr$44 Y=ram_out -.param INIT_VALUE 10101100 -.subckt LUT3 A[0]=i_buf_out[2] A[1]=i_buf_out[0] A[2]=i_buf_out[1] Y=lut_out -.param INIT_VALUE 00111110 -.subckt LUT2 A[0]=dffnre_out A[1]=i_buf_mux1_sel Y=out -.param INIT_VALUE 1001 -.subckt LUT3 A[0]=ff_inst1.D A[1]=acc_out A[2]=i_buf_mux2_sel Y=mux2_out -.param INIT_VALUE 10101100 -.subckt CARRY_CHAIN CIN=out COUT=acc_out G=g_ibuf O=ff_inst1.D P=p_ibuf -.subckt I_BUF EN=ibuf0_en I=clk O=clk_buf_out -.subckt DFFRE C=clk_buf_out D=mux2_out E=$true Q=Q_buff_in R=rst_i_buf_out -.subckt DFFNRE C=clk_buf_out D=lut_out E=$true Q=dffnre_out R=rst_i_buf_out -.subckt I_BUF_DS EN=ibuf1_en I_N=in_n[0] I_P=in_p[0] O=i_buf_out[0] -.subckt I_BUF_DS EN=ibuf2_en I_N=in_n[1] I_P=in_p[1] O=i_buf_out[1] -.subckt I_BUF_DS EN=ibuf3_en I_N=in_n[2] I_P=in_p[2] O=i_buf_out[2] -.subckt I_BUF_DS EN=ibuf4_en I_N=rst_n I_P=rst_p O=rst_i_buf_out -.subckt I_BUF_DS EN=ibuf5_en I_N=mux1_sel_n I_P=mux1_sel_p O=i_buf_mux1_sel -.subckt I_BUF_DS EN=ibuf6_en I_N=mux2_sel_n I_P=mux2_sel_p O=i_buf_mux2_sel -.subckt I_BUF EN=ibuf10_en I=ram_addr[0] O=ram_inst.addr[0] -.subckt I_BUF EN=ibuf11_en I=ram_addr[1] O=ram_inst.addr[1] -.subckt I_BUF EN=ibuf12_en I=ram_addr[2] O=ram_inst.addr[2] -.subckt I_BUF EN=ibuf13_en I=ram_addr[3] O=ram_inst.addr[3] -.subckt I_BUF EN=ibuf14_en I=ram_addr[4] O=ram_inst.addr[4] -.subckt I_BUF EN=ibuf15_en I=ram_addr[5] O=ram_inst.addr[5] -.subckt I_BUF EN=ibuf16_en I=obuft_oe O=ibuf_obuft_oe -.subckt I_BUF EN=ibuf7_en I=P O=p_ibuf -.subckt I_BUF EN=ibuf8_en I=G O=g_ibuf -.subckt I_BUF EN=ibuf9_en I=ram_we O=ram_inst.we -.subckt O_BUF_DS I=ram_out O_N=q_n O_P=q_p -.subckt O_BUFT_DS I=ff_inst1.Q O_N=buft_out_n O_P=buft_out_p T=ibuf_obuft_oe -.subckt TDP_RAM18KX2 ADDR_A1[0]=$false ADDR_A1[1]=$false ADDR_A1[2]=$false ADDR_A1[3]=ram_inst.addr[0] ADDR_A1[4]=ram_inst.addr[1] ADDR_A1[5]=ram_inst.addr[2] ADDR_A1[6]=ram_inst.addr[3] ADDR_A1[7]=ram_inst.addr[4] ADDR_A1[8]=ram_inst.addr[5] ADDR_A1[9]=$false ADDR_A1[10]=$false ADDR_A1[11]=$false ADDR_A1[12]=$false ADDR_A1[13]=$false ADDR_A2[0]=$undef ADDR_A2[1]=$undef ADDR_A2[2]=$undef ADDR_A2[3]=$undef ADDR_A2[4]=$undef ADDR_A2[5]=$undef ADDR_A2[6]=$undef ADDR_A2[7]=$undef ADDR_A2[8]=$undef ADDR_A2[9]=$undef ADDR_A2[10]=$undef ADDR_A2[11]=$undef ADDR_A2[12]=$undef ADDR_A2[13]=$undef ADDR_B1[0]=$false ADDR_B1[1]=$false ADDR_B1[2]=$false ADDR_B1[3]=ram_inst.addr[0] ADDR_B1[4]=ram_inst.addr[1] ADDR_B1[5]=ram_inst.addr[2] ADDR_B1[6]=ram_inst.addr[3] ADDR_B1[7]=ram_inst.addr[4] ADDR_B1[8]=ram_inst.addr[5] ADDR_B1[9]=$false ADDR_B1[10]=$false ADDR_B1[11]=$false ADDR_B1[12]=$false ADDR_B1[13]=$false ADDR_B2[0]=$undef ADDR_B2[1]=$undef ADDR_B2[2]=$undef ADDR_B2[3]=$undef ADDR_B2[4]=$undef ADDR_B2[5]=$undef ADDR_B2[6]=$undef ADDR_B2[7]=$undef ADDR_B2[8]=$undef ADDR_B2[9]=$undef ADDR_B2[10]=$undef ADDR_B2[11]=$undef ADDR_B2[12]=$undef ADDR_B2[13]=$undef BE_A1[0]=$false BE_A1[1]=$false BE_A2[0]=$false BE_A2[1]=$false BE_B1[0]=ram_inst.we BE_B1[1]=$false BE_B2[0]=$undef BE_B2[1]=$undef CLK_A1=clk CLK_A2=$undef CLK_B1=clk CLK_B2=$undef RDATA_A1[0]=$abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] RDATA_A1[1]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[1] RDATA_A1[2]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[2] RDATA_A1[3]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[3] RDATA_A1[4]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[4] RDATA_A1[5]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[5] RDATA_A1[6]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[6] RDATA_A1[7]=$auto$memory_dff.cc:781:handle_rd_port_addr$50[7] RDATA_A1[8]=$auto$memory_libmap.cc:1863:emit_port$52[8] RDATA_A1[9]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[9] RDATA_A1[10]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[10] RDATA_A1[11]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[11] RDATA_A1[12]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[12] RDATA_A1[13]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[13] RDATA_A1[14]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[14] RDATA_A1[15]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[15] RDATA_A2[0]=$techmap72\ram_inst.ram.0.0.C1DATA RDATA_A2[1]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[1] RDATA_A2[2]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[2] RDATA_A2[3]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[3] RDATA_A2[4]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[4] RDATA_A2[5]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[5] RDATA_A2[6]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[6] RDATA_A2[7]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[7] RDATA_A2[8]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[8] RDATA_A2[9]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[9] RDATA_A2[10]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[10] RDATA_A2[11]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[11] RDATA_A2[12]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[12] RDATA_A2[13]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[13] RDATA_A2[14]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[14] RDATA_A2[15]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[15] RDATA_B1[0]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[0] RDATA_B1[1]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[1] RDATA_B1[2]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[2] RDATA_B1[3]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[3] RDATA_B1[4]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[4] RDATA_B1[5]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[5] RDATA_B1[6]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[6] RDATA_B1[7]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[7] RDATA_B1[8]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[8] RDATA_B1[9]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[9] RDATA_B1[10]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[10] RDATA_B1[11]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[11] RDATA_B1[12]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[12] RDATA_B1[13]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[13] RDATA_B1[14]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[14] RDATA_B1[15]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[15] RDATA_B2[0]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[0] RDATA_B2[1]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[1] RDATA_B2[2]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[2] RDATA_B2[3]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[3] RDATA_B2[4]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[4] RDATA_B2[5]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[5] RDATA_B2[6]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[6] RDATA_B2[7]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[7] RDATA_B2[8]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[8] RDATA_B2[9]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[9] RDATA_B2[10]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[10] RDATA_B2[11]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[11] RDATA_B2[12]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[12] RDATA_B2[13]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[13] RDATA_B2[14]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[14] RDATA_B2[15]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[15] REN_A1=$true REN_A2=$undef REN_B1=$false REN_B2=$false RPARITY_A1[0]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[16] RPARITY_A1[1]=$techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[17] RPARITY_A2[0]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[16] RPARITY_A2[1]=$techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[17] RPARITY_B1[0]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[16] RPARITY_B1[1]=$techmap72\ram_inst.ram.0.0.PORT_B1_RDATA[17] RPARITY_B2[0]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[16] RPARITY_B2[1]=$techmap72\ram_inst.ram.0.0.PORT_B2_RDATA[17] WDATA_A1[0]=$undef WDATA_A1[1]=$undef WDATA_A1[2]=$undef WDATA_A1[3]=$undef WDATA_A1[4]=$undef WDATA_A1[5]=$undef WDATA_A1[6]=$undef WDATA_A1[7]=$undef WDATA_A1[8]=$undef WDATA_A1[9]=$undef WDATA_A1[10]=$undef WDATA_A1[11]=$undef WDATA_A1[12]=$undef WDATA_A1[13]=$undef WDATA_A1[14]=$undef WDATA_A1[15]=$undef WDATA_A2[0]=$undef WDATA_A2[1]=$undef WDATA_A2[2]=$undef WDATA_A2[3]=$undef WDATA_A2[4]=$undef WDATA_A2[5]=$undef WDATA_A2[6]=$undef WDATA_A2[7]=$undef WDATA_A2[8]=$undef WDATA_A2[9]=$undef WDATA_A2[10]=$undef WDATA_A2[11]=$undef WDATA_A2[12]=$undef WDATA_A2[13]=$undef WDATA_A2[14]=$undef WDATA_A2[15]=$undef WDATA_B1[0]=Q_buff_in WDATA_B1[1]=$false WDATA_B1[2]=$false WDATA_B1[3]=$false WDATA_B1[4]=$false WDATA_B1[5]=$false WDATA_B1[6]=$false WDATA_B1[7]=$false WDATA_B1[8]=$undef WDATA_B1[9]=$undef WDATA_B1[10]=$undef WDATA_B1[11]=$undef WDATA_B1[12]=$undef WDATA_B1[13]=$undef WDATA_B1[14]=$undef WDATA_B1[15]=$undef WDATA_B2[0]=$undef WDATA_B2[1]=$undef WDATA_B2[2]=$undef WDATA_B2[3]=$undef WDATA_B2[4]=$undef WDATA_B2[5]=$undef WDATA_B2[6]=$undef WDATA_B2[7]=$undef WDATA_B2[8]=$undef WDATA_B2[9]=$undef WDATA_B2[10]=$undef WDATA_B2[11]=$undef WDATA_B2[12]=$undef WDATA_B2[13]=$undef WDATA_B2[14]=$undef WDATA_B2[15]=$undef WEN_A1=$false WEN_A2=$false WEN_B1=ram_inst.we WEN_B2=$undef WPARITY_A1[0]=$undef WPARITY_A1[1]=$undef WPARITY_A2[0]=$undef WPARITY_A2[1]=$undef WPARITY_B1[0]=$undef WPARITY_B1[1]=$undef WPARITY_B2[0]=$undef WPARITY_B2[1]=$undef -.param INIT1 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-.param INIT1_PARITY 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -.param INIT2 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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-.param INIT2_PARITY 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -.param READ_WIDTH_A1 00000000000000000000000000001001 -.param READ_WIDTH_A2 00000000000000000000000000000001 -.param READ_WIDTH_B1 00000000000000000000000000001001 -.param READ_WIDTH_B2 00000000000000000000000000000001 -.param WRITE_WIDTH_A1 00000000000000000000000000001001 -.param WRITE_WIDTH_A2 00000000000000000000000000000001 -.param WRITE_WIDTH_B1 00000000000000000000000000001001 -.param WRITE_WIDTH_B2 00000000000000000000000000000001 -.names $techmap72\ram_inst.ram.0.0.C1DATA $techmap72\ram_inst.ram.0.0.PORT_A2_RDATA[0] -1 1 -.names $abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[0] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[1] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[1] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[2] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[2] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[3] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[3] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[4] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[4] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[5] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[5] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[6] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[6] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[7] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[7] -1 1 -.names $auto$memory_libmap.cc:1863:emit_port$52[8] $techmap72\ram_inst.ram.0.0.PORT_A1_RDATA[8] -1 1 -.names $abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] $auto$memory_libmap.cc:1863:emit_port$52[0] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[1] $auto$memory_libmap.cc:1863:emit_port$52[1] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[2] $auto$memory_libmap.cc:1863:emit_port$52[2] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[3] $auto$memory_libmap.cc:1863:emit_port$52[3] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[4] $auto$memory_libmap.cc:1863:emit_port$52[4] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[5] $auto$memory_libmap.cc:1863:emit_port$52[5] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[6] $auto$memory_libmap.cc:1863:emit_port$52[6] -1 1 -.names $auto$memory_dff.cc:781:handle_rd_port_addr$50[7] $auto$memory_libmap.cc:1863:emit_port$52[7] -1 1 -.names $abc$319$auto$memory_dff.cc:781:handle_rd_port_addr$50[0] $auto$memory_dff.cc:781:handle_rd_port_addr$50[0] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[1] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[2] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[3] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[4] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[5] -1 1 -.names $auto$memory_dff.cc:776:handle_rd_port_addr$46[7] $auto$memory_dff.cc:776:handle_rd_port_addr$46[6] -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_2/synthesis/primitive_example_design_2_post_synth.v b/design_edit/Tests/primitive_example_design_2/synthesis/primitive_example_design_2_post_synth.v deleted file mode 100644 index b039f731d..000000000 --- a/design_edit/Tests/primitive_example_design_2/synthesis/primitive_example_design_2_post_synth.v +++ /dev/null @@ -1,513 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module primitive_example_design_2(in_n, in_p, clk, rst_n, rst_p, mux1_sel_n, mux1_sel_p, mux2_sel_n, mux2_sel_p, ibuf0_en, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en, ibuf5_en, ibuf6_en, ibuf7_en, ibuf8_en, ibuf9_en, ibuf10_en, ibuf11_en -, ibuf12_en, ibuf13_en, ibuf14_en, ibuf15_en, ibuf16_en, P, G, ram_addr, ram_we, obuft_oe, q_p, q_n, buft_out_p, buft_out_n); - input G; - input P; - output buft_out_n; - output buft_out_p; - input clk; - input ibuf0_en; - input ibuf10_en; - input ibuf11_en; - input ibuf12_en; - input ibuf13_en; - input ibuf14_en; - input ibuf15_en; - input ibuf16_en; - input ibuf1_en; - input ibuf2_en; - input ibuf3_en; - input ibuf4_en; - input ibuf5_en; - input ibuf6_en; - input ibuf7_en; - input ibuf8_en; - input ibuf9_en; - input [2:0] in_n; - input [2:0] in_p; - input mux1_sel_n; - input mux1_sel_p; - input mux2_sel_n; - input mux2_sel_p; - input obuft_oe; - output q_n; - output q_p; - input [5:0] ram_addr; - input ram_we; - input rst_n; - input rst_p; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] _00_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _01_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] _02_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _03_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] _04_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _05_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] _06_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire _07_; - wire _08_; - (* keep = 32'h00000001 *) - wire _09_; - (* keep = 32'h00000001 *) - (* unused_bits = "1 2 3 4 5 6 7" *) - wire [7:0] _10_; - (* unused_bits = "1 2 3 4 5 6 7" *) - wire [7:0] _11_; - (* unused_bits = "1 2 3 4 5 6 7 8" *) - wire [8:0] _12_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:461.28-461.34" *) - (* unused_bits = "0" *) - wire _13_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:498.14-498.27" *) - (* unused_bits = "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _14_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:500.14-500.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _15_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:499.14-499.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _16_; - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:501.14-501.27" *) - (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17" *) - wire [17:0] _17_; - (* src = "./rtl/primitive_example_design_2.v:6.13-6.14" *) - (* src = "./rtl/primitive_example_design_2.v:6.13-6.14" *) - wire G; - (* src = "./rtl/primitive_example_design_2.v:6.11-6.12" *) - (* src = "./rtl/primitive_example_design_2.v:6.11-6.12" *) - wire P; - (* src = "./rtl/primitive_example_design_2.v:22.10-22.19" *) - wire Q_buff_in; - (* src = "./rtl/primitive_example_design_2.v:20.18-20.25" *) - wire acc_out; - (* src = "./rtl/primitive_example_design_2.v:10.31-10.41" *) - (* src = "./rtl/primitive_example_design_2.v:10.31-10.41" *) - wire buft_out_n; - (* src = "./rtl/primitive_example_design_2.v:10.20-10.30" *) - (* src = "./rtl/primitive_example_design_2.v:10.20-10.30" *) - wire buft_out_p; - (* src = "./rtl/primitive_example_design_2.v:3.11-3.14" *) - (* src = "./rtl/primitive_example_design_2.v:3.11-3.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_2.v:15.21-15.32" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_2.v:19.10-19.20" *) - wire dffnre_out; - (* hdlname = "ff_inst1 D" *) - (* src = "./rtl/primitive_example_design_2.v:49.15-49.66|./rtl/primitive_example_design_2.v:80.11-80.12" *) - wire \ff_inst1.D ; - (* hdlname = "ff_inst1 Q" *) - (* keep = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:49.15-49.66|./rtl/primitive_example_design_2.v:81.16-81.17" *) - wire \ff_inst1.Q ; - (* src = "./rtl/primitive_example_design_2.v:18.21-18.27" *) - wire g_ibuf; - (* src = "./rtl/primitive_example_design_2.v:17.24-17.38" *) - wire i_buf_mux1_sel; - (* src = "./rtl/primitive_example_design_2.v:17.39-17.53" *) - wire i_buf_mux2_sel; - (* src = "./rtl/primitive_example_design_2.v:13.16-13.25" *) - wire [2:0] i_buf_out; - (* src = "./rtl/primitive_example_design_2.v:5.11-5.19" *) - (* src = "./rtl/primitive_example_design_2.v:5.11-5.19" *) - wire ibuf0_en; - (* src = "./rtl/primitive_example_design_2.v:5.101-5.110" *) - (* src = "./rtl/primitive_example_design_2.v:5.101-5.110" *) - wire ibuf10_en; - (* src = "./rtl/primitive_example_design_2.v:5.111-5.120" *) - (* src = "./rtl/primitive_example_design_2.v:5.111-5.120" *) - wire ibuf11_en; - (* src = "./rtl/primitive_example_design_2.v:5.121-5.130" *) - (* src = "./rtl/primitive_example_design_2.v:5.121-5.130" *) - wire ibuf12_en; - (* src = "./rtl/primitive_example_design_2.v:5.131-5.140" *) - (* src = "./rtl/primitive_example_design_2.v:5.131-5.140" *) - wire ibuf13_en; - (* src = "./rtl/primitive_example_design_2.v:5.141-5.150" *) - (* src = "./rtl/primitive_example_design_2.v:5.141-5.150" *) - wire ibuf14_en; - (* src = "./rtl/primitive_example_design_2.v:5.151-5.160" *) - (* src = "./rtl/primitive_example_design_2.v:5.151-5.160" *) - wire ibuf15_en; - (* src = "./rtl/primitive_example_design_2.v:5.161-5.170" *) - (* src = "./rtl/primitive_example_design_2.v:5.161-5.170" *) - wire ibuf16_en; - (* src = "./rtl/primitive_example_design_2.v:5.20-5.28" *) - (* src = "./rtl/primitive_example_design_2.v:5.20-5.28" *) - wire ibuf1_en; - (* src = "./rtl/primitive_example_design_2.v:5.29-5.37" *) - (* src = "./rtl/primitive_example_design_2.v:5.29-5.37" *) - wire ibuf2_en; - (* src = "./rtl/primitive_example_design_2.v:5.38-5.46" *) - (* src = "./rtl/primitive_example_design_2.v:5.38-5.46" *) - wire ibuf3_en; - (* src = "./rtl/primitive_example_design_2.v:5.47-5.55" *) - (* src = "./rtl/primitive_example_design_2.v:5.47-5.55" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_2.v:5.56-5.64" *) - (* src = "./rtl/primitive_example_design_2.v:5.56-5.64" *) - wire ibuf5_en; - (* src = "./rtl/primitive_example_design_2.v:5.65-5.73" *) - (* src = "./rtl/primitive_example_design_2.v:5.65-5.73" *) - wire ibuf6_en; - (* src = "./rtl/primitive_example_design_2.v:5.74-5.82" *) - (* src = "./rtl/primitive_example_design_2.v:5.74-5.82" *) - wire ibuf7_en; - (* src = "./rtl/primitive_example_design_2.v:5.83-5.91" *) - (* src = "./rtl/primitive_example_design_2.v:5.83-5.91" *) - wire ibuf8_en; - (* src = "./rtl/primitive_example_design_2.v:5.92-5.100" *) - (* src = "./rtl/primitive_example_design_2.v:5.92-5.100" *) - wire ibuf9_en; - (* src = "./rtl/primitive_example_design_2.v:24.16-24.29" *) - wire ibuf_obuft_oe; - (* src = "./rtl/primitive_example_design_2.v:2.17-2.21" *) - (* src = "./rtl/primitive_example_design_2.v:2.17-2.21" *) - wire [2:0] in_n; - (* src = "./rtl/primitive_example_design_2.v:2.22-2.26" *) - (* src = "./rtl/primitive_example_design_2.v:2.22-2.26" *) - wire [2:0] in_p; - (* src = "./rtl/primitive_example_design_2.v:16.10-16.17" *) - wire lut_out; - (* src = "./rtl/primitive_example_design_2.v:4.11-4.21" *) - (* src = "./rtl/primitive_example_design_2.v:4.11-4.21" *) - wire mux1_sel_n; - (* src = "./rtl/primitive_example_design_2.v:4.22-4.32" *) - (* src = "./rtl/primitive_example_design_2.v:4.22-4.32" *) - wire mux1_sel_p; - (* src = "./rtl/primitive_example_design_2.v:21.10-21.18" *) - wire mux2_out; - (* src = "./rtl/primitive_example_design_2.v:4.33-4.43" *) - (* src = "./rtl/primitive_example_design_2.v:4.33-4.43" *) - wire mux2_sel_n; - (* src = "./rtl/primitive_example_design_2.v:4.44-4.54" *) - (* src = "./rtl/primitive_example_design_2.v:4.44-4.54" *) - wire mux2_sel_p; - (* src = "./rtl/primitive_example_design_2.v:9.11-9.19" *) - (* src = "./rtl/primitive_example_design_2.v:9.11-9.19" *) - wire obuft_oe; - (* src = "./rtl/primitive_example_design_2.v:18.10-18.13" *) - wire out; - (* src = "./rtl/primitive_example_design_2.v:18.14-18.20" *) - wire p_ibuf; - (* src = "./rtl/primitive_example_design_2.v:10.16-10.19" *) - (* src = "./rtl/primitive_example_design_2.v:10.16-10.19" *) - wire q_n; - (* src = "./rtl/primitive_example_design_2.v:10.12-10.15" *) - (* src = "./rtl/primitive_example_design_2.v:10.12-10.15" *) - wire q_p; - (* src = "./rtl/primitive_example_design_2.v:7.17-7.25" *) - (* src = "./rtl/primitive_example_design_2.v:7.17-7.25" *) - wire [5:0] ram_addr; - (* hdlname = "ram_inst addr" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:95.27-95.31" *) - wire [5:0] \ram_inst.addr ; - (* hdlname = "ram_inst we" *) - (* src = "./rtl/primitive_example_design_2.v:61.27-61.116|./rtl/primitive_example_design_2.v:96.8-96.10" *) - wire \ram_inst.we ; - (* src = "./rtl/primitive_example_design_2.v:23.10-23.17" *) - wire ram_out; - (* src = "./rtl/primitive_example_design_2.v:8.11-8.17" *) - (* src = "./rtl/primitive_example_design_2.v:8.11-8.17" *) - wire ram_we; - (* src = "./rtl/primitive_example_design_2.v:17.10-17.23" *) - wire rst_i_buf_out; - (* src = "./rtl/primitive_example_design_2.v:3.16-3.21" *) - (* src = "./rtl/primitive_example_design_2.v:3.16-3.21" *) - wire rst_n; - (* src = "./rtl/primitive_example_design_2.v:3.22-3.27" *) - (* src = "./rtl/primitive_example_design_2.v:3.22-3.27" *) - wire rst_p; - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'hac) - ) _18_ ( - .Y(mux2_out), - .A({ i_buf_mux2_sel, acc_out, \ff_inst1.D }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _19_ ( - .C(clk), - .D(Q_buff_in), - .E(1'h1), - .Q(_10_[0]), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _20_ ( - .C(clk), - .D(\ff_inst1.D ), - .E(1'h1), - .Q(\ff_inst1.Q ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h3e) - ) _21_ ( - .Y(lut_out), - .A({ i_buf_out[1:0], i_buf_out[2] }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h9) - ) _22_ ( - .Y(out), - .A({ i_buf_mux1_sel, dffnre_out }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE _23_ ( - .C(clk), - .D(\ram_inst.we ), - .E(1'h1), - .Q(_09_), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'hac) - ) _24_ ( - .Y(ram_out), - .A({ _09_, _08_, _10_[0] }) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:59.17-59.93" *) - CARRY_CHAIN carry_chain_inst ( - .CIN(out), - .COUT(acc_out), - .G(g_ibuf), - .O(\ff_inst1.D ), - .P(p_ibuf) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:26.11-26.63" *) - I_BUF clk_buf_inst ( - .EN(ibuf0_en), - .I(clk), - .O(clk_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:55.11-55.90" *) - DFFRE ff_inst ( - .C(clk_buf_out), - .D(mux2_out), - .E(1'h1), - .Q(Q_buff_in), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:45.12-45.92" *) - DFFNRE ffn_inst ( - .C(clk_buf_out), - .D(lut_out), - .E(1'h1), - .Q(dffnre_out), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:28.14-28.88" *) - I_BUF_DS ibuf_ds_inst1 ( - .EN(ibuf1_en), - .I_N(in_n[0]), - .I_P(in_p[0]), - .O(i_buf_out[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:29.14-29.88" *) - I_BUF_DS ibuf_ds_inst2 ( - .EN(ibuf2_en), - .I_N(in_n[1]), - .I_P(in_p[1]), - .O(i_buf_out[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:30.14-30.88" *) - I_BUF_DS ibuf_ds_inst3 ( - .EN(ibuf3_en), - .I_N(in_n[2]), - .I_P(in_p[2]), - .O(i_buf_out[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:31.14-31.85" *) - I_BUF_DS ibuf_ds_inst4 ( - .EN(ibuf4_en), - .I_N(rst_n), - .I_P(rst_p), - .O(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:32.14-32.96" *) - I_BUF_DS ibuf_ds_inst5 ( - .EN(ibuf5_en), - .I_N(mux1_sel_n), - .I_P(mux1_sel_p), - .O(i_buf_mux1_sel) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:33.14-33.96" *) - I_BUF_DS ibuf_ds_inst6 ( - .EN(ibuf6_en), - .I_N(mux2_sel_n), - .I_P(mux2_sel_p), - .O(i_buf_mux2_sel) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:37.11-37.77" *) - I_BUF ibuf_inst10 ( - .EN(ibuf10_en), - .I(ram_addr[0]), - .O(\ram_inst.addr [0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:38.11-38.77" *) - I_BUF ibuf_inst11 ( - .EN(ibuf11_en), - .I(ram_addr[1]), - .O(\ram_inst.addr [1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:39.11-39.77" *) - I_BUF ibuf_inst12 ( - .EN(ibuf12_en), - .I(ram_addr[2]), - .O(\ram_inst.addr [2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:40.11-40.77" *) - I_BUF ibuf_inst13 ( - .EN(ibuf13_en), - .I(ram_addr[3]), - .O(\ram_inst.addr [3]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:41.11-41.77" *) - I_BUF ibuf_inst14 ( - .EN(ibuf14_en), - .I(ram_addr[4]), - .O(\ram_inst.addr [4]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:42.11-42.77" *) - I_BUF ibuf_inst15 ( - .EN(ibuf15_en), - .I(ram_addr[5]), - .O(\ram_inst.addr [5]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:43.11-43.70" *) - I_BUF ibuf_inst16 ( - .EN(ibuf16_en), - .I(obuft_oe), - .O(ibuf_obuft_oe) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:34.11-34.54" *) - I_BUF ibuf_inst7 ( - .EN(ibuf7_en), - .I(P), - .O(p_ibuf) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:35.11-35.54" *) - I_BUF ibuf_inst8 ( - .EN(ibuf8_en), - .I(G), - .O(g_ibuf) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:36.11-36.65" *) - I_BUF ibuf_inst9 ( - .EN(ibuf9_en), - .I(ram_we), - .O(\ram_inst.we ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:53.14-53.62" *) - O_BUF_DS o_buff_ds_inst ( - .I(ram_out), - .O_N(q_n), - .O_P(q_p) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_2.v:51.15-51.92" *) - O_BUFT_DS obuft_ds_inst ( - .I(\ff_inst1.Q ), - .O_N(buft_out_n), - .O_P(buft_out_p), - .T(ibuf_obuft_oe) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_map_new_version.v:495.4-506.3|/nfs_scratch/scratch/eda/behzad/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/brams_final_map_new_version.v:645.7-684.2" *) - TDP_RAM18KX2 #( - .INIT1(16384'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT1_PARITY(2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT2(16384'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .INIT2_PARITY(2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), - .READ_WIDTH_A1(32'h00000009), - .READ_WIDTH_A2(32'sh00000001), - .READ_WIDTH_B1(32'h00000009), - .READ_WIDTH_B2(32'sh00000001), - .WRITE_WIDTH_A1(32'h00000009), - .WRITE_WIDTH_A2(32'sh00000001), - .WRITE_WIDTH_B1(32'h00000009), - .WRITE_WIDTH_B2(32'sh00000001) - ) \ram_inst.ram.0.0 ( - .ADDR_A1({ 5'h00, \ram_inst.addr , 3'h0 }), - .ADDR_A2(14'hxxxx), - .ADDR_B1({ 5'h00, \ram_inst.addr , 3'h0 }), - .ADDR_B2(14'hxxxx), - .BE_A1(2'h0), - .BE_A2(2'h0), - .BE_B1({ 1'h0, \ram_inst.we }), - .BE_B2(2'hx), - .CLK_A1(clk), - .CLK_A2(1'hx), - .CLK_B1(clk), - .CLK_B2(1'hx), - .RDATA_A1({ _14_[15:9], _12_[8], _11_[7:1], _08_ }), - .RDATA_A2({ _15_[15:1], _13_ }), - .RDATA_B1(_16_[15:0]), - .RDATA_B2(_17_[15:0]), - .REN_A1(1'h1), - .REN_A2(1'hx), - .REN_B1(1'h0), - .REN_B2(1'h0), - .RPARITY_A1(_14_[17:16]), - .RPARITY_A2(_15_[17:16]), - .RPARITY_B1(_16_[17:16]), - .RPARITY_B2(_17_[17:16]), - .WDATA_A1(16'hxxxx), - .WDATA_A2(16'hxxxx), - .WDATA_B1({ 15'bxxxxxxxx0000000, Q_buff_in }), - .WDATA_B2(16'hxxxx), - .WEN_A1(1'h0), - .WEN_A2(1'h0), - .WEN_B1(\ram_inst.we ), - .WEN_B2(1'hx), - .WPARITY_A1(2'hx), - .WPARITY_A2(2'hx), - .WPARITY_B1(2'hx), - .WPARITY_B2(2'hx) - ); - assign _15_[0] = _13_; - assign _14_[8:0] = { _12_[8], _11_[7:1], _08_ }; - assign _12_[7:0] = { _11_[7:1], _08_ }; - assign _11_[0] = _08_; - assign _10_[6:1] = { _10_[7], _10_[7], _10_[7], _10_[7], _10_[7], _10_[7] }; -endmodule diff --git a/design_edit/Tests/primitive_example_design_3/gold/interface.json b/design_edit/Tests/primitive_example_design_3/gold/interface.json deleted file mode 100644 index 384b04965..000000000 --- a/design_edit/Tests/primitive_example_design_3/gold/interface.json +++ /dev/null @@ -1,2859 +0,0 @@ -{ - "IO_Instances": { - "gen_i_buf[0].i_buf_instance": { - "module": "I_BUF", - "ports": { - "EN": null, - "I": [ - { - "Actual": "A", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "a_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "gen_i_buf[0].i_buf_instance_b": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf2_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "B", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "b_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "gen_i_buf[0].i_buf_instance_shift": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf3_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "SHIFT_RIGHT", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_shift_right", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "gen_i_buf[10].i_buf_instance": { - "module": "I_BUF", - "ports": { - "EN": null, - "I": [ - { - "Actual": "A", - "FUNC": "IN_DIR", - "lsb": 10, - "msb": 10 - } - ], - "O": [ - { - "Actual": "a_out", - "FUNC": "OUT_DIR", - "lsb": 10, - "msb": 10 - } - ] - } - }, - "gen_i_buf[10].i_buf_instance_b": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf2_en", - "FUNC": "IN_DIR", - "lsb": 10, - "msb": 10 - } - ], - "I": [ - { - "Actual": "B", - "FUNC": "IN_DIR", - "lsb": 10, - "msb": 10 - } - ], - "O": [ - { - "Actual": "b_out", - "FUNC": "OUT_DIR", - "lsb": 10, - "msb": 10 - } - ] - } - }, - "gen_i_buf[11].i_buf_instance": { - "module": "I_BUF", - "ports": { - "EN": null, - "I": [ - { - "Actual": "A", - "FUNC": "IN_DIR", - "lsb": 11, - "msb": 11 - } - ], - "O": [ - { - "Actual": "a_out", - "FUNC": "OUT_DIR", - "lsb": 11, - "msb": 11 - } - ] - } - }, - "gen_i_buf[11].i_buf_instance_b": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf2_en", - "FUNC": "IN_DIR", - "lsb": 11, - "msb": 11 - } - ], - "I": [ - { - "Actual": "B", - "FUNC": "IN_DIR", - "lsb": 11, - "msb": 11 - } - ], - "O": [ - { - "Actual": "b_out", - "FUNC": "OUT_DIR", - "lsb": 11, - "msb": 11 - } - ] - } - }, - "gen_i_buf[12].i_buf_instance": { - "module": "I_BUF", - "ports": { - "EN": null, - "I": [ - { - "Actual": "A", - "FUNC": "IN_DIR", - "lsb": 12, - "msb": 12 - } - ], - "O": [ - { - "Actual": "a_out", - "FUNC": "OUT_DIR", - "lsb": 12, - "msb": 12 - } - ] - } - }, - "gen_i_buf[12].i_buf_instance_b": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf2_en", - "FUNC": "IN_DIR", - "lsb": 12, - "msb": 12 - } - ], - "I": [ - { - "Actual": "B", - "FUNC": "IN_DIR", - "lsb": 12, - "msb": 12 - } - ], - "O": [ - { - "Actual": "b_out", - "FUNC": "OUT_DIR", - "lsb": 12, - "msb": 12 - } - ] - } - }, - "gen_i_buf[13].i_buf_instance": { - "module": "I_BUF", - "ports": { - "EN": null, - "I": [ - { - "Actual": "A", - "FUNC": "IN_DIR", - "lsb": 13, - "msb": 13 - } - ], - "O": [ - { - "Actual": "a_out", - "FUNC": "OUT_DIR", - "lsb": 13, - "msb": 13 - } - ] - } - }, - "gen_i_buf[13].i_buf_instance_b": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf2_en", - "FUNC": "IN_DIR", - "lsb": 13, - "msb": 13 - } - ], - "I": [ - { - "Actual": "B", - "FUNC": "IN_DIR", - "lsb": 13, - "msb": 13 - } - ], - "O": [ - { - "Actual": "b_out", - "FUNC": "OUT_DIR", - "lsb": 13, - "msb": 13 - } - ] - } - }, - "gen_i_buf[14].i_buf_instance": { - "module": "I_BUF", - "ports": { - "EN": null, - "I": [ - { - "Actual": "A", - "FUNC": "IN_DIR", - "lsb": 14, - "msb": 14 - } - ], - "O": [ - { - "Actual": "a_out", - "FUNC": "OUT_DIR", - "lsb": 14, - "msb": 14 - } - ] - } - }, - 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"ACC_FIR", - "FUNC": "IN_DIR", - "lsb": 4, - "msb": 4 - } - ], - "O": [ - { - "Actual": "i_buf_ACC_FIR", - "FUNC": "OUT_DIR", - "lsb": 4, - "msb": 4 - } - ] - } - }, - "i_buf_instance9": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf4_en", - "FUNC": "IN_DIR", - "lsb": 7, - "msb": 7 - } - ], - "I": [ - { - "Actual": "ACC_FIR", - "FUNC": "IN_DIR", - "lsb": 5, - "msb": 5 - } - ], - "O": [ - { - "Actual": "i_buf_ACC_FIR", - "FUNC": "OUT_DIR", - "lsb": 5, - "msb": 5 - } - ] - } - } - } -} diff --git a/design_edit/Tests/primitive_example_design_3/gold/io_config.json b/design_edit/Tests/primitive_example_design_3/gold/io_config.json deleted file mode 100644 index e4b16f70f..000000000 --- a/design_edit/Tests/primitive_example_design_3/gold/io_config.json +++ /dev/null @@ -1,4050 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\A (index=0, width=20, offset=0)", - " Detect input port \\A (index=1, width=20, offset=0)", - " Detect input port \\A (index=2, width=20, offset=0)", - " Detect input port \\A (index=3, width=20, offset=0)", - " Detect input port \\A (index=4, width=20, offset=0)", - " Detect input port \\A (index=5, width=20, offset=0)", - " Detect input port \\A (index=6, width=20, offset=0)", - " Detect input port \\A (index=7, width=20, offset=0)", - " Detect input port \\A (index=8, width=20, offset=0)", - " Detect input port \\A (index=9, width=20, offset=0)", - " Detect input port \\A (index=10, width=20, offset=0)", - " Detect input port \\A (index=11, width=20, offset=0)", - " Detect input port \\A (index=12, width=20, offset=0)", - " Detect input port \\A (index=13, width=20, offset=0)", - " Detect input port \\A (index=14, width=20, offset=0)", - " Detect input port \\A (index=15, width=20, offset=0)", - " Detect input port \\A (index=16, width=20, offset=0)", - " Detect input port \\A (index=17, width=20, offset=0)", - " Detect input port \\A (index=18, width=20, offset=0)", - " Detect input port \\A (index=19, width=20, offset=0)", - " Detect input port \\ACC_FIR (index=0, width=6, offset=0)", - " Detect input port \\ACC_FIR (index=1, width=6, offset=0)", - " Detect input port \\ACC_FIR (index=2, width=6, offset=0)", - " Detect input port \\ACC_FIR (index=3, width=6, offset=0)", - " Detect input port \\ACC_FIR (index=4, width=6, offset=0)", - " Detect input port \\ACC_FIR (index=5, width=6, offset=0)", - " Detect input port \\B (index=0, width=18, offset=0)", - " Detect input port \\B (index=1, width=18, offset=0)", - " Detect input port \\B (index=2, width=18, offset=0)", - " Detect input port \\B (index=3, width=18, offset=0)", - " Detect input port \\B (index=4, width=18, offset=0)", - " Detect input port \\B (index=5, width=18, offset=0)", - " Detect input port \\B (index=6, width=18, offset=0)", - " Detect input port \\B (index=7, width=18, offset=0)", - " Detect input port \\B (index=8, width=18, offset=0)", - " Detect input port \\B (index=9, width=18, offset=0)", - " Detect input port \\B (index=10, width=18, offset=0)", - " Detect input port \\B (index=11, width=18, offset=0)", - " Detect input port \\B (index=12, width=18, offset=0)", - " Detect input port \\B (index=13, width=18, offset=0)", - " Detect input port \\B (index=14, width=18, offset=0)", - " Detect input port \\B (index=15, width=18, offset=0)", - " Detect input port \\B (index=16, width=18, offset=0)", - " Detect input port \\B (index=17, width=18, offset=0)", - " Detect input port \\CLK (index=0, width=1, offset=0)", - " Detect output port \\DLY_B (index=0, width=18, offset=0)", - " Detect output port \\DLY_B (index=1, width=18, offset=0)", - " Detect output port \\DLY_B (index=2, width=18, offset=0)", - " Detect output port \\DLY_B (index=3, width=18, offset=0)", - " Detect output port \\DLY_B (index=4, width=18, offset=0)", - " Detect output port \\DLY_B (index=5, width=18, offset=0)", - " Detect output port \\DLY_B (index=6, width=18, offset=0)", - " Detect output port \\DLY_B (index=7, width=18, offset=0)", - " Detect output port \\DLY_B (index=8, width=18, offset=0)", - " Detect output port \\DLY_B (index=9, width=18, offset=0)", - " Detect output port \\DLY_B (index=10, width=18, offset=0)", - " Detect output port \\DLY_B (index=11, width=18, offset=0)", - " Detect output port \\DLY_B (index=12, width=18, offset=0)", - " Detect output port \\DLY_B (index=13, width=18, offset=0)", - " Detect output port \\DLY_B (index=14, width=18, offset=0)", - " Detect output port \\DLY_B (index=15, width=18, offset=0)", - " Detect output port \\DLY_B (index=16, width=18, offset=0)", - " Detect output port \\DLY_B (index=17, width=18, offset=0)", - " Detect input port \\FEEDBACK (index=0, width=3, offset=0)", - " Detect input port \\FEEDBACK (index=1, width=3, offset=0)", - " Detect input port \\FEEDBACK (index=2, width=3, offset=0)", - " Detect input port \\LOAD_ACC (index=0, width=1, offset=0)", - " Detect input port \\RESET (index=0, width=1, offset=0)", - " Detect input port \\ROUND (index=0, width=1, offset=0)", - " Detect input port \\SATURATE (index=0, width=1, offset=0)", - " Detect input port \\SHIFT_RIGHT (index=0, width=6, offset=0)", - " Detect input port \\SHIFT_RIGHT (index=1, width=6, offset=0)", - " Detect input port \\SHIFT_RIGHT (index=2, width=6, offset=0)", - " Detect input port \\SHIFT_RIGHT (index=3, width=6, offset=0)", - " Detect input port \\SHIFT_RIGHT (index=4, width=6, offset=0)", - " Detect input port \\SHIFT_RIGHT (index=5, width=6, offset=0)", - " Detect input port \\SUBTRACT (index=0, width=1, offset=0)", - " Detect input port \\UNSIGNED_A (index=0, width=1, offset=0)", - " Detect input port \\UNSIGNED_B (index=0, width=1, offset=0)", - " Detect output port \\Z (index=0, width=38, offset=0)", - " Detect output port \\Z (index=1, width=38, offset=0)", - " Detect output port \\Z (index=2, width=38, offset=0)", - " Detect output port \\Z (index=3, width=38, offset=0)", - " Detect output port \\Z (index=4, width=38, offset=0)", - " Detect output port \\Z (index=5, width=38, offset=0)", - " Detect output port \\Z (index=6, width=38, offset=0)", - " Detect output port \\Z (index=7, width=38, offset=0)", - " Detect output port \\Z (index=8, width=38, offset=0)", - " Detect output port \\Z (index=9, width=38, offset=0)", - " Detect output port \\Z (index=10, width=38, offset=0)", - " Detect output port \\Z (index=11, width=38, offset=0)", - " Detect output port \\Z (index=12, width=38, offset=0)", - " Detect output port \\Z (index=13, width=38, offset=0)", - " Detect output port \\Z (index=14, width=38, offset=0)", - " Detect output port \\Z (index=15, width=38, offset=0)", - " Detect output port \\Z (index=16, width=38, offset=0)", - " Detect output port \\Z (index=17, width=38, offset=0)", - " Detect output port \\Z (index=18, width=38, offset=0)", - " Detect output port \\Z (index=19, width=38, offset=0)", - " Detect output port \\Z (index=20, width=38, offset=0)", - " Detect output port \\Z (index=21, width=38, offset=0)", - " Detect output port \\Z (index=22, width=38, offset=0)", - " Detect output port \\Z (index=23, width=38, offset=0)", - " Detect output port \\Z (index=24, width=38, offset=0)", - " Detect output port \\Z (index=25, width=38, offset=0)", - " Detect output port \\Z (index=26, width=38, offset=0)", - " Detect output port \\Z (index=27, width=38, offset=0)", - " Detect output port \\Z (index=28, width=38, offset=0)", - " Detect output port \\Z (index=29, width=38, offset=0)", - " Detect output port \\Z (index=30, width=38, offset=0)", - " Detect output port \\Z (index=31, width=38, offset=0)", - " Detect output port \\Z (index=32, width=38, offset=0)", - " Detect output port \\Z (index=33, width=38, offset=0)", - " Detect output port \\Z (index=34, width=38, offset=0)", - " Detect output port \\Z (index=35, width=38, offset=0)", - " Detect output port \\Z (index=36, width=38, offset=0)", - " Detect output port \\Z (index=37, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=0, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=1, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=2, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=3, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=4, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=5, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=6, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=7, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=8, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=9, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=10, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=11, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=12, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=13, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=14, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=15, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=16, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=17, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=18, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=19, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=20, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=21, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=22, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=23, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=24, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=25, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=26, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=27, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=28, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=29, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=30, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=31, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=32, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=33, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=34, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=35, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=36, width=38, offset=0)", - " Detect input port \\i_buft_oe (index=37, width=38, offset=0)", - " Detect input port \\ibuf1_en (index=0, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=1, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=2, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=3, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=4, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=5, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=6, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=7, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=8, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=9, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=10, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=11, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=12, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=13, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=14, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=15, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=16, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=17, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=18, width=20, offset=0)", - " Detect input port \\ibuf1_en (index=19, width=20, offset=0)", - " Detect input port \\ibuf2_en (index=0, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=1, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=2, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=3, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=4, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=5, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=6, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=7, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=8, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=9, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=10, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=11, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=12, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=13, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=14, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=15, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=16, width=18, offset=0)", - " Detect input port \\ibuf2_en (index=17, width=18, offset=0)", - " Detect input port \\ibuf3_en (index=0, width=6, offset=0)", - " Detect input port \\ibuf3_en (index=1, width=6, offset=0)", - " Detect input port \\ibuf3_en (index=2, width=6, offset=0)", - " Detect input port \\ibuf3_en (index=3, width=6, offset=0)", - " Detect input port \\ibuf3_en (index=4, width=6, offset=0)", - " Detect input port \\ibuf3_en (index=5, width=6, offset=0)", - " Detect input port \\ibuf4_en (index=0, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=1, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=2, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=3, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=4, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=5, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=6, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=7, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=8, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=9, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=10, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=11, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=12, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=13, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=14, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=15, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=16, width=18, offset=0)", - " Detect input port \\ibuf4_en (index=17, width=18, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_3.Z", - " Cell port \\O is connected to output port \\Z[37]", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe", - " Cell port \\I is connected to input port \\i_buft_oe[1]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_1", - " Cell port \\I is connected to input port \\i_buft_oe[2]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_10", - " Cell port \\I is connected to input port \\i_buft_oe[11]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_11", - " Cell port \\I is connected to input port \\i_buft_oe[12]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_12", - " Cell port \\I is connected to input port \\i_buft_oe[13]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_13", - " Cell port \\I is connected to input port \\i_buft_oe[14]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_14", - " Cell port \\I is connected to input port \\i_buft_oe[15]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_15", - " Cell port \\I is connected to input port \\i_buft_oe[16]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_16", - " Cell port \\I is connected to input port \\i_buft_oe[17]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_17", - " Cell port \\I is connected to input port \\i_buft_oe[18]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_18", - " Cell port \\I is connected to input port \\i_buft_oe[19]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_19", - " Cell port \\I is connected to input port \\i_buft_oe[20]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_2", - " Cell port \\I is connected to input port \\i_buft_oe[3]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_20", - " Cell port \\I is connected to input port \\i_buft_oe[21]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_21", - " Cell port \\I is connected to input port \\i_buft_oe[22]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_22", - " Cell port \\I is connected to input port \\i_buft_oe[23]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_23", - " Cell port \\I is connected to input port \\i_buft_oe[24]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_24", - " Cell port \\I is connected to input port \\i_buft_oe[25]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_25", - " Cell port \\I is connected to input port \\i_buft_oe[26]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_26", - " Cell port \\I is connected to input port \\i_buft_oe[27]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_27", - " Cell port \\I is connected to input port \\i_buft_oe[28]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_28", - " Cell port \\I is connected to input port \\i_buft_oe[29]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_29", - " Cell port \\I is connected to input port \\i_buft_oe[30]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_3", - " Cell port \\I is connected to input port \\i_buft_oe[4]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_30", - " Cell port \\I is connected to input port \\i_buft_oe[31]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_31", - " Cell port \\I is connected to input port \\i_buft_oe[32]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_32", - " Cell port \\I is connected to input port \\i_buft_oe[33]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_33", - " Cell port \\I is connected to input port \\i_buft_oe[34]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_34", - " Cell port \\I is connected to input port \\i_buft_oe[35]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_35", - " Cell port \\I is connected to input port \\i_buft_oe[36]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_36", - " Cell port \\I is connected to input port \\i_buft_oe[37]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_4", - " Cell port \\I is connected to input port \\i_buft_oe[5]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_5", - " Cell port \\I is connected to input port \\i_buft_oe[6]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_6", - " Cell port \\I is connected to input port \\i_buft_oe[7]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_7", - " Cell port \\I is connected to input port \\i_buft_oe[8]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_8", - " Cell port \\I is connected to input port \\i_buft_oe[9]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.i_buft_oe_9", - " Cell port \\I is connected to input port \\i_buft_oe[10]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en", - " Cell port \\I is connected to input port \\ibuf1_en[0]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_1", - " Cell port \\I is connected to input port \\ibuf1_en[1]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_10", - " Cell port \\I is connected to input port \\ibuf1_en[10]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_11", - " Cell port \\I is connected to input port \\ibuf1_en[11]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_12", - " Cell port \\I is connected to input port \\ibuf1_en[12]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_13", - " Cell port \\I is connected to input port \\ibuf1_en[13]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_14", - " Cell port \\I is connected to input port \\ibuf1_en[14]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_15", - " Cell port \\I is connected to input port \\ibuf1_en[15]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_16", - " Cell port \\I is connected to input port \\ibuf1_en[16]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_17", - " Cell port \\I is connected to input port \\ibuf1_en[17]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_18", - " Cell port \\I is connected to input port \\ibuf1_en[18]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_19", - " Cell port \\I is connected to input port \\ibuf1_en[19]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_2", - " Cell port \\I is connected to input port \\ibuf1_en[2]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_3", - " Cell port \\I is connected to input port \\ibuf1_en[3]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_4", - " Cell port \\I is connected to input port \\ibuf1_en[4]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_5", - " Cell port \\I is connected to input port \\ibuf1_en[5]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_6", - " Cell port \\I is connected to input port \\ibuf1_en[6]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_7", - " Cell port \\I is connected to input port \\ibuf1_en[7]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_8", - " Cell port \\I is connected to input port \\ibuf1_en[8]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf1_en_9", - " Cell port \\I is connected to input port \\ibuf1_en[9]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en", - " Cell port \\I is connected to input port \\ibuf2_en[0]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_1", - " Cell port \\I is connected to input port \\ibuf2_en[1]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_10", - " Cell port \\I is connected to input port \\ibuf2_en[10]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_11", - " Cell port \\I is connected to input port \\ibuf2_en[11]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_12", - " Cell port \\I is connected to input port \\ibuf2_en[12]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_13", - " Cell port \\I is connected to input port \\ibuf2_en[13]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_14", - " Cell port \\I is connected to input port \\ibuf2_en[14]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_15", - " Cell port \\I is connected to input port \\ibuf2_en[15]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_16", - " Cell port \\I is connected to input port \\ibuf2_en[16]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_17", - " Cell port \\I is connected to input port \\ibuf2_en[17]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_2", - " Cell port \\I is connected to input port \\ibuf2_en[2]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_3", - " Cell port \\I is connected to input port \\ibuf2_en[3]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_4", - " Cell port \\I is connected to input port \\ibuf2_en[4]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_5", - " Cell port \\I is connected to input port \\ibuf2_en[5]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_6", - " Cell port \\I is connected to input port \\ibuf2_en[6]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_7", - " Cell port \\I is connected to input port \\ibuf2_en[7]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_8", - " Cell port \\I is connected to input port \\ibuf2_en[8]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf2_en_9", - " Cell port \\I is connected to input port \\ibuf2_en[9]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf3_en", - " Cell port \\I is connected to input port \\ibuf3_en[0]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf3_en_1", - " Cell port \\I is connected to input port \\ibuf3_en[1]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf3_en_2", - " Cell port \\I is connected to input port \\ibuf3_en[2]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf3_en_3", - " Cell port \\I is connected to input port \\ibuf3_en[3]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf3_en_4", - " Cell port \\I is connected to input port \\ibuf3_en[4]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf3_en_5", - " Cell port \\I is connected to input port \\ibuf3_en[5]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en", - " Cell port \\I is connected to input port \\ibuf4_en[0]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_1", - " Cell port \\I is connected to input port \\ibuf4_en[1]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_10", - " Cell port \\I is connected to input port \\ibuf4_en[10]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_11", - " Cell port \\I is connected to input port \\ibuf4_en[11]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_12", - " Cell port \\I is connected to input port \\ibuf4_en[12]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_13", - " Cell port \\I is connected to input port \\ibuf4_en[13]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_14", - " Cell port \\I is connected to input port \\ibuf4_en[14]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_15", - " Cell port \\I is connected to input port \\ibuf4_en[15]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_16", - " Cell port \\I is connected to input port \\ibuf4_en[16]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_17", - " Cell port \\I is connected to input port \\ibuf4_en[17]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_2", - " Cell port \\I is connected to input port \\ibuf4_en[2]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_3", - " Cell port \\I is connected to input port \\ibuf4_en[3]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_4", - " Cell port \\I is connected to input port \\ibuf4_en[4]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_5", - " Cell port \\I is connected to input port \\ibuf4_en[5]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_6", - " Cell port \\I is connected to input port \\ibuf4_en[6]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_7", - " Cell port \\I is connected to input port \\ibuf4_en[7]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_8", - " Cell port \\I is connected to input port \\ibuf4_en[8]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_3.ibuf4_en_9", - " Cell port \\I is connected to input port \\ibuf4_en[9]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF \\gen_i_buf[0].i_buf_instance", - " Cell port \\I is connected to input port \\A[0]", - " Get important connection of cell \\I_BUF \\gen_i_buf[0].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[0]", - " Get important connection of cell \\I_BUF \\gen_i_buf[0].i_buf_instance_shift", - " Cell port \\I is connected to input port \\SHIFT_RIGHT[0]", - " Get important connection of cell \\I_BUF \\gen_i_buf[10].i_buf_instance", - " Cell port \\I is connected to input port \\A[10]", - " Get important connection of cell \\I_BUF \\gen_i_buf[10].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[10]", - " Get important connection of cell \\I_BUF \\gen_i_buf[11].i_buf_instance", - " Cell port \\I is connected to input port \\A[11]", - " Get important connection of cell \\I_BUF \\gen_i_buf[11].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[11]", - " Get important connection of cell \\I_BUF \\gen_i_buf[12].i_buf_instance", - " Cell port \\I is connected to input port \\A[12]", - " Get important connection of cell \\I_BUF \\gen_i_buf[12].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[12]", - " Get important connection of cell \\I_BUF \\gen_i_buf[13].i_buf_instance", - " Cell port \\I is connected to input port \\A[13]", - " Get important connection of cell \\I_BUF \\gen_i_buf[13].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[13]", - " Get important connection of cell \\I_BUF \\gen_i_buf[14].i_buf_instance", - " Cell port \\I is connected to input port \\A[14]", - " Get important connection of cell \\I_BUF \\gen_i_buf[14].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[14]", - " Get important connection of cell \\I_BUF \\gen_i_buf[15].i_buf_instance", - " Cell port \\I is connected to input port \\A[15]", - " Get important connection of cell \\I_BUF \\gen_i_buf[15].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[15]", - " Get important connection of cell \\I_BUF \\gen_i_buf[16].i_buf_instance", - " Cell port \\I is connected to input port \\A[16]", - " Get important connection of cell \\I_BUF \\gen_i_buf[16].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[16]", - " Get important connection of cell \\I_BUF \\gen_i_buf[17].i_buf_instance", - " Cell port \\I is connected to input port \\A[17]", - " Get important connection of cell \\I_BUF \\gen_i_buf[17].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[17]", - " Get important connection of cell \\I_BUF \\gen_i_buf[18].i_buf_instance", - " Cell port \\I is connected to input port \\A[18]", - " Get important connection of cell \\I_BUF \\gen_i_buf[19].i_buf_instance", - " Cell port \\I is connected to input port \\A[19]", - " Get important connection of cell \\I_BUF \\gen_i_buf[1].i_buf_instance", - " Cell port \\I is connected to input port \\A[1]", - " Get important connection of cell \\I_BUF \\gen_i_buf[1].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[1]", - " Get important connection of cell \\I_BUF \\gen_i_buf[1].i_buf_instance_shift", - " Cell port \\I is connected to input port \\SHIFT_RIGHT[1]", - " Get important connection of cell \\I_BUF \\gen_i_buf[2].i_buf_instance", - " Cell port \\I is connected to input port \\A[2]", - " Get important connection of cell \\I_BUF \\gen_i_buf[2].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[2]", - " Get important connection of cell \\I_BUF \\gen_i_buf[2].i_buf_instance_shift", - " Cell port \\I is connected to input port \\SHIFT_RIGHT[2]", - " Get important connection of cell \\I_BUF \\gen_i_buf[3].i_buf_instance", - " Cell port \\I is connected to input port \\A[3]", - " Get important connection of cell \\I_BUF \\gen_i_buf[3].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[3]", - " Get important connection of cell \\I_BUF \\gen_i_buf[3].i_buf_instance_shift", - " Cell port \\I is connected to input port \\SHIFT_RIGHT[3]", - " Get important connection of cell \\I_BUF \\gen_i_buf[4].i_buf_instance", - " Cell port \\I is connected to input port \\A[4]", - " Get important connection of cell \\I_BUF \\gen_i_buf[4].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[4]", - " Get important connection of cell \\I_BUF \\gen_i_buf[4].i_buf_instance_shift", - " Cell port \\I is connected to input port \\SHIFT_RIGHT[4]", - " Get important connection of cell \\I_BUF \\gen_i_buf[5].i_buf_instance", - " Cell port \\I is connected to input port \\A[5]", - " Get important connection of cell \\I_BUF \\gen_i_buf[5].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[5]", - " Get important connection of cell \\I_BUF \\gen_i_buf[5].i_buf_instance_shift", - " Cell port \\I is connected to input port \\SHIFT_RIGHT[5]", - " Get important connection of cell \\I_BUF \\gen_i_buf[6].i_buf_instance", - " Cell port \\I is connected to input port \\A[6]", - " Get important connection of cell \\I_BUF \\gen_i_buf[6].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[6]", - " Get important connection of cell \\I_BUF \\gen_i_buf[7].i_buf_instance", - " Cell port \\I is connected to input port \\A[7]", - " Get important connection of cell \\I_BUF \\gen_i_buf[7].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[7]", - " Get important connection of cell \\I_BUF \\gen_i_buf[8].i_buf_instance", - " Cell port \\I is connected to input port \\A[8]", - " Get important connection of cell \\I_BUF \\gen_i_buf[8].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[8]", - " Get important connection of cell \\I_BUF \\gen_i_buf[9].i_buf_instance", - " Cell port \\I is connected to input port \\A[9]", - " Get important connection of cell \\I_BUF \\gen_i_buf[9].i_buf_instance_b", - " Cell port \\I is connected to input port \\B[9]", - " Get important connection of cell \\O_BUF \\gen_o_buf[0].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[0]", - " Get important connection of cell \\O_BUF \\gen_o_buf[10].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[10]", - " Get important connection of cell \\O_BUF \\gen_o_buf[11].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[11]", - " Get important connection of cell \\O_BUF \\gen_o_buf[12].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[12]", - " Get important connection of cell \\O_BUF \\gen_o_buf[13].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[13]", - " Get important connection of cell \\O_BUF \\gen_o_buf[14].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[14]", - " Get important connection of cell \\O_BUF \\gen_o_buf[15].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[15]", - " Get important connection of cell \\O_BUF \\gen_o_buf[16].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[16]", - " Get important connection of cell \\O_BUF \\gen_o_buf[17].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[17]", - " Get important connection of cell \\O_BUF \\gen_o_buf[1].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[1]", - " Get important connection of cell \\O_BUF \\gen_o_buf[2].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[2]", - " Get important connection of cell \\O_BUF \\gen_o_buf[3].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[3]", - " Get important connection of cell \\O_BUF \\gen_o_buf[4].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[4]", - " Get important connection of cell \\O_BUF \\gen_o_buf[5].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[5]", - " Get important connection of cell \\O_BUF \\gen_o_buf[6].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[6]", - " Get important connection of cell \\O_BUF \\gen_o_buf[7].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[7]", - " Get important connection of cell \\O_BUF \\gen_o_buf[8].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[8]", - " Get important connection of cell \\O_BUF \\gen_o_buf[9].o_buf_instance_a", - " Cell port \\O is connected to output port \\DLY_B[9]", - " Get important connection of cell \\I_BUF \\i_buf_instance10", - " Cell port \\I is connected to input port \\RESET", - " Get important connection of cell \\I_BUF \\i_buf_instance11", - " Cell port \\I is connected to input port \\FEEDBACK[0]", - " Get important connection of cell \\I_BUF \\i_buf_instance12", - " Cell port \\I is connected to input port \\FEEDBACK[1]", - " Get important connection of cell \\I_BUF \\i_buf_instance13", - " Cell port \\I is connected to input port \\FEEDBACK[2]", - " Get important connection of cell \\I_BUF \\i_buf_instance14", - " Cell port \\I is connected to input port \\LOAD_ACC", - " Get important connection of cell \\I_BUF \\i_buf_instance15", - " Cell port \\I is connected to input port \\SATURATE", - " Get important connection of cell \\I_BUF \\i_buf_instance16", - " Cell port \\I is connected to input port \\ROUND", - " Get important connection of cell \\I_BUF \\i_buf_instance17", - " Cell port \\I is connected to input port \\SUBTRACT", - " Get important connection of cell \\I_BUF \\i_buf_instance18", - " Cell port \\I is connected to input port \\UNSIGNED_A", - " Get important connection of cell \\I_BUF \\i_buf_instance19", - " Cell port \\I is connected to input port \\UNSIGNED_B", - " Get important connection of cell \\I_BUF \\i_buf_instance2", - " Cell port \\I is connected to input port \\CLK", - " Get important connection of cell \\I_BUF \\i_buf_instance3", - "Debug: Try to look for wire $iopadmap$i_buft_oe[0]", - " Debug: $iopadmap$Z[37] -> ", - " Debug: $iopadmap$i_buft_oe[0] -> \\i_buft_oe[0]", - " Cell port \\I is connected to input port \\i_buft_oe[0]", - " Debug: status: 1", - " Get important connection of cell \\I_BUF \\i_buf_instance4", - " Cell port \\I is connected to input port \\ACC_FIR[0]", - " Get important connection of cell \\I_BUF \\i_buf_instance5", - " Cell port \\I is connected to input port \\ACC_FIR[1]", - " Get important connection of cell \\I_BUF \\i_buf_instance6", - " Cell port \\I is connected to input port \\ACC_FIR[2]", - " Get important connection of cell \\I_BUF \\i_buf_instance7", - " Cell port \\I is connected to input port \\ACC_FIR[3]", - " Get important connection of cell \\I_BUF \\i_buf_instance8", - " Cell port \\I is connected to input port \\ACC_FIR[4]", - " Get important connection of cell \\I_BUF \\i_buf_instance9", - " Cell port \\I is connected to input port \\ACC_FIR[5]", - " Trace Clock Buffer", - " Try \\I_BUF \\i_buf_instance2 out connection: $auto$clkbufmap.cc:263:execute$398", - " Connected $auto$clkbufmap.cc:262:execute$397", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_3.Z", - "linked_object" : "Z[37]", - "linked_objects" : { - "Z[37]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$Z[37]", - "O" : "Z[37]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe", - "linked_object" : "i_buft_oe[1]", - "linked_objects" : { - "i_buft_oe[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[1]", - "O" : "$iopadmap$i_buft_oe[1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_1", - "linked_object" : "i_buft_oe[2]", - "linked_objects" : { - "i_buft_oe[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[2]", - "O" : "$iopadmap$i_buft_oe[2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_10", - "linked_object" : "i_buft_oe[11]", - "linked_objects" : { - "i_buft_oe[11]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[11]", - "O" : "$iopadmap$i_buft_oe[11]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_11", - "linked_object" : "i_buft_oe[12]", - "linked_objects" : { - "i_buft_oe[12]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[12]", - "O" : "$iopadmap$i_buft_oe[12]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_12", - "linked_object" : "i_buft_oe[13]", - "linked_objects" : { - "i_buft_oe[13]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[13]", - "O" : "$iopadmap$i_buft_oe[13]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_13", - "linked_object" : "i_buft_oe[14]", - "linked_objects" : { - "i_buft_oe[14]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[14]", - "O" : "$iopadmap$i_buft_oe[14]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_14", - "linked_object" : "i_buft_oe[15]", - "linked_objects" : { - "i_buft_oe[15]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[15]", - "O" : "$iopadmap$i_buft_oe[15]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_15", - "linked_object" : "i_buft_oe[16]", - "linked_objects" : { - "i_buft_oe[16]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[16]", - "O" : "$iopadmap$i_buft_oe[16]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_16", - "linked_object" : "i_buft_oe[17]", - "linked_objects" : { - "i_buft_oe[17]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[17]", - "O" : "$iopadmap$i_buft_oe[17]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_17", - "linked_object" : "i_buft_oe[18]", - "linked_objects" : { - "i_buft_oe[18]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[18]", - "O" : "$iopadmap$i_buft_oe[18]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_18", - "linked_object" : "i_buft_oe[19]", - "linked_objects" : { - "i_buft_oe[19]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[19]", - "O" : "$iopadmap$i_buft_oe[19]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_19", - "linked_object" : "i_buft_oe[20]", - "linked_objects" : { - "i_buft_oe[20]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[20]", - "O" : "$iopadmap$i_buft_oe[20]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_2", - "linked_object" : "i_buft_oe[3]", - "linked_objects" : { - "i_buft_oe[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[3]", - "O" : "$iopadmap$i_buft_oe[3]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_20", - "linked_object" : "i_buft_oe[21]", - "linked_objects" : { - "i_buft_oe[21]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[21]", - "O" : "$iopadmap$i_buft_oe[21]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_21", - "linked_object" : "i_buft_oe[22]", - "linked_objects" : { - "i_buft_oe[22]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[22]", - "O" : "$iopadmap$i_buft_oe[22]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_22", - "linked_object" : "i_buft_oe[23]", - "linked_objects" : { - "i_buft_oe[23]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[23]", - "O" : "$iopadmap$i_buft_oe[23]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_23", - "linked_object" : "i_buft_oe[24]", - "linked_objects" : { - "i_buft_oe[24]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[24]", - "O" : "$iopadmap$i_buft_oe[24]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_24", - "linked_object" : "i_buft_oe[25]", - "linked_objects" : { - "i_buft_oe[25]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[25]", - "O" : "$iopadmap$i_buft_oe[25]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_25", - "linked_object" : "i_buft_oe[26]", - "linked_objects" : { - "i_buft_oe[26]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[26]", - "O" : "$iopadmap$i_buft_oe[26]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_26", - "linked_object" : "i_buft_oe[27]", - "linked_objects" : { - "i_buft_oe[27]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[27]", - "O" : "$iopadmap$i_buft_oe[27]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_27", - "linked_object" : "i_buft_oe[28]", - "linked_objects" : { - "i_buft_oe[28]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[28]", - "O" : "$iopadmap$i_buft_oe[28]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_28", - "linked_object" : "i_buft_oe[29]", - "linked_objects" : { - "i_buft_oe[29]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[29]", - "O" : "$iopadmap$i_buft_oe[29]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_29", - "linked_object" : "i_buft_oe[30]", - "linked_objects" : { - "i_buft_oe[30]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[30]", - "O" : "$iopadmap$i_buft_oe[30]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_3", - "linked_object" : "i_buft_oe[4]", - "linked_objects" : { - "i_buft_oe[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[4]", - "O" : "$iopadmap$i_buft_oe[4]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_30", - "linked_object" : "i_buft_oe[31]", - "linked_objects" : { - "i_buft_oe[31]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[31]", - "O" : "$iopadmap$i_buft_oe[31]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_31", - "linked_object" : "i_buft_oe[32]", - "linked_objects" : { - "i_buft_oe[32]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[32]", - "O" : "$iopadmap$i_buft_oe[32]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_32", - "linked_object" : "i_buft_oe[33]", - "linked_objects" : { - "i_buft_oe[33]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[33]", - "O" : "$iopadmap$i_buft_oe[33]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_33", - "linked_object" : "i_buft_oe[34]", - "linked_objects" : { - "i_buft_oe[34]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[34]", - "O" : "$iopadmap$i_buft_oe[34]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_34", - "linked_object" : "i_buft_oe[35]", - "linked_objects" : { - "i_buft_oe[35]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[35]", - "O" : "$iopadmap$i_buft_oe[35]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_35", - "linked_object" : "i_buft_oe[36]", - "linked_objects" : { - "i_buft_oe[36]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[36]", - "O" : "$iopadmap$i_buft_oe[36]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_36", - "linked_object" : "i_buft_oe[37]", - "linked_objects" : { - "i_buft_oe[37]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[37]", - "O" : "$iopadmap$i_buft_oe[37]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_4", - "linked_object" : "i_buft_oe[5]", - "linked_objects" : { - "i_buft_oe[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[5]", - "O" : "$iopadmap$i_buft_oe[5]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_5", - "linked_object" : "i_buft_oe[6]", - "linked_objects" : { - "i_buft_oe[6]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[6]", - "O" : "$iopadmap$i_buft_oe[6]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_6", - "linked_object" : "i_buft_oe[7]", - "linked_objects" : { - "i_buft_oe[7]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[7]", - "O" : "$iopadmap$i_buft_oe[7]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_7", - "linked_object" : "i_buft_oe[8]", - "linked_objects" : { - "i_buft_oe[8]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[8]", - "O" : "$iopadmap$i_buft_oe[8]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_8", - "linked_object" : "i_buft_oe[9]", - "linked_objects" : { - "i_buft_oe[9]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[9]", - "O" : "$iopadmap$i_buft_oe[9]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.i_buft_oe_9", - "linked_object" : "i_buft_oe[10]", - "linked_objects" : { - "i_buft_oe[10]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "i_buft_oe[10]", - "O" : "$iopadmap$i_buft_oe[10]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en", - "linked_object" : "ibuf1_en[0]", - "linked_objects" : { - "ibuf1_en[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[0]", - "O" : "$iopadmap$ibuf1_en[0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_1", - "linked_object" : "ibuf1_en[1]", - "linked_objects" : { - "ibuf1_en[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[1]", - "O" : "$iopadmap$ibuf1_en[1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_10", - "linked_object" : "ibuf1_en[10]", - "linked_objects" : { - "ibuf1_en[10]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[10]", - "O" : "$iopadmap$ibuf1_en[10]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_11", - "linked_object" : "ibuf1_en[11]", - "linked_objects" : { - "ibuf1_en[11]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[11]", - "O" : "$iopadmap$ibuf1_en[11]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_12", - "linked_object" : "ibuf1_en[12]", - "linked_objects" : { - "ibuf1_en[12]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[12]", - "O" : "$iopadmap$ibuf1_en[12]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_13", - "linked_object" : "ibuf1_en[13]", - "linked_objects" : { - "ibuf1_en[13]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[13]", - "O" : "$iopadmap$ibuf1_en[13]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_14", - "linked_object" : "ibuf1_en[14]", - "linked_objects" : { - "ibuf1_en[14]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[14]", - "O" : "$iopadmap$ibuf1_en[14]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_15", - "linked_object" : "ibuf1_en[15]", - "linked_objects" : { - "ibuf1_en[15]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[15]", - "O" : "$iopadmap$ibuf1_en[15]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_16", - "linked_object" : "ibuf1_en[16]", - "linked_objects" : { - "ibuf1_en[16]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[16]", - "O" : "$iopadmap$ibuf1_en[16]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_17", - "linked_object" : "ibuf1_en[17]", - "linked_objects" : { - "ibuf1_en[17]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[17]", - "O" : "$iopadmap$ibuf1_en[17]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_18", - "linked_object" : "ibuf1_en[18]", - "linked_objects" : { - "ibuf1_en[18]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[18]", - "O" : "$iopadmap$ibuf1_en[18]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_19", - "linked_object" : "ibuf1_en[19]", - "linked_objects" : { - "ibuf1_en[19]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[19]", - "O" : "$iopadmap$ibuf1_en[19]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_2", - "linked_object" : "ibuf1_en[2]", - "linked_objects" : { - "ibuf1_en[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[2]", - "O" : "$iopadmap$ibuf1_en[2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_3", - "linked_object" : "ibuf1_en[3]", - "linked_objects" : { - "ibuf1_en[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[3]", - "O" : "$iopadmap$ibuf1_en[3]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_4", - "linked_object" : "ibuf1_en[4]", - "linked_objects" : { - "ibuf1_en[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[4]", - "O" : "$iopadmap$ibuf1_en[4]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_5", - "linked_object" : "ibuf1_en[5]", - "linked_objects" : { - "ibuf1_en[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[5]", - "O" : "$iopadmap$ibuf1_en[5]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_6", - "linked_object" : "ibuf1_en[6]", - "linked_objects" : { - "ibuf1_en[6]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[6]", - "O" : "$iopadmap$ibuf1_en[6]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_7", - "linked_object" : "ibuf1_en[7]", - "linked_objects" : { - "ibuf1_en[7]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[7]", - "O" : "$iopadmap$ibuf1_en[7]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_8", - "linked_object" : "ibuf1_en[8]", - "linked_objects" : { - "ibuf1_en[8]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[8]", - "O" : "$iopadmap$ibuf1_en[8]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf1_en_9", - "linked_object" : "ibuf1_en[9]", - "linked_objects" : { - "ibuf1_en[9]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en[9]", - "O" : "$iopadmap$ibuf1_en[9]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en", - "linked_object" : "ibuf2_en[0]", - "linked_objects" : { - "ibuf2_en[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[0]", - "O" : "$iopadmap$ibuf2_en[0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_1", - "linked_object" : "ibuf2_en[1]", - "linked_objects" : { - "ibuf2_en[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[1]", - "O" : "$iopadmap$ibuf2_en[1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_10", - "linked_object" : "ibuf2_en[10]", - "linked_objects" : { - "ibuf2_en[10]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[10]", - "O" : "$iopadmap$ibuf2_en[10]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_11", - "linked_object" : "ibuf2_en[11]", - "linked_objects" : { - "ibuf2_en[11]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[11]", - "O" : "$iopadmap$ibuf2_en[11]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_12", - "linked_object" : "ibuf2_en[12]", - "linked_objects" : { - "ibuf2_en[12]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[12]", - "O" : "$iopadmap$ibuf2_en[12]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_13", - "linked_object" : "ibuf2_en[13]", - "linked_objects" : { - "ibuf2_en[13]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[13]", - "O" : "$iopadmap$ibuf2_en[13]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_14", - "linked_object" : "ibuf2_en[14]", - "linked_objects" : { - "ibuf2_en[14]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[14]", - "O" : "$iopadmap$ibuf2_en[14]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_15", - "linked_object" : "ibuf2_en[15]", - "linked_objects" : { - "ibuf2_en[15]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[15]", - "O" : "$iopadmap$ibuf2_en[15]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_16", - "linked_object" : "ibuf2_en[16]", - "linked_objects" : { - "ibuf2_en[16]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[16]", - "O" : "$iopadmap$ibuf2_en[16]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_17", - "linked_object" : "ibuf2_en[17]", - "linked_objects" : { - "ibuf2_en[17]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[17]", - "O" : "$iopadmap$ibuf2_en[17]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_2", - "linked_object" : "ibuf2_en[2]", - "linked_objects" : { - "ibuf2_en[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[2]", - "O" : "$iopadmap$ibuf2_en[2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_3", - "linked_object" : "ibuf2_en[3]", - "linked_objects" : { - "ibuf2_en[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[3]", - "O" : "$iopadmap$ibuf2_en[3]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_4", - "linked_object" : "ibuf2_en[4]", - "linked_objects" : { - "ibuf2_en[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[4]", - "O" : "$iopadmap$ibuf2_en[4]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_5", - "linked_object" : "ibuf2_en[5]", - "linked_objects" : { - "ibuf2_en[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[5]", - "O" : "$iopadmap$ibuf2_en[5]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_6", - "linked_object" : "ibuf2_en[6]", - "linked_objects" : { - "ibuf2_en[6]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[6]", - "O" : "$iopadmap$ibuf2_en[6]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_7", - "linked_object" : "ibuf2_en[7]", - "linked_objects" : { - "ibuf2_en[7]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[7]", - "O" : "$iopadmap$ibuf2_en[7]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_8", - "linked_object" : "ibuf2_en[8]", - "linked_objects" : { - "ibuf2_en[8]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[8]", - "O" : "$iopadmap$ibuf2_en[8]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf2_en_9", - "linked_object" : "ibuf2_en[9]", - "linked_objects" : { - "ibuf2_en[9]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en[9]", - "O" : "$iopadmap$ibuf2_en[9]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf3_en", - "linked_object" : "ibuf3_en[0]", - "linked_objects" : { - "ibuf3_en[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf3_en[0]", - "O" : "$iopadmap$ibuf3_en[0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf3_en_1", - "linked_object" : "ibuf3_en[1]", - "linked_objects" : { - "ibuf3_en[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf3_en[1]", - "O" : "$iopadmap$ibuf3_en[1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf3_en_2", - "linked_object" : "ibuf3_en[2]", - "linked_objects" : { - "ibuf3_en[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf3_en[2]", - "O" : "$iopadmap$ibuf3_en[2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf3_en_3", - "linked_object" : "ibuf3_en[3]", - "linked_objects" : { - "ibuf3_en[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf3_en[3]", - "O" : "$iopadmap$ibuf3_en[3]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf3_en_4", - "linked_object" : "ibuf3_en[4]", - "linked_objects" : { - "ibuf3_en[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf3_en[4]", - "O" : "$iopadmap$ibuf3_en[4]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf3_en_5", - "linked_object" : "ibuf3_en[5]", - "linked_objects" : { - "ibuf3_en[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf3_en[5]", - "O" : "$iopadmap$ibuf3_en[5]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en", - "linked_object" : "ibuf4_en[0]", - "linked_objects" : { - "ibuf4_en[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[0]", - "O" : "$iopadmap$ibuf4_en[0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_1", - "linked_object" : "ibuf4_en[1]", - "linked_objects" : { - "ibuf4_en[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[1]", - "O" : "$iopadmap$ibuf4_en[1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_10", - "linked_object" : "ibuf4_en[10]", - "linked_objects" : { - "ibuf4_en[10]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[10]", - "O" : "$iopadmap$ibuf4_en[10]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_11", - "linked_object" : "ibuf4_en[11]", - "linked_objects" : { - "ibuf4_en[11]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[11]", - "O" : "$iopadmap$ibuf4_en[11]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_12", - "linked_object" : "ibuf4_en[12]", - "linked_objects" : { - "ibuf4_en[12]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[12]", - "O" : "$iopadmap$ibuf4_en[12]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_13", - "linked_object" : "ibuf4_en[13]", - "linked_objects" : { - "ibuf4_en[13]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[13]", - "O" : "$iopadmap$ibuf4_en[13]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_14", - "linked_object" : "ibuf4_en[14]", - "linked_objects" : { - "ibuf4_en[14]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[14]", - "O" : "$iopadmap$ibuf4_en[14]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_15", - "linked_object" : "ibuf4_en[15]", - "linked_objects" : { - "ibuf4_en[15]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[15]", - "O" : "$iopadmap$ibuf4_en[15]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_16", - "linked_object" : "ibuf4_en[16]", - "linked_objects" : { - "ibuf4_en[16]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[16]", - "O" : "$iopadmap$ibuf4_en[16]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_17", - "linked_object" : "ibuf4_en[17]", - "linked_objects" : { - "ibuf4_en[17]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[17]", - "O" : "$iopadmap$ibuf4_en[17]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_2", - "linked_object" : "ibuf4_en[2]", - "linked_objects" : { - "ibuf4_en[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[2]", - "O" : "$iopadmap$ibuf4_en[2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_3", - "linked_object" : "ibuf4_en[3]", - "linked_objects" : { - "ibuf4_en[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[3]", - "O" : "$iopadmap$ibuf4_en[3]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_4", - "linked_object" : "ibuf4_en[4]", - "linked_objects" : { - "ibuf4_en[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[4]", - "O" : "$iopadmap$ibuf4_en[4]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_5", - "linked_object" : "ibuf4_en[5]", - "linked_objects" : { - "ibuf4_en[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[5]", - "O" : "$iopadmap$ibuf4_en[5]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_6", - "linked_object" : "ibuf4_en[6]", - "linked_objects" : { - "ibuf4_en[6]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[6]", - "O" : "$iopadmap$ibuf4_en[6]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_7", - "linked_object" : "ibuf4_en[7]", - "linked_objects" : { - "ibuf4_en[7]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[7]", - "O" : "$iopadmap$ibuf4_en[7]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_8", - "linked_object" : "ibuf4_en[8]", - "linked_objects" : { - "ibuf4_en[8]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[8]", - "O" : "$iopadmap$ibuf4_en[8]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_3.ibuf4_en_9", - "linked_object" : "ibuf4_en[9]", - "linked_objects" : { - "ibuf4_en[9]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en[9]", - "O" : "$iopadmap$ibuf4_en[9]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[0].i_buf_instance", - "linked_object" : "A[0]", - "linked_objects" : { - "A[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[0]", - "O" : "a_out[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[0].i_buf_instance_b", - "linked_object" : "B[0]", - "linked_objects" : { - "B[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[0]", - "O" : "b_out[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[0].i_buf_instance_shift", - "linked_object" : "SHIFT_RIGHT[0]", - "linked_objects" : { - "SHIFT_RIGHT[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "SHIFT_RIGHT[0]", - "O" : "i_buf_shift_right[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[10].i_buf_instance", - "linked_object" : "A[10]", - "linked_objects" : { - "A[10]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[10]", - "O" : "a_out[10]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[10].i_buf_instance_b", - "linked_object" : "B[10]", - "linked_objects" : { - "B[10]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[10]", - "O" : "b_out[10]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[11].i_buf_instance", - "linked_object" : "A[11]", - "linked_objects" : { - "A[11]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[11]", - "O" : "a_out[11]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[11].i_buf_instance_b", - "linked_object" : "B[11]", - "linked_objects" : { - "B[11]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[11]", - "O" : "b_out[11]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[12].i_buf_instance", - "linked_object" : "A[12]", - "linked_objects" : { - "A[12]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[12]", - "O" : "a_out[12]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[12].i_buf_instance_b", - "linked_object" : "B[12]", - "linked_objects" : { - "B[12]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[12]", - "O" : "b_out[12]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[13].i_buf_instance", - "linked_object" : "A[13]", - "linked_objects" : { - "A[13]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[13]", - "O" : "a_out[13]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[13].i_buf_instance_b", - "linked_object" : "B[13]", - "linked_objects" : { - "B[13]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[13]", - "O" : "b_out[13]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[14].i_buf_instance", - "linked_object" : "A[14]", - "linked_objects" : { - "A[14]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[14]", - "O" : "a_out[14]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[14].i_buf_instance_b", - "linked_object" : "B[14]", - "linked_objects" : { - "B[14]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[14]", - "O" : "b_out[14]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[15].i_buf_instance", - "linked_object" : "A[15]", - "linked_objects" : { - "A[15]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[15]", - "O" : "a_out[15]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[15].i_buf_instance_b", - "linked_object" : "B[15]", - "linked_objects" : { - "B[15]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[15]", - "O" : "b_out[15]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[16].i_buf_instance", - "linked_object" : "A[16]", - "linked_objects" : { - "A[16]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[16]", - "O" : "a_out[16]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[16].i_buf_instance_b", - "linked_object" : "B[16]", - "linked_objects" : { - "B[16]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[16]", - "O" : "b_out[16]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[17].i_buf_instance", - "linked_object" : "A[17]", - "linked_objects" : { - "A[17]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[17]", - "O" : "a_out[17]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[17].i_buf_instance_b", - "linked_object" : "B[17]", - "linked_objects" : { - "B[17]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[17]", - "O" : "b_out[17]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[18].i_buf_instance", - "linked_object" : "A[18]", - "linked_objects" : { - "A[18]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[18]", - "O" : "a_out[18]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[19].i_buf_instance", - "linked_object" : "A[19]", - "linked_objects" : { - "A[19]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[19]", - "O" : "a_out[19]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[1].i_buf_instance", - "linked_object" : "A[1]", - "linked_objects" : { - "A[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[1]", - "O" : "a_out[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[1].i_buf_instance_b", - "linked_object" : "B[1]", - "linked_objects" : { - "B[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[1]", - "O" : "b_out[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[1].i_buf_instance_shift", - "linked_object" : "SHIFT_RIGHT[1]", - "linked_objects" : { - "SHIFT_RIGHT[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "SHIFT_RIGHT[1]", - "O" : "i_buf_shift_right[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[2].i_buf_instance", - "linked_object" : "A[2]", - "linked_objects" : { - "A[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[2]", - "O" : "a_out[2]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[2].i_buf_instance_b", - "linked_object" : "B[2]", - "linked_objects" : { - "B[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[2]", - "O" : "b_out[2]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[2].i_buf_instance_shift", - "linked_object" : "SHIFT_RIGHT[2]", - "linked_objects" : { - "SHIFT_RIGHT[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "SHIFT_RIGHT[2]", - "O" : "i_buf_shift_right[2]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[3].i_buf_instance", - "linked_object" : "A[3]", - "linked_objects" : { - "A[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[3]", - "O" : "a_out[3]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[3].i_buf_instance_b", - "linked_object" : "B[3]", - "linked_objects" : { - "B[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[3]", - "O" : "b_out[3]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[3].i_buf_instance_shift", - "linked_object" : "SHIFT_RIGHT[3]", - "linked_objects" : { - "SHIFT_RIGHT[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "SHIFT_RIGHT[3]", - "O" : "i_buf_shift_right[3]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[4].i_buf_instance", - "linked_object" : "A[4]", - "linked_objects" : { - "A[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[4]", - "O" : "a_out[4]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[4].i_buf_instance_b", - "linked_object" : "B[4]", - "linked_objects" : { - "B[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[4]", - "O" : "b_out[4]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[4].i_buf_instance_shift", - "linked_object" : "SHIFT_RIGHT[4]", - "linked_objects" : { - "SHIFT_RIGHT[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "SHIFT_RIGHT[4]", - "O" : "i_buf_shift_right[4]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[5].i_buf_instance", - "linked_object" : "A[5]", - "linked_objects" : { - "A[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[5]", - "O" : "a_out[5]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[5].i_buf_instance_b", - "linked_object" : "B[5]", - "linked_objects" : { - "B[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[5]", - "O" : "b_out[5]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[5].i_buf_instance_shift", - "linked_object" : "SHIFT_RIGHT[5]", - "linked_objects" : { - "SHIFT_RIGHT[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "SHIFT_RIGHT[5]", - "O" : "i_buf_shift_right[5]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[6].i_buf_instance", - "linked_object" : "A[6]", - "linked_objects" : { - "A[6]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[6]", - "O" : "a_out[6]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[6].i_buf_instance_b", - "linked_object" : "B[6]", - "linked_objects" : { - "B[6]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[6]", - "O" : "b_out[6]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[7].i_buf_instance", - "linked_object" : "A[7]", - "linked_objects" : { - "A[7]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[7]", - "O" : "a_out[7]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[7].i_buf_instance_b", - "linked_object" : "B[7]", - "linked_objects" : { - "B[7]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[7]", - "O" : "b_out[7]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[8].i_buf_instance", - "linked_object" : "A[8]", - "linked_objects" : { - "A[8]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[8]", - "O" : "a_out[8]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[8].i_buf_instance_b", - "linked_object" : "B[8]", - "linked_objects" : { - "B[8]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[8]", - "O" : "b_out[8]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[9].i_buf_instance", - "linked_object" : "A[9]", - "linked_objects" : { - "A[9]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "A[9]", - "O" : "a_out[9]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "gen_i_buf[9].i_buf_instance_b", - "linked_object" : "B[9]", - "linked_objects" : { - "B[9]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "B[9]", - "O" : "b_out[9]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[0].o_buf_instance_a", - "linked_object" : "DLY_B[0]", - "linked_objects" : { - "DLY_B[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[0]", - "O" : "DLY_B[0]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[10].o_buf_instance_a", - "linked_object" : "DLY_B[10]", - "linked_objects" : { - "DLY_B[10]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[10]", - "O" : "DLY_B[10]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[11].o_buf_instance_a", - "linked_object" : "DLY_B[11]", - "linked_objects" : { - "DLY_B[11]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[11]", - "O" : "DLY_B[11]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[12].o_buf_instance_a", - "linked_object" : "DLY_B[12]", - "linked_objects" : { - "DLY_B[12]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[12]", - "O" : "DLY_B[12]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[13].o_buf_instance_a", - "linked_object" : "DLY_B[13]", - "linked_objects" : { - "DLY_B[13]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[13]", - "O" : "DLY_B[13]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[14].o_buf_instance_a", - "linked_object" : "DLY_B[14]", - "linked_objects" : { - "DLY_B[14]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[14]", - "O" : "DLY_B[14]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[15].o_buf_instance_a", - "linked_object" : "DLY_B[15]", - "linked_objects" : { - "DLY_B[15]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[15]", - "O" : "DLY_B[15]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[16].o_buf_instance_a", - "linked_object" : "DLY_B[16]", - "linked_objects" : { - "DLY_B[16]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[16]", - "O" : "DLY_B[16]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[17].o_buf_instance_a", - "linked_object" : "DLY_B[17]", - "linked_objects" : { - "DLY_B[17]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[17]", - "O" : "DLY_B[17]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[1].o_buf_instance_a", - "linked_object" : "DLY_B[1]", - "linked_objects" : { - "DLY_B[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[1]", - "O" : "DLY_B[1]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[2].o_buf_instance_a", - "linked_object" : "DLY_B[2]", - "linked_objects" : { - "DLY_B[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[2]", - "O" : "DLY_B[2]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[3].o_buf_instance_a", - "linked_object" : "DLY_B[3]", - "linked_objects" : { - "DLY_B[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[3]", - "O" : "DLY_B[3]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[4].o_buf_instance_a", - "linked_object" : "DLY_B[4]", - "linked_objects" : { - "DLY_B[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[4]", - "O" : "DLY_B[4]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[5].o_buf_instance_a", - "linked_object" : "DLY_B[5]", - "linked_objects" : { - "DLY_B[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[5]", - "O" : "DLY_B[5]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[6].o_buf_instance_a", - "linked_object" : "DLY_B[6]", - "linked_objects" : { - "DLY_B[6]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[6]", - "O" : "DLY_B[6]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[7].o_buf_instance_a", - "linked_object" : "DLY_B[7]", - "linked_objects" : { - "DLY_B[7]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[7]", - "O" : "DLY_B[7]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[8].o_buf_instance_a", - "linked_object" : "DLY_B[8]", - "linked_objects" : { - "DLY_B[8]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[8]", - "O" : "DLY_B[8]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "gen_o_buf[9].o_buf_instance_a", - "linked_object" : "DLY_B[9]", - "linked_objects" : { - "DLY_B[9]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "o_buf_dly_b[9]", - "O" : "DLY_B[9]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance10", - "linked_object" : "RESET", - "linked_objects" : { - "RESET" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "RESET", - "O" : "i_buf_reset" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance11", - "linked_object" : "FEEDBACK[0]", - "linked_objects" : { - "FEEDBACK[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "FEEDBACK[0]", - "O" : "i_buf_feedback[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance12", - "linked_object" : "FEEDBACK[1]", - "linked_objects" : { - "FEEDBACK[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "FEEDBACK[1]", - "O" : "i_buf_feedback[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance13", - "linked_object" : "FEEDBACK[2]", - "linked_objects" : { - "FEEDBACK[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "FEEDBACK[2]", - "O" : "i_buf_feedback[2]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance14", - "linked_object" : "LOAD_ACC", - "linked_objects" : { - "LOAD_ACC" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "LOAD_ACC", - "O" : "i_buf_load_acc" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance15", - "linked_object" : "SATURATE", - "linked_objects" : { - "SATURATE" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "SATURATE", - "O" : "i_buf_saturate" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance16", - "linked_object" : "ROUND", - "linked_objects" : { - "ROUND" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ROUND", - "O" : "i_buf_round" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance17", - "linked_object" : "SUBTRACT", - "linked_objects" : { - "SUBTRACT" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "SUBTRACT", - "O" : "i_buf_subtract" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance18", - "linked_object" : "UNSIGNED_A", - "linked_objects" : { - "UNSIGNED_A" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "UNSIGNED_A", - "O" : "i_buf_unsigned_a" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance19", - "linked_object" : "UNSIGNED_B", - "linked_objects" : { - "UNSIGNED_B" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "UNSIGNED_B", - "O" : "i_buf_unsigned_b" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance2", - "linked_object" : "CLK", - "linked_objects" : { - "CLK" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "CLK", - "O" : "$auto$clkbufmap.cc:263:execute$398" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$397", - "linked_object" : "CLK", - "linked_objects" : { - "CLK" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$398", - "O" : "i_buf_clk" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance3", - "linked_object" : "i_buft_oe[0]", - "linked_objects" : { - "i_buft_oe[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$i_buft_oe[0]", - "O" : "i_buft_oe_in" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance4", - "linked_object" : "ACC_FIR[0]", - "linked_objects" : { - "ACC_FIR[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ACC_FIR[0]", - "O" : "i_buf_ACC_FIR[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance5", - "linked_object" : "ACC_FIR[1]", - "linked_objects" : { - "ACC_FIR[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ACC_FIR[1]", - "O" : "i_buf_ACC_FIR[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance6", - "linked_object" : "ACC_FIR[2]", - "linked_objects" : { - "ACC_FIR[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ACC_FIR[2]", - "O" : "i_buf_ACC_FIR[2]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance7", - "linked_object" : "ACC_FIR[3]", - "linked_objects" : { - "ACC_FIR[3]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ACC_FIR[3]", - "O" : "i_buf_ACC_FIR[3]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance8", - "linked_object" : "ACC_FIR[4]", - "linked_objects" : { - "ACC_FIR[4]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ACC_FIR[4]", - "O" : "i_buf_ACC_FIR[4]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "i_buf_instance9", - "linked_object" : "ACC_FIR[5]", - "linked_objects" : { - "ACC_FIR[5]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ACC_FIR[5]", - "O" : "i_buf_ACC_FIR[5]" - }, - "parameters" : { - } - } - ] -} diff --git a/design_edit/Tests/primitive_example_design_3/gold/primitive_example_design_3_post_synth.eblif b/design_edit/Tests/primitive_example_design_3/gold/primitive_example_design_3_post_synth.eblif deleted file mode 100644 index 0d2c25000..000000000 --- a/design_edit/Tests/primitive_example_design_3/gold/primitive_example_design_3_post_synth.eblif +++ /dev/null @@ -1,96 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_primitive_example_design_3 -.inputs i_buft_oe[0] i_buft_oe[1] i_buft_oe[2] i_buft_oe[3] i_buft_oe[4] i_buft_oe[5] i_buft_oe[6] i_buft_oe[7] i_buft_oe[8] i_buft_oe[9] i_buft_oe[10] i_buft_oe[11] i_buft_oe[12] i_buft_oe[13] i_buft_oe[14] i_buft_oe[15] i_buft_oe[16] i_buft_oe[17] i_buft_oe[18] i_buft_oe[19] i_buft_oe[20] i_buft_oe[21] i_buft_oe[22] i_buft_oe[23] i_buft_oe[24] i_buft_oe[25] i_buft_oe[26] i_buft_oe[27] i_buft_oe[28] i_buft_oe[29] i_buft_oe[30] i_buft_oe[31] i_buft_oe[32] i_buft_oe[33] i_buft_oe[34] i_buft_oe[35] i_buft_oe[36] i_buft_oe[37] a_out[0] a_out[1] a_out[2] a_out[3] a_out[4] a_out[5] a_out[6] a_out[7] a_out[8] a_out[9] a_out[10] a_out[11] a_out[12] a_out[13] a_out[14] a_out[15] a_out[16] a_out[17] a_out[18] a_out[19] b_out[0] b_out[1] b_out[2] b_out[3] b_out[4] b_out[5] b_out[6] b_out[7] b_out[8] b_out[9] b_out[10] b_out[11] b_out[12] b_out[13] b_out[14] b_out[15] b_out[16] b_out[17] i_buf_reset i_buf_load_acc i_buf_saturate i_buf_clk i_buf_ACC_FIR[0] i_buf_ACC_FIR[1] i_buf_ACC_FIR[2] i_buf_ACC_FIR[3] i_buf_ACC_FIR[4] i_buf_ACC_FIR[5] i_buf_feedback[0] i_buf_feedback[1] i_buf_feedback[2] i_buf_shift_right[0] i_buf_shift_right[1] i_buf_shift_right[2] i_buf_shift_right[3] i_buf_shift_right[4] i_buf_shift_right[5] i_buf_round i_buf_subtract i_buf_unsigned_a i_buf_unsigned_b $iopadmap$ibuf1_en[0] $iopadmap$ibuf1_en[1] $iopadmap$ibuf1_en[2] $iopadmap$ibuf1_en[3] $iopadmap$ibuf1_en[4] $iopadmap$ibuf1_en[5] $iopadmap$ibuf1_en[6] $iopadmap$ibuf1_en[7] $iopadmap$ibuf1_en[8] $iopadmap$ibuf1_en[9] $iopadmap$ibuf1_en[10] $iopadmap$ibuf1_en[11] $iopadmap$ibuf1_en[12] $iopadmap$ibuf1_en[13] $iopadmap$ibuf1_en[14] $iopadmap$ibuf1_en[15] $iopadmap$ibuf1_en[16] $iopadmap$ibuf1_en[17] $iopadmap$ibuf1_en[18] $iopadmap$ibuf1_en[19] -.outputs Z[0] Z[1] Z[2] Z[3] Z[4] Z[5] Z[6] Z[7] Z[8] Z[9] Z[10] Z[11] Z[12] Z[13] Z[14] Z[15] Z[16] Z[17] Z[18] Z[19] Z[20] Z[21] Z[22] Z[23] Z[24] Z[25] Z[26] Z[27] Z[28] Z[29] Z[30] Z[31] Z[32] Z[33] Z[34] Z[35] Z[36] Z[37] z_out[0] z_out[1] z_out[2] z_out[3] z_out[4] z_out[5] z_out[6] z_out[7] z_out[8] z_out[9] z_out[10] z_out[11] z_out[12] z_out[13] z_out[14] z_out[15] z_out[16] z_out[17] z_out[18] z_out[19] z_out[20] z_out[21] z_out[22] z_out[23] z_out[24] z_out[25] z_out[26] z_out[27] z_out[28] z_out[29] z_out[30] z_out[31] z_out[32] z_out[33] z_out[34] z_out[35] z_out[36] z_out[37] o_buf_dly_b[0] o_buf_dly_b[1] o_buf_dly_b[2] o_buf_dly_b[3] o_buf_dly_b[4] o_buf_dly_b[5] o_buf_dly_b[6] o_buf_dly_b[7] o_buf_dly_b[8] o_buf_dly_b[9] o_buf_dly_b[10] o_buf_dly_b[11] o_buf_dly_b[12] o_buf_dly_b[13] o_buf_dly_b[14] o_buf_dly_b[15] o_buf_dly_b[16] o_buf_dly_b[17] -.names $false -.names $true -1 -.names $undef -.subckt DSP38 A[0]=a_out[0] A[1]=a_out[1] A[2]=a_out[2] A[3]=a_out[3] A[4]=a_out[4] A[5]=a_out[5] A[6]=a_out[6] A[7]=a_out[7] A[8]=a_out[8] A[9]=a_out[9] A[10]=a_out[10] A[11]=a_out[11] A[12]=a_out[12] A[13]=a_out[13] A[14]=a_out[14] A[15]=a_out[15] A[16]=a_out[16] A[17]=a_out[17] A[18]=a_out[18] A[19]=a_out[19] ACC_FIR[0]=i_buf_ACC_FIR[0] ACC_FIR[1]=i_buf_ACC_FIR[1] ACC_FIR[2]=i_buf_ACC_FIR[2] ACC_FIR[3]=i_buf_ACC_FIR[3] ACC_FIR[4]=i_buf_ACC_FIR[4] ACC_FIR[5]=i_buf_ACC_FIR[5] B[0]=b_out[0] B[1]=b_out[1] B[2]=b_out[2] B[3]=b_out[3] B[4]=b_out[4] B[5]=b_out[5] B[6]=b_out[6] B[7]=b_out[7] B[8]=b_out[8] B[9]=b_out[9] B[10]=b_out[10] B[11]=b_out[11] B[12]=b_out[12] B[13]=b_out[13] B[14]=b_out[14] B[15]=b_out[15] B[16]=b_out[16] B[17]=b_out[17] CLK=i_buf_clk DLY_B[0]=o_buf_dly_b[0] DLY_B[1]=o_buf_dly_b[1] DLY_B[2]=o_buf_dly_b[2] DLY_B[3]=o_buf_dly_b[3] DLY_B[4]=o_buf_dly_b[4] DLY_B[5]=o_buf_dly_b[5] DLY_B[6]=o_buf_dly_b[6] DLY_B[7]=o_buf_dly_b[7] DLY_B[8]=o_buf_dly_b[8] DLY_B[9]=o_buf_dly_b[9] DLY_B[10]=o_buf_dly_b[10] DLY_B[11]=o_buf_dly_b[11] DLY_B[12]=o_buf_dly_b[12] DLY_B[13]=o_buf_dly_b[13] DLY_B[14]=o_buf_dly_b[14] DLY_B[15]=o_buf_dly_b[15] DLY_B[16]=o_buf_dly_b[16] DLY_B[17]=o_buf_dly_b[17] FEEDBACK[0]=i_buf_feedback[0] FEEDBACK[1]=i_buf_feedback[1] FEEDBACK[2]=i_buf_feedback[2] LOAD_ACC=i_buf_load_acc RESET=i_buf_reset ROUND=i_buf_round SATURATE=i_buf_saturate SHIFT_RIGHT[0]=i_buf_shift_right[0] SHIFT_RIGHT[1]=i_buf_shift_right[1] SHIFT_RIGHT[2]=i_buf_shift_right[2] SHIFT_RIGHT[3]=i_buf_shift_right[3] SHIFT_RIGHT[4]=i_buf_shift_right[4] SHIFT_RIGHT[5]=i_buf_shift_right[5] SUBTRACT=i_buf_subtract UNSIGNED_A=i_buf_unsigned_a UNSIGNED_B=i_buf_unsigned_b Z[0]=z_out[0] Z[1]=z_out[1] Z[2]=z_out[2] Z[3]=z_out[3] Z[4]=z_out[4] Z[5]=z_out[5] Z[6]=z_out[6] Z[7]=z_out[7] Z[8]=z_out[8] Z[9]=z_out[9] Z[10]=z_out[10] Z[11]=z_out[11] Z[12]=z_out[12] Z[13]=z_out[13] Z[14]=z_out[14] Z[15]=z_out[15] Z[16]=z_out[16] Z[17]=z_out[17] Z[18]=z_out[18] Z[19]=z_out[19] Z[20]=z_out[20] Z[21]=z_out[21] Z[22]=z_out[22] Z[23]=z_out[23] Z[24]=z_out[24] Z[25]=z_out[25] Z[26]=z_out[26] Z[27]=z_out[27] Z[28]=z_out[28] Z[29]=z_out[29] Z[30]=z_out[30] Z[31]=z_out[31] Z[32]=z_out[32] Z[33]=z_out[33] Z[34]=z_out[34] Z[35]=z_out[35] Z[36]=z_out[36] Z[37]=z_out[37] -.param COEFF_0 00000000000000000000 -.param COEFF_1 00000000000000000000 -.param COEFF_2 00000000000000000000 -.param COEFF_3 00000000000000000000 -.param DSP_MODE "MULTIPLY_ACCUMULATE" -.param INPUT_REG_EN "TRUE" -.param OUTPUT_REG_EN "TRUE" -.names $undef $iopadmap$Z[37] -1 1 -.names i_buft_oe[0] $iopadmap$i_buft_oe[0] -1 1 -.names $iopadmap$Z[0] Z[0] -1 1 -.names $iopadmap$Z[1] Z[1] -1 1 -.names $iopadmap$Z[2] Z[2] -1 1 -.names $iopadmap$Z[3] Z[3] -1 1 -.names $iopadmap$Z[4] Z[4] -1 1 -.names $iopadmap$Z[5] Z[5] -1 1 -.names $iopadmap$Z[6] Z[6] -1 1 -.names $iopadmap$Z[7] Z[7] -1 1 -.names $iopadmap$Z[8] Z[8] -1 1 -.names $iopadmap$Z[9] Z[9] -1 1 -.names $iopadmap$Z[10] Z[10] -1 1 -.names $iopadmap$Z[11] Z[11] -1 1 -.names $iopadmap$Z[12] Z[12] -1 1 -.names $iopadmap$Z[13] Z[13] -1 1 -.names $iopadmap$Z[14] Z[14] -1 1 -.names $iopadmap$Z[15] Z[15] -1 1 -.names $iopadmap$Z[16] Z[16] -1 1 -.names $iopadmap$Z[17] Z[17] -1 1 -.names $iopadmap$Z[18] Z[18] -1 1 -.names $iopadmap$Z[19] Z[19] -1 1 -.names $iopadmap$Z[20] Z[20] -1 1 -.names $iopadmap$Z[21] Z[21] -1 1 -.names $iopadmap$Z[22] Z[22] -1 1 -.names $iopadmap$Z[23] Z[23] -1 1 -.names $iopadmap$Z[24] Z[24] -1 1 -.names $iopadmap$Z[25] Z[25] -1 1 -.names $iopadmap$Z[26] Z[26] -1 1 -.names $iopadmap$Z[27] Z[27] -1 1 -.names $iopadmap$Z[28] Z[28] -1 1 -.names $iopadmap$Z[29] Z[29] -1 1 -.names $iopadmap$Z[30] Z[30] -1 1 -.names $iopadmap$Z[31] Z[31] -1 1 -.names $iopadmap$Z[32] Z[32] -1 1 -.names $iopadmap$Z[33] Z[33] -1 1 -.names $iopadmap$Z[34] Z[34] -1 1 -.names $iopadmap$Z[35] Z[35] -1 1 -.names $iopadmap$Z[36] Z[36] -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_3/gold/primitive_example_design_3_post_synth.v b/design_edit/Tests/primitive_example_design_3/gold/primitive_example_design_3_post_synth.v deleted file mode 100644 index 5b95f28bd..000000000 --- a/design_edit/Tests/primitive_example_design_3/gold/primitive_example_design_3_post_synth.v +++ /dev/null @@ -1,746 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_primitive_example_design_3(i_buft_oe, Z, z_out, a_out, b_out, i_buf_reset, i_buf_load_acc, i_buf_saturate, i_buf_clk, i_buf_ACC_FIR, o_buf_dly_b, i_buf_feedback, i_buf_shift_right, i_buf_round, i_buf_subtract, i_buf_unsigned_a, i_buf_unsigned_b, \$iopadmap$ibuf1_en ); - output [37:0] Z; - input [19:0] a_out; - input [17:0] b_out; - input [5:0] i_buf_ACC_FIR; - input i_buf_clk; - input [2:0] i_buf_feedback; - input i_buf_load_acc; - input i_buf_reset; - input i_buf_round; - input i_buf_saturate; - input [5:0] i_buf_shift_right; - input i_buf_subtract; - input i_buf_unsigned_a; - input i_buf_unsigned_b; - input [37:0] i_buft_oe; - input [19:0] \$iopadmap$ibuf1_en ; - output [17:0] o_buf_dly_b; - output [37:0] z_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap404$iopadmap$primitive_example_design_3.ibuf1_en_18.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap405$iopadmap$primitive_example_design_3.ibuf2_en_7.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap405$iopadmap$primitive_example_design_3.ibuf2_en_7.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap405$iopadmap$primitive_example_design_3.ibuf2_en_7.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap406$iopadmap$primitive_example_design_3.ibuf1_en_19.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap406$iopadmap$primitive_example_design_3.ibuf1_en_19.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap406$iopadmap$primitive_example_design_3.ibuf1_en_19.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap407$iopadmap$primitive_example_design_3.ibuf2_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap407$iopadmap$primitive_example_design_3.ibuf2_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap407$iopadmap$primitive_example_design_3.ibuf2_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap408$iopadmap$primitive_example_design_3.ibuf2_en_1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap408$iopadmap$primitive_example_design_3.ibuf2_en_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap408$iopadmap$primitive_example_design_3.ibuf2_en_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap409$iopadmap$primitive_example_design_3.ibuf1_en_5.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap409$iopadmap$primitive_example_design_3.ibuf1_en_5.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap409$iopadmap$primitive_example_design_3.ibuf1_en_5.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap410$iopadmap$primitive_example_design_3.ibuf1_en_14.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap410$iopadmap$primitive_example_design_3.ibuf1_en_14.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap410$iopadmap$primitive_example_design_3.ibuf1_en_14.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap411$iopadmap$primitive_example_design_3.i_buft_oe_35.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap411$iopadmap$primitive_example_design_3.i_buft_oe_35.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap411$iopadmap$primitive_example_design_3.i_buft_oe_35.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap412$iopadmap$primitive_example_design_3.ibuf1_en_6.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap412$iopadmap$primitive_example_design_3.ibuf1_en_6.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap412$iopadmap$primitive_example_design_3.ibuf1_en_6.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap413$iopadmap$primitive_example_design_3.i_buft_oe_36.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap413$iopadmap$primitive_example_design_3.i_buft_oe_36.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap413$iopadmap$primitive_example_design_3.i_buft_oe_36.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap414$iopadmap$primitive_example_design_3.ibuf1_en_2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap414$iopadmap$primitive_example_design_3.ibuf1_en_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap414$iopadmap$primitive_example_design_3.ibuf1_en_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap415$iopadmap$primitive_example_design_3.ibuf1_en_9.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap415$iopadmap$primitive_example_design_3.ibuf1_en_9.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap415$iopadmap$primitive_example_design_3.ibuf1_en_9.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap416$iopadmap$primitive_example_design_3.ibuf1_en_1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap416$iopadmap$primitive_example_design_3.ibuf1_en_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap416$iopadmap$primitive_example_design_3.ibuf1_en_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap417$iopadmap$primitive_example_design_3.i_buft_oe_34.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap417$iopadmap$primitive_example_design_3.i_buft_oe_34.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap417$iopadmap$primitive_example_design_3.i_buft_oe_34.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap418$iopadmap$primitive_example_design_3.ibuf2_en_5.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap418$iopadmap$primitive_example_design_3.ibuf2_en_5.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap418$iopadmap$primitive_example_design_3.ibuf2_en_5.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap419$iopadmap$primitive_example_design_3.ibuf1_en_13.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap419$iopadmap$primitive_example_design_3.ibuf1_en_13.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap419$iopadmap$primitive_example_design_3.ibuf1_en_13.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap420$iopadmap$primitive_example_design_3.ibuf1_en_8.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap420$iopadmap$primitive_example_design_3.ibuf1_en_8.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap420$iopadmap$primitive_example_design_3.ibuf1_en_8.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap421$iopadmap$primitive_example_design_3.ibuf1_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap421$iopadmap$primitive_example_design_3.ibuf1_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap421$iopadmap$primitive_example_design_3.ibuf1_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap422$iopadmap$primitive_example_design_3.ibuf1_en_7.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap422$iopadmap$primitive_example_design_3.ibuf1_en_7.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap422$iopadmap$primitive_example_design_3.ibuf1_en_7.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap423$iopadmap$primitive_example_design_3.ibuf4_en_9.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap423$iopadmap$primitive_example_design_3.ibuf4_en_9.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap423$iopadmap$primitive_example_design_3.ibuf4_en_9.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap424$iopadmap$primitive_example_design_3.i_buft_oe_26.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap424$iopadmap$primitive_example_design_3.i_buft_oe_26.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap424$iopadmap$primitive_example_design_3.i_buft_oe_26.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap425$iopadmap$primitive_example_design_3.i_buft_oe_1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap425$iopadmap$primitive_example_design_3.i_buft_oe_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap425$iopadmap$primitive_example_design_3.i_buft_oe_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap426$iopadmap$primitive_example_design_3.ibuf4_en_7.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap426$iopadmap$primitive_example_design_3.ibuf4_en_7.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap426$iopadmap$primitive_example_design_3.ibuf4_en_7.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap427$iopadmap$primitive_example_design_3.i_buft_oe_25.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap427$iopadmap$primitive_example_design_3.i_buft_oe_25.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap427$iopadmap$primitive_example_design_3.i_buft_oe_25.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap428$iopadmap$primitive_example_design_3.ibuf4_en_12.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap428$iopadmap$primitive_example_design_3.ibuf4_en_12.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap428$iopadmap$primitive_example_design_3.ibuf4_en_12.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap429$iopadmap$primitive_example_design_3.ibuf1_en_3.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap429$iopadmap$primitive_example_design_3.ibuf1_en_3.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap429$iopadmap$primitive_example_design_3.ibuf1_en_3.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap430$iopadmap$primitive_example_design_3.ibuf1_en_4.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap430$iopadmap$primitive_example_design_3.ibuf1_en_4.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap430$iopadmap$primitive_example_design_3.ibuf1_en_4.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap431$iopadmap$primitive_example_design_3.ibuf4_en_3.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap431$iopadmap$primitive_example_design_3.ibuf4_en_3.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap431$iopadmap$primitive_example_design_3.ibuf4_en_3.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap432$iopadmap$primitive_example_design_3.ibuf4_en_13.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap432$iopadmap$primitive_example_design_3.ibuf4_en_13.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap432$iopadmap$primitive_example_design_3.ibuf4_en_13.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap433$iopadmap$primitive_example_design_3.i_buft_oe_24.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap433$iopadmap$primitive_example_design_3.i_buft_oe_24.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap433$iopadmap$primitive_example_design_3.i_buft_oe_24.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap434$iopadmap$primitive_example_design_3.i_buft_oe_30.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap434$iopadmap$primitive_example_design_3.i_buft_oe_30.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap434$iopadmap$primitive_example_design_3.i_buft_oe_30.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap435$iopadmap$primitive_example_design_3.i_buft_oe_33.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap435$iopadmap$primitive_example_design_3.i_buft_oe_33.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap435$iopadmap$primitive_example_design_3.i_buft_oe_33.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap436$iopadmap$primitive_example_design_3.i_buft_oe_31.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap436$iopadmap$primitive_example_design_3.i_buft_oe_31.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap436$iopadmap$primitive_example_design_3.i_buft_oe_31.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap437$iopadmap$primitive_example_design_3.i_buft_oe_15.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap437$iopadmap$primitive_example_design_3.i_buft_oe_15.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap437$iopadmap$primitive_example_design_3.i_buft_oe_15.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap438$iopadmap$primitive_example_design_3.i_buft_oe_32.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap438$iopadmap$primitive_example_design_3.i_buft_oe_32.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap438$iopadmap$primitive_example_design_3.i_buft_oe_32.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap439$iopadmap$primitive_example_design_3.i_buft_oe_8.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap439$iopadmap$primitive_example_design_3.i_buft_oe_8.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap439$iopadmap$primitive_example_design_3.i_buft_oe_8.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap440$iopadmap$primitive_example_design_3.i_buft_oe_4.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap440$iopadmap$primitive_example_design_3.i_buft_oe_4.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap440$iopadmap$primitive_example_design_3.i_buft_oe_4.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap441$iopadmap$primitive_example_design_3.i_buft_oe_28.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap441$iopadmap$primitive_example_design_3.i_buft_oe_28.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap441$iopadmap$primitive_example_design_3.i_buft_oe_28.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap442$iopadmap$primitive_example_design_3.ibuf4_en_4.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap442$iopadmap$primitive_example_design_3.ibuf4_en_4.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap442$iopadmap$primitive_example_design_3.ibuf4_en_4.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap443$iopadmap$primitive_example_design_3.ibuf2_en_8.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap443$iopadmap$primitive_example_design_3.ibuf2_en_8.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap443$iopadmap$primitive_example_design_3.ibuf2_en_8.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap444$iopadmap$primitive_example_design_3.i_buft_oe_2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap444$iopadmap$primitive_example_design_3.i_buft_oe_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap444$iopadmap$primitive_example_design_3.i_buft_oe_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap445$iopadmap$primitive_example_design_3.ibuf2_en_17.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap445$iopadmap$primitive_example_design_3.ibuf2_en_17.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap445$iopadmap$primitive_example_design_3.ibuf2_en_17.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap446$iopadmap$primitive_example_design_3.i_buft_oe_5.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap446$iopadmap$primitive_example_design_3.i_buft_oe_5.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap446$iopadmap$primitive_example_design_3.i_buft_oe_5.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap447$iopadmap$primitive_example_design_3.i_buft_oe_29.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap447$iopadmap$primitive_example_design_3.i_buft_oe_29.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap447$iopadmap$primitive_example_design_3.i_buft_oe_29.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap448$iopadmap$primitive_example_design_3.i_buft_oe_16.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap448$iopadmap$primitive_example_design_3.i_buft_oe_16.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap448$iopadmap$primitive_example_design_3.i_buft_oe_16.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap449$iopadmap$primitive_example_design_3.i_buft_oe_13.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap449$iopadmap$primitive_example_design_3.i_buft_oe_13.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap449$iopadmap$primitive_example_design_3.i_buft_oe_13.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap450$iopadmap$primitive_example_design_3.i_buft_oe_17.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap450$iopadmap$primitive_example_design_3.i_buft_oe_17.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap450$iopadmap$primitive_example_design_3.i_buft_oe_17.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap451$iopadmap$primitive_example_design_3.i_buft_oe_14.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap451$iopadmap$primitive_example_design_3.i_buft_oe_14.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap451$iopadmap$primitive_example_design_3.i_buft_oe_14.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap452$iopadmap$primitive_example_design_3.ibuf4_en_6.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap452$iopadmap$primitive_example_design_3.ibuf4_en_6.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap452$iopadmap$primitive_example_design_3.ibuf4_en_6.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap453$iopadmap$primitive_example_design_3.i_buft_oe_12.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap453$iopadmap$primitive_example_design_3.i_buft_oe_12.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap453$iopadmap$primitive_example_design_3.i_buft_oe_12.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap454$iopadmap$primitive_example_design_3.ibuf4_en_8.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap454$iopadmap$primitive_example_design_3.ibuf4_en_8.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap454$iopadmap$primitive_example_design_3.ibuf4_en_8.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap455$iopadmap$primitive_example_design_3.i_buft_oe_3.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap455$iopadmap$primitive_example_design_3.i_buft_oe_3.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap455$iopadmap$primitive_example_design_3.i_buft_oe_3.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap456$iopadmap$primitive_example_design_3.i_buft_oe_10.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap456$iopadmap$primitive_example_design_3.i_buft_oe_10.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap456$iopadmap$primitive_example_design_3.i_buft_oe_10.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap457$iopadmap$primitive_example_design_3.i_buft_oe_11.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap457$iopadmap$primitive_example_design_3.i_buft_oe_11.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap457$iopadmap$primitive_example_design_3.i_buft_oe_11.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap458$iopadmap$primitive_example_design_3.ibuf4_en_16.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap458$iopadmap$primitive_example_design_3.ibuf4_en_16.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap458$iopadmap$primitive_example_design_3.ibuf4_en_16.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap459$iopadmap$primitive_example_design_3.ibuf4_en_10.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap459$iopadmap$primitive_example_design_3.ibuf4_en_10.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap459$iopadmap$primitive_example_design_3.ibuf4_en_10.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap460$iopadmap$primitive_example_design_3.i_buft_oe_20.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap460$iopadmap$primitive_example_design_3.i_buft_oe_20.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap460$iopadmap$primitive_example_design_3.i_buft_oe_20.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap461$iopadmap$primitive_example_design_3.i_buft_oe_27.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap461$iopadmap$primitive_example_design_3.i_buft_oe_27.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap461$iopadmap$primitive_example_design_3.i_buft_oe_27.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap462$iopadmap$primitive_example_design_3.i_buft_oe_22.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap462$iopadmap$primitive_example_design_3.i_buft_oe_22.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap462$iopadmap$primitive_example_design_3.i_buft_oe_22.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap463$iopadmap$primitive_example_design_3.i_buft_oe_18.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap463$iopadmap$primitive_example_design_3.i_buft_oe_18.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap463$iopadmap$primitive_example_design_3.i_buft_oe_18.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap464$iopadmap$primitive_example_design_3.i_buft_oe_23.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap464$iopadmap$primitive_example_design_3.i_buft_oe_23.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap464$iopadmap$primitive_example_design_3.i_buft_oe_23.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap465$iopadmap$primitive_example_design_3.ibuf4_en_5.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap465$iopadmap$primitive_example_design_3.ibuf4_en_5.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap465$iopadmap$primitive_example_design_3.ibuf4_en_5.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap466$iopadmap$primitive_example_design_3.i_buft_oe_7.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap466$iopadmap$primitive_example_design_3.i_buft_oe_7.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap466$iopadmap$primitive_example_design_3.i_buft_oe_7.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap467$iopadmap$primitive_example_design_3.ibuf4_en_17.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap467$iopadmap$primitive_example_design_3.ibuf4_en_17.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap467$iopadmap$primitive_example_design_3.ibuf4_en_17.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap468$iopadmap$primitive_example_design_3.ibuf4_en_15.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap468$iopadmap$primitive_example_design_3.ibuf4_en_15.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap468$iopadmap$primitive_example_design_3.ibuf4_en_15.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap469$iopadmap$primitive_example_design_3.i_buft_oe_9.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap469$iopadmap$primitive_example_design_3.i_buft_oe_9.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap469$iopadmap$primitive_example_design_3.i_buft_oe_9.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap470$iopadmap$primitive_example_design_3.ibuf4_en_11.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap470$iopadmap$primitive_example_design_3.ibuf4_en_11.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap470$iopadmap$primitive_example_design_3.ibuf4_en_11.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap471$iopadmap$primitive_example_design_3.ibuf4_en_14.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap471$iopadmap$primitive_example_design_3.ibuf4_en_14.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap471$iopadmap$primitive_example_design_3.ibuf4_en_14.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap472$iopadmap$primitive_example_design_3.i_buft_oe_6.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap472$iopadmap$primitive_example_design_3.i_buft_oe_6.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap472$iopadmap$primitive_example_design_3.i_buft_oe_6.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap473$iopadmap$primitive_example_design_3.i_buft_oe.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap473$iopadmap$primitive_example_design_3.i_buft_oe.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap473$iopadmap$primitive_example_design_3.i_buft_oe.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap474$iopadmap$primitive_example_design_3.ibuf2_en_4.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap474$iopadmap$primitive_example_design_3.ibuf2_en_4.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap474$iopadmap$primitive_example_design_3.ibuf2_en_4.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap475$iopadmap$primitive_example_design_3.ibuf2_en_3.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap475$iopadmap$primitive_example_design_3.ibuf2_en_3.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap475$iopadmap$primitive_example_design_3.ibuf2_en_3.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap476$iopadmap$primitive_example_design_3.ibuf1_en_12.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap476$iopadmap$primitive_example_design_3.ibuf1_en_12.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap476$iopadmap$primitive_example_design_3.ibuf1_en_12.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap477$iopadmap$primitive_example_design_3.ibuf1_en_11.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap477$iopadmap$primitive_example_design_3.ibuf1_en_11.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap477$iopadmap$primitive_example_design_3.ibuf1_en_11.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap478$iopadmap$primitive_example_design_3.ibuf1_en_10.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap478$iopadmap$primitive_example_design_3.ibuf1_en_10.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap478$iopadmap$primitive_example_design_3.ibuf1_en_10.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap479$iopadmap$primitive_example_design_3.Z.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap479$iopadmap$primitive_example_design_3.Z.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap479$iopadmap$primitive_example_design_3.Z.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap480$iopadmap$primitive_example_design_3.ibuf2_en_16.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap480$iopadmap$primitive_example_design_3.ibuf2_en_16.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap480$iopadmap$primitive_example_design_3.ibuf2_en_16.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap481$iopadmap$primitive_example_design_3.ibuf2_en_15.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap481$iopadmap$primitive_example_design_3.ibuf2_en_15.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap481$iopadmap$primitive_example_design_3.ibuf2_en_15.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap482$iopadmap$primitive_example_design_3.ibuf2_en_14.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap482$iopadmap$primitive_example_design_3.ibuf2_en_14.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap482$iopadmap$primitive_example_design_3.ibuf2_en_14.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap483$iopadmap$primitive_example_design_3.ibuf2_en_13.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap483$iopadmap$primitive_example_design_3.ibuf2_en_13.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap483$iopadmap$primitive_example_design_3.ibuf2_en_13.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap484$iopadmap$primitive_example_design_3.ibuf4_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap484$iopadmap$primitive_example_design_3.ibuf4_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap484$iopadmap$primitive_example_design_3.ibuf4_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap485$iopadmap$primitive_example_design_3.ibuf2_en_12.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap485$iopadmap$primitive_example_design_3.ibuf2_en_12.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap485$iopadmap$primitive_example_design_3.ibuf2_en_12.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap486$iopadmap$primitive_example_design_3.ibuf3_en_5.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap486$iopadmap$primitive_example_design_3.ibuf3_en_5.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap486$iopadmap$primitive_example_design_3.ibuf3_en_5.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap487$iopadmap$primitive_example_design_3.ibuf2_en_11.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap487$iopadmap$primitive_example_design_3.ibuf2_en_11.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap487$iopadmap$primitive_example_design_3.ibuf2_en_11.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap488$iopadmap$primitive_example_design_3.ibuf3_en_4.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap488$iopadmap$primitive_example_design_3.ibuf3_en_4.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap488$iopadmap$primitive_example_design_3.ibuf3_en_4.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap489$iopadmap$primitive_example_design_3.ibuf4_en_1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap489$iopadmap$primitive_example_design_3.ibuf4_en_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap489$iopadmap$primitive_example_design_3.ibuf4_en_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap490$iopadmap$primitive_example_design_3.ibuf3_en_3.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap490$iopadmap$primitive_example_design_3.ibuf3_en_3.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap490$iopadmap$primitive_example_design_3.ibuf3_en_3.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap491$iopadmap$primitive_example_design_3.ibuf3_en_2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap491$iopadmap$primitive_example_design_3.ibuf3_en_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap491$iopadmap$primitive_example_design_3.ibuf3_en_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap492$iopadmap$primitive_example_design_3.ibuf4_en_2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap492$iopadmap$primitive_example_design_3.ibuf4_en_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap492$iopadmap$primitive_example_design_3.ibuf4_en_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap493$iopadmap$primitive_example_design_3.ibuf3_en_1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap493$iopadmap$primitive_example_design_3.ibuf3_en_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap493$iopadmap$primitive_example_design_3.ibuf3_en_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap494$iopadmap$primitive_example_design_3.ibuf2_en_10.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap494$iopadmap$primitive_example_design_3.ibuf2_en_10.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap494$iopadmap$primitive_example_design_3.ibuf2_en_10.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap495$iopadmap$primitive_example_design_3.ibuf3_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap495$iopadmap$primitive_example_design_3.ibuf3_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap495$iopadmap$primitive_example_design_3.ibuf3_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap496$iopadmap$primitive_example_design_3.ibuf2_en_9.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap496$iopadmap$primitive_example_design_3.ibuf2_en_9.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap496$iopadmap$primitive_example_design_3.ibuf2_en_9.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap497$iopadmap$primitive_example_design_3.ibuf2_en_2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap497$iopadmap$primitive_example_design_3.ibuf2_en_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap497$iopadmap$primitive_example_design_3.ibuf2_en_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap498$iopadmap$primitive_example_design_3.i_buft_oe_19.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap498$iopadmap$primitive_example_design_3.i_buft_oe_19.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap498$iopadmap$primitive_example_design_3.i_buft_oe_19.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap499$iopadmap$primitive_example_design_3.i_buft_oe_21.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap499$iopadmap$primitive_example_design_3.i_buft_oe_21.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap499$iopadmap$primitive_example_design_3.i_buft_oe_21.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap403$iopadmap$primitive_example_design_3.ibuf2_en_6.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap400$iopadmap$primitive_example_design_3.ibuf1_en_15.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap400$iopadmap$primitive_example_design_3.ibuf1_en_15.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap402$iopadmap$primitive_example_design_3.ibuf1_en_17.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap404$iopadmap$primitive_example_design_3.ibuf1_en_18.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap401$iopadmap$primitive_example_design_3.ibuf1_en_16.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap400$iopadmap$primitive_example_design_3.ibuf1_en_15.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap402$iopadmap$primitive_example_design_3.ibuf1_en_17.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap402$iopadmap$primitive_example_design_3.ibuf1_en_17.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap401$iopadmap$primitive_example_design_3.ibuf1_en_16.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap404$iopadmap$primitive_example_design_3.ibuf1_en_18.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap401$iopadmap$primitive_example_design_3.ibuf1_en_16.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap403$iopadmap$primitive_example_design_3.ibuf2_en_6.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap403$iopadmap$primitive_example_design_3.ibuf2_en_6.I ; - (* src = "./rtl/primitive_example_design_3.v:6.19-6.20" *) - (* src = "./rtl/primitive_example_design_3.v:6.19-6.20" *) - wire [37:0] Z; - (* src = "./rtl/primitive_example_design_3.v:25.15-25.20" *) - (* src = "./rtl/primitive_example_design_3.v:25.15-25.20" *) - wire [19:0] a_out; - (* src = "./rtl/primitive_example_design_3.v:26.15-26.20" *) - (* src = "./rtl/primitive_example_design_3.v:26.15-26.20" *) - wire [17:0] b_out; - (* src = "./rtl/primitive_example_design_3.v:28.14-28.27" *) - (* src = "./rtl/primitive_example_design_3.v:28.14-28.27" *) - wire [5:0] i_buf_ACC_FIR; - (* src = "./rtl/primitive_example_design_3.v:27.63-27.72" *) - (* src = "./rtl/primitive_example_design_3.v:27.63-27.72" *) - wire i_buf_clk; - (* src = "./rtl/primitive_example_design_3.v:30.14-30.28" *) - (* src = "./rtl/primitive_example_design_3.v:30.14-30.28" *) - wire [2:0] i_buf_feedback; - (* src = "./rtl/primitive_example_design_3.v:27.33-27.47" *) - (* src = "./rtl/primitive_example_design_3.v:27.33-27.47" *) - wire i_buf_load_acc; - (* src = "./rtl/primitive_example_design_3.v:27.21-27.32" *) - (* src = "./rtl/primitive_example_design_3.v:27.21-27.32" *) - wire i_buf_reset; - (* src = "./rtl/primitive_example_design_3.v:32.8-32.19" *) - (* src = "./rtl/primitive_example_design_3.v:32.8-32.19" *) - wire i_buf_round; - (* src = "./rtl/primitive_example_design_3.v:27.48-27.62" *) - (* src = "./rtl/primitive_example_design_3.v:27.48-27.62" *) - wire i_buf_saturate; - (* src = "./rtl/primitive_example_design_3.v:31.14-31.31" *) - (* src = "./rtl/primitive_example_design_3.v:31.14-31.31" *) - wire [5:0] i_buf_shift_right; - (* src = "./rtl/primitive_example_design_3.v:32.20-32.34" *) - (* src = "./rtl/primitive_example_design_3.v:32.20-32.34" *) - wire i_buf_subtract; - (* src = "./rtl/primitive_example_design_3.v:32.35-32.51" *) - (* src = "./rtl/primitive_example_design_3.v:32.35-32.51" *) - wire i_buf_unsigned_a; - (* src = "./rtl/primitive_example_design_3.v:32.52-32.68" *) - (* src = "./rtl/primitive_example_design_3.v:32.52-32.68" *) - wire i_buf_unsigned_b; - (* src = "./rtl/primitive_example_design_3.v:4.18-4.27" *) - (* src = "./rtl/primitive_example_design_3.v:4.18-4.27" *) - wire [37:0] i_buft_oe; - wire [19:0] \$iopadmap$ibuf1_en ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap399$auto$clkbufmap.cc:262:execute$397.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap399$auto$clkbufmap.cc:262:execute$397.I ; - wire [37:0] \$iopadmap$Z ; - wire [37:0] \$iopadmap$i_buft_oe ; - wire [17:0] o_buf_dly_b; - (* src = "./rtl/primitive_example_design_3.v:24.15-24.20" *) - (* unused_bits = "37" *) - (* src = "./rtl/primitive_example_design_3.v:24.15-24.20" *) - (* unused_bits = "37" *) - wire [37:0] z_out; - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:97.6-111.17" *) - DSP38 #( - .COEFF_0(20'h00000), - .COEFF_1(20'h00000), - .COEFF_2(20'h00000), - .COEFF_3(20'h00000), - .DSP_MODE("MULTIPLY_ACCUMULATE"), - .INPUT_REG_EN("TRUE"), - .OUTPUT_REG_EN("TRUE") - ) dsp38_inst ( - .A(a_out), - .ACC_FIR(i_buf_ACC_FIR), - .B(b_out), - .CLK(i_buf_clk), - .DLY_B(o_buf_dly_b), - .FEEDBACK(i_buf_feedback), - .LOAD_ACC(i_buf_load_acc), - .RESET(i_buf_reset), - .ROUND(i_buf_round), - .SATURATE(i_buf_saturate), - .SHIFT_RIGHT(i_buf_shift_right), - .SUBTRACT(i_buf_subtract), - .UNSIGNED_A(i_buf_unsigned_a), - .UNSIGNED_B(i_buf_unsigned_b), - .Z(z_out) - ); - assign \$iopadmap$Z [37] = 1'hx; - assign \$iopadmap$i_buft_oe [0] = i_buft_oe[0]; - assign Z[0] = \$iopadmap$Z [0]; - assign Z[1] = \$iopadmap$Z [1]; - assign Z[2] = \$iopadmap$Z [2]; - assign Z[3] = \$iopadmap$Z [3]; - assign Z[4] = \$iopadmap$Z [4]; - assign Z[5] = \$iopadmap$Z [5]; - assign Z[6] = \$iopadmap$Z [6]; - assign Z[7] = \$iopadmap$Z [7]; - assign Z[8] = \$iopadmap$Z [8]; - assign Z[9] = \$iopadmap$Z [9]; - assign Z[10] = \$iopadmap$Z [10]; - assign Z[11] = \$iopadmap$Z [11]; - assign Z[12] = \$iopadmap$Z [12]; - assign Z[13] = \$iopadmap$Z [13]; - assign Z[14] = \$iopadmap$Z [14]; - assign Z[15] = \$iopadmap$Z [15]; - assign Z[16] = \$iopadmap$Z [16]; - assign Z[17] = \$iopadmap$Z [17]; - assign Z[18] = \$iopadmap$Z [18]; - assign Z[19] = \$iopadmap$Z [19]; - assign Z[20] = \$iopadmap$Z [20]; - assign Z[21] = \$iopadmap$Z [21]; - assign Z[22] = \$iopadmap$Z [22]; - assign Z[23] = \$iopadmap$Z [23]; - assign Z[24] = \$iopadmap$Z [24]; - assign Z[25] = \$iopadmap$Z [25]; - assign Z[26] = \$iopadmap$Z [26]; - assign Z[27] = \$iopadmap$Z [27]; - assign Z[28] = \$iopadmap$Z [28]; - assign Z[29] = \$iopadmap$Z [29]; - assign Z[30] = \$iopadmap$Z [30]; - assign Z[31] = \$iopadmap$Z [31]; - assign Z[32] = \$iopadmap$Z [32]; - assign Z[33] = \$iopadmap$Z [33]; - assign Z[34] = \$iopadmap$Z [34]; - assign Z[35] = \$iopadmap$Z [35]; - assign Z[36] = \$iopadmap$Z [36]; -endmodule diff --git a/design_edit/Tests/primitive_example_design_3/gold/wrapper_primitive_example_design_3_post_synth.eblif b/design_edit/Tests/primitive_example_design_3/gold/wrapper_primitive_example_design_3_post_synth.eblif deleted file mode 100644 index aa50ef8c4..000000000 --- a/design_edit/Tests/primitive_example_design_3/gold/wrapper_primitive_example_design_3_post_synth.eblif +++ /dev/null @@ -1,1036 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model primitive_example_design_3 -.inputs A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] A[19] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] B[8] B[9] B[10] B[11] B[12] B[13] B[14] B[15] B[16] B[17] i_buft_oe[0] i_buft_oe[1] i_buft_oe[2] i_buft_oe[3] i_buft_oe[4] i_buft_oe[5] i_buft_oe[6] i_buft_oe[7] i_buft_oe[8] i_buft_oe[9] i_buft_oe[10] i_buft_oe[11] i_buft_oe[12] i_buft_oe[13] i_buft_oe[14] i_buft_oe[15] i_buft_oe[16] i_buft_oe[17] i_buft_oe[18] i_buft_oe[19] i_buft_oe[20] i_buft_oe[21] i_buft_oe[22] i_buft_oe[23] i_buft_oe[24] i_buft_oe[25] i_buft_oe[26] i_buft_oe[27] i_buft_oe[28] i_buft_oe[29] i_buft_oe[30] i_buft_oe[31] i_buft_oe[32] i_buft_oe[33] i_buft_oe[34] i_buft_oe[35] i_buft_oe[36] i_buft_oe[37] ACC_FIR[0] ACC_FIR[1] ACC_FIR[2] ACC_FIR[3] ACC_FIR[4] ACC_FIR[5] CLK RESET FEEDBACK[0] FEEDBACK[1] FEEDBACK[2] LOAD_ACC SATURATE SHIFT_RIGHT[0] SHIFT_RIGHT[1] SHIFT_RIGHT[2] SHIFT_RIGHT[3] SHIFT_RIGHT[4] SHIFT_RIGHT[5] ROUND SUBTRACT UNSIGNED_A UNSIGNED_B ibuf1_en[0] ibuf1_en[1] ibuf1_en[2] ibuf1_en[3] ibuf1_en[4] ibuf1_en[5] ibuf1_en[6] ibuf1_en[7] ibuf1_en[8] ibuf1_en[9] ibuf1_en[10] ibuf1_en[11] ibuf1_en[12] ibuf1_en[13] ibuf1_en[14] ibuf1_en[15] ibuf1_en[16] ibuf1_en[17] ibuf1_en[18] ibuf1_en[19] ibuf2_en[0] ibuf2_en[1] ibuf2_en[2] ibuf2_en[3] ibuf2_en[4] ibuf2_en[5] ibuf2_en[6] ibuf2_en[7] ibuf2_en[8] ibuf2_en[9] ibuf2_en[10] ibuf2_en[11] ibuf2_en[12] ibuf2_en[13] ibuf2_en[14] ibuf2_en[15] ibuf2_en[16] ibuf2_en[17] ibuf3_en[0] ibuf3_en[1] ibuf3_en[2] ibuf3_en[3] ibuf3_en[4] ibuf3_en[5] ibuf4_en[0] ibuf4_en[1] ibuf4_en[2] ibuf4_en[3] ibuf4_en[4] ibuf4_en[5] ibuf4_en[6] ibuf4_en[7] ibuf4_en[8] ibuf4_en[9] ibuf4_en[10] ibuf4_en[11] ibuf4_en[12] ibuf4_en[13] ibuf4_en[14] ibuf4_en[15] ibuf4_en[16] ibuf4_en[17] -.outputs Z[0] Z[1] Z[2] Z[3] Z[4] Z[5] Z[6] Z[7] Z[8] Z[9] Z[10] Z[11] Z[12] Z[13] Z[14] Z[15] Z[16] Z[17] Z[18] Z[19] Z[20] Z[21] Z[22] Z[23] Z[24] Z[25] Z[26] Z[27] Z[28] Z[29] Z[30] Z[31] Z[32] Z[33] Z[34] Z[35] Z[36] Z[37] DLY_B[0] DLY_B[1] DLY_B[2] DLY_B[3] DLY_B[4] DLY_B[5] DLY_B[6] DLY_B[7] DLY_B[8] DLY_B[9] DLY_B[10] DLY_B[11] DLY_B[12] DLY_B[13] DLY_B[14] DLY_B[15] DLY_B[16] DLY_B[17] -.names $false -.names $true -1 -.names $undef -.subckt fabric_primitive_example_design_3 $iopadmap$ibuf1_en[0]=$iopadmap$ibuf1_en[0] $iopadmap$ibuf1_en[1]=$iopadmap$ibuf1_en[1] $iopadmap$ibuf1_en[2]=$iopadmap$ibuf1_en[2] $iopadmap$ibuf1_en[3]=$iopadmap$ibuf1_en[3] $iopadmap$ibuf1_en[4]=$iopadmap$ibuf1_en[4] $iopadmap$ibuf1_en[5]=$iopadmap$ibuf1_en[5] $iopadmap$ibuf1_en[6]=$iopadmap$ibuf1_en[6] $iopadmap$ibuf1_en[7]=$iopadmap$ibuf1_en[7] $iopadmap$ibuf1_en[8]=$iopadmap$ibuf1_en[8] $iopadmap$ibuf1_en[9]=$iopadmap$ibuf1_en[9] $iopadmap$ibuf1_en[10]=$iopadmap$ibuf1_en[10] $iopadmap$ibuf1_en[11]=$iopadmap$ibuf1_en[11] $iopadmap$ibuf1_en[12]=$iopadmap$ibuf1_en[12] $iopadmap$ibuf1_en[13]=$iopadmap$ibuf1_en[13] $iopadmap$ibuf1_en[14]=$iopadmap$ibuf1_en[14] $iopadmap$ibuf1_en[15]=$iopadmap$ibuf1_en[15] $iopadmap$ibuf1_en[16]=$iopadmap$ibuf1_en[16] $iopadmap$ibuf1_en[17]=$iopadmap$ibuf1_en[17] $iopadmap$ibuf1_en[18]=$iopadmap$ibuf1_en[18] $iopadmap$ibuf1_en[19]=$iopadmap$ibuf1_en[19] Z[0]=Z[0] Z[1]=Z[1] Z[2]=Z[2] Z[3]=Z[3] Z[4]=Z[4] Z[5]=Z[5] Z[6]=Z[6] Z[7]=Z[7] Z[8]=Z[8] Z[9]=Z[9] Z[10]=Z[10] Z[11]=Z[11] Z[12]=Z[12] Z[13]=Z[13] Z[14]=Z[14] Z[15]=Z[15] Z[16]=Z[16] Z[17]=Z[17] Z[18]=Z[18] Z[19]=Z[19] Z[20]=Z[20] Z[21]=Z[21] Z[22]=Z[22] Z[23]=Z[23] Z[24]=Z[24] Z[25]=Z[25] Z[26]=Z[26] Z[27]=Z[27] Z[28]=Z[28] Z[29]=Z[29] Z[30]=Z[30] Z[31]=Z[31] Z[32]=Z[32] Z[33]=Z[33] Z[34]=Z[34] Z[35]=Z[35] Z[36]=Z[36] Z[37]=Z[37] a_out[0]=a_out[0] a_out[1]=a_out[1] a_out[2]=a_out[2] a_out[3]=a_out[3] a_out[4]=a_out[4] a_out[5]=a_out[5] a_out[6]=a_out[6] a_out[7]=a_out[7] a_out[8]=a_out[8] a_out[9]=a_out[9] a_out[10]=a_out[10] a_out[11]=a_out[11] a_out[12]=a_out[12] a_out[13]=a_out[13] a_out[14]=a_out[14] a_out[15]=a_out[15] a_out[16]=a_out[16] a_out[17]=a_out[17] a_out[18]=a_out[18] a_out[19]=a_out[19] b_out[0]=b_out[0] b_out[1]=b_out[1] b_out[2]=b_out[2] b_out[3]=b_out[3] b_out[4]=b_out[4] b_out[5]=b_out[5] b_out[6]=b_out[6] b_out[7]=b_out[7] b_out[8]=b_out[8] b_out[9]=b_out[9] b_out[10]=b_out[10] b_out[11]=b_out[11] b_out[12]=b_out[12] b_out[13]=b_out[13] b_out[14]=b_out[14] b_out[15]=b_out[15] b_out[16]=b_out[16] b_out[17]=b_out[17] i_buf_ACC_FIR[0]=i_buf_ACC_FIR[0] i_buf_ACC_FIR[1]=i_buf_ACC_FIR[1] i_buf_ACC_FIR[2]=i_buf_ACC_FIR[2] i_buf_ACC_FIR[3]=i_buf_ACC_FIR[3] i_buf_ACC_FIR[4]=i_buf_ACC_FIR[4] i_buf_ACC_FIR[5]=i_buf_ACC_FIR[5] i_buf_clk=i_buf_clk i_buf_feedback[0]=i_buf_feedback[0] i_buf_feedback[1]=i_buf_feedback[1] i_buf_feedback[2]=i_buf_feedback[2] i_buf_load_acc=i_buf_load_acc i_buf_reset=i_buf_reset i_buf_round=i_buf_round i_buf_saturate=i_buf_saturate i_buf_shift_right[0]=i_buf_shift_right[0] i_buf_shift_right[1]=i_buf_shift_right[1] i_buf_shift_right[2]=i_buf_shift_right[2] i_buf_shift_right[3]=i_buf_shift_right[3] i_buf_shift_right[4]=i_buf_shift_right[4] i_buf_shift_right[5]=i_buf_shift_right[5] i_buf_subtract=i_buf_subtract i_buf_unsigned_a=i_buf_unsigned_a i_buf_unsigned_b=i_buf_unsigned_b i_buft_oe[0]=i_buft_oe[0] i_buft_oe[1]=i_buft_oe[1] i_buft_oe[2]=i_buft_oe[2] i_buft_oe[3]=i_buft_oe[3] i_buft_oe[4]=i_buft_oe[4] i_buft_oe[5]=i_buft_oe[5] i_buft_oe[6]=i_buft_oe[6] i_buft_oe[7]=i_buft_oe[7] i_buft_oe[8]=i_buft_oe[8] i_buft_oe[9]=i_buft_oe[9] i_buft_oe[10]=i_buft_oe[10] i_buft_oe[11]=i_buft_oe[11] i_buft_oe[12]=i_buft_oe[12] i_buft_oe[13]=i_buft_oe[13] i_buft_oe[14]=i_buft_oe[14] i_buft_oe[15]=i_buft_oe[15] i_buft_oe[16]=i_buft_oe[16] i_buft_oe[17]=i_buft_oe[17] i_buft_oe[18]=i_buft_oe[18] i_buft_oe[19]=i_buft_oe[19] i_buft_oe[20]=i_buft_oe[20] i_buft_oe[21]=i_buft_oe[21] i_buft_oe[22]=i_buft_oe[22] i_buft_oe[23]=i_buft_oe[23] i_buft_oe[24]=i_buft_oe[24] i_buft_oe[25]=i_buft_oe[25] i_buft_oe[26]=i_buft_oe[26] i_buft_oe[27]=i_buft_oe[27] i_buft_oe[28]=i_buft_oe[28] i_buft_oe[29]=i_buft_oe[29] i_buft_oe[30]=i_buft_oe[30] i_buft_oe[31]=i_buft_oe[31] i_buft_oe[32]=i_buft_oe[32] i_buft_oe[33]=i_buft_oe[33] i_buft_oe[34]=i_buft_oe[34] i_buft_oe[35]=i_buft_oe[35] i_buft_oe[36]=i_buft_oe[36] i_buft_oe[37]=i_buft_oe[37] o_buf_dly_b[0]=o_buf_dly_b[0] o_buf_dly_b[1]=o_buf_dly_b[1] o_buf_dly_b[2]=o_buf_dly_b[2] o_buf_dly_b[3]=o_buf_dly_b[3] o_buf_dly_b[4]=o_buf_dly_b[4] o_buf_dly_b[5]=o_buf_dly_b[5] o_buf_dly_b[6]=o_buf_dly_b[6] o_buf_dly_b[7]=o_buf_dly_b[7] o_buf_dly_b[8]=o_buf_dly_b[8] o_buf_dly_b[9]=o_buf_dly_b[9] o_buf_dly_b[10]=o_buf_dly_b[10] o_buf_dly_b[11]=o_buf_dly_b[11] o_buf_dly_b[12]=o_buf_dly_b[12] o_buf_dly_b[13]=o_buf_dly_b[13] o_buf_dly_b[14]=o_buf_dly_b[14] o_buf_dly_b[15]=o_buf_dly_b[15] o_buf_dly_b[16]=o_buf_dly_b[16] o_buf_dly_b[17]=o_buf_dly_b[17] z_out[0]=z_out[0] z_out[1]=z_out[1] z_out[2]=z_out[2] z_out[3]=z_out[3] z_out[4]=z_out[4] z_out[5]=z_out[5] z_out[6]=z_out[6] z_out[7]=z_out[7] z_out[8]=z_out[8] z_out[9]=z_out[9] z_out[10]=z_out[10] z_out[11]=z_out[11] z_out[12]=z_out[12] z_out[13]=z_out[13] z_out[14]=z_out[14] z_out[15]=z_out[15] z_out[16]=z_out[16] z_out[17]=z_out[17] z_out[18]=z_out[18] z_out[19]=z_out[19] z_out[20]=z_out[20] z_out[21]=z_out[21] z_out[22]=z_out[22] z_out[23]=z_out[23] z_out[24]=z_out[24] z_out[25]=z_out[25] z_out[26]=z_out[26] z_out[27]=z_out[27] z_out[28]=z_out[28] z_out[29]=z_out[29] z_out[30]=z_out[30] z_out[31]=z_out[31] z_out[32]=z_out[32] z_out[33]=z_out[33] z_out[34]=z_out[34] z_out[35]=z_out[35] z_out[36]=z_out[36] z_out[37]=z_out[37] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[0] O=$auto$rs_design_edit.cc:682:execute$501.a_out[0] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[0] I=$auto$rs_design_edit.cc:682:execute$501.B[0] O=$auto$rs_design_edit.cc:682:execute$501.b_out[0] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en[0] I=$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT[0] O=$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right[0] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[10] O=$auto$rs_design_edit.cc:682:execute$501.a_out[10] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[10] I=$auto$rs_design_edit.cc:682:execute$501.B[10] O=$auto$rs_design_edit.cc:682:execute$501.b_out[10] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[11] O=$auto$rs_design_edit.cc:682:execute$501.a_out[11] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[11] I=$auto$rs_design_edit.cc:682:execute$501.B[11] O=$auto$rs_design_edit.cc:682:execute$501.b_out[11] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[12] O=$auto$rs_design_edit.cc:682:execute$501.a_out[12] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[12] I=$auto$rs_design_edit.cc:682:execute$501.B[12] O=$auto$rs_design_edit.cc:682:execute$501.b_out[12] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[13] O=$auto$rs_design_edit.cc:682:execute$501.a_out[13] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[13] I=$auto$rs_design_edit.cc:682:execute$501.B[13] O=$auto$rs_design_edit.cc:682:execute$501.b_out[13] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[14] O=$auto$rs_design_edit.cc:682:execute$501.a_out[14] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[14] I=$auto$rs_design_edit.cc:682:execute$501.B[14] O=$auto$rs_design_edit.cc:682:execute$501.b_out[14] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[15] O=$auto$rs_design_edit.cc:682:execute$501.a_out[15] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[15] I=$auto$rs_design_edit.cc:682:execute$501.B[15] O=$auto$rs_design_edit.cc:682:execute$501.b_out[15] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[16] O=$auto$rs_design_edit.cc:682:execute$501.a_out[16] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[16] I=$auto$rs_design_edit.cc:682:execute$501.B[16] O=$auto$rs_design_edit.cc:682:execute$501.b_out[16] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[17] O=$auto$rs_design_edit.cc:682:execute$501.a_out[17] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[17] I=$auto$rs_design_edit.cc:682:execute$501.B[17] O=$auto$rs_design_edit.cc:682:execute$501.b_out[17] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[18] O=$auto$rs_design_edit.cc:682:execute$501.a_out[18] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[19] O=$auto$rs_design_edit.cc:682:execute$501.a_out[19] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[1] O=$auto$rs_design_edit.cc:682:execute$501.a_out[1] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[1] I=$auto$rs_design_edit.cc:682:execute$501.B[1] O=$auto$rs_design_edit.cc:682:execute$501.b_out[1] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en[1] I=$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT[1] O=$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right[1] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[2] O=$auto$rs_design_edit.cc:682:execute$501.a_out[2] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[2] I=$auto$rs_design_edit.cc:682:execute$501.B[2] O=$auto$rs_design_edit.cc:682:execute$501.b_out[2] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en[2] I=$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT[2] O=$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right[2] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[3] O=$auto$rs_design_edit.cc:682:execute$501.a_out[3] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[3] I=$auto$rs_design_edit.cc:682:execute$501.B[3] O=$auto$rs_design_edit.cc:682:execute$501.b_out[3] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en[3] I=$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT[3] O=$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right[3] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[4] O=$auto$rs_design_edit.cc:682:execute$501.a_out[4] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[4] I=$auto$rs_design_edit.cc:682:execute$501.B[4] O=$auto$rs_design_edit.cc:682:execute$501.b_out[4] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en[4] I=$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT[4] O=$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right[4] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[5] O=$auto$rs_design_edit.cc:682:execute$501.a_out[5] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[5] I=$auto$rs_design_edit.cc:682:execute$501.B[5] O=$auto$rs_design_edit.cc:682:execute$501.b_out[5] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en[5] I=$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT[5] O=$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right[5] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[6] O=$auto$rs_design_edit.cc:682:execute$501.a_out[6] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[6] I=$auto$rs_design_edit.cc:682:execute$501.B[6] O=$auto$rs_design_edit.cc:682:execute$501.b_out[6] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[7] O=$auto$rs_design_edit.cc:682:execute$501.a_out[7] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[7] I=$auto$rs_design_edit.cc:682:execute$501.B[7] O=$auto$rs_design_edit.cc:682:execute$501.b_out[7] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[8] O=$auto$rs_design_edit.cc:682:execute$501.a_out[8] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[8] I=$auto$rs_design_edit.cc:682:execute$501.B[8] O=$auto$rs_design_edit.cc:682:execute$501.b_out[8] -.subckt I_BUF EN=$undef I=$auto$rs_design_edit.cc:682:execute$501.A[9] O=$auto$rs_design_edit.cc:682:execute$501.a_out[9] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en[9] I=$auto$rs_design_edit.cc:682:execute$501.B[9] O=$auto$rs_design_edit.cc:682:execute$501.b_out[9] -.subckt O_BUF I=$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[0] O=$auto$rs_design_edit.cc:682:execute$501.DLY_B[0] -.subckt O_BUF I=$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[10] O=$auto$rs_design_edit.cc:682:execute$501.DLY_B[10] -.subckt O_BUF I=$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[11] O=$auto$rs_design_edit.cc:682:execute$501.DLY_B[11] -.subckt O_BUF I=$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[12] O=$auto$rs_design_edit.cc:682:execute$501.DLY_B[12] -.subckt O_BUF I=$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[13] O=$auto$rs_design_edit.cc:682:execute$501.DLY_B[13] -.subckt O_BUF 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$auto$rs_design_edit.cc:682:execute$501.i_buft_oe[34] -1 1 -.names i_buft_oe[35] $auto$rs_design_edit.cc:682:execute$501.i_buft_oe[35] -1 1 -.names i_buft_oe[36] $auto$rs_design_edit.cc:682:execute$501.i_buft_oe[36] -1 1 -.names i_buft_oe[37] $auto$rs_design_edit.cc:682:execute$501.i_buft_oe[37] -1 1 -.names ibuf1_en[0] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[0] -1 1 -.names ibuf1_en[1] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[1] -1 1 -.names ibuf1_en[2] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[2] -1 1 -.names ibuf1_en[3] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[3] -1 1 -.names ibuf1_en[4] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[4] -1 1 -.names ibuf1_en[5] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[5] -1 1 -.names ibuf1_en[6] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[6] -1 1 -.names ibuf1_en[7] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[7] -1 1 -.names ibuf1_en[8] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[8] -1 1 -.names ibuf1_en[9] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[9] -1 1 -.names ibuf1_en[10] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[10] -1 1 -.names ibuf1_en[11] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[11] -1 1 -.names ibuf1_en[12] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[12] -1 1 -.names ibuf1_en[13] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[13] -1 1 -.names ibuf1_en[14] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[14] -1 1 -.names ibuf1_en[15] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[15] -1 1 -.names ibuf1_en[16] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[16] -1 1 -.names ibuf1_en[17] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[17] -1 1 -.names ibuf1_en[18] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[18] -1 1 -.names ibuf1_en[19] $auto$rs_design_edit.cc:682:execute$501.ibuf1_en[19] -1 1 -.names ibuf2_en[0] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[0] -1 1 -.names ibuf2_en[1] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[1] -1 1 -.names ibuf2_en[2] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[2] -1 1 -.names ibuf2_en[3] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[3] -1 1 -.names ibuf2_en[4] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[4] -1 1 -.names ibuf2_en[5] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[5] -1 1 -.names ibuf2_en[6] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[6] -1 1 -.names ibuf2_en[7] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[7] -1 1 -.names ibuf2_en[8] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[8] -1 1 -.names ibuf2_en[9] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[9] -1 1 -.names ibuf2_en[10] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[10] -1 1 -.names ibuf2_en[11] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[11] -1 1 -.names ibuf2_en[12] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[12] -1 1 -.names ibuf2_en[13] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[13] -1 1 -.names ibuf2_en[14] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[14] -1 1 -.names ibuf2_en[15] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[15] -1 1 -.names ibuf2_en[16] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[16] -1 1 -.names ibuf2_en[17] $auto$rs_design_edit.cc:682:execute$501.ibuf2_en[17] -1 1 -.names ibuf3_en[0] $auto$rs_design_edit.cc:682:execute$501.ibuf3_en[0] -1 1 -.names ibuf3_en[1] $auto$rs_design_edit.cc:682:execute$501.ibuf3_en[1] -1 1 -.names ibuf3_en[2] $auto$rs_design_edit.cc:682:execute$501.ibuf3_en[2] -1 1 -.names ibuf3_en[3] $auto$rs_design_edit.cc:682:execute$501.ibuf3_en[3] -1 1 -.names ibuf3_en[4] $auto$rs_design_edit.cc:682:execute$501.ibuf3_en[4] -1 1 -.names ibuf3_en[5] $auto$rs_design_edit.cc:682:execute$501.ibuf3_en[5] -1 1 -.names ibuf4_en[0] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[0] -1 1 -.names ibuf4_en[1] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[1] -1 1 -.names ibuf4_en[2] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[2] -1 1 -.names ibuf4_en[3] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[3] -1 1 -.names ibuf4_en[4] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[4] -1 1 -.names ibuf4_en[5] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[5] -1 1 -.names ibuf4_en[6] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[6] -1 1 -.names ibuf4_en[7] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[7] -1 1 -.names ibuf4_en[8] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[8] -1 1 -.names ibuf4_en[9] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[9] -1 1 -.names ibuf4_en[10] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[10] -1 1 -.names ibuf4_en[11] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[11] -1 1 -.names ibuf4_en[12] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[12] -1 1 -.names ibuf4_en[13] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[13] -1 1 -.names ibuf4_en[14] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[14] -1 1 -.names ibuf4_en[15] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[15] -1 1 -.names ibuf4_en[16] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[16] -1 1 -.names ibuf4_en[17] $auto$rs_design_edit.cc:682:execute$501.ibuf4_en[17] -1 1 -.names o_buf_dly_b[0] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[0] -1 1 -.names o_buf_dly_b[1] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[1] -1 1 -.names o_buf_dly_b[2] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[2] -1 1 -.names o_buf_dly_b[3] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[3] -1 1 -.names o_buf_dly_b[4] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[4] -1 1 -.names o_buf_dly_b[5] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[5] -1 1 -.names o_buf_dly_b[6] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[6] -1 1 -.names o_buf_dly_b[7] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[7] -1 1 -.names o_buf_dly_b[8] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[8] -1 1 -.names o_buf_dly_b[9] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[9] -1 1 -.names o_buf_dly_b[10] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[10] -1 1 -.names o_buf_dly_b[11] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[11] -1 1 -.names o_buf_dly_b[12] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[12] -1 1 -.names o_buf_dly_b[13] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[13] -1 1 -.names o_buf_dly_b[14] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[14] -1 1 -.names o_buf_dly_b[15] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[15] -1 1 -.names o_buf_dly_b[16] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[16] -1 1 -.names o_buf_dly_b[17] $auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b[17] -1 1 -.names z_out[0] $auto$rs_design_edit.cc:682:execute$501.z_out[0] -1 1 -.names z_out[1] $auto$rs_design_edit.cc:682:execute$501.z_out[1] -1 1 -.names z_out[2] $auto$rs_design_edit.cc:682:execute$501.z_out[2] -1 1 -.names z_out[3] $auto$rs_design_edit.cc:682:execute$501.z_out[3] -1 1 -.names z_out[4] $auto$rs_design_edit.cc:682:execute$501.z_out[4] -1 1 -.names z_out[5] $auto$rs_design_edit.cc:682:execute$501.z_out[5] -1 1 -.names z_out[6] $auto$rs_design_edit.cc:682:execute$501.z_out[6] -1 1 -.names z_out[7] $auto$rs_design_edit.cc:682:execute$501.z_out[7] -1 1 -.names z_out[8] $auto$rs_design_edit.cc:682:execute$501.z_out[8] -1 1 -.names z_out[9] $auto$rs_design_edit.cc:682:execute$501.z_out[9] -1 1 -.names z_out[10] $auto$rs_design_edit.cc:682:execute$501.z_out[10] -1 1 -.names z_out[11] $auto$rs_design_edit.cc:682:execute$501.z_out[11] -1 1 -.names z_out[12] $auto$rs_design_edit.cc:682:execute$501.z_out[12] -1 1 -.names z_out[13] $auto$rs_design_edit.cc:682:execute$501.z_out[13] -1 1 -.names z_out[14] $auto$rs_design_edit.cc:682:execute$501.z_out[14] -1 1 -.names z_out[15] $auto$rs_design_edit.cc:682:execute$501.z_out[15] -1 1 -.names z_out[16] $auto$rs_design_edit.cc:682:execute$501.z_out[16] -1 1 -.names z_out[17] $auto$rs_design_edit.cc:682:execute$501.z_out[17] -1 1 -.names z_out[18] $auto$rs_design_edit.cc:682:execute$501.z_out[18] -1 1 -.names z_out[19] $auto$rs_design_edit.cc:682:execute$501.z_out[19] -1 1 -.names z_out[20] $auto$rs_design_edit.cc:682:execute$501.z_out[20] -1 1 -.names z_out[21] $auto$rs_design_edit.cc:682:execute$501.z_out[21] -1 1 -.names z_out[22] $auto$rs_design_edit.cc:682:execute$501.z_out[22] -1 1 -.names z_out[23] $auto$rs_design_edit.cc:682:execute$501.z_out[23] -1 1 -.names z_out[24] $auto$rs_design_edit.cc:682:execute$501.z_out[24] -1 1 -.names z_out[25] $auto$rs_design_edit.cc:682:execute$501.z_out[25] -1 1 -.names z_out[26] $auto$rs_design_edit.cc:682:execute$501.z_out[26] -1 1 -.names z_out[27] $auto$rs_design_edit.cc:682:execute$501.z_out[27] -1 1 -.names z_out[28] $auto$rs_design_edit.cc:682:execute$501.z_out[28] -1 1 -.names z_out[29] $auto$rs_design_edit.cc:682:execute$501.z_out[29] -1 1 -.names z_out[30] $auto$rs_design_edit.cc:682:execute$501.z_out[30] -1 1 -.names z_out[31] $auto$rs_design_edit.cc:682:execute$501.z_out[31] -1 1 -.names z_out[32] $auto$rs_design_edit.cc:682:execute$501.z_out[32] -1 1 -.names z_out[33] $auto$rs_design_edit.cc:682:execute$501.z_out[33] -1 1 -.names z_out[34] $auto$rs_design_edit.cc:682:execute$501.z_out[34] -1 1 -.names z_out[35] $auto$rs_design_edit.cc:682:execute$501.z_out[35] -1 1 -.names z_out[36] $auto$rs_design_edit.cc:682:execute$501.z_out[36] -1 1 -.names z_out[37] $auto$rs_design_edit.cc:682:execute$501.z_out[37] -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_3/gold/wrapper_primitive_example_design_3_post_synth.v b/design_edit/Tests/primitive_example_design_3/gold/wrapper_primitive_example_design_3_post_synth.v deleted file mode 100644 index 006e1534a..000000000 --- a/design_edit/Tests/primitive_example_design_3/gold/wrapper_primitive_example_design_3_post_synth.v +++ /dev/null @@ -1,2062 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module primitive_example_design_3(A, B, i_buft_oe, ACC_FIR, Z, DLY_B, CLK, RESET, FEEDBACK, LOAD_ACC, SATURATE, SHIFT_RIGHT, ROUND, SUBTRACT, UNSIGNED_A, UNSIGNED_B, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en); - input [5:0] ACC_FIR; - input [17:0] B; - input CLK; - output [17:0] DLY_B; - input [2:0] FEEDBACK; - input LOAD_ACC; - input RESET; - input ROUND; - input SATURATE; - input [5:0] SHIFT_RIGHT; - input SUBTRACT; - input UNSIGNED_A; - input UNSIGNED_B; - output [37:0] Z; - input [37:0] i_buft_oe; - input [19:0] ibuf1_en; - input [17:0] ibuf2_en; - input [5:0] ibuf3_en; - input [17:0] ibuf4_en; - input [19:0] A; - wire \$flatten$auto$rs_design_edit.cc:682:execute$501.$auto$clkbufmap.cc:263:execute$398 ; - wire [37:0] \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z ; - wire [37:0] \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe ; - wire [19:0] \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en ; - wire [17:0] \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en ; - wire [5:0] \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en ; - wire [17:0] \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en ; - (* src = "./rtl/primitive_example_design_3.v:24.15-24.20" *) - (* unused_bits = "37" *) - wire [37:0] \$auto$rs_design_edit.cc:682:execute$501.z_out ; - wire [17:0] \$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b ; - (* src = "./rtl/primitive_example_design_3.v:21.18-21.26" *) - wire [17:0] \$auto$rs_design_edit.cc:682:execute$501.ibuf4_en ; - (* src = "./rtl/primitive_example_design_3.v:20.17-20.25" *) - wire [5:0] \$auto$rs_design_edit.cc:682:execute$501.ibuf3_en ; - (* src = "./rtl/primitive_example_design_3.v:19.18-19.26" *) - wire [17:0] \$auto$rs_design_edit.cc:682:execute$501.ibuf2_en ; - (* src = "./rtl/primitive_example_design_3.v:18.18-18.26" *) - wire [19:0] \$auto$rs_design_edit.cc:682:execute$501.ibuf1_en ; - (* src = "./rtl/primitive_example_design_3.v:8.11-8.14" *) - wire \$auto$rs_design_edit.cc:682:execute$501.CLK ; - (* src = "./rtl/primitive_example_design_3.v:5.17-5.24" *) - wire [5:0] \$auto$rs_design_edit.cc:682:execute$501.ACC_FIR ; - (* src = "./rtl/primitive_example_design_3.v:27.8-27.20" *) - wire \$auto$rs_design_edit.cc:682:execute$501.i_buft_oe_in ; - (* src = "./rtl/primitive_example_design_3.v:4.18-4.27" *) - wire [37:0] \$auto$rs_design_edit.cc:682:execute$501.i_buft_oe ; - (* src = "./rtl/primitive_example_design_3.v:32.52-32.68" *) - wire \$auto$rs_design_edit.cc:682:execute$501.i_buf_unsigned_b ; - (* src = "./rtl/primitive_example_design_3.v:32.35-32.51" *) - wire \$auto$rs_design_edit.cc:682:execute$501.i_buf_unsigned_a ; - (* src = "./rtl/primitive_example_design_3.v:32.20-32.34" *) - wire \$auto$rs_design_edit.cc:682:execute$501.i_buf_subtract ; - (* src = "./rtl/primitive_example_design_3.v:31.14-31.31" *) - wire [5:0] \$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right ; - (* src = "./rtl/primitive_example_design_3.v:27.48-27.62" *) - wire \$auto$rs_design_edit.cc:682:execute$501.i_buf_saturate ; - (* src = "./rtl/primitive_example_design_3.v:32.8-32.19" *) - wire \$auto$rs_design_edit.cc:682:execute$501.i_buf_round ; - (* src = "./rtl/primitive_example_design_3.v:27.21-27.32" *) - wire \$auto$rs_design_edit.cc:682:execute$501.i_buf_reset ; - (* src = "./rtl/primitive_example_design_3.v:27.33-27.47" *) - wire \$auto$rs_design_edit.cc:682:execute$501.i_buf_load_acc ; - (* src = "./rtl/primitive_example_design_3.v:30.14-30.28" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$501.i_buf_feedback ; - (* src = "./rtl/primitive_example_design_3.v:27.63-27.72" *) - wire \$auto$rs_design_edit.cc:682:execute$501.i_buf_clk ; - (* src = "./rtl/primitive_example_design_3.v:28.14-28.27" *) - wire [5:0] \$auto$rs_design_edit.cc:682:execute$501.i_buf_ACC_FIR ; - (* src = "./rtl/primitive_example_design_3.v:26.15-26.20" *) - wire [17:0] \$auto$rs_design_edit.cc:682:execute$501.b_out ; - (* src = "./rtl/primitive_example_design_3.v:25.15-25.20" *) - wire [19:0] \$auto$rs_design_edit.cc:682:execute$501.a_out ; - (* src = "./rtl/primitive_example_design_3.v:6.19-6.20" *) - wire [37:0] \$auto$rs_design_edit.cc:682:execute$501.Z ; - (* src = "./rtl/primitive_example_design_3.v:17.11-17.21" *) - wire \$auto$rs_design_edit.cc:682:execute$501.UNSIGNED_B ; - (* src = "./rtl/primitive_example_design_3.v:16.11-16.21" *) - wire \$auto$rs_design_edit.cc:682:execute$501.UNSIGNED_A ; - (* src = "./rtl/primitive_example_design_3.v:10.17-10.25" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$501.FEEDBACK ; - (* src = "./rtl/primitive_example_design_3.v:11.11-11.19" *) - wire \$auto$rs_design_edit.cc:682:execute$501.LOAD_ACC ; - (* src = "./rtl/primitive_example_design_3.v:3.18-3.19" *) - wire [17:0] \$auto$rs_design_edit.cc:682:execute$501.B ; - (* src = "./rtl/primitive_example_design_3.v:2.18-2.19" *) - wire [19:0] \$auto$rs_design_edit.cc:682:execute$501.A ; - (* src = "./rtl/primitive_example_design_3.v:7.23-7.28" *) - wire [17:0] \$auto$rs_design_edit.cc:682:execute$501.DLY_B ; - (* src = "./rtl/primitive_example_design_3.v:9.11-9.16" *) - wire \$auto$rs_design_edit.cc:682:execute$501.RESET ; - (* src = "./rtl/primitive_example_design_3.v:15.11-15.19" *) - wire \$auto$rs_design_edit.cc:682:execute$501.SUBTRACT ; - (* src = "./rtl/primitive_example_design_3.v:13.17-13.28" *) - wire [5:0] \$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT ; - (* src = "./rtl/primitive_example_design_3.v:12.11-12.19" *) - wire \$auto$rs_design_edit.cc:682:execute$501.SATURATE ; - (* src = "./rtl/primitive_example_design_3.v:14.11-14.16" *) - wire \$auto$rs_design_edit.cc:682:execute$501.ROUND ; - (* src = "./rtl/primitive_example_design_3.v:5.17-5.24" *) - (* src = "./rtl/primitive_example_design_3.v:5.17-5.24" *) - wire [5:0] ACC_FIR; - (* src = "./rtl/primitive_example_design_3.v:3.18-3.19" *) - (* src = "./rtl/primitive_example_design_3.v:3.18-3.19" *) - wire [17:0] B; - (* src = "./rtl/primitive_example_design_3.v:8.11-8.14" *) - (* src = "./rtl/primitive_example_design_3.v:8.11-8.14" *) - wire CLK; - (* src = "./rtl/primitive_example_design_3.v:7.23-7.28" *) - (* src = "./rtl/primitive_example_design_3.v:7.23-7.28" *) - wire [17:0] DLY_B; - (* src = "./rtl/primitive_example_design_3.v:10.17-10.25" *) - (* src = "./rtl/primitive_example_design_3.v:10.17-10.25" *) - wire [2:0] FEEDBACK; - (* src = "./rtl/primitive_example_design_3.v:11.11-11.19" *) - (* src = "./rtl/primitive_example_design_3.v:11.11-11.19" *) - wire LOAD_ACC; - (* src = "./rtl/primitive_example_design_3.v:9.11-9.16" *) - (* src = "./rtl/primitive_example_design_3.v:9.11-9.16" *) - wire RESET; - (* src = "./rtl/primitive_example_design_3.v:14.11-14.16" *) - (* src = "./rtl/primitive_example_design_3.v:14.11-14.16" *) - wire ROUND; - (* src = "./rtl/primitive_example_design_3.v:12.11-12.19" *) - (* src = "./rtl/primitive_example_design_3.v:12.11-12.19" *) - wire SATURATE; - (* src = "./rtl/primitive_example_design_3.v:13.17-13.28" *) - (* src = "./rtl/primitive_example_design_3.v:13.17-13.28" *) - wire [5:0] SHIFT_RIGHT; - (* src = "./rtl/primitive_example_design_3.v:15.11-15.19" *) - (* src = "./rtl/primitive_example_design_3.v:15.11-15.19" *) - wire SUBTRACT; - (* src = "./rtl/primitive_example_design_3.v:16.11-16.21" *) - (* src = "./rtl/primitive_example_design_3.v:16.11-16.21" *) - wire UNSIGNED_A; - (* src = "./rtl/primitive_example_design_3.v:17.11-17.21" *) - (* src = "./rtl/primitive_example_design_3.v:17.11-17.21" *) - wire UNSIGNED_B; - (* src = "./rtl/primitive_example_design_3.v:6.19-6.20" *) - (* src = "./rtl/primitive_example_design_3.v:6.19-6.20" *) - wire [37:0] Z; - (* src = "./rtl/primitive_example_design_3.v:25.15-25.20" *) - wire [19:0] a_out; - (* src = "./rtl/primitive_example_design_3.v:26.15-26.20" *) - wire [17:0] b_out; - (* src = "./rtl/primitive_example_design_3.v:28.14-28.27" *) - wire [5:0] i_buf_ACC_FIR; - (* src = "./rtl/primitive_example_design_3.v:27.63-27.72" *) - wire i_buf_clk; - (* src = "./rtl/primitive_example_design_3.v:30.14-30.28" *) - wire [2:0] i_buf_feedback; - (* src = "./rtl/primitive_example_design_3.v:27.33-27.47" *) - wire i_buf_load_acc; - (* src = "./rtl/primitive_example_design_3.v:27.21-27.32" *) - wire i_buf_reset; - (* src = "./rtl/primitive_example_design_3.v:32.8-32.19" *) - wire i_buf_round; - (* src = "./rtl/primitive_example_design_3.v:27.48-27.62" *) - wire i_buf_saturate; - (* src = "./rtl/primitive_example_design_3.v:31.14-31.31" *) - wire [5:0] i_buf_shift_right; - (* src = "./rtl/primitive_example_design_3.v:32.20-32.34" *) - wire i_buf_subtract; - (* src = "./rtl/primitive_example_design_3.v:32.35-32.51" *) - wire i_buf_unsigned_a; - (* src = "./rtl/primitive_example_design_3.v:32.52-32.68" *) - wire i_buf_unsigned_b; - (* src = "./rtl/primitive_example_design_3.v:4.18-4.27" *) - (* src = "./rtl/primitive_example_design_3.v:4.18-4.27" *) - wire [37:0] i_buft_oe; - (* src = "./rtl/primitive_example_design_3.v:27.8-27.20" *) - wire i_buft_oe_in; - (* src = "./rtl/primitive_example_design_3.v:18.18-18.26" *) - (* src = "./rtl/primitive_example_design_3.v:18.18-18.26" *) - wire [19:0] ibuf1_en; - (* src = "./rtl/primitive_example_design_3.v:19.18-19.26" *) - (* src = "./rtl/primitive_example_design_3.v:19.18-19.26" *) - wire [17:0] ibuf2_en; - (* src = "./rtl/primitive_example_design_3.v:20.17-20.25" *) - (* src = "./rtl/primitive_example_design_3.v:20.17-20.25" *) - wire [5:0] ibuf3_en; - (* src = "./rtl/primitive_example_design_3.v:21.18-21.26" *) - (* src = "./rtl/primitive_example_design_3.v:21.18-21.26" *) - wire [17:0] ibuf4_en; - wire [17:0] o_buf_dly_b; - (* src = "./rtl/primitive_example_design_3.v:2.18-2.19" *) - (* src = "./rtl/primitive_example_design_3.v:2.18-2.19" *) - wire [19:0] A; - (* src = "./rtl/primitive_example_design_3.v:24.15-24.20" *) - (* unused_bits = "37" *) - wire [37:0] z_out; - wire [17:0] \$iopadmap$ibuf4_en ; - wire [5:0] \$iopadmap$ibuf3_en ; - wire [17:0] \$iopadmap$ibuf2_en ; - wire [19:0] \$iopadmap$ibuf1_en ; - wire [37:0] \$iopadmap$i_buft_oe ; - wire [37:0] \$iopadmap$Z ; - wire \$auto$clkbufmap.cc:263:execute$398 ; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.Z ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [37]), - .O(\$auto$rs_design_edit.cc:682:execute$501.Z [37]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [1]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [2]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_10 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [11]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [11]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_11 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [12]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [12]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_12 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [13]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [13]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_13 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [14]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [14]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_14 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [15]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [15]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_15 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [16]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [16]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_16 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [17]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [17]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_17 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [18]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [18]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_18 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [19]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [19]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_19 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [20]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [20]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [3]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [3]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_20 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [21]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [21]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_21 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [22]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [22]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_22 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [23]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [23]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_23 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [24]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [24]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_24 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [25]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [25]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_25 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [26]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [26]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_26 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [27]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [27]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_27 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [28]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [28]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_28 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [29]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [29]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_29 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [30]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [30]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_3 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [4]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [4]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_30 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [31]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [31]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_31 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [32]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [32]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_32 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [33]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [33]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_33 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [34]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [34]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_34 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [35]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [35]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_35 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [36]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [36]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_36 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [37]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [37]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_4 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [5]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [5]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_5 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [6]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [6]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_6 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [7]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [7]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_7 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [8]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [8]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_8 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [9]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [9]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.i_buft_oe_9 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe [10]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [10]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [0]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [1]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_10 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [10]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [10]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_11 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [11]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [11]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_12 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [12]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [12]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_13 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [13]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [13]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_14 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [14]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [14]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_15 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [15]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [15]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_16 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [16]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [16]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_17 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [17]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [17]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_18 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [18]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [18]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_19 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [19]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [19]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [2]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_3 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [3]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [3]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_4 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [4]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [4]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_5 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [5]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [5]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_6 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [6]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [6]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_7 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [7]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [7]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_8 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [8]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [8]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf1_en_9 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf1_en [9]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en [9]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [0]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [1]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_10 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [10]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [10]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_11 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [11]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [11]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_12 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [12]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [12]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_13 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [13]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [13]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_14 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [14]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [14]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_15 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [15]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [15]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_16 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [16]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [16]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_17 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [17]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [17]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [2]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_3 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [3]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [3]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_4 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [4]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [4]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_5 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [5]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [5]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_6 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [6]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [6]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_7 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [7]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [7]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_8 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [8]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [8]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf2_en_9 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf2_en [9]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [9]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf3_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf3_en [0]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf3_en_1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf3_en [1]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf3_en_2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf3_en [2]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf3_en_3 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf3_en [3]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [3]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf3_en_4 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf3_en [4]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [4]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf3_en_5 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf3_en [5]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [5]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [0]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [1]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_10 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [10]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [10]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_11 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [11]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [11]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_12 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [12]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [12]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_13 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [13]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [13]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_14 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [14]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [14]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_15 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [15]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [15]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_16 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [16]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [16]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_17 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [17]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [17]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [2]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_3 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [3]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [3]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_4 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [4]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [4]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_5 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [5]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [5]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_6 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [6]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [6]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_7 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [7]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [7]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_8 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [8]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [8]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$primitive_example_design_3.ibuf4_en_9 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$501.ibuf4_en [9]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [9]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:62.9-62.79" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance9 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [7]), - .I(\$auto$rs_design_edit.cc:682:execute$501.ACC_FIR [5]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_ACC_FIR [5]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[0].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [0]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[0].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [0]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [0]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[0].i_buf_instance_shift ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [0]), - .I(\$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT [0]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[10].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [10]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [10]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[10].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [10]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [10]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [10]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[11].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [11]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [11]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[11].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [11]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [11]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [11]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[12].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [12]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [12]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[12].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [12]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [12]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [12]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[13].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [13]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [13]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[13].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [13]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [13]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [13]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[14].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [14]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [14]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[14].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [14]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [14]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [14]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[15].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [15]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [15]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[15].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [15]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [15]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [15]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[16].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [16]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [16]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[16].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [16]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [16]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [16]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[17].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [17]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [17]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[17].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [17]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [17]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [17]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[18].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [18]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [18]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[19].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [19]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [19]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[1].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [1]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[1].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [1]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [1]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[1].i_buf_instance_shift ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [1]), - .I(\$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT [1]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[2].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [2]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[2].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [2]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [2]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[2].i_buf_instance_shift ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [2]), - .I(\$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT [2]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[3].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [3]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[3].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [3]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [3]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[3].i_buf_instance_shift ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [3]), - .I(\$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT [3]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right [3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[4].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [4]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [4]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[4].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [4]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [4]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [4]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[4].i_buf_instance_shift ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [4]), - .I(\$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT [4]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right [4]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[5].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [5]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [5]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[5].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [5]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [5]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [5]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[5].i_buf_instance_shift ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf3_en [5]), - .I(\$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT [5]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right [5]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[6].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [6]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [6]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[6].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [6]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [6]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [6]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[7].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [7]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [7]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[7].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [7]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [7]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [7]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[8].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [8]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [8]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[8].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [8]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [8]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [8]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[9].i_buf_instance ( - .EN(1'hx), - .I(\$auto$rs_design_edit.cc:682:execute$501.A [9]), - .O(\$auto$rs_design_edit.cc:682:execute$501.a_out [9]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_i_buf[9].i_buf_instance_b ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf2_en [9]), - .I(\$auto$rs_design_edit.cc:682:execute$501.B [9]), - .O(\$auto$rs_design_edit.cc:682:execute$501.b_out [9]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[0].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [0]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[10].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [10]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [10]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[11].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [11]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [11]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[12].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [12]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [12]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[13].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [13]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [13]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[14].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [14]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [14]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[15].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [15]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [15]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[16].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [16]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [16]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[17].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [17]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [17]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[1].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [1]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[2].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [2]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[3].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [3]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[4].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [4]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [4]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[5].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [5]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [5]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[6].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [6]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [6]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[7].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [7]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [7]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[8].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [8]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [8]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$501.gen_o_buf[9].o_buf_instance_a ( - .I(\$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b [9]), - .O(\$auto$rs_design_edit.cc:682:execute$501.DLY_B [9]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[0].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [0]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [0]), - .T(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe_in ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[10].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [10]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [10]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[11].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [11]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [11]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[12].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [12]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [12]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[13].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [13]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [13]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[14].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [14]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [14]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[15].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [15]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [15]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[16].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [16]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [16]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[17].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [17]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [17]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[18].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [18]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [18]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[19].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [19]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [19]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[1].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [1]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [1]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[20].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [20]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [20]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[21].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [21]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [21]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[22].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [22]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [22]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[23].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [23]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [23]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[24].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [24]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [24]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[25].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [25]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [25]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[26].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [26]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [26]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[27].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [27]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [27]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[28].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [28]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [28]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[29].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [29]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [29]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[2].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [2]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [2]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[30].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [30]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [30]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[31].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [31]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [31]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[32].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [32]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [32]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[33].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [33]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [33]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[34].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [34]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [34]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[35].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [35]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [35]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[36].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [36]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [36]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[3].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [3]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [3]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[4].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [4]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [4]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[5].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [5]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [5]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[6].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [6]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [6]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[7].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [7]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [7]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[8].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [8]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [8]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \$auto$rs_design_edit.cc:682:execute$501.gen_o_buft[9].o_buft_inst ( - .I(\$auto$rs_design_edit.cc:682:execute$501.z_out [9]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$Z [9]), - .T(1'hx) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:63.9-63.70" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance10 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [8]), - .I(\$auto$rs_design_edit.cc:682:execute$501.RESET ), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_reset ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:64.9-64.82" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance11 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [9]), - .I(\$auto$rs_design_edit.cc:682:execute$501.FEEDBACK [0]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_feedback [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:65.9-65.83" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance12 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [10]), - .I(\$auto$rs_design_edit.cc:682:execute$501.FEEDBACK [1]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_feedback [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:66.9-66.83" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance13 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [11]), - .I(\$auto$rs_design_edit.cc:682:execute$501.FEEDBACK [2]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_feedback [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:67.9-67.77" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance14 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [12]), - .I(\$auto$rs_design_edit.cc:682:execute$501.LOAD_ACC ), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_load_acc ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:68.9-68.77" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance15 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [13]), - .I(\$auto$rs_design_edit.cc:682:execute$501.SATURATE ), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_saturate ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:69.9-69.71" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance16 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [14]), - .I(\$auto$rs_design_edit.cc:682:execute$501.ROUND ), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_round ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:70.9-70.77" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance17 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [15]), - .I(\$auto$rs_design_edit.cc:682:execute$501.SUBTRACT ), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_subtract ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:71.9-71.81" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance18 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [16]), - .I(\$auto$rs_design_edit.cc:682:execute$501.UNSIGNED_A ), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_unsigned_a ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:72.9-72.81" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance19 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [17]), - .I(\$auto$rs_design_edit.cc:682:execute$501.UNSIGNED_B ), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_unsigned_b ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:55.9-55.65" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance2 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [0]), - .I(\$auto$rs_design_edit.cc:682:execute$501.CLK ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$501.$auto$clkbufmap.cc:263:execute$398 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:56.9-56.74" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance3 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [1]), - .I(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$i_buft_oe [0]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buft_oe_in ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:57.9-57.79" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance4 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [2]), - .I(\$auto$rs_design_edit.cc:682:execute$501.ACC_FIR [0]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_ACC_FIR [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:58.9-58.79" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance5 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [3]), - .I(\$auto$rs_design_edit.cc:682:execute$501.ACC_FIR [1]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_ACC_FIR [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:59.9-59.79" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance6 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [4]), - .I(\$auto$rs_design_edit.cc:682:execute$501.ACC_FIR [2]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_ACC_FIR [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:60.9-60.79" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance7 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [5]), - .I(\$auto$rs_design_edit.cc:682:execute$501.ACC_FIR [3]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_ACC_FIR [3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_3.v:61.9-61.79" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$501.i_buf_instance8 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf4_en [6]), - .I(\$auto$rs_design_edit.cc:682:execute$501.ACC_FIR [4]), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_ACC_FIR [4]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$501.$auto$clkbufmap.cc:262:execute$397 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$501.$auto$clkbufmap.cc:263:execute$398 ), - .O(\$auto$rs_design_edit.cc:682:execute$501.i_buf_clk ) - ); - fabric_primitive_example_design_3 \$auto$rs_design_edit.cc:680:execute$500 ( - .\$iopadmap$ibuf1_en (\$iopadmap$ibuf1_en ), - .Z(Z), - .a_out(a_out), - .b_out(b_out), - .i_buf_ACC_FIR(i_buf_ACC_FIR), - .i_buf_clk(i_buf_clk), - .i_buf_feedback(i_buf_feedback), - .i_buf_load_acc(i_buf_load_acc), - .i_buf_reset(i_buf_reset), - .i_buf_round(i_buf_round), - .i_buf_saturate(i_buf_saturate), - .i_buf_shift_right(i_buf_shift_right), - .i_buf_subtract(i_buf_subtract), - .i_buf_unsigned_a(i_buf_unsigned_a), - .i_buf_unsigned_b(i_buf_unsigned_b), - .i_buft_oe(i_buft_oe), - .o_buf_dly_b(o_buf_dly_b), - .z_out(z_out) - ); - assign \$iopadmap$ibuf1_en = \$flatten$auto$rs_design_edit.cc:682:execute$501.$iopadmap$ibuf1_en ; - assign \$auto$rs_design_edit.cc:682:execute$501.A = A; - assign \$auto$rs_design_edit.cc:682:execute$501.ACC_FIR = ACC_FIR; - assign \$auto$rs_design_edit.cc:682:execute$501.B = B; - assign \$auto$rs_design_edit.cc:682:execute$501.CLK = CLK; - assign DLY_B = \$auto$rs_design_edit.cc:682:execute$501.DLY_B ; - assign \$auto$rs_design_edit.cc:682:execute$501.FEEDBACK = FEEDBACK; - assign \$auto$rs_design_edit.cc:682:execute$501.LOAD_ACC = LOAD_ACC; - assign \$auto$rs_design_edit.cc:682:execute$501.RESET = RESET; - assign \$auto$rs_design_edit.cc:682:execute$501.ROUND = ROUND; - assign \$auto$rs_design_edit.cc:682:execute$501.SATURATE = SATURATE; - assign \$auto$rs_design_edit.cc:682:execute$501.SHIFT_RIGHT = SHIFT_RIGHT; - assign \$auto$rs_design_edit.cc:682:execute$501.SUBTRACT = SUBTRACT; - assign \$auto$rs_design_edit.cc:682:execute$501.UNSIGNED_A = UNSIGNED_A; - assign \$auto$rs_design_edit.cc:682:execute$501.UNSIGNED_B = UNSIGNED_B; - assign Z = \$auto$rs_design_edit.cc:682:execute$501.Z ; - assign a_out = \$auto$rs_design_edit.cc:682:execute$501.a_out ; - assign b_out = \$auto$rs_design_edit.cc:682:execute$501.b_out ; - assign i_buf_ACC_FIR = \$auto$rs_design_edit.cc:682:execute$501.i_buf_ACC_FIR ; - assign i_buf_clk = \$auto$rs_design_edit.cc:682:execute$501.i_buf_clk ; - assign i_buf_feedback = \$auto$rs_design_edit.cc:682:execute$501.i_buf_feedback ; - assign i_buf_load_acc = \$auto$rs_design_edit.cc:682:execute$501.i_buf_load_acc ; - assign i_buf_reset = \$auto$rs_design_edit.cc:682:execute$501.i_buf_reset ; - assign i_buf_round = \$auto$rs_design_edit.cc:682:execute$501.i_buf_round ; - assign i_buf_saturate = \$auto$rs_design_edit.cc:682:execute$501.i_buf_saturate ; - assign i_buf_shift_right = \$auto$rs_design_edit.cc:682:execute$501.i_buf_shift_right ; - assign i_buf_subtract = \$auto$rs_design_edit.cc:682:execute$501.i_buf_subtract ; - assign i_buf_unsigned_a = \$auto$rs_design_edit.cc:682:execute$501.i_buf_unsigned_a ; - assign i_buf_unsigned_b = \$auto$rs_design_edit.cc:682:execute$501.i_buf_unsigned_b ; - assign \$auto$rs_design_edit.cc:682:execute$501.i_buft_oe = i_buft_oe; - assign \$auto$rs_design_edit.cc:682:execute$501.ibuf1_en = ibuf1_en; - assign \$auto$rs_design_edit.cc:682:execute$501.ibuf2_en = ibuf2_en; - assign \$auto$rs_design_edit.cc:682:execute$501.ibuf3_en = ibuf3_en; - assign \$auto$rs_design_edit.cc:682:execute$501.ibuf4_en = ibuf4_en; - assign \$auto$rs_design_edit.cc:682:execute$501.o_buf_dly_b = o_buf_dly_b; - assign \$auto$rs_design_edit.cc:682:execute$501.z_out = z_out; -endmodule diff --git a/design_edit/Tests/primitive_example_design_3/primitive_example_design_3.ys b/design_edit/Tests/primitive_example_design_3/primitive_example_design_3.ys deleted file mode 100644 index 67e224d9a..000000000 --- a/design_edit/Tests/primitive_example_design_3/primitive_example_design_3.ys +++ /dev/null @@ -1,19 +0,0 @@ -# Yosys synthesis script for O_SERDES_primitive_inst -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./rtl/primitive_example_design_3.v - - -# Technology mapping -hierarchy -top primitive_example_design_3 - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal delay -effort high -carry auto -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -json ./tmp/io_config.json -w ./tmp/wrapper_primitive_example_design_3_post_synth.v ./tmp/wrapper_primitive_example_design_3_post_synth.eblif -write_verilog -noexpr -nodec -norename -v ./tmp/primitive_example_design_3_post_synth.v -write_blif -param ./tmp/primitive_example_design_3_post_synth.eblif \ No newline at end of file diff --git a/design_edit/Tests/primitive_example_design_3/rtl/primitive_example_design_3.v b/design_edit/Tests/primitive_example_design_3/rtl/primitive_example_design_3.v deleted file mode 100644 index ae80668af..000000000 --- a/design_edit/Tests/primitive_example_design_3/rtl/primitive_example_design_3.v +++ /dev/null @@ -1,113 +0,0 @@ -module primitive_example_design_3( - input [19:0] A, - input [17:0] B, - input [37:0] i_buft_oe, - input [5:0] ACC_FIR, - output [37:0] Z, - output reg [17:0] DLY_B, - input CLK, - input RESET, - input [2:0] FEEDBACK, - input LOAD_ACC, - input SATURATE, - input [5:0] SHIFT_RIGHT, - input ROUND, - input SUBTRACT, - input UNSIGNED_A, - input UNSIGNED_B, - input [19:0] ibuf1_en, - input [17:0] ibuf2_en, - input [5:0] ibuf3_en, - input [17:0] ibuf4_en - ); - - wire [37:0] z_out; - wire [19:0] a_out; - wire [17:0] b_out; - wire i_buft_oe_in,i_buf_reset,i_buf_load_acc,i_buf_saturate,i_buf_clk; - wire [5:0] i_buf_ACC_FIR; - wire [31:0] o_buf_dly_b; - wire [2:0] i_buf_feedback; - wire [5:0] i_buf_shift_right; - wire i_buf_round,i_buf_subtract,i_buf_unsigned_a,i_buf_unsigned_b; - - genvar i; - generate - for (i = 0; i < 20; i = i + 1) begin : gen_i_buf - I_BUF i_buf_instance (.I(A[i]),.EN(ibuf_en[i]),.O(a_out[i])); - end - endgenerate - - genvar j; - generate - for (j = 0; j < 18; j = j + 1) begin : gen_i_buf - I_BUF i_buf_instance_b (.I(B[j]),.EN(ibuf2_en[j]),.O(b_out[j])); - end - endgenerate - - genvar j; - generate - for (j = 0; j < 6; j = j + 1) begin : gen_i_buf - I_BUF i_buf_instance_shift (.I(SHIFT_RIGHT[j]),.EN(ibuf3_en[j]),.O(i_buf_shift_right[j])); - end - endgenerate - - I_BUF i_buf_instance2 (.I(CLK),.EN(ibuf4_en[0]),.O(i_buf_clk)); - I_BUF i_buf_instance3 (.I(i_buft_oe),.EN(ibuf4_en[1]),.O(i_buft_oe_in)); - I_BUF i_buf_instance4 (.I(ACC_FIR[0]),.EN(ibuf4_en[2]),.O(i_buf_ACC_FIR[0])); - I_BUF i_buf_instance5 (.I(ACC_FIR[1]),.EN(ibuf4_en[3]),.O(i_buf_ACC_FIR[1])); - I_BUF i_buf_instance6 (.I(ACC_FIR[2]),.EN(ibuf4_en[4]),.O(i_buf_ACC_FIR[2])); - I_BUF i_buf_instance7 (.I(ACC_FIR[3]),.EN(ibuf4_en[5]),.O(i_buf_ACC_FIR[3])); - I_BUF i_buf_instance8 (.I(ACC_FIR[4]),.EN(ibuf4_en[6]),.O(i_buf_ACC_FIR[4])); - I_BUF i_buf_instance9 (.I(ACC_FIR[5]),.EN(ibuf4_en[7]),.O(i_buf_ACC_FIR[5])); - I_BUF i_buf_instance10 (.I(RESET),.EN(ibuf4_en[8]),.O(i_buf_reset)); - I_BUF i_buf_instance11 (.I(FEEDBACK[0]),.EN(ibuf4_en[9]),.O(i_buf_feedback[0])); - I_BUF i_buf_instance12 (.I(FEEDBACK[1]),.EN(ibuf4_en[10]),.O(i_buf_feedback[1])); - I_BUF i_buf_instance13 (.I(FEEDBACK[2]),.EN(ibuf4_en[11]),.O(i_buf_feedback[2])); - I_BUF i_buf_instance14 (.I(LOAD_ACC),.EN(ibuf4_en[12]),.O(i_buf_load_acc)); - I_BUF i_buf_instance15 (.I(SATURATE),.EN(ibuf4_en[13]),.O(i_buf_saturate)); - I_BUF i_buf_instance16 (.I(ROUND),.EN(ibuf4_en[14]),.O(i_buf_round)); - I_BUF i_buf_instance17 (.I(SUBTRACT),.EN(ibuf4_en[15]),.O(i_buf_subtract)); - I_BUF i_buf_instance18 (.I(UNSIGNED_A),.EN(ibuf4_en[16]),.O(i_buf_unsigned_a)); - I_BUF i_buf_instance19 (.I(UNSIGNED_B),.EN(ibuf4_en[17]),.O(i_buf_unsigned_b)); - - - genvar j; - generate - for (j = 0; j < 37; j = j + 1) begin : gen_o_buft - O_BUFT o_buft_inst (.I(z_out[j]),.T(i_buft_oe_in[j]),.O(Z[j])); - end - endgenerate - - genvar j; - generate - for (j = 0; j < 18; j = j + 1) begin : gen_o_buf - O_BUF o_buf_instance_a (.I(o_buf_dly_b[j]),.O(DLY_B[j])); - end - endgenerate - - DSP38 #( - .DSP_MODE("MULTIPLY_ACCUMULATE"), - .COEFF_0(20'h00000), - .COEFF_1(20'h00000), - .COEFF_2(20'h00000), - .COEFF_3(20'h00000), - .OUTPUT_REG_EN("TRUE"), - .INPUT_REG_EN("TRUE") - )dsp38_inst (.A(a_out), - .ACC_FIR(i_buf_ACC_FIR), - .B(b_out), - .CLK(i_buf_clk), - .DLY_B(o_buf_dly_b), - .FEEDBACK(i_buf_feedback), - .LOAD_ACC(i_buf_load_acc), - .RESET(i_buf_reset), - .ROUND(i_buf_round), - .SATURATE(i_buf_saturate), - .SHIFT_RIGHT(i_buf_shift_right), - .SUBTRACT(i_buf_subtract), - .UNSIGNED_A(i_buf_unsigned_a), - .UNSIGNED_B(i_buf_unsigned_b), - .Z(z_out)); - -endmodule diff --git a/design_edit/Tests/primitive_example_design_3/synthesis/primitive_example_design_3_post_synth.eblif b/design_edit/Tests/primitive_example_design_3/synthesis/primitive_example_design_3_post_synth.eblif deleted file mode 100644 index ba3245d46..000000000 --- a/design_edit/Tests/primitive_example_design_3/synthesis/primitive_example_design_3_post_synth.eblif +++ /dev/null @@ -1,137 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model primitive_example_design_3 -.inputs A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] A[19] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] B[8] B[9] B[10] B[11] B[12] B[13] B[14] B[15] B[16] B[17] i_buft_oe[0] i_buft_oe[1] i_buft_oe[2] i_buft_oe[3] i_buft_oe[4] i_buft_oe[5] i_buft_oe[6] i_buft_oe[7] i_buft_oe[8] i_buft_oe[9] i_buft_oe[10] i_buft_oe[11] i_buft_oe[12] i_buft_oe[13] i_buft_oe[14] i_buft_oe[15] i_buft_oe[16] i_buft_oe[17] i_buft_oe[18] i_buft_oe[19] i_buft_oe[20] i_buft_oe[21] i_buft_oe[22] i_buft_oe[23] i_buft_oe[24] i_buft_oe[25] i_buft_oe[26] i_buft_oe[27] i_buft_oe[28] i_buft_oe[29] i_buft_oe[30] i_buft_oe[31] i_buft_oe[32] i_buft_oe[33] i_buft_oe[34] i_buft_oe[35] i_buft_oe[36] i_buft_oe[37] ACC_FIR[0] ACC_FIR[1] ACC_FIR[2] ACC_FIR[3] ACC_FIR[4] ACC_FIR[5] CLK RESET FEEDBACK[0] FEEDBACK[1] FEEDBACK[2] LOAD_ACC SATURATE SHIFT_RIGHT[0] SHIFT_RIGHT[1] SHIFT_RIGHT[2] SHIFT_RIGHT[3] SHIFT_RIGHT[4] SHIFT_RIGHT[5] ROUND SUBTRACT UNSIGNED_A UNSIGNED_B ibuf1_en[0] ibuf1_en[1] ibuf1_en[2] ibuf1_en[3] ibuf1_en[4] ibuf1_en[5] ibuf1_en[6] ibuf1_en[7] ibuf1_en[8] ibuf1_en[9] ibuf1_en[10] ibuf1_en[11] ibuf1_en[12] ibuf1_en[13] ibuf1_en[14] ibuf1_en[15] ibuf1_en[16] ibuf1_en[17] ibuf1_en[18] ibuf1_en[19] ibuf2_en[0] ibuf2_en[1] ibuf2_en[2] ibuf2_en[3] ibuf2_en[4] ibuf2_en[5] ibuf2_en[6] ibuf2_en[7] ibuf2_en[8] ibuf2_en[9] ibuf2_en[10] ibuf2_en[11] ibuf2_en[12] ibuf2_en[13] ibuf2_en[14] ibuf2_en[15] ibuf2_en[16] ibuf2_en[17] ibuf3_en[0] ibuf3_en[1] ibuf3_en[2] ibuf3_en[3] ibuf3_en[4] ibuf3_en[5] ibuf4_en[0] ibuf4_en[1] ibuf4_en[2] ibuf4_en[3] ibuf4_en[4] ibuf4_en[5] ibuf4_en[6] ibuf4_en[7] ibuf4_en[8] ibuf4_en[9] ibuf4_en[10] ibuf4_en[11] ibuf4_en[12] ibuf4_en[13] ibuf4_en[14] ibuf4_en[15] ibuf4_en[16] ibuf4_en[17] -.outputs Z[0] Z[1] Z[2] Z[3] Z[4] Z[5] Z[6] Z[7] Z[8] Z[9] Z[10] Z[11] Z[12] Z[13] Z[14] Z[15] Z[16] Z[17] Z[18] Z[19] Z[20] Z[21] Z[22] Z[23] Z[24] Z[25] Z[26] Z[27] Z[28] Z[29] Z[30] Z[31] Z[32] Z[33] Z[34] Z[35] Z[36] Z[37] DLY_B[0] DLY_B[1] DLY_B[2] DLY_B[3] DLY_B[4] DLY_B[5] DLY_B[6] DLY_B[7] DLY_B[8] DLY_B[9] DLY_B[10] DLY_B[11] DLY_B[12] DLY_B[13] DLY_B[14] DLY_B[15] DLY_B[16] DLY_B[17] -.names $false -.names $true -1 -.names $undef -.subckt DSP38 A[0]=a_out[0] A[1]=a_out[1] A[2]=a_out[2] A[3]=a_out[3] A[4]=a_out[4] A[5]=a_out[5] A[6]=a_out[6] A[7]=a_out[7] A[8]=a_out[8] A[9]=a_out[9] A[10]=a_out[10] A[11]=a_out[11] A[12]=a_out[12] A[13]=a_out[13] A[14]=a_out[14] A[15]=a_out[15] A[16]=a_out[16] A[17]=a_out[17] A[18]=a_out[18] A[19]=a_out[19] ACC_FIR[0]=i_buf_ACC_FIR[0] ACC_FIR[1]=i_buf_ACC_FIR[1] ACC_FIR[2]=i_buf_ACC_FIR[2] ACC_FIR[3]=i_buf_ACC_FIR[3] ACC_FIR[4]=i_buf_ACC_FIR[4] ACC_FIR[5]=i_buf_ACC_FIR[5] B[0]=b_out[0] B[1]=b_out[1] B[2]=b_out[2] B[3]=b_out[3] B[4]=b_out[4] B[5]=b_out[5] B[6]=b_out[6] B[7]=b_out[7] B[8]=b_out[8] B[9]=b_out[9] B[10]=b_out[10] B[11]=b_out[11] B[12]=b_out[12] B[13]=b_out[13] B[14]=b_out[14] B[15]=b_out[15] B[16]=b_out[16] B[17]=b_out[17] CLK=i_buf_clk DLY_B[0]=o_buf_dly_b[0] DLY_B[1]=o_buf_dly_b[1] DLY_B[2]=o_buf_dly_b[2] DLY_B[3]=o_buf_dly_b[3] DLY_B[4]=o_buf_dly_b[4] DLY_B[5]=o_buf_dly_b[5] DLY_B[6]=o_buf_dly_b[6] DLY_B[7]=o_buf_dly_b[7] DLY_B[8]=o_buf_dly_b[8] DLY_B[9]=o_buf_dly_b[9] DLY_B[10]=o_buf_dly_b[10] DLY_B[11]=o_buf_dly_b[11] DLY_B[12]=o_buf_dly_b[12] DLY_B[13]=o_buf_dly_b[13] DLY_B[14]=o_buf_dly_b[14] DLY_B[15]=o_buf_dly_b[15] DLY_B[16]=o_buf_dly_b[16] DLY_B[17]=o_buf_dly_b[17] FEEDBACK[0]=i_buf_feedback[0] FEEDBACK[1]=i_buf_feedback[1] FEEDBACK[2]=i_buf_feedback[2] LOAD_ACC=i_buf_load_acc RESET=i_buf_reset ROUND=i_buf_round SATURATE=i_buf_saturate SHIFT_RIGHT[0]=i_buf_shift_right[0] SHIFT_RIGHT[1]=i_buf_shift_right[1] SHIFT_RIGHT[2]=i_buf_shift_right[2] SHIFT_RIGHT[3]=i_buf_shift_right[3] SHIFT_RIGHT[4]=i_buf_shift_right[4] SHIFT_RIGHT[5]=i_buf_shift_right[5] SUBTRACT=i_buf_subtract UNSIGNED_A=i_buf_unsigned_a UNSIGNED_B=i_buf_unsigned_b Z[0]=z_out[0] Z[1]=z_out[1] Z[2]=z_out[2] Z[3]=z_out[3] Z[4]=z_out[4] Z[5]=z_out[5] Z[6]=z_out[6] Z[7]=z_out[7] Z[8]=z_out[8] Z[9]=z_out[9] Z[10]=z_out[10] Z[11]=z_out[11] Z[12]=z_out[12] Z[13]=z_out[13] Z[14]=z_out[14] Z[15]=z_out[15] Z[16]=z_out[16] Z[17]=z_out[17] Z[18]=z_out[18] Z[19]=z_out[19] Z[20]=z_out[20] Z[21]=z_out[21] Z[22]=z_out[22] Z[23]=z_out[23] Z[24]=z_out[24] Z[25]=z_out[25] Z[26]=z_out[26] Z[27]=z_out[27] Z[28]=z_out[28] Z[29]=z_out[29] Z[30]=z_out[30] Z[31]=z_out[31] Z[32]=z_out[32] Z[33]=z_out[33] Z[34]=z_out[34] Z[35]=z_out[35] Z[36]=z_out[36] Z[37]=z_out[37] -.param COEFF_0 00000000000000000000 -.param COEFF_1 00000000000000000000 -.param COEFF_2 00000000000000000000 -.param COEFF_3 00000000000000000000 -.param DSP_MODE "MULTIPLY_ACCUMULATE" -.param INPUT_REG_EN "TRUE" -.param OUTPUT_REG_EN "TRUE" -.subckt I_BUF EN=$undef I=A[0] O=a_out[0] -.subckt I_BUF EN=ibuf2_en[0] I=B[0] O=b_out[0] -.subckt I_BUF EN=ibuf3_en[0] I=SHIFT_RIGHT[0] O=i_buf_shift_right[0] -.subckt I_BUF EN=$undef I=A[10] O=a_out[10] -.subckt I_BUF EN=ibuf2_en[10] I=B[10] O=b_out[10] -.subckt I_BUF EN=$undef I=A[11] O=a_out[11] -.subckt I_BUF EN=ibuf2_en[11] I=B[11] O=b_out[11] -.subckt I_BUF EN=$undef I=A[12] O=a_out[12] -.subckt I_BUF EN=ibuf2_en[12] I=B[12] O=b_out[12] -.subckt I_BUF EN=$undef I=A[13] O=a_out[13] -.subckt I_BUF EN=ibuf2_en[13] I=B[13] O=b_out[13] -.subckt I_BUF EN=$undef I=A[14] O=a_out[14] -.subckt I_BUF EN=ibuf2_en[14] I=B[14] O=b_out[14] -.subckt I_BUF EN=$undef I=A[15] O=a_out[15] -.subckt I_BUF EN=ibuf2_en[15] I=B[15] O=b_out[15] -.subckt I_BUF EN=$undef I=A[16] O=a_out[16] -.subckt I_BUF EN=ibuf2_en[16] I=B[16] O=b_out[16] -.subckt I_BUF EN=$undef I=A[17] O=a_out[17] -.subckt I_BUF EN=ibuf2_en[17] I=B[17] O=b_out[17] -.subckt I_BUF EN=$undef I=A[18] O=a_out[18] -.subckt I_BUF EN=$undef I=A[19] O=a_out[19] -.subckt I_BUF EN=$undef I=A[1] O=a_out[1] -.subckt I_BUF EN=ibuf2_en[1] I=B[1] O=b_out[1] -.subckt I_BUF EN=ibuf3_en[1] I=SHIFT_RIGHT[1] O=i_buf_shift_right[1] -.subckt I_BUF EN=$undef I=A[2] O=a_out[2] -.subckt I_BUF EN=ibuf2_en[2] I=B[2] O=b_out[2] -.subckt I_BUF EN=ibuf3_en[2] I=SHIFT_RIGHT[2] O=i_buf_shift_right[2] -.subckt I_BUF EN=$undef I=A[3] O=a_out[3] -.subckt I_BUF EN=ibuf2_en[3] I=B[3] O=b_out[3] -.subckt I_BUF EN=ibuf3_en[3] I=SHIFT_RIGHT[3] O=i_buf_shift_right[3] -.subckt I_BUF EN=$undef I=A[4] O=a_out[4] -.subckt I_BUF EN=ibuf2_en[4] I=B[4] O=b_out[4] -.subckt I_BUF EN=ibuf3_en[4] I=SHIFT_RIGHT[4] O=i_buf_shift_right[4] -.subckt I_BUF EN=$undef I=A[5] O=a_out[5] -.subckt I_BUF EN=ibuf2_en[5] I=B[5] O=b_out[5] -.subckt I_BUF EN=ibuf3_en[5] I=SHIFT_RIGHT[5] O=i_buf_shift_right[5] -.subckt I_BUF EN=$undef I=A[6] O=a_out[6] -.subckt I_BUF EN=ibuf2_en[6] I=B[6] O=b_out[6] -.subckt I_BUF EN=$undef I=A[7] O=a_out[7] -.subckt I_BUF EN=ibuf2_en[7] I=B[7] O=b_out[7] -.subckt I_BUF EN=$undef I=A[8] O=a_out[8] -.subckt I_BUF EN=ibuf2_en[8] I=B[8] O=b_out[8] -.subckt I_BUF EN=$undef I=A[9] O=a_out[9] -.subckt I_BUF EN=ibuf2_en[9] I=B[9] O=b_out[9] -.subckt O_BUF I=o_buf_dly_b[0] O=DLY_B[0] -.subckt O_BUF I=o_buf_dly_b[10] O=DLY_B[10] -.subckt O_BUF I=o_buf_dly_b[11] O=DLY_B[11] -.subckt O_BUF I=o_buf_dly_b[12] O=DLY_B[12] -.subckt O_BUF I=o_buf_dly_b[13] O=DLY_B[13] -.subckt O_BUF I=o_buf_dly_b[14] O=DLY_B[14] -.subckt O_BUF I=o_buf_dly_b[15] O=DLY_B[15] -.subckt O_BUF I=o_buf_dly_b[16] O=DLY_B[16] -.subckt O_BUF I=o_buf_dly_b[17] O=DLY_B[17] -.subckt O_BUF I=o_buf_dly_b[1] O=DLY_B[1] -.subckt O_BUF I=o_buf_dly_b[2] O=DLY_B[2] -.subckt O_BUF I=o_buf_dly_b[3] O=DLY_B[3] -.subckt O_BUF I=o_buf_dly_b[4] O=DLY_B[4] -.subckt O_BUF I=o_buf_dly_b[5] O=DLY_B[5] -.subckt O_BUF I=o_buf_dly_b[6] O=DLY_B[6] -.subckt O_BUF I=o_buf_dly_b[7] O=DLY_B[7] -.subckt O_BUF I=o_buf_dly_b[8] O=DLY_B[8] -.subckt O_BUF I=o_buf_dly_b[9] O=DLY_B[9] -.subckt O_BUFT I=z_out[0] O=Z[0] T=i_buft_oe_in -.subckt O_BUFT I=z_out[10] O=Z[10] T=$undef -.subckt O_BUFT I=z_out[11] O=Z[11] T=$undef -.subckt O_BUFT I=z_out[12] O=Z[12] T=$undef -.subckt O_BUFT I=z_out[13] O=Z[13] T=$undef -.subckt O_BUFT I=z_out[14] O=Z[14] T=$undef -.subckt O_BUFT I=z_out[15] O=Z[15] T=$undef -.subckt O_BUFT I=z_out[16] O=Z[16] T=$undef -.subckt O_BUFT I=z_out[17] O=Z[17] T=$undef -.subckt O_BUFT I=z_out[18] O=Z[18] T=$undef -.subckt O_BUFT I=z_out[19] O=Z[19] T=$undef -.subckt O_BUFT I=z_out[1] O=Z[1] T=$undef -.subckt O_BUFT I=z_out[20] O=Z[20] T=$undef -.subckt O_BUFT I=z_out[21] O=Z[21] T=$undef -.subckt O_BUFT I=z_out[22] O=Z[22] T=$undef -.subckt O_BUFT I=z_out[23] O=Z[23] T=$undef -.subckt O_BUFT I=z_out[24] O=Z[24] T=$undef -.subckt O_BUFT I=z_out[25] O=Z[25] T=$undef -.subckt O_BUFT I=z_out[26] O=Z[26] T=$undef -.subckt O_BUFT I=z_out[27] O=Z[27] T=$undef -.subckt O_BUFT I=z_out[28] O=Z[28] T=$undef -.subckt O_BUFT I=z_out[29] O=Z[29] T=$undef -.subckt O_BUFT I=z_out[2] O=Z[2] T=$undef -.subckt O_BUFT I=z_out[30] O=Z[30] T=$undef -.subckt O_BUFT I=z_out[31] O=Z[31] T=$undef -.subckt O_BUFT I=z_out[32] O=Z[32] T=$undef -.subckt O_BUFT I=z_out[33] O=Z[33] T=$undef -.subckt O_BUFT I=z_out[34] O=Z[34] T=$undef -.subckt O_BUFT I=z_out[35] O=Z[35] T=$undef -.subckt O_BUFT I=z_out[36] O=Z[36] T=$undef -.subckt O_BUFT I=z_out[3] O=Z[3] T=$undef -.subckt O_BUFT I=z_out[4] O=Z[4] T=$undef -.subckt O_BUFT I=z_out[5] O=Z[5] T=$undef -.subckt O_BUFT I=z_out[6] O=Z[6] T=$undef -.subckt O_BUFT I=z_out[7] O=Z[7] T=$undef -.subckt O_BUFT I=z_out[8] O=Z[8] T=$undef -.subckt O_BUFT I=z_out[9] O=Z[9] T=$undef -.subckt I_BUF EN=ibuf4_en[8] I=RESET O=i_buf_reset -.subckt I_BUF EN=ibuf4_en[9] I=FEEDBACK[0] O=i_buf_feedback[0] -.subckt I_BUF EN=ibuf4_en[10] I=FEEDBACK[1] O=i_buf_feedback[1] -.subckt I_BUF EN=ibuf4_en[11] I=FEEDBACK[2] O=i_buf_feedback[2] -.subckt I_BUF EN=ibuf4_en[12] I=LOAD_ACC O=i_buf_load_acc -.subckt I_BUF EN=ibuf4_en[13] I=SATURATE O=i_buf_saturate -.subckt I_BUF EN=ibuf4_en[14] I=ROUND O=i_buf_round -.subckt I_BUF EN=ibuf4_en[15] I=SUBTRACT O=i_buf_subtract -.subckt I_BUF EN=ibuf4_en[16] I=UNSIGNED_A O=i_buf_unsigned_a -.subckt I_BUF EN=ibuf4_en[17] I=UNSIGNED_B O=i_buf_unsigned_b -.subckt I_BUF EN=ibuf4_en[0] I=CLK O=i_buf_clk -.subckt I_BUF EN=ibuf4_en[1] I=i_buft_oe[0] O=i_buft_oe_in -.subckt I_BUF EN=ibuf4_en[2] I=ACC_FIR[0] O=i_buf_ACC_FIR[0] -.subckt I_BUF EN=ibuf4_en[3] I=ACC_FIR[1] O=i_buf_ACC_FIR[1] -.subckt I_BUF EN=ibuf4_en[4] I=ACC_FIR[2] O=i_buf_ACC_FIR[2] -.subckt I_BUF EN=ibuf4_en[5] I=ACC_FIR[3] O=i_buf_ACC_FIR[3] -.subckt I_BUF EN=ibuf4_en[6] I=ACC_FIR[4] O=i_buf_ACC_FIR[4] -.subckt I_BUF EN=ibuf4_en[7] I=ACC_FIR[5] O=i_buf_ACC_FIR[5] -.names $undef Z[37] -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_3/synthesis/primitive_example_design_3_post_synth.v b/design_edit/Tests/primitive_example_design_3/synthesis/primitive_example_design_3_post_synth.v deleted file mode 100644 index 552c3e316..000000000 --- a/design_edit/Tests/primitive_example_design_3/synthesis/primitive_example_design_3_post_synth.v +++ /dev/null @@ -1,945 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module primitive_example_design_3(A, B, i_buft_oe, ACC_FIR, Z, DLY_B, CLK, RESET, FEEDBACK, LOAD_ACC, SATURATE, SHIFT_RIGHT, ROUND, SUBTRACT, UNSIGNED_A, UNSIGNED_B, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en); - input [19:0] A; - input [5:0] ACC_FIR; - input [17:0] B; - input CLK; - output [17:0] DLY_B; - input [2:0] FEEDBACK; - input LOAD_ACC; - input RESET; - input ROUND; - input SATURATE; - input [5:0] SHIFT_RIGHT; - input SUBTRACT; - input UNSIGNED_A; - input UNSIGNED_B; - output [37:0] Z; - input [37:0] i_buft_oe; - input [19:0] ibuf1_en; - input [17:0] ibuf2_en; - input [5:0] ibuf3_en; - input [17:0] ibuf4_en; - (* src = "./rtl/primitive_example_design_3.v:2.18-2.19" *) - (* src = "./rtl/primitive_example_design_3.v:2.18-2.19" *) - wire [19:0] A; - (* src = "./rtl/primitive_example_design_3.v:5.17-5.24" *) - (* src = "./rtl/primitive_example_design_3.v:5.17-5.24" *) - wire [5:0] ACC_FIR; - (* src = "./rtl/primitive_example_design_3.v:3.18-3.19" *) - (* src = "./rtl/primitive_example_design_3.v:3.18-3.19" *) - wire [17:0] B; - (* src = "./rtl/primitive_example_design_3.v:8.11-8.14" *) - (* src = "./rtl/primitive_example_design_3.v:8.11-8.14" *) - wire CLK; - (* src = "./rtl/primitive_example_design_3.v:7.23-7.28" *) - (* src = "./rtl/primitive_example_design_3.v:7.23-7.28" *) - wire [17:0] DLY_B; - (* src = "./rtl/primitive_example_design_3.v:10.17-10.25" *) - (* src = "./rtl/primitive_example_design_3.v:10.17-10.25" *) - wire [2:0] FEEDBACK; - (* src = "./rtl/primitive_example_design_3.v:11.11-11.19" *) - (* src = "./rtl/primitive_example_design_3.v:11.11-11.19" *) - wire LOAD_ACC; - (* src = "./rtl/primitive_example_design_3.v:9.11-9.16" *) - (* src = "./rtl/primitive_example_design_3.v:9.11-9.16" *) - wire RESET; - (* src = "./rtl/primitive_example_design_3.v:14.11-14.16" *) - (* src = "./rtl/primitive_example_design_3.v:14.11-14.16" *) - wire ROUND; - (* src = "./rtl/primitive_example_design_3.v:12.11-12.19" *) - (* src = "./rtl/primitive_example_design_3.v:12.11-12.19" *) - wire SATURATE; - (* src = "./rtl/primitive_example_design_3.v:13.17-13.28" *) - (* src = "./rtl/primitive_example_design_3.v:13.17-13.28" *) - wire [5:0] SHIFT_RIGHT; - (* src = "./rtl/primitive_example_design_3.v:15.11-15.19" *) - (* src = "./rtl/primitive_example_design_3.v:15.11-15.19" *) - wire SUBTRACT; - (* src = "./rtl/primitive_example_design_3.v:16.11-16.21" *) - (* src = "./rtl/primitive_example_design_3.v:16.11-16.21" *) - wire UNSIGNED_A; - (* src = "./rtl/primitive_example_design_3.v:17.11-17.21" *) - (* src = "./rtl/primitive_example_design_3.v:17.11-17.21" *) - wire UNSIGNED_B; - (* src = "./rtl/primitive_example_design_3.v:6.19-6.20" *) - (* src = "./rtl/primitive_example_design_3.v:6.19-6.20" *) - wire [37:0] Z; - (* src = "./rtl/primitive_example_design_3.v:25.15-25.20" *) - wire [19:0] a_out; - (* src = "./rtl/primitive_example_design_3.v:26.15-26.20" *) - wire [17:0] b_out; - (* src = "./rtl/primitive_example_design_3.v:28.14-28.27" *) - wire [5:0] i_buf_ACC_FIR; - (* src = "./rtl/primitive_example_design_3.v:27.63-27.72" *) - wire i_buf_clk; - (* src = "./rtl/primitive_example_design_3.v:30.14-30.28" *) - wire [2:0] i_buf_feedback; - (* src = "./rtl/primitive_example_design_3.v:27.33-27.47" *) - wire i_buf_load_acc; - (* src = "./rtl/primitive_example_design_3.v:27.21-27.32" *) - wire i_buf_reset; - (* src = "./rtl/primitive_example_design_3.v:32.8-32.19" *) - wire i_buf_round; - (* src = "./rtl/primitive_example_design_3.v:27.48-27.62" *) - wire i_buf_saturate; - (* src = "./rtl/primitive_example_design_3.v:31.14-31.31" *) - wire [5:0] i_buf_shift_right; - (* src = "./rtl/primitive_example_design_3.v:32.20-32.34" *) - wire i_buf_subtract; - (* src = "./rtl/primitive_example_design_3.v:32.35-32.51" *) - wire i_buf_unsigned_a; - (* src = "./rtl/primitive_example_design_3.v:32.52-32.68" *) - wire i_buf_unsigned_b; - (* src = "./rtl/primitive_example_design_3.v:4.18-4.27" *) - (* src = "./rtl/primitive_example_design_3.v:4.18-4.27" *) - wire [37:0] i_buft_oe; - (* src = "./rtl/primitive_example_design_3.v:27.8-27.20" *) - wire i_buft_oe_in; - (* src = "./rtl/primitive_example_design_3.v:18.18-18.26" *) - (* src = "./rtl/primitive_example_design_3.v:18.18-18.26" *) - wire [19:0] ibuf1_en; - (* src = "./rtl/primitive_example_design_3.v:19.18-19.26" *) - (* src = "./rtl/primitive_example_design_3.v:19.18-19.26" *) - wire [17:0] ibuf2_en; - (* src = "./rtl/primitive_example_design_3.v:20.17-20.25" *) - (* src = "./rtl/primitive_example_design_3.v:20.17-20.25" *) - wire [5:0] ibuf3_en; - (* src = "./rtl/primitive_example_design_3.v:21.18-21.26" *) - (* src = "./rtl/primitive_example_design_3.v:21.18-21.26" *) - wire [17:0] ibuf4_en; - wire [17:0] o_buf_dly_b; - (* src = "./rtl/primitive_example_design_3.v:24.15-24.20" *) - (* unused_bits = "37" *) - wire [37:0] z_out; - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:97.6-111.17" *) - DSP38 #( - .COEFF_0(20'h00000), - .COEFF_1(20'h00000), - .COEFF_2(20'h00000), - .COEFF_3(20'h00000), - .DSP_MODE("MULTIPLY_ACCUMULATE"), - .INPUT_REG_EN("TRUE"), - .OUTPUT_REG_EN("TRUE") - ) dsp38_inst ( - .A(a_out), - .ACC_FIR(i_buf_ACC_FIR), - .B(b_out), - .CLK(i_buf_clk), - .DLY_B(o_buf_dly_b), - .FEEDBACK(i_buf_feedback), - .LOAD_ACC(i_buf_load_acc), - .RESET(i_buf_reset), - .ROUND(i_buf_round), - .SATURATE(i_buf_saturate), - .SHIFT_RIGHT(i_buf_shift_right), - .SUBTRACT(i_buf_subtract), - .UNSIGNED_A(i_buf_unsigned_a), - .UNSIGNED_B(i_buf_unsigned_b), - .Z(z_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[0].i_buf_instance ( - .EN(1'hx), - .I(A[0]), - .O(a_out[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[0].i_buf_instance_b ( - .EN(ibuf2_en[0]), - .I(B[0]), - .O(b_out[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \gen_i_buf[0].i_buf_instance_shift ( - .EN(ibuf3_en[0]), - .I(SHIFT_RIGHT[0]), - .O(i_buf_shift_right[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[10].i_buf_instance ( - .EN(1'hx), - .I(A[10]), - .O(a_out[10]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[10].i_buf_instance_b ( - .EN(ibuf2_en[10]), - .I(B[10]), - .O(b_out[10]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[11].i_buf_instance ( - .EN(1'hx), - .I(A[11]), - .O(a_out[11]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[11].i_buf_instance_b ( - .EN(ibuf2_en[11]), - .I(B[11]), - .O(b_out[11]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[12].i_buf_instance ( - .EN(1'hx), - .I(A[12]), - .O(a_out[12]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[12].i_buf_instance_b ( - .EN(ibuf2_en[12]), - .I(B[12]), - .O(b_out[12]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[13].i_buf_instance ( - .EN(1'hx), - .I(A[13]), - .O(a_out[13]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[13].i_buf_instance_b ( - .EN(ibuf2_en[13]), - .I(B[13]), - .O(b_out[13]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[14].i_buf_instance ( - .EN(1'hx), - .I(A[14]), - .O(a_out[14]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[14].i_buf_instance_b ( - .EN(ibuf2_en[14]), - .I(B[14]), - .O(b_out[14]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[15].i_buf_instance ( - .EN(1'hx), - .I(A[15]), - .O(a_out[15]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[15].i_buf_instance_b ( - .EN(ibuf2_en[15]), - .I(B[15]), - .O(b_out[15]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[16].i_buf_instance ( - .EN(1'hx), - .I(A[16]), - .O(a_out[16]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[16].i_buf_instance_b ( - .EN(ibuf2_en[16]), - .I(B[16]), - .O(b_out[16]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[17].i_buf_instance ( - .EN(1'hx), - .I(A[17]), - .O(a_out[17]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[17].i_buf_instance_b ( - .EN(ibuf2_en[17]), - .I(B[17]), - .O(b_out[17]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[18].i_buf_instance ( - .EN(1'hx), - .I(A[18]), - .O(a_out[18]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[19].i_buf_instance ( - .EN(1'hx), - .I(A[19]), - .O(a_out[19]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[1].i_buf_instance ( - .EN(1'hx), - .I(A[1]), - .O(a_out[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[1].i_buf_instance_b ( - .EN(ibuf2_en[1]), - .I(B[1]), - .O(b_out[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \gen_i_buf[1].i_buf_instance_shift ( - .EN(ibuf3_en[1]), - .I(SHIFT_RIGHT[1]), - .O(i_buf_shift_right[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[2].i_buf_instance ( - .EN(1'hx), - .I(A[2]), - .O(a_out[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[2].i_buf_instance_b ( - .EN(ibuf2_en[2]), - .I(B[2]), - .O(b_out[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \gen_i_buf[2].i_buf_instance_shift ( - .EN(ibuf3_en[2]), - .I(SHIFT_RIGHT[2]), - .O(i_buf_shift_right[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[3].i_buf_instance ( - .EN(1'hx), - .I(A[3]), - .O(a_out[3]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[3].i_buf_instance_b ( - .EN(ibuf2_en[3]), - .I(B[3]), - .O(b_out[3]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \gen_i_buf[3].i_buf_instance_shift ( - .EN(ibuf3_en[3]), - .I(SHIFT_RIGHT[3]), - .O(i_buf_shift_right[3]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[4].i_buf_instance ( - .EN(1'hx), - .I(A[4]), - .O(a_out[4]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[4].i_buf_instance_b ( - .EN(ibuf2_en[4]), - .I(B[4]), - .O(b_out[4]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \gen_i_buf[4].i_buf_instance_shift ( - .EN(ibuf3_en[4]), - .I(SHIFT_RIGHT[4]), - .O(i_buf_shift_right[4]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[5].i_buf_instance ( - .EN(1'hx), - .I(A[5]), - .O(a_out[5]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[5].i_buf_instance_b ( - .EN(ibuf2_en[5]), - .I(B[5]), - .O(b_out[5]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:51.13-51.96" *) - I_BUF \gen_i_buf[5].i_buf_instance_shift ( - .EN(ibuf3_en[5]), - .I(SHIFT_RIGHT[5]), - .O(i_buf_shift_right[5]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[6].i_buf_instance ( - .EN(1'hx), - .I(A[6]), - .O(a_out[6]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[6].i_buf_instance_b ( - .EN(ibuf2_en[6]), - .I(B[6]), - .O(b_out[6]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[7].i_buf_instance ( - .EN(1'hx), - .I(A[7]), - .O(a_out[7]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[7].i_buf_instance_b ( - .EN(ibuf2_en[7]), - .I(B[7]), - .O(b_out[7]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[8].i_buf_instance ( - .EN(1'hx), - .I(A[8]), - .O(a_out[8]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[8].i_buf_instance_b ( - .EN(ibuf2_en[8]), - .I(B[8]), - .O(b_out[8]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:37.13-37.67" *) - I_BUF \gen_i_buf[9].i_buf_instance ( - .EN(1'hx), - .I(A[9]), - .O(a_out[9]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:44.13-44.70" *) - I_BUF \gen_i_buf[9].i_buf_instance_b ( - .EN(ibuf2_en[9]), - .I(B[9]), - .O(b_out[9]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[0].o_buf_instance_a ( - .I(o_buf_dly_b[0]), - .O(DLY_B[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[10].o_buf_instance_a ( - .I(o_buf_dly_b[10]), - .O(DLY_B[10]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[11].o_buf_instance_a ( - .I(o_buf_dly_b[11]), - .O(DLY_B[11]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[12].o_buf_instance_a ( - .I(o_buf_dly_b[12]), - .O(DLY_B[12]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[13].o_buf_instance_a ( - .I(o_buf_dly_b[13]), - .O(DLY_B[13]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[14].o_buf_instance_a ( - .I(o_buf_dly_b[14]), - .O(DLY_B[14]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[15].o_buf_instance_a ( - .I(o_buf_dly_b[15]), - .O(DLY_B[15]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[16].o_buf_instance_a ( - .I(o_buf_dly_b[16]), - .O(DLY_B[16]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[17].o_buf_instance_a ( - .I(o_buf_dly_b[17]), - .O(DLY_B[17]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[1].o_buf_instance_a ( - .I(o_buf_dly_b[1]), - .O(DLY_B[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[2].o_buf_instance_a ( - .I(o_buf_dly_b[2]), - .O(DLY_B[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[3].o_buf_instance_a ( - .I(o_buf_dly_b[3]), - .O(DLY_B[3]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[4].o_buf_instance_a ( - .I(o_buf_dly_b[4]), - .O(DLY_B[4]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[5].o_buf_instance_a ( - .I(o_buf_dly_b[5]), - .O(DLY_B[5]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[6].o_buf_instance_a ( - .I(o_buf_dly_b[6]), - .O(DLY_B[6]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[7].o_buf_instance_a ( - .I(o_buf_dly_b[7]), - .O(DLY_B[7]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[8].o_buf_instance_a ( - .I(o_buf_dly_b[8]), - .O(DLY_B[8]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:85.13-85.63" *) - O_BUF \gen_o_buf[9].o_buf_instance_a ( - .I(o_buf_dly_b[9]), - .O(DLY_B[9]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[0].o_buft_inst ( - .I(z_out[0]), - .O(Z[0]), - .T(i_buft_oe_in) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[10].o_buft_inst ( - .I(z_out[10]), - .O(Z[10]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[11].o_buft_inst ( - .I(z_out[11]), - .O(Z[11]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[12].o_buft_inst ( - .I(z_out[12]), - .O(Z[12]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[13].o_buft_inst ( - .I(z_out[13]), - .O(Z[13]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[14].o_buft_inst ( - .I(z_out[14]), - .O(Z[14]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[15].o_buft_inst ( - .I(z_out[15]), - .O(Z[15]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[16].o_buft_inst ( - .I(z_out[16]), - .O(Z[16]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[17].o_buft_inst ( - .I(z_out[17]), - .O(Z[17]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[18].o_buft_inst ( - .I(z_out[18]), - .O(Z[18]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[19].o_buft_inst ( - .I(z_out[19]), - .O(Z[19]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[1].o_buft_inst ( - .I(z_out[1]), - .O(Z[1]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[20].o_buft_inst ( - .I(z_out[20]), - .O(Z[20]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[21].o_buft_inst ( - .I(z_out[21]), - .O(Z[21]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[22].o_buft_inst ( - .I(z_out[22]), - .O(Z[22]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[23].o_buft_inst ( - .I(z_out[23]), - .O(Z[23]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[24].o_buft_inst ( - .I(z_out[24]), - .O(Z[24]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[25].o_buft_inst ( - .I(z_out[25]), - .O(Z[25]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[26].o_buft_inst ( - .I(z_out[26]), - .O(Z[26]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[27].o_buft_inst ( - .I(z_out[27]), - .O(Z[27]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[28].o_buft_inst ( - .I(z_out[28]), - .O(Z[28]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[29].o_buft_inst ( - .I(z_out[29]), - .O(Z[29]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[2].o_buft_inst ( - .I(z_out[2]), - .O(Z[2]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[30].o_buft_inst ( - .I(z_out[30]), - .O(Z[30]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[31].o_buft_inst ( - .I(z_out[31]), - .O(Z[31]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[32].o_buft_inst ( - .I(z_out[32]), - .O(Z[32]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[33].o_buft_inst ( - .I(z_out[33]), - .O(Z[33]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[34].o_buft_inst ( - .I(z_out[34]), - .O(Z[34]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[35].o_buft_inst ( - .I(z_out[35]), - .O(Z[35]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[36].o_buft_inst ( - .I(z_out[36]), - .O(Z[36]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[3].o_buft_inst ( - .I(z_out[3]), - .O(Z[3]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[4].o_buft_inst ( - .I(z_out[4]), - .O(Z[4]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[5].o_buft_inst ( - .I(z_out[5]), - .O(Z[5]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[6].o_buft_inst ( - .I(z_out[6]), - .O(Z[6]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[7].o_buft_inst ( - .I(z_out[7]), - .O(Z[7]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[8].o_buft_inst ( - .I(z_out[8]), - .O(Z[8]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:78.16-78.71" *) - O_BUFT \gen_o_buft[9].o_buft_inst ( - .I(z_out[9]), - .O(Z[9]), - .T(1'hx) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:63.9-63.70" *) - I_BUF i_buf_instance10 ( - .EN(ibuf4_en[8]), - .I(RESET), - .O(i_buf_reset) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:64.9-64.82" *) - I_BUF i_buf_instance11 ( - .EN(ibuf4_en[9]), - .I(FEEDBACK[0]), - .O(i_buf_feedback[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:65.9-65.83" *) - I_BUF i_buf_instance12 ( - .EN(ibuf4_en[10]), - .I(FEEDBACK[1]), - .O(i_buf_feedback[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:66.9-66.83" *) - I_BUF i_buf_instance13 ( - .EN(ibuf4_en[11]), - .I(FEEDBACK[2]), - .O(i_buf_feedback[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:67.9-67.77" *) - I_BUF i_buf_instance14 ( - .EN(ibuf4_en[12]), - .I(LOAD_ACC), - .O(i_buf_load_acc) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:68.9-68.77" *) - I_BUF i_buf_instance15 ( - .EN(ibuf4_en[13]), - .I(SATURATE), - .O(i_buf_saturate) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:69.9-69.71" *) - I_BUF i_buf_instance16 ( - .EN(ibuf4_en[14]), - .I(ROUND), - .O(i_buf_round) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:70.9-70.77" *) - I_BUF i_buf_instance17 ( - .EN(ibuf4_en[15]), - .I(SUBTRACT), - .O(i_buf_subtract) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:71.9-71.81" *) - I_BUF i_buf_instance18 ( - .EN(ibuf4_en[16]), - .I(UNSIGNED_A), - .O(i_buf_unsigned_a) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:72.9-72.81" *) - I_BUF i_buf_instance19 ( - .EN(ibuf4_en[17]), - .I(UNSIGNED_B), - .O(i_buf_unsigned_b) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:55.9-55.65" *) - I_BUF i_buf_instance2 ( - .EN(ibuf4_en[0]), - .I(CLK), - .O(i_buf_clk) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:56.9-56.74" *) - I_BUF i_buf_instance3 ( - .EN(ibuf4_en[1]), - .I(i_buft_oe[0]), - .O(i_buft_oe_in) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:57.9-57.79" *) - I_BUF i_buf_instance4 ( - .EN(ibuf4_en[2]), - .I(ACC_FIR[0]), - .O(i_buf_ACC_FIR[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:58.9-58.79" *) - I_BUF i_buf_instance5 ( - .EN(ibuf4_en[3]), - .I(ACC_FIR[1]), - .O(i_buf_ACC_FIR[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:59.9-59.79" *) - I_BUF i_buf_instance6 ( - .EN(ibuf4_en[4]), - .I(ACC_FIR[2]), - .O(i_buf_ACC_FIR[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:60.9-60.79" *) - I_BUF i_buf_instance7 ( - .EN(ibuf4_en[5]), - .I(ACC_FIR[3]), - .O(i_buf_ACC_FIR[3]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:61.9-61.79" *) - I_BUF i_buf_instance8 ( - .EN(ibuf4_en[6]), - .I(ACC_FIR[4]), - .O(i_buf_ACC_FIR[4]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_3.v:62.9-62.79" *) - I_BUF i_buf_instance9 ( - .EN(ibuf4_en[7]), - .I(ACC_FIR[5]), - .O(i_buf_ACC_FIR[5]) - ); - assign Z[37] = 1'hx; -endmodule diff --git a/design_edit/Tests/primitive_example_design_4/gold/interface.json b/design_edit/Tests/primitive_example_design_4/gold/interface.json deleted file mode 100644 index d9377c6f3..000000000 --- a/design_edit/Tests/primitive_example_design_4/gold/interface.json +++ /dev/null @@ -1,228 +0,0 @@ -{ - "IO_Instances": { - "clk_buf_inst": { - "module": "CLK_BUF", - "ports": { - "I": [ - { - "Actual": "clk", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "clk_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst1": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf2_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst2": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf3_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ] - } - }, - "ibuf_inst3": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf4_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ] - } - }, - "ibuf_inst4": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf5_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "rst", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "rst_i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "obuf_ds_inst1": { - "module": "O_BUF_DS", - "ports": { - "I": [ - { - "Actual": "dffre_out", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_N": [ - { - "Actual": "q_n", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_P": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "obuf_ds_inst2": { - "module": "O_BUF_DS", - "ports": { - "I": [ - { - "Actual": "dffre_out", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O_N": [ - { - "Actual": "q_n", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O_P": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ] - } - }, - "obuf_ds_inst3": { - "module": "O_BUF_DS", - "ports": { - "I": [ - { - "Actual": "dffre_out", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O_N": [ - { - "Actual": "q_n", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O_P": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ] - } - } - } -} diff --git a/design_edit/Tests/primitive_example_design_4/gold/io_config.json b/design_edit/Tests/primitive_example_design_4/gold/io_config.json deleted file mode 100644 index c940a0cb3..000000000 --- a/design_edit/Tests/primitive_example_design_4/gold/io_config.json +++ /dev/null @@ -1,379 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\clk (index=0, width=1, offset=0)", - " Detect input port \\ibuf1_en (index=0, width=1, offset=0)", - " Detect input port \\ibuf2_en (index=0, width=1, offset=0)", - " Detect input port \\ibuf3_en (index=0, width=1, offset=0)", - " Detect input port \\ibuf4_en (index=0, width=1, offset=0)", - " Detect input port \\ibuf5_en (index=0, width=1, offset=0)", - " Detect input port \\in (index=0, width=3, offset=0)", - " Detect input port \\in (index=1, width=3, offset=0)", - " Detect input port \\in (index=2, width=3, offset=0)", - " Detect output port \\q_n (index=0, width=3, offset=0)", - " Detect output port \\q_n (index=1, width=3, offset=0)", - " Detect output port \\q_n (index=2, width=3, offset=0)", - " Detect output port \\q_p (index=0, width=3, offset=0)", - " Detect output port \\q_p (index=1, width=3, offset=0)", - " Detect output port \\q_p (index=2, width=3, offset=0)", - " Detect input port \\rst (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_4.clk", - " Cell port \\I is connected to input port \\clk", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_4.ibuf1_en", - " Cell port \\I is connected to input port \\ibuf1_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_4.ibuf2_en", - " Cell port \\I is connected to input port \\ibuf2_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_4.ibuf3_en", - " Cell port \\I is connected to input port \\ibuf3_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_4.ibuf4_en", - " Cell port \\I is connected to input port \\ibuf4_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_4.ibuf5_en", - " Cell port \\I is connected to input port \\ibuf5_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_4.q_n", - " Cell port \\O is connected to output port \\q_n[0]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_4.q_n_1", - " Cell port \\O is connected to output port \\q_n[1]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_4.q_n_2", - " Cell port \\O is connected to output port \\q_n[2]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_4.q_p", - " Cell port \\O is connected to output port \\q_p[0]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_4.q_p_1", - " Cell port \\O is connected to output port \\q_p[1]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_4.q_p_2", - " Cell port \\O is connected to output port \\q_p[2]", - " Get important connection of cell \\I_BUF \\ibuf_inst1", - " Cell port \\I is connected to input port \\in[0]", - " Get important connection of cell \\I_BUF \\ibuf_inst2", - " Cell port \\I is connected to input port \\in[1]", - " Get important connection of cell \\I_BUF \\ibuf_inst3", - " Cell port \\I is connected to input port \\in[2]", - " Get important connection of cell \\I_BUF \\ibuf_inst4", - " Cell port \\I is connected to input port \\rst", - " Trace Clock Buffer", - " Try \\I_BUF $iopadmap$primitive_example_design_4.clk out connection: $iopadmap$clk", - " Connected \\clk_buf_inst", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_4.clk", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "clk", - "O" : "$iopadmap$clk" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "CLK_BUF", - "name" : "clk_buf_inst", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk", - "O" : "clk_buf_out" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_4.ibuf1_en", - "linked_object" : "ibuf1_en", - "linked_objects" : { - "ibuf1_en" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf1_en", - "O" : "$iopadmap$ibuf1_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_4.ibuf2_en", - "linked_object" : "ibuf2_en", - "linked_objects" : { - "ibuf2_en" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf2_en", - "O" : "$iopadmap$ibuf2_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_4.ibuf3_en", - "linked_object" : "ibuf3_en", - "linked_objects" : { - "ibuf3_en" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf3_en", - "O" : "$iopadmap$ibuf3_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_4.ibuf4_en", - "linked_object" : "ibuf4_en", - "linked_objects" : { - "ibuf4_en" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf4_en", - "O" : "$iopadmap$ibuf4_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_4.ibuf5_en", - "linked_object" : "ibuf5_en", - "linked_objects" : { - "ibuf5_en" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf5_en", - "O" : "$iopadmap$ibuf5_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_4.q_n", - "linked_object" : "q_n[0]", - "linked_objects" : { - "q_n[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_n[0]", - "O" : "q_n[0]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_4.q_n_1", - "linked_object" : "q_n[1]", - "linked_objects" : { - "q_n[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_n[1]", - "O" : "q_n[1]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_4.q_n_2", - "linked_object" : "q_n[2]", - "linked_objects" : { - "q_n[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_n[2]", - "O" : "q_n[2]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_4.q_p", - "linked_object" : "q_p[0]", - "linked_objects" : { - "q_p[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_p[0]", - "O" : "q_p[0]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_4.q_p_1", - "linked_object" : "q_p[1]", - "linked_objects" : { - "q_p[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_p[1]", - "O" : "q_p[1]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_4.q_p_2", - "linked_object" : "q_p[2]", - "linked_objects" : { - "q_p[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_p[2]", - "O" : "q_p[2]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst1", - "linked_object" : "in[0]", - "linked_objects" : { - "in[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "in[0]", - "O" : "i_buf_out[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst2", - "linked_object" : "in[1]", - "linked_objects" : { - "in[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "in[1]", - "O" : "i_buf_out[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst3", - "linked_object" : "in[2]", - "linked_objects" : { - "in[2]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "in[2]", - "O" : "i_buf_out[2]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst4", - "linked_object" : "rst", - "linked_objects" : { - "rst" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "rst", - "O" : "rst_i_buf_out" - }, - "parameters" : { - } - } - ] -} diff --git a/design_edit/Tests/primitive_example_design_4/gold/primitive_example_design_4_post_synth.eblif b/design_edit/Tests/primitive_example_design_4/gold/primitive_example_design_4_post_synth.eblif deleted file mode 100644 index a1d31072d..000000000 --- a/design_edit/Tests/primitive_example_design_4/gold/primitive_example_design_4_post_synth.eblif +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_primitive_example_design_4 -.inputs i_buf_out[0] i_buf_out[1] i_buf_out[2] rst_i_buf_out clk_buf_out $iopadmap$ibuf1_en -.outputs dffre_out[0] dffre_out[1] dffre_out[2] -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=clk_buf_out D=i_buf_out[0] E=$true Q=dffre_out[0] R=rst_i_buf_out -.subckt DFFRE C=clk_buf_out D=i_buf_out[1] E=$true Q=dffre_out[1] R=rst_i_buf_out -.subckt DFFRE C=clk_buf_out D=i_buf_out[2] E=$true Q=dffre_out[2] R=rst_i_buf_out -.end diff --git a/design_edit/Tests/primitive_example_design_4/gold/primitive_example_design_4_post_synth.v b/design_edit/Tests/primitive_example_design_4/gold/primitive_example_design_4_post_synth.v deleted file mode 100644 index 0fd7ea0e9..000000000 --- a/design_edit/Tests/primitive_example_design_4/gold/primitive_example_design_4_post_synth.v +++ /dev/null @@ -1,121 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_primitive_example_design_4(i_buf_out, rst_i_buf_out, dffre_out, clk_buf_out, \$iopadmap$ibuf1_en ); - input clk_buf_out; - output [2:0] dffre_out; - input [2:0] i_buf_out; - input \$iopadmap$ibuf1_en ; - input rst_i_buf_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap399$iopadmap$primitive_example_design_4.q_p_2.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap399$iopadmap$primitive_example_design_4.q_p_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap399$iopadmap$primitive_example_design_4.q_p_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap400$iopadmap$primitive_example_design_4.q_p_1.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap400$iopadmap$primitive_example_design_4.q_p_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap400$iopadmap$primitive_example_design_4.q_p_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap401$iopadmap$primitive_example_design_4.q_n_1.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap401$iopadmap$primitive_example_design_4.q_n_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap401$iopadmap$primitive_example_design_4.q_n_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap402$iopadmap$primitive_example_design_4.q_p.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap402$iopadmap$primitive_example_design_4.q_p.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap402$iopadmap$primitive_example_design_4.q_p.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap403$iopadmap$primitive_example_design_4.q_n.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap403$iopadmap$primitive_example_design_4.q_n.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap403$iopadmap$primitive_example_design_4.q_n.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap404$iopadmap$primitive_example_design_4.ibuf2_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap404$iopadmap$primitive_example_design_4.ibuf2_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap404$iopadmap$primitive_example_design_4.ibuf2_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap405$iopadmap$primitive_example_design_4.ibuf3_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap405$iopadmap$primitive_example_design_4.ibuf3_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap405$iopadmap$primitive_example_design_4.ibuf3_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap406$iopadmap$primitive_example_design_4.ibuf4_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap406$iopadmap$primitive_example_design_4.ibuf4_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap406$iopadmap$primitive_example_design_4.ibuf4_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap407$iopadmap$primitive_example_design_4.ibuf1_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap407$iopadmap$primitive_example_design_4.ibuf1_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap407$iopadmap$primitive_example_design_4.ibuf1_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap398$iopadmap$primitive_example_design_4.clk.EN ; - (* src = "./rtl/primitive_example_design_4.v:13.38-13.49" *) - (* src = "./rtl/primitive_example_design_4.v:13.38-13.49" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_4.v:11.16-11.25" *) - (* src = "./rtl/primitive_example_design_4.v:11.16-11.25" *) - wire [2:0] dffre_out; - (* src = "./rtl/primitive_example_design_4.v:9.16-9.25" *) - (* src = "./rtl/primitive_example_design_4.v:9.16-9.25" *) - wire [2:0] i_buf_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap397$iopadmap$primitive_example_design_4.ibuf5_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap397$iopadmap$primitive_example_design_4.ibuf5_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap397$iopadmap$primitive_example_design_4.ibuf5_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap396$iopadmap$primitive_example_design_4.q_n_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap396$iopadmap$primitive_example_design_4.q_n_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap396$iopadmap$primitive_example_design_4.q_n_2.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap398$iopadmap$primitive_example_design_4.clk.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap398$iopadmap$primitive_example_design_4.clk.I ; - wire \$iopadmap$ibuf1_en ; - (* src = "./rtl/primitive_example_design_4.v:10.10-10.23" *) - (* src = "./rtl/primitive_example_design_4.v:10.10-10.23" *) - wire rst_i_buf_out; - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:25.11-25.98" *) - DFFRE ff_inst2 ( - .C(clk_buf_out), - .D(i_buf_out[1]), - .E(1'h1), - .Q(dffre_out[1]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:26.11-26.98" *) - DFFRE ff_inst3 ( - .C(clk_buf_out), - .D(i_buf_out[2]), - .E(1'h1), - .Q(dffre_out[2]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:24.11-24.98" *) - DFFRE ff_inst1 ( - .C(clk_buf_out), - .D(i_buf_out[0]), - .E(1'h1), - .Q(dffre_out[0]), - .R(rst_i_buf_out) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_4/gold/wrapper_primitive_example_design_4_post_synth.eblif b/design_edit/Tests/primitive_example_design_4/gold/wrapper_primitive_example_design_4_post_synth.eblif deleted file mode 100644 index 747a98554..000000000 --- a/design_edit/Tests/primitive_example_design_4/gold/wrapper_primitive_example_design_4_post_synth.eblif +++ /dev/null @@ -1,87 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model primitive_example_design_4 -.inputs in[0] in[1] in[2] clk rst ibuf1_en ibuf2_en ibuf3_en ibuf4_en ibuf5_en -.outputs q_n[0] q_n[1] q_n[2] q_p[0] q_p[1] q_p[2] -.names $false -.names $true -1 -.names $undef -.subckt fabric_primitive_example_design_4 $iopadmap$ibuf1_en=$iopadmap$ibuf1_en clk_buf_out=clk_buf_out dffre_out[0]=dffre_out[0] dffre_out[1]=dffre_out[1] dffre_out[2]=dffre_out[2] i_buf_out[0]=i_buf_out[0] i_buf_out[1]=i_buf_out[1] i_buf_out[2]=i_buf_out[2] rst_i_buf_out=rst_i_buf_out -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$clk O=$auto$rs_design_edit.cc:682:execute$409.clk_buf_out -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf2_en I=$auto$rs_design_edit.cc:682:execute$409.in[0] O=$auto$rs_design_edit.cc:682:execute$409.i_buf_out[0] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf3_en I=$auto$rs_design_edit.cc:682:execute$409.in[1] O=$auto$rs_design_edit.cc:682:execute$409.i_buf_out[1] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf4_en I=$auto$rs_design_edit.cc:682:execute$409.in[2] O=$auto$rs_design_edit.cc:682:execute$409.i_buf_out[2] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf5_en I=$auto$rs_design_edit.cc:682:execute$409.rst O=$auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out -.subckt O_BUF_DS I=$auto$rs_design_edit.cc:682:execute$409.dffre_out[0] O_N=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n[0] O_P=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p[0] -.subckt O_BUF_DS I=$auto$rs_design_edit.cc:682:execute$409.dffre_out[1] O_N=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n[1] O_P=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p[1] -.subckt O_BUF_DS I=$auto$rs_design_edit.cc:682:execute$409.dffre_out[2] O_N=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n[2] O_P=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p[2] -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.clk O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.ibuf1_en O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf1_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.ibuf2_en O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf2_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.ibuf3_en O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf3_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.ibuf4_en O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf4_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.ibuf5_en O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf5_en -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n[0] O=$auto$rs_design_edit.cc:682:execute$409.q_n[0] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n[1] O=$auto$rs_design_edit.cc:682:execute$409.q_n[1] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n[2] O=$auto$rs_design_edit.cc:682:execute$409.q_n[2] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p[0] O=$auto$rs_design_edit.cc:682:execute$409.q_p[0] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p[1] O=$auto$rs_design_edit.cc:682:execute$409.q_p[1] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p[2] O=$auto$rs_design_edit.cc:682:execute$409.q_p[2] -.names $flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf1_en $iopadmap$ibuf1_en -1 1 -.names clk $auto$rs_design_edit.cc:682:execute$409.clk -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.clk_buf_out clk_buf_out -1 1 -.names dffre_out[0] $auto$rs_design_edit.cc:682:execute$409.dffre_out[0] -1 1 -.names dffre_out[1] $auto$rs_design_edit.cc:682:execute$409.dffre_out[1] -1 1 -.names dffre_out[2] $auto$rs_design_edit.cc:682:execute$409.dffre_out[2] -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.i_buf_out[0] i_buf_out[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.i_buf_out[1] i_buf_out[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.i_buf_out[2] i_buf_out[2] -1 1 -.names ibuf1_en $auto$rs_design_edit.cc:682:execute$409.ibuf1_en -1 1 -.names ibuf2_en $auto$rs_design_edit.cc:682:execute$409.ibuf2_en -1 1 -.names ibuf3_en $auto$rs_design_edit.cc:682:execute$409.ibuf3_en -1 1 -.names ibuf4_en $auto$rs_design_edit.cc:682:execute$409.ibuf4_en -1 1 -.names ibuf5_en $auto$rs_design_edit.cc:682:execute$409.ibuf5_en -1 1 -.names in[0] $auto$rs_design_edit.cc:682:execute$409.in[0] -1 1 -.names in[1] $auto$rs_design_edit.cc:682:execute$409.in[1] -1 1 -.names in[2] $auto$rs_design_edit.cc:682:execute$409.in[2] -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.q_n[0] q_n[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.q_n[1] q_n[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.q_n[2] q_n[2] -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.q_p[0] q_p[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.q_p[1] q_p[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.q_p[2] q_p[2] -1 1 -.names rst $auto$rs_design_edit.cc:682:execute$409.rst -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out rst_i_buf_out -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_4/gold/wrapper_primitive_example_design_4_post_synth.v b/design_edit/Tests/primitive_example_design_4/gold/wrapper_primitive_example_design_4_post_synth.v deleted file mode 100644 index 9dedebf25..000000000 --- a/design_edit/Tests/primitive_example_design_4/gold/wrapper_primitive_example_design_4_post_synth.v +++ /dev/null @@ -1,275 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module primitive_example_design_4(in, clk, rst, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en, ibuf5_en, q_n, q_p); - output [2:0] q_p; - input ibuf1_en; - input ibuf4_en; - input clk; - input [2:0] in; - input ibuf2_en; - input ibuf3_en; - output [2:0] q_n; - input rst; - input ibuf5_en; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$clk ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf1_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf2_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf3_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf4_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf5_en ; - wire [2:0] \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n ; - wire [2:0] \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p ; - (* src = "./rtl/primitive_example_design_4.v:10.10-10.23" *) - wire \$auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out ; - (* src = "./rtl/primitive_example_design_4.v:3.16-3.19" *) - wire \$auto$rs_design_edit.cc:682:execute$409.rst ; - (* src = "./rtl/primitive_example_design_4.v:11.16-11.25" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$409.dffre_out ; - (* src = "./rtl/primitive_example_design_4.v:9.16-9.25" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$409.i_buf_out ; - (* src = "./rtl/primitive_example_design_4.v:3.11-3.14" *) - wire \$auto$rs_design_edit.cc:682:execute$409.clk ; - (* src = "./rtl/primitive_example_design_4.v:6.18-6.21" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$409.q_p ; - (* src = "./rtl/primitive_example_design_4.v:5.18-5.21" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$409.q_n ; - (* src = "./rtl/primitive_example_design_4.v:4.20-4.28" *) - wire \$auto$rs_design_edit.cc:682:execute$409.ibuf2_en ; - (* src = "./rtl/primitive_example_design_4.v:2.17-2.19" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$409.in ; - (* src = "./rtl/primitive_example_design_4.v:4.38-4.46" *) - wire \$auto$rs_design_edit.cc:682:execute$409.ibuf4_en ; - (* src = "./rtl/primitive_example_design_4.v:4.11-4.19" *) - wire \$auto$rs_design_edit.cc:682:execute$409.ibuf1_en ; - (* src = "./rtl/primitive_example_design_4.v:4.29-4.37" *) - wire \$auto$rs_design_edit.cc:682:execute$409.ibuf3_en ; - (* src = "./rtl/primitive_example_design_4.v:4.47-4.55" *) - wire \$auto$rs_design_edit.cc:682:execute$409.ibuf5_en ; - (* src = "./rtl/primitive_example_design_4.v:13.38-13.49" *) - wire \$auto$rs_design_edit.cc:682:execute$409.clk_buf_out ; - (* src = "./rtl/primitive_example_design_4.v:6.18-6.21" *) - (* src = "./rtl/primitive_example_design_4.v:6.18-6.21" *) - wire [2:0] q_p; - (* src = "./rtl/primitive_example_design_4.v:4.11-4.19" *) - (* src = "./rtl/primitive_example_design_4.v:4.11-4.19" *) - wire ibuf1_en; - (* src = "./rtl/primitive_example_design_4.v:4.38-4.46" *) - (* src = "./rtl/primitive_example_design_4.v:4.38-4.46" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_4.v:3.11-3.14" *) - (* src = "./rtl/primitive_example_design_4.v:3.11-3.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_4.v:11.16-11.25" *) - wire [2:0] dffre_out; - (* src = "./rtl/primitive_example_design_4.v:2.17-2.19" *) - (* src = "./rtl/primitive_example_design_4.v:2.17-2.19" *) - wire [2:0] in; - (* src = "./rtl/primitive_example_design_4.v:4.20-4.28" *) - (* src = "./rtl/primitive_example_design_4.v:4.20-4.28" *) - wire ibuf2_en; - (* src = "./rtl/primitive_example_design_4.v:4.29-4.37" *) - (* src = "./rtl/primitive_example_design_4.v:4.29-4.37" *) - wire ibuf3_en; - (* src = "./rtl/primitive_example_design_4.v:5.18-5.21" *) - (* src = "./rtl/primitive_example_design_4.v:5.18-5.21" *) - wire [2:0] q_n; - (* src = "./rtl/primitive_example_design_4.v:9.16-9.25" *) - wire [2:0] i_buf_out; - (* src = "./rtl/primitive_example_design_4.v:13.38-13.49" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_4.v:3.16-3.19" *) - (* src = "./rtl/primitive_example_design_4.v:3.16-3.19" *) - wire rst; - (* src = "./rtl/primitive_example_design_4.v:10.10-10.23" *) - wire rst_i_buf_out; - (* src = "./rtl/primitive_example_design_4.v:4.47-4.55" *) - (* src = "./rtl/primitive_example_design_4.v:4.47-4.55" *) - wire ibuf5_en; - wire [2:0] \$iopadmap$q_p ; - wire [2:0] \$iopadmap$q_n ; - wire \$iopadmap$ibuf5_en ; - wire \$iopadmap$ibuf4_en ; - wire \$iopadmap$ibuf3_en ; - wire \$iopadmap$ibuf2_en ; - wire \$iopadmap$ibuf1_en ; - wire \$iopadmap$clk ; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.ibuf1_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.ibuf1_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf1_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.ibuf2_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.ibuf2_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf2_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.ibuf3_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.ibuf3_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf3_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.ibuf4_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.ibuf4_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf4_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.ibuf5_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.ibuf5_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf5_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.q_n ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n [0]), - .O(\$auto$rs_design_edit.cc:682:execute$409.q_n [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.q_n_1 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n [1]), - .O(\$auto$rs_design_edit.cc:682:execute$409.q_n [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.q_n_2 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n [2]), - .O(\$auto$rs_design_edit.cc:682:execute$409.q_n [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.q_p ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p [0]), - .O(\$auto$rs_design_edit.cc:682:execute$409.q_p [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.q_p_1 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p [1]), - .O(\$auto$rs_design_edit.cc:682:execute$409.q_p [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.q_p_2 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p [2]), - .O(\$auto$rs_design_edit.cc:682:execute$409.q_p [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_4.v:13.13-13.51" *) - CLK_BUF \$auto$rs_design_edit.cc:682:execute$409.clk_buf_inst ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$clk ), - .O(\$auto$rs_design_edit.cc:682:execute$409.clk_buf_out ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_4.v:15.14-15.72" *) - O_BUF_DS \$auto$rs_design_edit.cc:682:execute$409.obuf_ds_inst1 ( - .I(\$auto$rs_design_edit.cc:682:execute$409.dffre_out [0]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n [0]), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_4.v:16.14-16.72" *) - O_BUF_DS \$auto$rs_design_edit.cc:682:execute$409.obuf_ds_inst2 ( - .I(\$auto$rs_design_edit.cc:682:execute$409.dffre_out [1]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n [1]), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_4.v:17.14-17.72" *) - O_BUF_DS \$auto$rs_design_edit.cc:682:execute$409.obuf_ds_inst3 ( - .I(\$auto$rs_design_edit.cc:682:execute$409.dffre_out [2]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n [2]), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_4.v:19.11-19.64" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$409.ibuf_inst1 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf2_en ), - .I(\$auto$rs_design_edit.cc:682:execute$409.in [0]), - .O(\$auto$rs_design_edit.cc:682:execute$409.i_buf_out [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_4.v:20.11-20.64" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$409.ibuf_inst2 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf3_en ), - .I(\$auto$rs_design_edit.cc:682:execute$409.in [1]), - .O(\$auto$rs_design_edit.cc:682:execute$409.i_buf_out [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_4.v:21.11-21.64" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$409.ibuf_inst3 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf4_en ), - .I(\$auto$rs_design_edit.cc:682:execute$409.in [2]), - .O(\$auto$rs_design_edit.cc:682:execute$409.i_buf_out [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_4.v:22.11-22.63" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$409.ibuf_inst4 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf5_en ), - .I(\$auto$rs_design_edit.cc:682:execute$409.rst ), - .O(\$auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_4.clk ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$clk ) - ); - fabric_primitive_example_design_4 \$auto$rs_design_edit.cc:680:execute$408 ( - .\$iopadmap$ibuf1_en (\$iopadmap$ibuf1_en ), - .clk_buf_out(clk_buf_out), - .dffre_out(dffre_out), - .i_buf_out(i_buf_out), - .rst_i_buf_out(rst_i_buf_out) - ); - assign \$iopadmap$ibuf1_en = \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf1_en ; - assign \$auto$rs_design_edit.cc:682:execute$409.clk = clk; - assign clk_buf_out = \$auto$rs_design_edit.cc:682:execute$409.clk_buf_out ; - assign \$auto$rs_design_edit.cc:682:execute$409.dffre_out = dffre_out; - assign i_buf_out = \$auto$rs_design_edit.cc:682:execute$409.i_buf_out ; - assign \$auto$rs_design_edit.cc:682:execute$409.ibuf1_en = ibuf1_en; - assign \$auto$rs_design_edit.cc:682:execute$409.ibuf2_en = ibuf2_en; - assign \$auto$rs_design_edit.cc:682:execute$409.ibuf3_en = ibuf3_en; - assign \$auto$rs_design_edit.cc:682:execute$409.ibuf4_en = ibuf4_en; - assign \$auto$rs_design_edit.cc:682:execute$409.ibuf5_en = ibuf5_en; - assign \$auto$rs_design_edit.cc:682:execute$409.in = in; - assign q_n = \$auto$rs_design_edit.cc:682:execute$409.q_n ; - assign q_p = \$auto$rs_design_edit.cc:682:execute$409.q_p ; - assign \$auto$rs_design_edit.cc:682:execute$409.rst = rst; - assign rst_i_buf_out = \$auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out ; -endmodule diff --git a/design_edit/Tests/primitive_example_design_4/primitive_example_design_4.pin b/design_edit/Tests/primitive_example_design_4/primitive_example_design_4.pin deleted file mode 100644 index 9e7f86757..000000000 --- a/design_edit/Tests/primitive_example_design_4/primitive_example_design_4.pin +++ /dev/null @@ -1,16 +0,0 @@ -#Pin Constraints -set_property PIN_LOC AB5 [get_ports clk] -set_property PIN_LOC P27 [get_ports ibuf1_en] -set_property PIN_LOC L22 [get_ports ibuf2_en] -set_property PIN_LOC N23 [get_ports ibuf3_en] -set_property PIN_LOC M23 [get_ports ibuf4_en] -set_property PIN_LOC N24 [get_ports ibuf5_en] -set_property PIN_LOC N26 [get_ports in[0]] -set_property PIN_LOC J24 [get_ports in[1]] -set_property PIN_LOC AG17 [get_ports q_n[0]] -set_property PIN_LOC AC15 [get_ports q_n[1]] -set_property PIN_LOC AF14 [get_ports q_p[0]] -set_property PIN_LOC AD17 [get_ports q_p[1]] -set_property PIN_LOC AG16 [get_ports rst] - - diff --git a/design_edit/Tests/primitive_example_design_4/primitive_example_design_4.ys b/design_edit/Tests/primitive_example_design_4/primitive_example_design_4.ys deleted file mode 100644 index aeb837920..000000000 --- a/design_edit/Tests/primitive_example_design_4/primitive_example_design_4.ys +++ /dev/null @@ -1,21 +0,0 @@ -# Yosys synthesis script for O_SERDES_primitive_inst -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./rtl/primitive_example_design_4.v - - -# Technology mapping -hierarchy -top primitive_example_design_4 - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal delay -effort high -carry auto -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -write_verilog -noexpr -nodec -norename -v ./tmp/primitive_example_design_4_post_synth.v -write_blif -param ./tmp/primitive_example_design_4_post_synth.eblif -plugin -i design-edit -design_edit -tech genesis3 -json ./tmp/io_config.json -w ./tmp/wrapper_primitive_example_design_4_post_synth.v ./tmp/wrapper_primitive_example_design_4_post_synth.eblif -write_verilog -noexpr -nodec -norename -v ./tmp/fabric_primitive_example_design_4_post_synth.v -write_blif -param ./tmp/fabric_primitive_example_design_4_post_synth.eblif \ No newline at end of file diff --git a/design_edit/Tests/primitive_example_design_4/rtl/primitive_example_design_4.v b/design_edit/Tests/primitive_example_design_4/rtl/primitive_example_design_4.v deleted file mode 100644 index 4706b1328..000000000 --- a/design_edit/Tests/primitive_example_design_4/rtl/primitive_example_design_4.v +++ /dev/null @@ -1,28 +0,0 @@ -module primitive_example_design_4( - input [2:0] in, - input clk, rst, - input ibuf1_en,ibuf2_en,ibuf3_en,ibuf4_en,ibuf5_en, - output [2:0] q_n, - output [2:0] q_p, - ); - - wire [2:0] i_buf_out; - wire rst_i_buf_out; - wire [2:0] dffre_out; - - CLK_BUF clk_buf_inst (.I(clk),.O(clk_buf_out)); - - O_BUF_DS obuf_ds_inst1 (.I(dffre_out[0]),.O_P(q_p[0]),.O_N(q_n[0])); - O_BUF_DS obuf_ds_inst2 (.I(dffre_out[1]),.O_P(q_p[1]),.O_N(q_n[1])); - O_BUF_DS obuf_ds_inst3 (.I(dffre_out[2]),.O_P(q_p[2]),.O_N(q_n[2])); - - I_BUF ibuf_inst1 (.I(in[0]),.EN(ibuf2_en),.O(i_buf_out[0])); - I_BUF ibuf_inst2 (.I(in[1]),.EN(ibuf3_en),.O(i_buf_out[1])); - I_BUF ibuf_inst3 (.I(in[2]),.EN(ibuf4_en),.O(i_buf_out[2])); - I_BUF ibuf_inst4 (.I(rst),.EN(ibuf5_en),.O(rst_i_buf_out)); - - DFFRE ff_inst1 (.D(i_buf_out[0]),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffre_out[0])); - DFFRE ff_inst2 (.D(i_buf_out[1]),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffre_out[1])); - DFFRE ff_inst3 (.D(i_buf_out[2]),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffre_out[2])); - -endmodule diff --git a/design_edit/Tests/primitive_example_design_4/synthesis/primitive_example_design_4_post_synth.eblif b/design_edit/Tests/primitive_example_design_4/synthesis/primitive_example_design_4_post_synth.eblif deleted file mode 100644 index 4a5a8fc1b..000000000 --- a/design_edit/Tests/primitive_example_design_4/synthesis/primitive_example_design_4_post_synth.eblif +++ /dev/null @@ -1,21 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model primitive_example_design_4 -.inputs in[0] in[1] in[2] clk rst ibuf1_en ibuf2_en ibuf3_en ibuf4_en ibuf5_en -.outputs q_n[0] q_n[1] q_n[2] q_p[0] q_p[1] q_p[2] -.names $false -.names $true -1 -.names $undef -.subckt CLK_BUF I=clk O=clk_buf_out -.subckt DFFRE C=clk_buf_out D=i_buf_out[0] E=$true Q=dffre_out[0] R=rst_i_buf_out -.subckt DFFRE C=clk_buf_out D=i_buf_out[1] E=$true Q=dffre_out[1] R=rst_i_buf_out -.subckt DFFRE C=clk_buf_out D=i_buf_out[2] E=$true Q=dffre_out[2] R=rst_i_buf_out -.subckt I_BUF EN=ibuf2_en I=in[0] O=i_buf_out[0] -.subckt I_BUF EN=ibuf3_en I=in[1] O=i_buf_out[1] -.subckt I_BUF EN=ibuf4_en I=in[2] O=i_buf_out[2] -.subckt I_BUF EN=ibuf5_en I=rst O=rst_i_buf_out -.subckt O_BUF_DS I=dffre_out[0] O_N=q_n[0] O_P=q_p[0] -.subckt O_BUF_DS I=dffre_out[1] O_N=q_n[1] O_P=q_p[1] -.subckt O_BUF_DS I=dffre_out[2] O_N=q_n[2] O_P=q_p[2] -.end diff --git a/design_edit/Tests/primitive_example_design_4/synthesis/primitive_example_design_4_post_synth.v b/design_edit/Tests/primitive_example_design_4/synthesis/primitive_example_design_4_post_synth.v deleted file mode 100644 index a3ef8db25..000000000 --- a/design_edit/Tests/primitive_example_design_4/synthesis/primitive_example_design_4_post_synth.v +++ /dev/null @@ -1,134 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module primitive_example_design_4(in, clk, rst, ibuf1_en, ibuf2_en, ibuf3_en, ibuf4_en, ibuf5_en, q_n, q_p); - input clk; - input ibuf1_en; - input ibuf2_en; - input ibuf3_en; - input ibuf4_en; - input ibuf5_en; - input [2:0] in; - output [2:0] q_n; - output [2:0] q_p; - input rst; - (* src = "./rtl/primitive_example_design_4.v:3.11-3.14" *) - (* src = "./rtl/primitive_example_design_4.v:3.11-3.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_4.v:13.38-13.49" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_4.v:11.16-11.25" *) - wire [2:0] dffre_out; - (* src = "./rtl/primitive_example_design_4.v:9.16-9.25" *) - wire [2:0] i_buf_out; - (* src = "./rtl/primitive_example_design_4.v:4.11-4.19" *) - (* src = "./rtl/primitive_example_design_4.v:4.11-4.19" *) - wire ibuf1_en; - (* src = "./rtl/primitive_example_design_4.v:4.20-4.28" *) - (* src = "./rtl/primitive_example_design_4.v:4.20-4.28" *) - wire ibuf2_en; - (* src = "./rtl/primitive_example_design_4.v:4.29-4.37" *) - (* src = "./rtl/primitive_example_design_4.v:4.29-4.37" *) - wire ibuf3_en; - (* src = "./rtl/primitive_example_design_4.v:4.38-4.46" *) - (* src = "./rtl/primitive_example_design_4.v:4.38-4.46" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_4.v:4.47-4.55" *) - (* src = "./rtl/primitive_example_design_4.v:4.47-4.55" *) - wire ibuf5_en; - (* src = "./rtl/primitive_example_design_4.v:2.17-2.19" *) - (* src = "./rtl/primitive_example_design_4.v:2.17-2.19" *) - wire [2:0] in; - (* src = "./rtl/primitive_example_design_4.v:5.18-5.21" *) - (* src = "./rtl/primitive_example_design_4.v:5.18-5.21" *) - wire [2:0] q_n; - (* src = "./rtl/primitive_example_design_4.v:6.18-6.21" *) - (* src = "./rtl/primitive_example_design_4.v:6.18-6.21" *) - wire [2:0] q_p; - (* src = "./rtl/primitive_example_design_4.v:3.16-3.19" *) - (* src = "./rtl/primitive_example_design_4.v:3.16-3.19" *) - wire rst; - (* src = "./rtl/primitive_example_design_4.v:10.10-10.23" *) - wire rst_i_buf_out; - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:13.13-13.51" *) - CLK_BUF clk_buf_inst ( - .I(clk), - .O(clk_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:24.11-24.98" *) - DFFRE ff_inst1 ( - .C(clk_buf_out), - .D(i_buf_out[0]), - .E(1'h1), - .Q(dffre_out[0]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:25.11-25.98" *) - DFFRE ff_inst2 ( - .C(clk_buf_out), - .D(i_buf_out[1]), - .E(1'h1), - .Q(dffre_out[1]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:26.11-26.98" *) - DFFRE ff_inst3 ( - .C(clk_buf_out), - .D(i_buf_out[2]), - .E(1'h1), - .Q(dffre_out[2]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:19.11-19.64" *) - I_BUF ibuf_inst1 ( - .EN(ibuf2_en), - .I(in[0]), - .O(i_buf_out[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:20.11-20.64" *) - I_BUF ibuf_inst2 ( - .EN(ibuf3_en), - .I(in[1]), - .O(i_buf_out[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:21.11-21.64" *) - I_BUF ibuf_inst3 ( - .EN(ibuf4_en), - .I(in[2]), - .O(i_buf_out[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:22.11-22.63" *) - I_BUF ibuf_inst4 ( - .EN(ibuf5_en), - .I(rst), - .O(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:15.14-15.72" *) - O_BUF_DS obuf_ds_inst1 ( - .I(dffre_out[0]), - .O_N(q_n[0]), - .O_P(q_p[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:16.14-16.72" *) - O_BUF_DS obuf_ds_inst2 ( - .I(dffre_out[1]), - .O_N(q_n[1]), - .O_P(q_p[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_4.v:17.14-17.72" *) - O_BUF_DS obuf_ds_inst3 ( - .I(dffre_out[2]), - .O_N(q_n[2]), - .O_P(q_p[2]) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_5/gold/interface.json b/design_edit/Tests/primitive_example_design_5/gold/interface.json deleted file mode 100644 index b106fbe67..000000000 --- a/design_edit/Tests/primitive_example_design_5/gold/interface.json +++ /dev/null @@ -1,403 +0,0 @@ -{ - "IO_Instances": { - "clk_buf_inst": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf1_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "clk", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "clk_buf_out", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst1": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf2_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst2": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf3_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "lsb": 1, - "msb": 1 - } - ] - } - }, - "ibuf_inst3": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf4_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "lsb": 2, - "msb": 2 - } - ] - } - }, - "ibuf_inst4": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf5_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "rst", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "rst_i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "iddr_ist1": { - "module": "I_DDR", - "ports": { - "C": [ - { - "Actual": "clk_buf_out", - "lsb": 0, - "msb": 0 - } - ], - "D": [ - { - "Actual": "i_buf_out", - "lsb": 0, - "msb": 0 - } - ], - "E": [ - { - "Actual": "iddr_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "Q": [ - { - "Actual": "$auto$hierarchy.cc:1408:execute$3", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - }, - { - "Actual": "iddr_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "R": [ - { - "Actual": "rst", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "iddr_ist2": { - "module": "I_DDR", - "ports": { - "C": [ - { - "Actual": "clk_buf_out", - "lsb": 0, - "msb": 0 - } - ], - "D": [ - { - "Actual": "i_buf_out", - "lsb": 1, - "msb": 1 - } - ], - "E": [ - { - "Actual": "iddr_en", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "Q": [ - { - "Actual": "$auto$hierarchy.cc:1408:execute$2", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - }, - { - "Actual": "iddr_out", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ], - "R": [ - { - "Actual": "rst", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "iddr_ist3": { - "module": "I_DDR", - "ports": { - "C": [ - { - "Actual": "clk_buf_out", - "lsb": 0, - "msb": 0 - } - ], - "D": [ - { - "Actual": "i_buf_out", - "lsb": 2, - "msb": 2 - } - ], - "E": [ - { - "Actual": "iddr_en", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "Q": [ - { - "Actual": "$auto$hierarchy.cc:1408:execute$1", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - }, - { - "Actual": "iddr_out", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ], - "R": [ - { - "Actual": "rst", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "o_buft_inst1": { - "module": "O_BUFT_DS", - "ports": { - "I": [ - { - "Actual": "dffre_out", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_N": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_P": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "T": [ - { - "Actual": "obuft_ds_en1", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "o_buft_inst2": { - "module": "O_BUFT_DS", - "ports": { - "I": [ - { - "Actual": "dffre_out", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O_N": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O_P": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 1, - "msb": 1 - } - ], - "T": [ - { - "Actual": "obuft_ds_en2", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "o_buft_inst3": { - "module": "O_BUFT_DS", - "ports": { - "I": [ - { - "Actual": "dffre_out", - "FUNC": "IN_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O_N": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ], - "O_P": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 2, - "msb": 2 - } - ], - "T": [ - { - "Actual": "obuft_ds_en3", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - } - } -} diff --git a/design_edit/Tests/primitive_example_design_5/gold/io_config.json b/design_edit/Tests/primitive_example_design_5/gold/io_config.json deleted file mode 100644 index dc8b64d82..000000000 --- a/design_edit/Tests/primitive_example_design_5/gold/io_config.json +++ /dev/null @@ -1,557 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\clk (index=0, width=1, offset=0)", - " Detect input port \\ibuf1_en (index=0, width=1, offset=0)", - " Detect input port \\ibuf2_en (index=0, width=1, offset=0)", - " Detect input port \\ibuf3_en (index=0, width=1, offset=0)", - " Detect input port \\ibuf4_en (index=0, width=1, offset=0)", - " Detect input port \\ibuf5_en (index=0, width=1, offset=0)", - " Detect input port \\iddr_en (index=0, width=3, offset=0)", - " Detect input port \\iddr_en (index=1, width=3, offset=0)", - " Detect input port \\iddr_en (index=2, width=3, offset=0)", - " Detect input port \\in (index=0, width=3, offset=0)", - " Detect input port \\in (index=1, width=3, offset=0)", - " Detect input port \\in (index=2, width=3, offset=0)", - " Detect input port \\obuft_ds_en1 (index=0, width=1, offset=0)", - " Detect input port \\obuft_ds_en2 (index=0, width=1, offset=0)", - " Detect input port \\obuft_ds_en3 (index=0, width=1, offset=0)", - " Detect output port \\q_n (index=0, width=3, offset=0)", - " Detect output port \\q_n (index=1, width=3, offset=0)", - " Detect output port \\q_n (index=2, width=3, offset=0)", - " Detect output port \\q_p (index=0, width=3, offset=0)", - " Detect output port \\q_p (index=1, width=3, offset=0)", - " Detect output port \\q_p (index=2, width=3, offset=0)", - " Detect input port \\rst (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.ibuf1_en", - " Cell port \\I is connected to input port \\ibuf1_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.ibuf2_en", - " Cell port \\I is connected to input port \\ibuf2_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.ibuf3_en", - " Cell port \\I is connected to input port \\ibuf3_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.ibuf4_en", - " Cell port \\I is connected to input port \\ibuf4_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.ibuf5_en", - " Cell port \\I is connected to input port \\ibuf5_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.iddr_en", - " Cell port \\I is connected to input port \\iddr_en[0]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.iddr_en_1", - " Cell port \\I is connected to input port \\iddr_en[1]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.iddr_en_2", - " Cell port \\I is connected to input port \\iddr_en[2]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.obuft_ds_en1", - " Cell port \\I is connected to input port \\obuft_ds_en1", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.obuft_ds_en2", - " Cell port \\I is connected to input port \\obuft_ds_en2", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_5.obuft_ds_en3", - " Cell port \\I is connected to input port \\obuft_ds_en3", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_5.q_n", - " Cell port \\O is connected to output port \\q_n[0]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_5.q_n_1", - " Cell port \\O is connected to output port \\q_n[1]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_5.q_n_2", - " Cell port \\O is connected to output port \\q_n[2]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_5.q_p", - " Cell port \\O is connected to output port \\q_p[0]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_5.q_p_1", - " Cell port \\O is connected to output port \\q_p[1]", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_5.q_p_2", - " Cell port \\O is connected to output port \\q_p[2]", - " Get important connection of cell \\I_BUF \\clk_buf_inst", - " Cell port \\I is connected to input port \\clk", - " Get important connection of cell \\I_BUF \\ibuf_inst1", - " Cell port \\I is connected to input port \\in[0]", - " Get important connection of cell \\I_BUF \\ibuf_inst2", - " Cell port \\I is connected to input port \\in[1]", - " Get important connection of cell \\I_BUF \\ibuf_inst3", - " Cell port \\I is connected to input port \\in[2]", - " Get important connection of cell \\I_BUF \\ibuf_inst4", - " Cell port \\I is connected to input port \\rst", - " Trace Clock Buffer", - " Try \\I_BUF \\clk_buf_inst out connection: $auto$clkbufmap.cc:263:execute$400", - " Connected $auto$clkbufmap.cc:262:execute$399", - " Assign location HR_3_1_0P (and properties) to Port obuft_ds_en2", - " Assign location HR_5_0_0P (and properties) to Port q_p[0]", - " Assign location HR_3_1_1P (and properties) to Port obuft_ds_en3", - " Assign location HR_3_1_4P (and properties) to Port iddr_en[2]", - " Assign location HR_3_0_9P (and properties) to Port obuft_ds_en1", - " Assign location HR_3_0_8P (and properties) to Port ibuf5_en", - " Assign location HR_3_0_7P (and properties) to Port ibuf4_en", - " Assign location HR_5_0_5P (and properties) to Port q_n[2]", - " Assign location HR_3_0_0P (and properties) to Port in[0]", - " Assign location HR_5_0_4P (and properties) to Port q_n[1]", - " Assign location HR_3_0_2P (and properties) to Port in[2]", - " Assign location HR_3_1_2P (and properties) to Port iddr_en[0]", - " Assign location HR_3_0_3P (and properties) to Port ibuf2_en", - " Assign location HR_3_1_3P (and properties) to Port iddr_en[1]", - " Assign location HR_5_0_2P (and properties) to Port q_p[2]", - " Assign location HR_5_0_1P (and properties) to Port q_p[1]", - " Assign location HR_3_0_4P (and properties) to Port ibuf1_en", - " Assign location HR_3_0_6P (and properties) to Port ibuf3_en", - " Assign location HR_2_0_0P (and properties) to Port clk", - " Assign location HR_3_0_1P (and properties) to Port in[1]", - " Assign location HR_5_0_3P (and properties) to Port q_n[0]", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.ibuf1_en", - "linked_object" : "ibuf1_en", - "linked_objects" : { - "ibuf1_en" : { - "location" : "HR_3_0_4P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "ibuf1_en", - "O" : "$iopadmap$ibuf1_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.ibuf2_en", - "linked_object" : "ibuf2_en", - "linked_objects" : { - "ibuf2_en" : { - "location" : "HR_3_0_3P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "ibuf2_en", - "O" : "$iopadmap$ibuf2_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.ibuf3_en", - "linked_object" : "ibuf3_en", - "linked_objects" : { - "ibuf3_en" : { - "location" : "HR_3_0_6P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "ibuf3_en", - "O" : "$iopadmap$ibuf3_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.ibuf4_en", - "linked_object" : "ibuf4_en", - "linked_objects" : { - "ibuf4_en" : { - "location" : "HR_3_0_7P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "ibuf4_en", - "O" : "$iopadmap$ibuf4_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.ibuf5_en", - "linked_object" : "ibuf5_en", - "linked_objects" : { - "ibuf5_en" : { - "location" : "HR_3_0_8P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "ibuf5_en", - "O" : "$iopadmap$ibuf5_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.iddr_en", - "linked_object" : "iddr_en[0]", - "linked_objects" : { - "iddr_en[0]" : { - "location" : "HR_3_1_2P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "iddr_en[0]", - "O" : "$iopadmap$iddr_en[0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.iddr_en_1", - "linked_object" : "iddr_en[1]", - "linked_objects" : { - "iddr_en[1]" : { - "location" : "HR_3_1_3P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "iddr_en[1]", - "O" : "$iopadmap$iddr_en[1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.iddr_en_2", - "linked_object" : "iddr_en[2]", - "linked_objects" : { - "iddr_en[2]" : { - "location" : "HR_3_1_4P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "iddr_en[2]", - "O" : "$iopadmap$iddr_en[2]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.obuft_ds_en1", - "linked_object" : "obuft_ds_en1", - "linked_objects" : { - "obuft_ds_en1" : { - "location" : "HR_3_0_9P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "obuft_ds_en1", - "O" : "$iopadmap$obuft_ds_en1" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.obuft_ds_en2", - "linked_object" : "obuft_ds_en2", - "linked_objects" : { - "obuft_ds_en2" : { - "location" : "HR_3_1_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "obuft_ds_en2", - "O" : "$iopadmap$obuft_ds_en2" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_5.obuft_ds_en3", - "linked_object" : "obuft_ds_en3", - "linked_objects" : { - "obuft_ds_en3" : { - "location" : "HR_3_1_1P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "obuft_ds_en3", - "O" : "$iopadmap$obuft_ds_en3" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_5.q_n", - "linked_object" : "q_n[0]", - "linked_objects" : { - "q_n[0]" : { - "location" : "HR_5_0_3P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_n[0]", - "O" : "q_n[0]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_5.q_n_1", - "linked_object" : "q_n[1]", - "linked_objects" : { - "q_n[1]" : { - "location" : "HR_5_0_4P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_n[1]", - "O" : "q_n[1]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_5.q_n_2", - "linked_object" : "q_n[2]", - "linked_objects" : { - "q_n[2]" : { - "location" : "HR_5_0_5P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_n[2]", - "O" : "q_n[2]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_5.q_p", - "linked_object" : "q_p[0]", - "linked_objects" : { - "q_p[0]" : { - "location" : "HR_5_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_p[0]", - "O" : "q_p[0]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_5.q_p_1", - "linked_object" : "q_p[1]", - "linked_objects" : { - "q_p[1]" : { - "location" : "HR_5_0_1P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_p[1]", - "O" : "q_p[1]" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_5.q_p_2", - "linked_object" : "q_p[2]", - "linked_objects" : { - "q_p[2]" : { - "location" : "HR_5_0_2P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_p[2]", - "O" : "q_p[2]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "clk_buf_inst", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HR_2_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "clk", - "O" : "$auto$clkbufmap.cc:263:execute$400" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$399", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HR_2_0_0P", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$400", - "O" : "clk_buf_out" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst1", - "linked_object" : "in[0]", - "linked_objects" : { - "in[0]" : { - "location" : "HR_3_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "in[0]", - "O" : "i_buf_out[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst2", - "linked_object" : "in[1]", - "linked_objects" : { - "in[1]" : { - "location" : "HR_3_0_1P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "in[1]", - "O" : "i_buf_out[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst3", - "linked_object" : "in[2]", - "linked_objects" : { - "in[2]" : { - "location" : "HR_3_0_2P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "in[2]", - "O" : "i_buf_out[2]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst4", - "linked_object" : "rst", - "linked_objects" : { - "rst" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "rst", - "O" : "rst_i_buf_out" - }, - "parameters" : { - } - } - ] -} diff --git a/design_edit/Tests/primitive_example_design_5/gold/primitive_example_design_5_post_synth.eblif b/design_edit/Tests/primitive_example_design_5/gold/primitive_example_design_5_post_synth.eblif deleted file mode 100644 index 4196ae0cf..000000000 --- a/design_edit/Tests/primitive_example_design_5/gold/primitive_example_design_5_post_synth.eblif +++ /dev/null @@ -1,19 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_primitive_example_design_5 -.inputs iddr_out[0] iddr_out[1] iddr_out[2] rst_i_buf_out clk_buf_out $auto$hierarchy.cc:1408:execute$1 $auto$hierarchy.cc:1408:execute$2 $auto$hierarchy.cc:1408:execute$3 -.outputs dffre_out[0] dffre_out[1] dffre_out[2] $iopadmap$q_n[0] $iopadmap$q_n[1] $iopadmap$q_n[2] -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=clk_buf_out D=iddr_out[0] E=$true Q=dffre_out[0] R=rst_i_buf_out -.subckt DFFRE C=clk_buf_out D=iddr_out[1] E=$true Q=dffre_out[1] R=rst_i_buf_out -.subckt DFFRE C=clk_buf_out D=iddr_out[2] E=$true Q=dffre_out[2] R=rst_i_buf_out -.names $undef $iopadmap$q_n[0] -1 1 -.names $undef $iopadmap$q_n[1] -1 1 -.names $undef $iopadmap$q_n[2] -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_5/gold/primitive_example_design_5_post_synth.v b/design_edit/Tests/primitive_example_design_5/gold/primitive_example_design_5_post_synth.v deleted file mode 100644 index 8d06716b8..000000000 --- a/design_edit/Tests/primitive_example_design_5/gold/primitive_example_design_5_post_synth.v +++ /dev/null @@ -1,168 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_primitive_example_design_5(iddr_out, dffre_out, rst_i_buf_out, clk_buf_out, \$auto$hierarchy.cc:1408:execute$1 , \$auto$hierarchy.cc:1408:execute$2 , \$auto$hierarchy.cc:1408:execute$3 , \$iopadmap$q_n ); - input clk_buf_out; - output [2:0] dffre_out; - input \$auto$hierarchy.cc:1408:execute$2 ; - input \$auto$hierarchy.cc:1408:execute$1 ; - input [2:0] iddr_out; - output [2:0] \$iopadmap$q_n ; - input \$auto$hierarchy.cc:1408:execute$3 ; - input rst_i_buf_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap405$iopadmap$primitive_example_design_5.ibuf2_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap405$iopadmap$primitive_example_design_5.ibuf2_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap405$iopadmap$primitive_example_design_5.ibuf2_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap406$iopadmap$primitive_example_design_5.q_n.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap406$iopadmap$primitive_example_design_5.q_n.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap406$iopadmap$primitive_example_design_5.q_n.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap407$iopadmap$primitive_example_design_5.ibuf5_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap407$iopadmap$primitive_example_design_5.ibuf5_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap407$iopadmap$primitive_example_design_5.ibuf5_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap408$iopadmap$primitive_example_design_5.q_n_2.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap408$iopadmap$primitive_example_design_5.q_n_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap408$iopadmap$primitive_example_design_5.q_n_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap409$iopadmap$primitive_example_design_5.obuft_ds_en3.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap409$iopadmap$primitive_example_design_5.obuft_ds_en3.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap409$iopadmap$primitive_example_design_5.obuft_ds_en3.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap410$iopadmap$primitive_example_design_5.q_p_1.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap410$iopadmap$primitive_example_design_5.q_p_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap410$iopadmap$primitive_example_design_5.q_p_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap411$iopadmap$primitive_example_design_5.q_p.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap411$iopadmap$primitive_example_design_5.q_p.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap411$iopadmap$primitive_example_design_5.q_p.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap412$iopadmap$primitive_example_design_5.iddr_en_1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap412$iopadmap$primitive_example_design_5.iddr_en_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap412$iopadmap$primitive_example_design_5.iddr_en_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap413$iopadmap$primitive_example_design_5.ibuf4_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap413$iopadmap$primitive_example_design_5.ibuf4_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap413$iopadmap$primitive_example_design_5.ibuf4_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap414$iopadmap$primitive_example_design_5.iddr_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap414$iopadmap$primitive_example_design_5.iddr_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap414$iopadmap$primitive_example_design_5.iddr_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap415$iopadmap$primitive_example_design_5.obuft_ds_en2.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap415$iopadmap$primitive_example_design_5.obuft_ds_en2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap415$iopadmap$primitive_example_design_5.obuft_ds_en2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap416$iopadmap$primitive_example_design_5.q_p_2.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap416$iopadmap$primitive_example_design_5.q_p_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap416$iopadmap$primitive_example_design_5.q_p_2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap417$iopadmap$primitive_example_design_5.ibuf3_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap417$iopadmap$primitive_example_design_5.ibuf3_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap417$iopadmap$primitive_example_design_5.ibuf3_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap418$iopadmap$primitive_example_design_5.ibuf1_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap418$iopadmap$primitive_example_design_5.ibuf1_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap418$iopadmap$primitive_example_design_5.ibuf1_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap404$iopadmap$primitive_example_design_5.q_n_1.C ; - (* src = "./rtl/primitive_example_design_5.v:18.50-18.61" *) - (* src = "./rtl/primitive_example_design_5.v:18.50-18.61" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_5.v:14.16-14.25" *) - (* src = "./rtl/primitive_example_design_5.v:14.16-14.25" *) - wire [2:0] dffre_out; - (* unused_bits = "0" *) - (* unused_bits = "0" *) - wire \$auto$hierarchy.cc:1408:execute$2 ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap403$iopadmap$primitive_example_design_5.iddr_en_2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap402$iopadmap$primitive_example_design_5.obuft_ds_en1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap402$iopadmap$primitive_example_design_5.obuft_ds_en1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap401$auto$clkbufmap.cc:262:execute$399.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap403$iopadmap$primitive_example_design_5.iddr_en_2.EN ; - (* unused_bits = "0" *) - (* unused_bits = "0" *) - wire \$auto$hierarchy.cc:1408:execute$1 ; - (* src = "./rtl/primitive_example_design_5.v:13.16-13.24" *) - (* src = "./rtl/primitive_example_design_5.v:13.16-13.24" *) - wire [2:0] iddr_out; - wire [2:0] \$iopadmap$q_n ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap403$iopadmap$primitive_example_design_5.iddr_en_2.O ; - (* unused_bits = "0" *) - (* unused_bits = "0" *) - wire \$auto$hierarchy.cc:1408:execute$3 ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap402$iopadmap$primitive_example_design_5.obuft_ds_en1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap404$iopadmap$primitive_example_design_5.q_n_1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap404$iopadmap$primitive_example_design_5.q_n_1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap401$auto$clkbufmap.cc:262:execute$399.I ; - (* src = "./rtl/primitive_example_design_5.v:16.10-16.23" *) - (* src = "./rtl/primitive_example_design_5.v:16.10-16.23" *) - wire rst_i_buf_out; - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:34.11-34.97" *) - DFFRE ff_inst2 ( - .C(clk_buf_out), - .D(iddr_out[1]), - .E(1'h1), - .Q(dffre_out[1]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:35.11-35.97" *) - DFFRE ff_inst3 ( - .C(clk_buf_out), - .D(iddr_out[2]), - .E(1'h1), - .Q(dffre_out[2]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:33.11-33.97" *) - DFFRE ff_inst1 ( - .C(clk_buf_out), - .D(iddr_out[0]), - .E(1'h1), - .Q(dffre_out[0]), - .R(rst_i_buf_out) - ); - assign \$iopadmap$q_n = 3'hx; -endmodule diff --git a/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_route.eblif b/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_route.eblif deleted file mode 100644 index 7d7035f76..000000000 --- a/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_route.eblif +++ /dev/null @@ -1,123 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model primitive_example_design_5 -.inputs in[0] in[1] in[2] ibuf2_en rst clk ibuf1_en ibuf3_en ibuf4_en ibuf5_en obuft_ds_en1 obuft_ds_en2 obuft_ds_en3 iddr_en[0] iddr_en[1] iddr_en[2] -.outputs q_p[0] q_p[1] q_p[2] q_n[0] q_n[1] q_n[2] -.names $false -.names $true -1 -.names $undef -.subckt fabric_primitive_example_design_5 $auto$hierarchy.cc:1408:execute$1=$auto$hierarchy.cc:1408:execute$1 $auto$hierarchy.cc:1408:execute$2=$auto$hierarchy.cc:1408:execute$2 $auto$hierarchy.cc:1408:execute$3=$auto$hierarchy.cc:1408:execute$3 $iopadmap$q_n[0]=$iopadmap$q_n[0] $iopadmap$q_n[1]=$iopadmap$q_n[1] $iopadmap$q_n[2]=$iopadmap$q_n[2] clk_buf_out=clk_buf_out dffre_out[0]=dffre_out[0] dffre_out[1]=dffre_out[1] dffre_out[2]=dffre_out[2] iddr_out[0]=iddr_out[0] iddr_out[1]=iddr_out[1] iddr_out[2]=iddr_out[2] rst_i_buf_out=rst_i_buf_out -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en I=$auto$rs_design_edit.cc:682:execute$420.clk O=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en I=$auto$rs_design_edit.cc:682:execute$420.in[0] O=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[0] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en I=$auto$rs_design_edit.cc:682:execute$420.in[1] O=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[1] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en I=$auto$rs_design_edit.cc:682:execute$420.in[2] O=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[2] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en I=$auto$rs_design_edit.cc:682:execute$420.rst O=$auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out -.subckt I_DDR C=$auto$rs_design_edit.cc:682:execute$420.clk_buf_out D=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[0] E=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[0] Q[0]=$auto$rs_design_edit.cc:682:execute$420.iddr_out[0] Q[1]=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 R=$auto$rs_design_edit.cc:682:execute$420.rst -.subckt I_DDR C=$auto$rs_design_edit.cc:682:execute$420.clk_buf_out D=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[1] E=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[1] Q[0]=$auto$rs_design_edit.cc:682:execute$420.iddr_out[1] Q[1]=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 R=$auto$rs_design_edit.cc:682:execute$420.rst -.subckt I_DDR C=$auto$rs_design_edit.cc:682:execute$420.clk_buf_out D=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[2] E=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[2] Q[0]=$auto$rs_design_edit.cc:682:execute$420.iddr_out[2] Q[1]=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 R=$auto$rs_design_edit.cc:682:execute$420.rst -.subckt O_BUFT_DS I=$auto$rs_design_edit.cc:682:execute$420.dffre_out[0] O_N=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[0] O_P=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[0] T=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 -.subckt O_BUFT_DS I=$auto$rs_design_edit.cc:682:execute$420.dffre_out[1] O_N=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[1] O_P=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[1] T=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 -.subckt O_BUFT_DS I=$auto$rs_design_edit.cc:682:execute$420.dffre_out[2] O_N=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[2] O_P=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[2] T=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 O=$auto$rs_design_edit.cc:682:execute$420.clk_buf_out -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf1_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf2_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf3_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf4_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf5_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.iddr_en[0] O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[0] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.iddr_en[1] O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[1] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.iddr_en[2] O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[2] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[0] O=$auto$rs_design_edit.cc:682:execute$420.q_n[0] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[1] O=$auto$rs_design_edit.cc:682:execute$420.q_n[1] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[2] O=$auto$rs_design_edit.cc:682:execute$420.q_n[2] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[0] O=$auto$rs_design_edit.cc:682:execute$420.q_p[0] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[1] O=$auto$rs_design_edit.cc:682:execute$420.q_p[1] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[2] O=$auto$rs_design_edit.cc:682:execute$420.q_p[2] -.names $flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 $auto$hierarchy.cc:1408:execute$1 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 $auto$hierarchy.cc:1408:execute$2 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 $auto$hierarchy.cc:1408:execute$3 -1 1 -.names $iopadmap$q_n[0] $flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[0] -1 1 -.names $iopadmap$q_n[1] $flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[1] -1 1 -.names $iopadmap$q_n[2] $flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[2] -1 1 -.names clk $auto$rs_design_edit.cc:682:execute$420.clk -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.clk_buf_out clk_buf_out -1 1 -.names dffre_out[0] $auto$rs_design_edit.cc:682:execute$420.dffre_out[0] -1 1 -.names dffre_out[1] $auto$rs_design_edit.cc:682:execute$420.dffre_out[1] -1 1 -.names dffre_out[2] $auto$rs_design_edit.cc:682:execute$420.dffre_out[2] -1 1 -.names ibuf1_en $auto$rs_design_edit.cc:682:execute$420.ibuf1_en -1 1 -.names ibuf2_en $auto$rs_design_edit.cc:682:execute$420.ibuf2_en -1 1 -.names ibuf3_en $auto$rs_design_edit.cc:682:execute$420.ibuf3_en -1 1 -.names ibuf4_en $auto$rs_design_edit.cc:682:execute$420.ibuf4_en -1 1 -.names ibuf5_en $auto$rs_design_edit.cc:682:execute$420.ibuf5_en -1 1 -.names iddr_en[0] $auto$rs_design_edit.cc:682:execute$420.iddr_en[0] -1 1 -.names iddr_en[1] $auto$rs_design_edit.cc:682:execute$420.iddr_en[1] -1 1 -.names iddr_en[2] $auto$rs_design_edit.cc:682:execute$420.iddr_en[2] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.iddr_out[0] iddr_out[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.iddr_out[1] iddr_out[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.iddr_out[2] iddr_out[2] -1 1 -.names in[0] $auto$rs_design_edit.cc:682:execute$420.in[0] -1 1 -.names in[1] $auto$rs_design_edit.cc:682:execute$420.in[1] -1 1 -.names in[2] $auto$rs_design_edit.cc:682:execute$420.in[2] -1 1 -.names obuft_ds_en1 $auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 -1 1 -.names obuft_ds_en2 $auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 -1 1 -.names obuft_ds_en3 $auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_n[0] q_n[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_n[1] q_n[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_n[2] q_n[2] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_p[0] q_p[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_p[1] q_p[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_p[2] q_p[2] -1 1 -.names rst $auto$rs_design_edit.cc:682:execute$420.rst -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out rst_i_buf_out -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_route.v b/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_route.v deleted file mode 100644 index d44c72c01..000000000 --- a/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_route.v +++ /dev/null @@ -1,426 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module primitive_example_design_5(in, ibuf2_en, rst, clk, ibuf1_en, ibuf3_en, ibuf4_en, ibuf5_en, obuft_ds_en1, obuft_ds_en2, obuft_ds_en3, iddr_en, q_p, q_n); - input clk; - input ibuf1_en; - input ibuf2_en; - input ibuf3_en; - input ibuf4_en; - input ibuf5_en; - input [2:0] iddr_en; - input [2:0] in; - input obuft_ds_en1; - input obuft_ds_en2; - input obuft_ds_en3; - output [2:0] q_n; - output [2:0] q_p; - input rst; - wire \$auto$clkbufmap.cc:263:execute$400 ; - (* unused_bits = "0" *) - wire \$auto$hierarchy.cc:1408:execute$1 ; - (* unused_bits = "0" *) - wire \$auto$hierarchy.cc:1408:execute$2 ; - (* unused_bits = "0" *) - wire \$auto$hierarchy.cc:1408:execute$3 ; - (* src = "./rtl/primitive_example_design_5.v:5.11-5.14" *) - wire \$auto$rs_design_edit.cc:682:execute$420.clk ; - (* src = "./rtl/primitive_example_design_5.v:18.50-18.61" *) - wire \$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ; - (* src = "./rtl/primitive_example_design_5.v:14.16-14.25" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.dffre_out ; - (* src = "./rtl/primitive_example_design_5.v:15.16-15.25" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.i_buf_out ; - (* src = "./rtl/primitive_example_design_5.v:6.11-6.19" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf1_en ; - (* src = "./rtl/primitive_example_design_5.v:3.11-3.19" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf2_en ; - (* src = "./rtl/primitive_example_design_5.v:6.29-6.37" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf3_en ; - (* src = "./rtl/primitive_example_design_5.v:6.38-6.46" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf4_en ; - (* src = "./rtl/primitive_example_design_5.v:6.47-6.55" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf5_en ; - (* src = "./rtl/primitive_example_design_5.v:8.17-8.24" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.iddr_en ; - (* src = "./rtl/primitive_example_design_5.v:13.16-13.24" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.iddr_out ; - (* src = "./rtl/primitive_example_design_5.v:2.17-2.19" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.in ; - (* src = "./rtl/primitive_example_design_5.v:7.11-7.23" *) - wire \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 ; - (* src = "./rtl/primitive_example_design_5.v:7.24-7.36" *) - wire \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 ; - (* src = "./rtl/primitive_example_design_5.v:7.37-7.49" *) - wire \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 ; - (* src = "./rtl/primitive_example_design_5.v:10.18-10.21" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.q_n ; - (* src = "./rtl/primitive_example_design_5.v:9.18-9.21" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.q_p ; - (* src = "./rtl/primitive_example_design_5.v:4.11-4.14" *) - wire \$auto$rs_design_edit.cc:682:execute$420.rst ; - (* src = "./rtl/primitive_example_design_5.v:16.10-16.23" *) - wire \$auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 ; - (* unused_bits = "0" *) - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 ; - (* unused_bits = "0" *) - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 ; - (* unused_bits = "0" *) - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en ; - wire [2:0] \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 ; - wire [2:0] \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n ; - wire [2:0] \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p ; - wire \$iopadmap$ibuf1_en ; - wire \$iopadmap$ibuf2_en ; - wire \$iopadmap$ibuf3_en ; - wire \$iopadmap$ibuf4_en ; - wire \$iopadmap$ibuf5_en ; - wire [2:0] \$iopadmap$iddr_en ; - wire \$iopadmap$obuft_ds_en1 ; - wire \$iopadmap$obuft_ds_en2 ; - wire \$iopadmap$obuft_ds_en3 ; - wire [2:0] \$iopadmap$q_n ; - wire [2:0] \$iopadmap$q_p ; - (* src = "./rtl/primitive_example_design_5.v:5.11-5.14" *) - (* src = "./rtl/primitive_example_design_5.v:5.11-5.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_5.v:18.50-18.61" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_5.v:14.16-14.25" *) - wire [2:0] dffre_out; - (* src = "./rtl/primitive_example_design_5.v:15.16-15.25" *) - wire [2:0] i_buf_out; - (* src = "./rtl/primitive_example_design_5.v:6.11-6.19" *) - (* src = "./rtl/primitive_example_design_5.v:6.11-6.19" *) - wire ibuf1_en; - (* src = "./rtl/primitive_example_design_5.v:3.11-3.19" *) - (* src = "./rtl/primitive_example_design_5.v:3.11-3.19" *) - wire ibuf2_en; - (* src = "./rtl/primitive_example_design_5.v:6.29-6.37" *) - (* src = "./rtl/primitive_example_design_5.v:6.29-6.37" *) - wire ibuf3_en; - (* src = "./rtl/primitive_example_design_5.v:6.38-6.46" *) - (* src = "./rtl/primitive_example_design_5.v:6.38-6.46" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_5.v:6.47-6.55" *) - (* src = "./rtl/primitive_example_design_5.v:6.47-6.55" *) - wire ibuf5_en; - (* src = "./rtl/primitive_example_design_5.v:8.17-8.24" *) - (* src = "./rtl/primitive_example_design_5.v:8.17-8.24" *) - wire [2:0] iddr_en; - (* src = "./rtl/primitive_example_design_5.v:13.16-13.24" *) - wire [2:0] iddr_out; - (* src = "./rtl/primitive_example_design_5.v:2.17-2.19" *) - (* src = "./rtl/primitive_example_design_5.v:2.17-2.19" *) - wire [2:0] in; - (* src = "./rtl/primitive_example_design_5.v:7.11-7.23" *) - (* src = "./rtl/primitive_example_design_5.v:7.11-7.23" *) - wire obuft_ds_en1; - (* src = "./rtl/primitive_example_design_5.v:7.24-7.36" *) - (* src = "./rtl/primitive_example_design_5.v:7.24-7.36" *) - wire obuft_ds_en2; - (* src = "./rtl/primitive_example_design_5.v:7.37-7.49" *) - (* src = "./rtl/primitive_example_design_5.v:7.37-7.49" *) - wire obuft_ds_en3; - (* src = "./rtl/primitive_example_design_5.v:10.18-10.21" *) - (* src = "./rtl/primitive_example_design_5.v:10.18-10.21" *) - wire [2:0] q_n; - (* src = "./rtl/primitive_example_design_5.v:9.18-9.21" *) - (* src = "./rtl/primitive_example_design_5.v:9.18-9.21" *) - wire [2:0] q_p; - (* src = "./rtl/primitive_example_design_5.v:4.11-4.14" *) - (* src = "./rtl/primitive_example_design_5.v:4.11-4.14" *) - wire rst; - (* src = "./rtl/primitive_example_design_5.v:16.10-16.23" *) - wire rst_i_buf_out; - fabric_primitive_example_design_5 \$auto$rs_design_edit.cc:680:execute$419 ( - .\iddr_out[2] (iddr_out[2]), - .\iddr_out[1] (iddr_out[1]), - .\iddr_out[0] (iddr_out[0]), - .\dffre_out[1] (dffre_out[1]), - .\dffre_out[0] (dffre_out[0]), - .\$iopadmap$q_n[1] (\$iopadmap$q_n [1]), - .\$iopadmap$q_n[0] (\$iopadmap$q_n [0]), - .\$auto$hierarchy.cc:1408:execute$2 (\$auto$hierarchy.cc:1408:execute$2 ), - .\$auto$hierarchy.cc:1408:execute$3 (\$auto$hierarchy.cc:1408:execute$3 ), - .\$auto$hierarchy.cc:1408:execute$1 (\$auto$hierarchy.cc:1408:execute$1 ), - .clk_buf_out(clk_buf_out), - .\$iopadmap$q_n[2] (\$iopadmap$q_n [2]), - .\dffre_out[2] (dffre_out[2]), - .rst_i_buf_out(rst_i_buf_out) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:18.11-18.63" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.clk_buf_inst ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:28.11-28.64" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.ibuf_inst1 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.in [0]), - .O(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:29.11-29.64" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.ibuf_inst2 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.in [1]), - .O(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:30.11-30.64" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.ibuf_inst3 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.in [2]), - .O(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:31.11-31.63" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.ibuf_inst4 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.rst ), - .O(\$auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:20.11-20.94" *) - I_DDR \$auto$rs_design_edit.cc:682:execute$420.iddr_ist1 ( - .C(\$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ), - .D(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [0]), - .E(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [0]), - .Q({ \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 , \$auto$rs_design_edit.cc:682:execute$420.iddr_out [0] }), - .R(\$auto$rs_design_edit.cc:682:execute$420.rst ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:21.11-21.94" *) - I_DDR \$auto$rs_design_edit.cc:682:execute$420.iddr_ist2 ( - .C(\$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ), - .D(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [1]), - .E(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [1]), - .Q({ \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 , \$auto$rs_design_edit.cc:682:execute$420.iddr_out [1] }), - .R(\$auto$rs_design_edit.cc:682:execute$420.rst ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:22.11-22.94" *) - I_DDR \$auto$rs_design_edit.cc:682:execute$420.iddr_ist3 ( - .C(\$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ), - .D(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [2]), - .E(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [2]), - .Q({ \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 , \$auto$rs_design_edit.cc:682:execute$420.iddr_out [2] }), - .R(\$auto$rs_design_edit.cc:682:execute$420.rst ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:24.15-24.89" *) - O_BUFT_DS \$auto$rs_design_edit.cc:682:execute$420.o_buft_inst1 ( - .I(\$auto$rs_design_edit.cc:682:execute$420.dffre_out [0]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [0]), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [0]), - .T(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:25.15-25.89" *) - O_BUFT_DS \$auto$rs_design_edit.cc:682:execute$420.o_buft_inst2 ( - .I(\$auto$rs_design_edit.cc:682:execute$420.dffre_out [1]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [1]), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [1]), - .T(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:26.15-26.89" *) - O_BUFT_DS \$auto$rs_design_edit.cc:682:execute$420.o_buft_inst3 ( - .I(\$auto$rs_design_edit.cc:682:execute$420.dffre_out [2]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [2]), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [2]), - .T(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:262:execute$399 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 ), - .O(\$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf1_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf1_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf2_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf2_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf3_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf3_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf4_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf4_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf5_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf5_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.iddr_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.iddr_en [0]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.iddr_en_1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.iddr_en [1]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.iddr_en_2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.iddr_en [2]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.obuft_ds_en1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.obuft_ds_en2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.obuft_ds_en3 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_n ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n [0]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_n [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_n_1 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n [1]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_n [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_n_2 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n [2]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_n [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_p ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [0]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_p [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_p_1 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [1]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_p [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_p_2 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [2]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_p [2]) - ); - assign \$auto$hierarchy.cc:1408:execute$1 = \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 ; - assign \$auto$hierarchy.cc:1408:execute$2 = \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 ; - assign \$auto$hierarchy.cc:1408:execute$3 = \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n = \$iopadmap$q_n ; - assign \$auto$rs_design_edit.cc:682:execute$420.clk = clk; - assign clk_buf_out = \$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ; - assign \$auto$rs_design_edit.cc:682:execute$420.dffre_out = dffre_out; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf1_en = ibuf1_en; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf2_en = ibuf2_en; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf3_en = ibuf3_en; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf4_en = ibuf4_en; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf5_en = ibuf5_en; - assign \$auto$rs_design_edit.cc:682:execute$420.iddr_en = iddr_en; - assign iddr_out = \$auto$rs_design_edit.cc:682:execute$420.iddr_out ; - assign \$auto$rs_design_edit.cc:682:execute$420.in = in; - assign \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 = obuft_ds_en1; - assign \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 = obuft_ds_en2; - assign \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 = obuft_ds_en3; - assign q_n = \$auto$rs_design_edit.cc:682:execute$420.q_n ; - assign q_p = \$auto$rs_design_edit.cc:682:execute$420.q_p ; - assign \$auto$rs_design_edit.cc:682:execute$420.rst = rst; - assign rst_i_buf_out = \$auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out ; -endmodule diff --git a/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_synth.eblif b/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_synth.eblif deleted file mode 100644 index 7d7035f76..000000000 --- a/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_synth.eblif +++ /dev/null @@ -1,123 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model primitive_example_design_5 -.inputs in[0] in[1] in[2] ibuf2_en rst clk ibuf1_en ibuf3_en ibuf4_en ibuf5_en obuft_ds_en1 obuft_ds_en2 obuft_ds_en3 iddr_en[0] iddr_en[1] iddr_en[2] -.outputs q_p[0] q_p[1] q_p[2] q_n[0] q_n[1] q_n[2] -.names $false -.names $true -1 -.names $undef -.subckt fabric_primitive_example_design_5 $auto$hierarchy.cc:1408:execute$1=$auto$hierarchy.cc:1408:execute$1 $auto$hierarchy.cc:1408:execute$2=$auto$hierarchy.cc:1408:execute$2 $auto$hierarchy.cc:1408:execute$3=$auto$hierarchy.cc:1408:execute$3 $iopadmap$q_n[0]=$iopadmap$q_n[0] $iopadmap$q_n[1]=$iopadmap$q_n[1] $iopadmap$q_n[2]=$iopadmap$q_n[2] clk_buf_out=clk_buf_out dffre_out[0]=dffre_out[0] dffre_out[1]=dffre_out[1] dffre_out[2]=dffre_out[2] iddr_out[0]=iddr_out[0] iddr_out[1]=iddr_out[1] iddr_out[2]=iddr_out[2] rst_i_buf_out=rst_i_buf_out -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en I=$auto$rs_design_edit.cc:682:execute$420.clk O=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en I=$auto$rs_design_edit.cc:682:execute$420.in[0] O=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[0] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en I=$auto$rs_design_edit.cc:682:execute$420.in[1] O=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[1] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en I=$auto$rs_design_edit.cc:682:execute$420.in[2] O=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[2] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en I=$auto$rs_design_edit.cc:682:execute$420.rst O=$auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out -.subckt I_DDR C=$auto$rs_design_edit.cc:682:execute$420.clk_buf_out D=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[0] E=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[0] Q[0]=$auto$rs_design_edit.cc:682:execute$420.iddr_out[0] Q[1]=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 R=$auto$rs_design_edit.cc:682:execute$420.rst -.subckt I_DDR C=$auto$rs_design_edit.cc:682:execute$420.clk_buf_out D=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[1] E=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[1] Q[0]=$auto$rs_design_edit.cc:682:execute$420.iddr_out[1] Q[1]=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 R=$auto$rs_design_edit.cc:682:execute$420.rst -.subckt I_DDR C=$auto$rs_design_edit.cc:682:execute$420.clk_buf_out D=$auto$rs_design_edit.cc:682:execute$420.i_buf_out[2] E=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[2] Q[0]=$auto$rs_design_edit.cc:682:execute$420.iddr_out[2] Q[1]=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 R=$auto$rs_design_edit.cc:682:execute$420.rst -.subckt O_BUFT_DS I=$auto$rs_design_edit.cc:682:execute$420.dffre_out[0] O_N=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[0] O_P=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[0] T=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 -.subckt O_BUFT_DS I=$auto$rs_design_edit.cc:682:execute$420.dffre_out[1] O_N=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[1] O_P=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[1] T=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 -.subckt O_BUFT_DS I=$auto$rs_design_edit.cc:682:execute$420.dffre_out[2] O_N=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[2] O_P=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[2] T=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 O=$auto$rs_design_edit.cc:682:execute$420.clk_buf_out -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf1_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf2_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf3_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf4_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.ibuf5_en O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.iddr_en[0] O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[0] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.iddr_en[1] O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[1] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.iddr_en[2] O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en[2] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 O=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[0] O=$auto$rs_design_edit.cc:682:execute$420.q_n[0] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[1] O=$auto$rs_design_edit.cc:682:execute$420.q_n[1] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[2] O=$auto$rs_design_edit.cc:682:execute$420.q_n[2] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[0] O=$auto$rs_design_edit.cc:682:execute$420.q_p[0] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[1] O=$auto$rs_design_edit.cc:682:execute$420.q_p[1] -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p[2] O=$auto$rs_design_edit.cc:682:execute$420.q_p[2] -.names $flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 $auto$hierarchy.cc:1408:execute$1 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 $auto$hierarchy.cc:1408:execute$2 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 $auto$hierarchy.cc:1408:execute$3 -1 1 -.names $iopadmap$q_n[0] $flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[0] -1 1 -.names $iopadmap$q_n[1] $flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[1] -1 1 -.names $iopadmap$q_n[2] $flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n[2] -1 1 -.names clk $auto$rs_design_edit.cc:682:execute$420.clk -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.clk_buf_out clk_buf_out -1 1 -.names dffre_out[0] $auto$rs_design_edit.cc:682:execute$420.dffre_out[0] -1 1 -.names dffre_out[1] $auto$rs_design_edit.cc:682:execute$420.dffre_out[1] -1 1 -.names dffre_out[2] $auto$rs_design_edit.cc:682:execute$420.dffre_out[2] -1 1 -.names ibuf1_en $auto$rs_design_edit.cc:682:execute$420.ibuf1_en -1 1 -.names ibuf2_en $auto$rs_design_edit.cc:682:execute$420.ibuf2_en -1 1 -.names ibuf3_en $auto$rs_design_edit.cc:682:execute$420.ibuf3_en -1 1 -.names ibuf4_en $auto$rs_design_edit.cc:682:execute$420.ibuf4_en -1 1 -.names ibuf5_en $auto$rs_design_edit.cc:682:execute$420.ibuf5_en -1 1 -.names iddr_en[0] $auto$rs_design_edit.cc:682:execute$420.iddr_en[0] -1 1 -.names iddr_en[1] $auto$rs_design_edit.cc:682:execute$420.iddr_en[1] -1 1 -.names iddr_en[2] $auto$rs_design_edit.cc:682:execute$420.iddr_en[2] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.iddr_out[0] iddr_out[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.iddr_out[1] iddr_out[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.iddr_out[2] iddr_out[2] -1 1 -.names in[0] $auto$rs_design_edit.cc:682:execute$420.in[0] -1 1 -.names in[1] $auto$rs_design_edit.cc:682:execute$420.in[1] -1 1 -.names in[2] $auto$rs_design_edit.cc:682:execute$420.in[2] -1 1 -.names obuft_ds_en1 $auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 -1 1 -.names obuft_ds_en2 $auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 -1 1 -.names obuft_ds_en3 $auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_n[0] q_n[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_n[1] q_n[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_n[2] q_n[2] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_p[0] q_p[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_p[1] q_p[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.q_p[2] q_p[2] -1 1 -.names rst $auto$rs_design_edit.cc:682:execute$420.rst -1 1 -.names $auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out rst_i_buf_out -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_synth.v b/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_synth.v deleted file mode 100644 index 304932472..000000000 --- a/design_edit/Tests/primitive_example_design_5/gold/wrapper_primitive_example_design_5_post_synth.v +++ /dev/null @@ -1,420 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module primitive_example_design_5(in, ibuf2_en, rst, clk, ibuf1_en, ibuf3_en, ibuf4_en, ibuf5_en, obuft_ds_en1, obuft_ds_en2, obuft_ds_en3, iddr_en, q_p, q_n); - input ibuf1_en; - input obuft_ds_en2; - input obuft_ds_en3; - output [2:0] q_n; - input clk; - input [2:0] iddr_en; - output [2:0] q_p; - input ibuf5_en; - input ibuf4_en; - input rst; - input obuft_ds_en1; - input ibuf2_en; - input [2:0] in; - input ibuf3_en; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 ; - (* unused_bits = "0" *) - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 ; - (* unused_bits = "0" *) - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 ; - (* unused_bits = "0" *) - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en ; - wire [2:0] \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 ; - wire [2:0] \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n ; - wire [2:0] \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p ; - (* src = "./rtl/primitive_example_design_5.v:16.10-16.23" *) - wire \$auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out ; - (* src = "./rtl/primitive_example_design_5.v:4.11-4.14" *) - wire \$auto$rs_design_edit.cc:682:execute$420.rst ; - (* src = "./rtl/primitive_example_design_5.v:9.18-9.21" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.q_p ; - (* src = "./rtl/primitive_example_design_5.v:6.38-6.46" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf4_en ; - (* src = "./rtl/primitive_example_design_5.v:10.18-10.21" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.q_n ; - (* src = "./rtl/primitive_example_design_5.v:7.37-7.49" *) - wire \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 ; - (* src = "./rtl/primitive_example_design_5.v:7.24-7.36" *) - wire \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 ; - (* src = "./rtl/primitive_example_design_5.v:3.11-3.19" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf2_en ; - (* src = "./rtl/primitive_example_design_5.v:18.50-18.61" *) - wire \$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ; - (* src = "./rtl/primitive_example_design_5.v:7.11-7.23" *) - wire \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 ; - (* src = "./rtl/primitive_example_design_5.v:15.16-15.25" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.i_buf_out ; - (* src = "./rtl/primitive_example_design_5.v:6.29-6.37" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf3_en ; - (* src = "./rtl/primitive_example_design_5.v:6.11-6.19" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf1_en ; - (* src = "./rtl/primitive_example_design_5.v:2.17-2.19" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.in ; - (* src = "./rtl/primitive_example_design_5.v:14.16-14.25" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.dffre_out ; - (* src = "./rtl/primitive_example_design_5.v:5.11-5.14" *) - wire \$auto$rs_design_edit.cc:682:execute$420.clk ; - (* src = "./rtl/primitive_example_design_5.v:13.16-13.24" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.iddr_out ; - (* src = "./rtl/primitive_example_design_5.v:8.17-8.24" *) - wire [2:0] \$auto$rs_design_edit.cc:682:execute$420.iddr_en ; - (* src = "./rtl/primitive_example_design_5.v:6.47-6.55" *) - wire \$auto$rs_design_edit.cc:682:execute$420.ibuf5_en ; - (* src = "./rtl/primitive_example_design_5.v:6.11-6.19" *) - (* src = "./rtl/primitive_example_design_5.v:6.11-6.19" *) - wire ibuf1_en; - (* src = "./rtl/primitive_example_design_5.v:7.24-7.36" *) - (* src = "./rtl/primitive_example_design_5.v:7.24-7.36" *) - wire obuft_ds_en2; - (* src = "./rtl/primitive_example_design_5.v:7.37-7.49" *) - (* src = "./rtl/primitive_example_design_5.v:7.37-7.49" *) - wire obuft_ds_en3; - (* src = "./rtl/primitive_example_design_5.v:10.18-10.21" *) - (* src = "./rtl/primitive_example_design_5.v:10.18-10.21" *) - wire [2:0] q_n; - (* src = "./rtl/primitive_example_design_5.v:13.16-13.24" *) - wire [2:0] iddr_out; - (* src = "./rtl/primitive_example_design_5.v:5.11-5.14" *) - (* src = "./rtl/primitive_example_design_5.v:5.11-5.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_5.v:8.17-8.24" *) - (* src = "./rtl/primitive_example_design_5.v:8.17-8.24" *) - wire [2:0] iddr_en; - (* src = "./rtl/primitive_example_design_5.v:14.16-14.25" *) - wire [2:0] dffre_out; - (* src = "./rtl/primitive_example_design_5.v:9.18-9.21" *) - (* src = "./rtl/primitive_example_design_5.v:9.18-9.21" *) - wire [2:0] q_p; - (* src = "./rtl/primitive_example_design_5.v:6.47-6.55" *) - (* src = "./rtl/primitive_example_design_5.v:6.47-6.55" *) - wire ibuf5_en; - (* src = "./rtl/primitive_example_design_5.v:18.50-18.61" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_5.v:6.38-6.46" *) - (* src = "./rtl/primitive_example_design_5.v:6.38-6.46" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_5.v:4.11-4.14" *) - (* src = "./rtl/primitive_example_design_5.v:4.11-4.14" *) - wire rst; - (* src = "./rtl/primitive_example_design_5.v:7.11-7.23" *) - (* src = "./rtl/primitive_example_design_5.v:7.11-7.23" *) - wire obuft_ds_en1; - (* src = "./rtl/primitive_example_design_5.v:3.11-3.19" *) - (* src = "./rtl/primitive_example_design_5.v:3.11-3.19" *) - wire ibuf2_en; - (* src = "./rtl/primitive_example_design_5.v:2.17-2.19" *) - (* src = "./rtl/primitive_example_design_5.v:2.17-2.19" *) - wire [2:0] in; - (* src = "./rtl/primitive_example_design_5.v:16.10-16.23" *) - wire rst_i_buf_out; - (* src = "./rtl/primitive_example_design_5.v:15.16-15.25" *) - wire [2:0] i_buf_out; - (* src = "./rtl/primitive_example_design_5.v:6.29-6.37" *) - (* src = "./rtl/primitive_example_design_5.v:6.29-6.37" *) - wire ibuf3_en; - wire [2:0] \$iopadmap$q_p ; - wire [2:0] \$iopadmap$q_n ; - wire \$iopadmap$obuft_ds_en3 ; - wire \$iopadmap$obuft_ds_en2 ; - wire \$iopadmap$obuft_ds_en1 ; - wire [2:0] \$iopadmap$iddr_en ; - wire \$iopadmap$ibuf5_en ; - wire \$iopadmap$ibuf4_en ; - wire \$iopadmap$ibuf3_en ; - wire \$iopadmap$ibuf2_en ; - wire \$iopadmap$ibuf1_en ; - (* unused_bits = "0" *) - wire \$auto$hierarchy.cc:1408:execute$3 ; - (* unused_bits = "0" *) - wire \$auto$hierarchy.cc:1408:execute$2 ; - (* unused_bits = "0" *) - wire \$auto$hierarchy.cc:1408:execute$1 ; - wire \$auto$clkbufmap.cc:263:execute$400 ; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf1_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf1_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf2_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf2_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf3_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf3_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf4_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf4_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.ibuf5_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.ibuf5_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.iddr_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.iddr_en [0]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.iddr_en_1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.iddr_en [1]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.iddr_en_2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.iddr_en [2]), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.obuft_ds_en1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.obuft_ds_en2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.obuft_ds_en3 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_n ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n [0]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_n [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_n_1 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n [1]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_n [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_n_2 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n [2]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_n [2]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_p ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [0]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_p [0]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_p_1 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [1]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_p [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$primitive_example_design_5.q_p_2 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [2]), - .O(\$auto$rs_design_edit.cc:682:execute$420.q_p [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:18.11-18.63" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.clk_buf_inst ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf1_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:24.15-24.89" *) - O_BUFT_DS \$auto$rs_design_edit.cc:682:execute$420.o_buft_inst1 ( - .I(\$auto$rs_design_edit.cc:682:execute$420.dffre_out [0]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [0]), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [0]), - .T(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en1 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:25.15-25.89" *) - O_BUFT_DS \$auto$rs_design_edit.cc:682:execute$420.o_buft_inst2 ( - .I(\$auto$rs_design_edit.cc:682:execute$420.dffre_out [1]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [1]), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [1]), - .T(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en2 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:26.15-26.89" *) - O_BUFT_DS \$auto$rs_design_edit.cc:682:execute$420.o_buft_inst3 ( - .I(\$auto$rs_design_edit.cc:682:execute$420.dffre_out [2]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [2]), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_p [2]), - .T(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$obuft_ds_en3 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:28.11-28.64" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.ibuf_inst1 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf2_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.in [0]), - .O(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:29.11-29.64" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.ibuf_inst2 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf3_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.in [1]), - .O(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:30.11-30.64" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.ibuf_inst3 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf4_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.in [2]), - .O(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:31.11-31.63" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$420.ibuf_inst4 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$ibuf5_en ), - .I(\$auto$rs_design_edit.cc:682:execute$420.rst ), - .O(\$auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:20.11-20.94" *) - I_DDR \$auto$rs_design_edit.cc:682:execute$420.iddr_ist1 ( - .C(\$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ), - .D(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [0]), - .E(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [0]), - .Q({ \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 , \$auto$rs_design_edit.cc:682:execute$420.iddr_out [0] }), - .R(\$auto$rs_design_edit.cc:682:execute$420.rst ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:21.11-21.94" *) - I_DDR \$auto$rs_design_edit.cc:682:execute$420.iddr_ist2 ( - .C(\$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ), - .D(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [1]), - .E(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [1]), - .Q({ \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 , \$auto$rs_design_edit.cc:682:execute$420.iddr_out [1] }), - .R(\$auto$rs_design_edit.cc:682:execute$420.rst ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_5.v:22.11-22.94" *) - I_DDR \$auto$rs_design_edit.cc:682:execute$420.iddr_ist3 ( - .C(\$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ), - .D(\$auto$rs_design_edit.cc:682:execute$420.i_buf_out [2]), - .E(\$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$iddr_en [2]), - .Q({ \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 , \$auto$rs_design_edit.cc:682:execute$420.iddr_out [2] }), - .R(\$auto$rs_design_edit.cc:682:execute$420.rst ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:262:execute$399 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$clkbufmap.cc:263:execute$400 ), - .O(\$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ) - ); - fabric_primitive_example_design_5 \$auto$rs_design_edit.cc:680:execute$419 ( - .\$auto$hierarchy.cc:1408:execute$1 (\$auto$hierarchy.cc:1408:execute$1 ), - .\$auto$hierarchy.cc:1408:execute$2 (\$auto$hierarchy.cc:1408:execute$2 ), - .\$auto$hierarchy.cc:1408:execute$3 (\$auto$hierarchy.cc:1408:execute$3 ), - .\$iopadmap$q_n (\$iopadmap$q_n ), - .clk_buf_out(clk_buf_out), - .dffre_out(dffre_out), - .iddr_out(iddr_out), - .rst_i_buf_out(rst_i_buf_out) - ); - assign \$auto$hierarchy.cc:1408:execute$1 = \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$1 ; - assign \$auto$hierarchy.cc:1408:execute$2 = \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$2 ; - assign \$auto$hierarchy.cc:1408:execute$3 = \$flatten$auto$rs_design_edit.cc:682:execute$420.$auto$hierarchy.cc:1408:execute$3 ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$420.$iopadmap$q_n = \$iopadmap$q_n ; - assign \$auto$rs_design_edit.cc:682:execute$420.clk = clk; - assign clk_buf_out = \$auto$rs_design_edit.cc:682:execute$420.clk_buf_out ; - assign \$auto$rs_design_edit.cc:682:execute$420.dffre_out = dffre_out; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf1_en = ibuf1_en; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf2_en = ibuf2_en; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf3_en = ibuf3_en; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf4_en = ibuf4_en; - assign \$auto$rs_design_edit.cc:682:execute$420.ibuf5_en = ibuf5_en; - assign \$auto$rs_design_edit.cc:682:execute$420.iddr_en = iddr_en; - assign iddr_out = \$auto$rs_design_edit.cc:682:execute$420.iddr_out ; - assign \$auto$rs_design_edit.cc:682:execute$420.in = in; - assign \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en1 = obuft_ds_en1; - assign \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en2 = obuft_ds_en2; - assign \$auto$rs_design_edit.cc:682:execute$420.obuft_ds_en3 = obuft_ds_en3; - assign q_n = \$auto$rs_design_edit.cc:682:execute$420.q_n ; - assign q_p = \$auto$rs_design_edit.cc:682:execute$420.q_p ; - assign \$auto$rs_design_edit.cc:682:execute$420.rst = rst; - assign rst_i_buf_out = \$auto$rs_design_edit.cc:682:execute$420.rst_i_buf_out ; -endmodule diff --git a/design_edit/Tests/primitive_example_design_5/new_sdc.txt b/design_edit/Tests/primitive_example_design_5/new_sdc.txt deleted file mode 100644 index 6b10b0bd4..000000000 --- a/design_edit/Tests/primitive_example_design_5/new_sdc.txt +++ /dev/null @@ -1,88 +0,0 @@ -name: HR_5_0_5P - pin: q_n[2] - properties: - mode : Mode_BP_SDR_A_TX -name: HR_5_0_1P - pin: q_p[1] - properties: - mode : Mode_BP_SDR_A_TX -name: HR_5_0_4P - pin: q_n[1] - properties: - mode : Mode_BP_SDR_A_TX -name: HR_2_0_0P - pin: clk - properties: - mode : Mode_BP_SDR_A_RX -name: HR_5_0_2P - pin: q_p[2] - properties: - mode : Mode_BP_SDR_A_TX -name: HR_3_1_3P - pin: iddr_en[1] - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_1P - pin: in[1] - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_5P - pin: ibuf2_en - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_2P - pin: in[2] - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_0P - pin: in[0] - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_3P - pin: ibuf2_en - properties: - mode : Mode_BP_SDR_A_RX -name: HR_5_0_3P - pin: q_n[0] - properties: - mode : Mode_BP_SDR_A_TX -name: HR_3_0_6P - pin: ibuf3_en - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_4P - pin: ibuf1_en - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_7P - pin: ibuf4_en - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_8P - pin: ibuf5_en - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_0_9P - pin: obuft_ds_en1 - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_1_4P - pin: iddr_en[2] - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_1_1P - pin: obuft_ds_en3 - properties: - mode : Mode_BP_SDR_A_RX -name: HR_3_1_2P - pin: iddr_en[0] - properties: - mode : Mode_BP_SDR_A_RX -name: HR_5_0_0P - pin: q_p[0] - properties: - mode : Mode_BP_SDR_A_TX -name: HR_3_1_0P - pin: obuft_ds_en2 - properties: - mode : Mode_BP_SDR_A_RX diff --git a/design_edit/Tests/primitive_example_design_5/primitive_example_design_5.pin b/design_edit/Tests/primitive_example_design_5/primitive_example_design_5.pin deleted file mode 100644 index 3c2611667..000000000 --- a/design_edit/Tests/primitive_example_design_5/primitive_example_design_5.pin +++ /dev/null @@ -1,65 +0,0 @@ -set_property mode Mode_BP_SDR_A_RX HR_3_0_0P -set_pin_loc in[0] HR_3_0_0P - -set_property mode Mode_BP_SDR_A_RX HR_3_0_1P -set_pin_loc in[1] HR_3_0_1P - -set_property mode Mode_BP_SDR_A_RX HR_3_0_2P -set_pin_loc in[2] HR_3_0_2P - -set_property mode Mode_BP_SDR_A_RX HR_3_0_3P -set_pin_loc ibuf2_en HR_3_0_3P - -set_property mode Mode_BP_SDR_A_RX HR_3_0_4P -set_pin_loc ibuf1_en HR_3_0_4P - -set_property mode Mode_BP_SDR_A_RX HR_3_0_5P -set_pin_loc ibuf2_en HR_3_0_5P - -set_property mode Mode_BP_SDR_A_RX HR_3_0_6P -set_pin_loc ibuf3_en HR_3_0_6P - -set_property mode Mode_BP_SDR_A_RX HR_3_0_7P -set_pin_loc ibuf4_en HR_3_0_7P - -set_property mode Mode_BP_SDR_A_RX HR_3_0_8P -set_pin_loc ibuf5_en HR_3_0_8P - -set_property mode Mode_BP_SDR_A_RX HR_3_0_9P -set_pin_loc obuft_ds_en1 HR_3_0_9P - -set_property mode Mode_BP_SDR_A_RX HR_3_1_0P -set_pin_loc obuft_ds_en2 HR_3_1_0P - -set_property mode Mode_BP_SDR_A_RX HR_3_1_1P -set_pin_loc obuft_ds_en3 HR_3_1_1P - -set_property mode Mode_BP_SDR_A_RX HR_3_1_2P -set_pin_loc iddr_en[0] HR_3_1_2P - -set_property mode Mode_BP_SDR_A_RX HR_3_1_3P -set_pin_loc iddr_en[1] HR_3_1_3P - -set_property mode Mode_BP_SDR_A_RX HR_3_1_4P -set_pin_loc iddr_en[2] HR_3_1_4P - -set_property mode Mode_BP_SDR_A_RX HR_2_0_0P -set_pin_loc clk HR_2_0_0P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_0P -set_pin_loc q_p[0] HR_5_0_0P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_1P -set_pin_loc q_p[1] HR_5_0_1P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_2P -set_pin_loc q_p[2] HR_5_0_2P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_3P -set_pin_loc q_n[0] HR_5_0_3P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_4P -set_pin_loc q_n[1] HR_5_0_4P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_5P -set_pin_loc q_n[2] HR_5_0_5P \ No newline at end of file diff --git a/design_edit/Tests/primitive_example_design_5/primitive_example_design_5.ys b/design_edit/Tests/primitive_example_design_5/primitive_example_design_5.ys deleted file mode 100644 index d8a86f59f..000000000 --- a/design_edit/Tests/primitive_example_design_5/primitive_example_design_5.ys +++ /dev/null @@ -1,19 +0,0 @@ -# Yosys synthesis script for O_SERDES_primitive_inst -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./rtl/primitive_example_design_5.v - - -# Technology mapping -hierarchy -top primitive_example_design_5 - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal delay -effort high -carry auto -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -sdc primitive_example_design_5.pin -json ./tmp/io_config.json -w ./tmp//wrapper_primitive_example_design_5_post_synth.v ./tmp//wrapper_primitive_example_design_5_post_synth.eblif -pr ./tmp//wrapper_primitive_example_design_5_post_route.v ./tmp//wrapper_primitive_example_design_5_post_route.eblif -write_verilog -noexpr -nodec -norename -v ./tmp//primitive_example_design_5_post_synth.v -write_blif -param ./tmp//primitive_example_design_5_post_synth.eblif \ No newline at end of file diff --git a/design_edit/Tests/primitive_example_design_5/rtl/primitive_example_design_5.v b/design_edit/Tests/primitive_example_design_5/rtl/primitive_example_design_5.v deleted file mode 100644 index 060444f56..000000000 --- a/design_edit/Tests/primitive_example_design_5/rtl/primitive_example_design_5.v +++ /dev/null @@ -1,37 +0,0 @@ -module primitive_example_design_5( - input [2:0] in, - input ibuf2_en, - input rst, - input clk, - input ibuf1_en,ibuf2_en,ibuf3_en,ibuf4_en,ibuf5_en, - input obuft_ds_en1,obuft_ds_en2,obuft_ds_en3, - input [2:0] iddr_en, - output [2:0] q_p, - output [2:0] q_n -); - - wire [2:0] iddr_out; - wire [2:0] dffre_out; - wire [2:0] i_buf_out; - wire rst_i_buf_out; - - I_BUF clk_buf_inst (.I(clk),.EN(ibuf1_en),.O(clk_buf_out)); - - I_DDR iddr_ist1 (.D(i_buf_out[0]),.R(rst),.E(iddr_en[0]),.C(clk_buf_out),.Q(iddr_out[0])); - I_DDR iddr_ist2 (.D(i_buf_out[1]),.R(rst),.E(iddr_en[1]),.C(clk_buf_out),.Q(iddr_out[1])); - I_DDR iddr_ist3 (.D(i_buf_out[2]),.R(rst),.E(iddr_en[2]),.C(clk_buf_out),.Q(iddr_out[2])); - - O_BUFT_DS o_buft_inst1 (.I(dffre_out[0]),.T(obuft_ds_en1),.O_P(q_p[0]),.O_N(q_p[0])); - O_BUFT_DS o_buft_inst2 (.I(dffre_out[1]),.T(obuft_ds_en2),.O_P(q_p[1]),.O_N(q_p[1])); - O_BUFT_DS o_buft_inst3 (.I(dffre_out[2]),.T(obuft_ds_en3),.O_P(q_p[2]),.O_N(q_p[2])); - - I_BUF ibuf_inst1 (.I(in[0]),.EN(ibuf2_en),.O(i_buf_out[0])); - I_BUF ibuf_inst2 (.I(in[1]),.EN(ibuf3_en),.O(i_buf_out[1])); - I_BUF ibuf_inst3 (.I(in[2]),.EN(ibuf4_en),.O(i_buf_out[2])); - I_BUF ibuf_inst4 (.I(rst),.EN(ibuf5_en),.O(rst_i_buf_out)); - - DFFRE ff_inst1 (.D(iddr_out[0]),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffre_out[0])); - DFFRE ff_inst2 (.D(iddr_out[1]),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffre_out[1])); - DFFRE ff_inst3 (.D(iddr_out[2]),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffre_out[2])); - -endmodule diff --git a/design_edit/Tests/primitive_example_design_5/synthesis/primitive_example_design_5_post_synth.eblif b/design_edit/Tests/primitive_example_design_5/synthesis/primitive_example_design_5_post_synth.eblif deleted file mode 100644 index d896148ec..000000000 --- a/design_edit/Tests/primitive_example_design_5/synthesis/primitive_example_design_5_post_synth.eblif +++ /dev/null @@ -1,30 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model primitive_example_design_5 -.inputs in[0] in[1] in[2] ibuf2_en rst clk ibuf1_en ibuf3_en ibuf4_en ibuf5_en obuft_ds_en1 obuft_ds_en2 obuft_ds_en3 iddr_en[0] iddr_en[1] iddr_en[2] -.outputs q_p[0] q_p[1] q_p[2] q_n[0] q_n[1] q_n[2] -.names $false -.names $true -1 -.names $undef -.subckt I_BUF EN=ibuf1_en I=clk O=clk_buf_out -.subckt DFFRE C=clk_buf_out D=iddr_out[0] E=$true Q=dffre_out[0] R=rst_i_buf_out -.subckt DFFRE C=clk_buf_out D=iddr_out[1] E=$true Q=dffre_out[1] R=rst_i_buf_out -.subckt DFFRE C=clk_buf_out D=iddr_out[2] E=$true Q=dffre_out[2] R=rst_i_buf_out -.subckt I_BUF EN=ibuf2_en I=in[0] O=i_buf_out[0] -.subckt I_BUF EN=ibuf3_en I=in[1] O=i_buf_out[1] -.subckt I_BUF EN=ibuf4_en I=in[2] O=i_buf_out[2] -.subckt I_BUF EN=ibuf5_en I=rst O=rst_i_buf_out -.subckt I_DDR C=clk_buf_out D=i_buf_out[0] E=iddr_en[0] Q[0]=iddr_out[0] Q[1]=$auto$hierarchy.cc:1408:execute$3 R=rst -.subckt I_DDR C=clk_buf_out D=i_buf_out[1] E=iddr_en[1] Q[0]=iddr_out[1] Q[1]=$auto$hierarchy.cc:1408:execute$2 R=rst -.subckt I_DDR C=clk_buf_out D=i_buf_out[2] E=iddr_en[2] Q[0]=iddr_out[2] Q[1]=$auto$hierarchy.cc:1408:execute$1 R=rst -.subckt O_BUFT_DS I=dffre_out[0] O_N=q_p[0] O_P=q_p[0] T=obuft_ds_en1 -.subckt O_BUFT_DS I=dffre_out[1] O_N=q_p[1] O_P=q_p[1] T=obuft_ds_en2 -.subckt O_BUFT_DS I=dffre_out[2] O_N=q_p[2] O_P=q_p[2] T=obuft_ds_en3 -.names $undef q_n[0] -1 1 -.names $undef q_n[1] -1 1 -.names $undef q_n[2] -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_5/synthesis/primitive_example_design_5_post_synth.v b/design_edit/Tests/primitive_example_design_5/synthesis/primitive_example_design_5_post_synth.v deleted file mode 100644 index a5af7c946..000000000 --- a/design_edit/Tests/primitive_example_design_5/synthesis/primitive_example_design_5_post_synth.v +++ /dev/null @@ -1,190 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module primitive_example_design_5(in, ibuf2_en, rst, clk, ibuf1_en, ibuf3_en, ibuf4_en, ibuf5_en, obuft_ds_en1, obuft_ds_en2, obuft_ds_en3, iddr_en, q_p, q_n); - input clk; - input ibuf1_en; - input ibuf2_en; - input ibuf3_en; - input ibuf4_en; - input ibuf5_en; - input [2:0] iddr_en; - input [2:0] in; - input obuft_ds_en1; - input obuft_ds_en2; - input obuft_ds_en3; - output [2:0] q_n; - output [2:0] q_p; - input rst; - (* unused_bits = "0" *) - wire _0_; - (* unused_bits = "0" *) - wire _1_; - (* unused_bits = "0" *) - wire _2_; - (* src = "./rtl/primitive_example_design_5.v:5.11-5.14" *) - (* src = "./rtl/primitive_example_design_5.v:5.11-5.14" *) - wire clk; - (* src = "./rtl/primitive_example_design_5.v:18.50-18.61" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_5.v:14.16-14.25" *) - wire [2:0] dffre_out; - (* src = "./rtl/primitive_example_design_5.v:15.16-15.25" *) - wire [2:0] i_buf_out; - (* src = "./rtl/primitive_example_design_5.v:6.11-6.19" *) - (* src = "./rtl/primitive_example_design_5.v:6.11-6.19" *) - wire ibuf1_en; - (* src = "./rtl/primitive_example_design_5.v:3.11-3.19" *) - (* src = "./rtl/primitive_example_design_5.v:3.11-3.19" *) - wire ibuf2_en; - (* src = "./rtl/primitive_example_design_5.v:6.29-6.37" *) - (* src = "./rtl/primitive_example_design_5.v:6.29-6.37" *) - wire ibuf3_en; - (* src = "./rtl/primitive_example_design_5.v:6.38-6.46" *) - (* src = "./rtl/primitive_example_design_5.v:6.38-6.46" *) - wire ibuf4_en; - (* src = "./rtl/primitive_example_design_5.v:6.47-6.55" *) - (* src = "./rtl/primitive_example_design_5.v:6.47-6.55" *) - wire ibuf5_en; - (* src = "./rtl/primitive_example_design_5.v:8.17-8.24" *) - (* src = "./rtl/primitive_example_design_5.v:8.17-8.24" *) - wire [2:0] iddr_en; - (* src = "./rtl/primitive_example_design_5.v:13.16-13.24" *) - wire [2:0] iddr_out; - (* src = "./rtl/primitive_example_design_5.v:2.17-2.19" *) - (* src = "./rtl/primitive_example_design_5.v:2.17-2.19" *) - wire [2:0] in; - (* src = "./rtl/primitive_example_design_5.v:7.11-7.23" *) - (* src = "./rtl/primitive_example_design_5.v:7.11-7.23" *) - wire obuft_ds_en1; - (* src = "./rtl/primitive_example_design_5.v:7.24-7.36" *) - (* src = "./rtl/primitive_example_design_5.v:7.24-7.36" *) - wire obuft_ds_en2; - (* src = "./rtl/primitive_example_design_5.v:7.37-7.49" *) - (* src = "./rtl/primitive_example_design_5.v:7.37-7.49" *) - wire obuft_ds_en3; - (* src = "./rtl/primitive_example_design_5.v:10.18-10.21" *) - (* src = "./rtl/primitive_example_design_5.v:10.18-10.21" *) - wire [2:0] q_n; - (* src = "./rtl/primitive_example_design_5.v:9.18-9.21" *) - (* src = "./rtl/primitive_example_design_5.v:9.18-9.21" *) - wire [2:0] q_p; - (* src = "./rtl/primitive_example_design_5.v:4.11-4.14" *) - (* src = "./rtl/primitive_example_design_5.v:4.11-4.14" *) - wire rst; - (* src = "./rtl/primitive_example_design_5.v:16.10-16.23" *) - wire rst_i_buf_out; - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:18.11-18.63" *) - I_BUF clk_buf_inst ( - .EN(ibuf1_en), - .I(clk), - .O(clk_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:33.11-33.97" *) - DFFRE ff_inst1 ( - .C(clk_buf_out), - .D(iddr_out[0]), - .E(1'h1), - .Q(dffre_out[0]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:34.11-34.97" *) - DFFRE ff_inst2 ( - .C(clk_buf_out), - .D(iddr_out[1]), - .E(1'h1), - .Q(dffre_out[1]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:35.11-35.97" *) - DFFRE ff_inst3 ( - .C(clk_buf_out), - .D(iddr_out[2]), - .E(1'h1), - .Q(dffre_out[2]), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:28.11-28.64" *) - I_BUF ibuf_inst1 ( - .EN(ibuf2_en), - .I(in[0]), - .O(i_buf_out[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:29.11-29.64" *) - I_BUF ibuf_inst2 ( - .EN(ibuf3_en), - .I(in[1]), - .O(i_buf_out[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:30.11-30.64" *) - I_BUF ibuf_inst3 ( - .EN(ibuf4_en), - .I(in[2]), - .O(i_buf_out[2]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:31.11-31.63" *) - I_BUF ibuf_inst4 ( - .EN(ibuf5_en), - .I(rst), - .O(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:20.11-20.94" *) - I_DDR iddr_ist1 ( - .C(clk_buf_out), - .D(i_buf_out[0]), - .E(iddr_en[0]), - .Q({ _2_, iddr_out[0] }), - .R(rst) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:21.11-21.94" *) - I_DDR iddr_ist2 ( - .C(clk_buf_out), - .D(i_buf_out[1]), - .E(iddr_en[1]), - .Q({ _1_, iddr_out[1] }), - .R(rst) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:22.11-22.94" *) - I_DDR iddr_ist3 ( - .C(clk_buf_out), - .D(i_buf_out[2]), - .E(iddr_en[2]), - .Q({ _0_, iddr_out[2] }), - .R(rst) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:24.15-24.89" *) - O_BUFT_DS o_buft_inst1 ( - .I(dffre_out[0]), - .O_N(q_p[0]), - .O_P(q_p[0]), - .T(obuft_ds_en1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:25.15-25.89" *) - O_BUFT_DS o_buft_inst2 ( - .I(dffre_out[1]), - .O_N(q_p[1]), - .O_P(q_p[1]), - .T(obuft_ds_en2) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_5.v:26.15-26.89" *) - O_BUFT_DS o_buft_inst3 ( - .I(dffre_out[2]), - .O_N(q_p[2]), - .O_P(q_p[2]), - .T(obuft_ds_en3) - ); - assign q_n = 3'hx; -endmodule diff --git a/design_edit/Tests/primitive_example_design_6/gold/interface.json b/design_edit/Tests/primitive_example_design_6/gold/interface.json deleted file mode 100644 index b278ca8d8..000000000 --- a/design_edit/Tests/primitive_example_design_6/gold/interface.json +++ /dev/null @@ -1,197 +0,0 @@ -{ - "IO_Instances": { - "clk_buf_inst": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf_oe1", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "clk", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "clk_buf_out", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst1": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf_oe2", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "ibuf_inst2": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf_oe3", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 1, - "msb": 1 - } - ], - "O": [ - { - "Actual": "i_buf_out", - "lsb": 1, - "msb": 1 - } - ] - } - }, - "ibuf_inst4": { - "module": "I_BUF", - "ports": { - "EN": [ - { - "Actual": "ibuf_oe4", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "I": [ - { - "Actual": "rst", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O": [ - { - "Actual": "rst_i_buf_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "iddr_ist1": { - "module": "O_DDR", - "ports": { - "C": [ - { - "Actual": "clk_buf_out", - "lsb": 0, - "msb": 0 - } - ], - "D": [ - { - "Actual": "i_buf_out", - "lsb": 0, - "msb": 1 - } - ], - "E": [ - { - "Actual": "oddr_en", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "Q": [ - { - "Actual": "oddr_out", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "R": [ - { - "Actual": "rst", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - }, - "o_buft_inst1": { - "module": "O_BUFT_DS", - "ports": { - "I": [ - { - "Actual": "in", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_N": [ - { - "Actual": "q_n", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "O_P": [ - { - "Actual": "q_p", - "FUNC": "OUT_DIR", - "lsb": 0, - "msb": 0 - } - ], - "T": [ - { - "Actual": "dffre_out", - "FUNC": "IN_DIR", - "lsb": 0, - "msb": 0 - } - ] - } - } - } -} diff --git a/design_edit/Tests/primitive_example_design_6/gold/io_config.json b/design_edit/Tests/primitive_example_design_6/gold/io_config.json deleted file mode 100644 index df8ba0528..000000000 --- a/design_edit/Tests/primitive_example_design_6/gold/io_config.json +++ /dev/null @@ -1,272 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\clk (index=0, width=1, offset=0)", - " Detect input port \\ibuf_oe1 (index=0, width=1, offset=0)", - " Detect input port \\ibuf_oe2 (index=0, width=1, offset=0)", - " Detect input port \\ibuf_oe3 (index=0, width=1, offset=0)", - " Detect input port \\ibuf_oe4 (index=0, width=1, offset=0)", - " Detect input port \\in (index=0, width=2, offset=0)", - " Detect input port \\in (index=1, width=2, offset=0)", - " Detect input port \\oddr_en (index=0, width=1, offset=0)", - " Detect output port \\q_n (index=0, width=1, offset=0)", - " Detect output port \\q_p (index=0, width=1, offset=0)", - " Detect input port \\rst (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_6.ibuf_oe1", - " Cell port \\I is connected to input port \\ibuf_oe1", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_6.ibuf_oe2", - " Cell port \\I is connected to input port \\ibuf_oe2", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_6.ibuf_oe3", - " Cell port \\I is connected to input port \\ibuf_oe3", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_6.ibuf_oe4", - " Cell port \\I is connected to input port \\ibuf_oe4", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$primitive_example_design_6.oddr_en", - " Cell port \\I is connected to input port \\oddr_en", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_6.q_n", - " Cell port \\O is connected to output port \\q_n", - " Get important connection of cell \\O_BUF $iopadmap$primitive_example_design_6.q_p", - " Cell port \\O is connected to output port \\q_p", - " Get important connection of cell \\I_BUF \\clk_buf_inst", - " Cell port \\I is connected to input port \\clk", - " Get important connection of cell \\I_BUF \\ibuf_inst1", - " Cell port \\I is connected to input port \\in[0]", - " Get important connection of cell \\I_BUF \\ibuf_inst2", - " Cell port \\I is connected to input port \\in[1]", - " Get important connection of cell \\I_BUF \\ibuf_inst4", - " Cell port \\I is connected to input port \\rst", - " Trace Clock Buffer", - " Try \\I_BUF \\clk_buf_inst out connection: $auto$clkbufmap.cc:263:execute$399", - " Connected $auto$clkbufmap.cc:262:execute$398", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_6.ibuf_oe1", - "linked_object" : "ibuf_oe1", - "linked_objects" : { - "ibuf_oe1" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf_oe1", - "O" : "$iopadmap$ibuf_oe1" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_6.ibuf_oe2", - "linked_object" : "ibuf_oe2", - "linked_objects" : { - "ibuf_oe2" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf_oe2", - "O" : "$iopadmap$ibuf_oe2" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_6.ibuf_oe3", - "linked_object" : "ibuf_oe3", - "linked_objects" : { - "ibuf_oe3" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf_oe3", - "O" : "$iopadmap$ibuf_oe3" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_6.ibuf_oe4", - "linked_object" : "ibuf_oe4", - "linked_objects" : { - "ibuf_oe4" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "ibuf_oe4", - "O" : "$iopadmap$ibuf_oe4" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$primitive_example_design_6.oddr_en", - "linked_object" : "oddr_en", - "linked_objects" : { - "oddr_en" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "oddr_en", - "O" : "$iopadmap$oddr_en" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_6.q_n", - "linked_object" : "q_n", - "linked_objects" : { - "q_n" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_n", - "O" : "q_n" - }, - "parameters" : { - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$primitive_example_design_6.q_p", - "linked_object" : "q_p", - "linked_objects" : { - "q_p" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$q_p", - "O" : "q_p" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "clk_buf_inst", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "clk", - "O" : "$auto$clkbufmap.cc:263:execute$399" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$398", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$399", - "O" : "clk_buf_out" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst1", - "linked_object" : "in[0]", - "linked_objects" : { - "in[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "in[0]", - "O" : "i_buf_out[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst2", - "linked_object" : "in[1]", - "linked_objects" : { - "in[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "in[1]", - "O" : "i_buf_out[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "ibuf_inst4", - "linked_object" : "rst", - "linked_objects" : { - "rst" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "rst", - "O" : "rst_i_buf_out" - }, - "parameters" : { - } - } - ] -} diff --git a/design_edit/Tests/primitive_example_design_6/gold/primitive_example_design_6_post_synth.eblif b/design_edit/Tests/primitive_example_design_6/gold/primitive_example_design_6_post_synth.eblif deleted file mode 100644 index 55a35a6fe..000000000 --- a/design_edit/Tests/primitive_example_design_6/gold/primitive_example_design_6_post_synth.eblif +++ /dev/null @@ -1,11 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_primitive_example_design_6 -.inputs oddr_out rst_i_buf_out clk_buf_out -.outputs dffre_out -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=clk_buf_out D=oddr_out E=$true Q=dffre_out R=rst_i_buf_out -.end diff --git a/design_edit/Tests/primitive_example_design_6/gold/primitive_example_design_6_post_synth.v b/design_edit/Tests/primitive_example_design_6/gold/primitive_example_design_6_post_synth.v deleted file mode 100644 index 6c7ec9886..000000000 --- a/design_edit/Tests/primitive_example_design_6/gold/primitive_example_design_6_post_synth.v +++ /dev/null @@ -1,71 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_primitive_example_design_6(oddr_out, dffre_out, rst_i_buf_out, clk_buf_out); - input clk_buf_out; - output dffre_out; - input oddr_out; - input rst_i_buf_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap404$iopadmap$primitive_example_design_6.ibuf_oe4.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap404$iopadmap$primitive_example_design_6.ibuf_oe4.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap404$iopadmap$primitive_example_design_6.ibuf_oe4.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap405$iopadmap$primitive_example_design_6.q_n.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap405$iopadmap$primitive_example_design_6.q_n.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap405$iopadmap$primitive_example_design_6.q_n.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap406$iopadmap$primitive_example_design_6.ibuf_oe3.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap406$iopadmap$primitive_example_design_6.ibuf_oe3.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap406$iopadmap$primitive_example_design_6.ibuf_oe3.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap407$iopadmap$primitive_example_design_6.ibuf_oe1.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap407$iopadmap$primitive_example_design_6.ibuf_oe1.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap407$iopadmap$primitive_example_design_6.ibuf_oe1.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap403$iopadmap$primitive_example_design_6.q_p.C ; - (* src = "./rtl/primitive_example_design_6.v:15.46-15.57" *) - (* src = "./rtl/primitive_example_design_6.v:15.46-15.57" *) - wire clk_buf_out; - wire dffre_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap400$auto$clkbufmap.cc:262:execute$398.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap402$iopadmap$primitive_example_design_6.oddr_en.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap402$iopadmap$primitive_example_design_6.oddr_en.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap402$iopadmap$primitive_example_design_6.oddr_en.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap401$iopadmap$primitive_example_design_6.ibuf_oe2.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap401$iopadmap$primitive_example_design_6.ibuf_oe2.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap401$iopadmap$primitive_example_design_6.ibuf_oe2.EN ; - wire oddr_out; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap403$iopadmap$primitive_example_design_6.q_p.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap403$iopadmap$primitive_example_design_6.q_p.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap400$auto$clkbufmap.cc:262:execute$398.O ; - (* src = "./rtl/primitive_example_design_6.v:13.6-13.19" *) - (* src = "./rtl/primitive_example_design_6.v:13.6-13.19" *) - wire rst_i_buf_out; - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_6.v:25.7-25.87" *) - DFFRE ff_inst1 ( - .C(clk_buf_out), - .D(oddr_out), - .E(1'h1), - .Q(dffre_out), - .R(rst_i_buf_out) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_6/gold/wrapper_primitive_example_design_6_post_synth.eblif b/design_edit/Tests/primitive_example_design_6/gold/wrapper_primitive_example_design_6_post_synth.eblif deleted file mode 100644 index a90841a89..000000000 --- a/design_edit/Tests/primitive_example_design_6/gold/wrapper_primitive_example_design_6_post_synth.eblif +++ /dev/null @@ -1,60 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model primitive_example_design_6 -.inputs clk in[0] in[1] rst oddr_en ibuf_oe1 ibuf_oe2 ibuf_oe3 ibuf_oe4 -.outputs q_p q_n -.names $false -.names $true -1 -.names $undef -.subckt fabric_primitive_example_design_6 clk_buf_out=clk_buf_out dffre_out=dffre_out oddr_out=oddr_out rst_i_buf_out=rst_i_buf_out -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe1 I=$auto$rs_design_edit.cc:682:execute$409.clk O=$flatten$auto$rs_design_edit.cc:682:execute$409.$auto$clkbufmap.cc:263:execute$399 -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe2 I=$auto$rs_design_edit.cc:682:execute$409.in[0] O=$auto$rs_design_edit.cc:682:execute$409.i_buf_out[0] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe3 I=$auto$rs_design_edit.cc:682:execute$409.in[1] O=$auto$rs_design_edit.cc:682:execute$409.i_buf_out[1] -.subckt I_BUF EN=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe4 I=$auto$rs_design_edit.cc:682:execute$409.rst O=$auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out -.subckt O_DDR C=$auto$rs_design_edit.cc:682:execute$409.clk_buf_out D[0]=$auto$rs_design_edit.cc:682:execute$409.i_buf_out[0] D[1]=$auto$rs_design_edit.cc:682:execute$409.i_buf_out[1] E=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$oddr_en Q=$auto$rs_design_edit.cc:682:execute$409.oddr_out R=$auto$rs_design_edit.cc:682:execute$409.rst -.subckt O_BUFT_DS I=$auto$rs_design_edit.cc:682:execute$409.in[0] O_N=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n O_P=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p T=$auto$rs_design_edit.cc:682:execute$409.dffre_out -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$auto$clkbufmap.cc:263:execute$399 O=$auto$rs_design_edit.cc:682:execute$409.clk_buf_out -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.ibuf_oe1 O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe1 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.ibuf_oe2 O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe2 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.ibuf_oe3 O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe3 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.ibuf_oe4 O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe4 -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$409.oddr_en O=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$oddr_en -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n O=$auto$rs_design_edit.cc:682:execute$409.q_n -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p O=$auto$rs_design_edit.cc:682:execute$409.q_p -.names clk $auto$rs_design_edit.cc:682:execute$409.clk -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.clk_buf_out clk_buf_out -1 1 -.names dffre_out $auto$rs_design_edit.cc:682:execute$409.dffre_out -1 1 -.names ibuf_oe1 $auto$rs_design_edit.cc:682:execute$409.ibuf_oe1 -1 1 -.names ibuf_oe2 $auto$rs_design_edit.cc:682:execute$409.ibuf_oe2 -1 1 -.names ibuf_oe3 $auto$rs_design_edit.cc:682:execute$409.ibuf_oe3 -1 1 -.names ibuf_oe4 $auto$rs_design_edit.cc:682:execute$409.ibuf_oe4 -1 1 -.names in[0] $auto$rs_design_edit.cc:682:execute$409.in[0] -1 1 -.names in[1] $auto$rs_design_edit.cc:682:execute$409.in[1] -1 1 -.names oddr_en $auto$rs_design_edit.cc:682:execute$409.oddr_en -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.oddr_out oddr_out -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.q_n q_n -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.q_p q_p -1 1 -.names rst $auto$rs_design_edit.cc:682:execute$409.rst -1 1 -.names $auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out rst_i_buf_out -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_6/gold/wrapper_primitive_example_design_6_post_synth.v b/design_edit/Tests/primitive_example_design_6/gold/wrapper_primitive_example_design_6_post_synth.v deleted file mode 100644 index 58a2f69cb..000000000 --- a/design_edit/Tests/primitive_example_design_6/gold/wrapper_primitive_example_design_6_post_synth.v +++ /dev/null @@ -1,231 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module primitive_example_design_6(clk, in, rst, q_p, q_n, oddr_en, ibuf_oe1, ibuf_oe2, ibuf_oe3, ibuf_oe4); - input ibuf_oe3; - input ibuf_oe4; - input [1:0] in; - output q_p; - input rst; - input ibuf_oe1; - output q_n; - input clk; - input ibuf_oe2; - input oddr_en; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$auto$clkbufmap.cc:263:execute$399 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe1 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe2 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe3 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe4 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$oddr_en ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p ; - (* src = "./rtl/primitive_example_design_6.v:13.6-13.19" *) - wire \$auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out ; - (* src = "./rtl/primitive_example_design_6.v:4.12-4.15" *) - wire \$auto$rs_design_edit.cc:682:execute$409.rst ; - (* src = "./rtl/primitive_example_design_6.v:4.7-4.10" *) - wire \$auto$rs_design_edit.cc:682:execute$409.clk ; - (* src = "./rtl/primitive_example_design_6.v:12.12-12.21" *) - wire [1:0] \$auto$rs_design_edit.cc:682:execute$409.i_buf_out ; - (* src = "./rtl/primitive_example_design_6.v:5.16-5.24" *) - wire \$auto$rs_design_edit.cc:682:execute$409.ibuf_oe2 ; - (* src = "./rtl/primitive_example_design_6.v:7.8-7.11" *) - wire \$auto$rs_design_edit.cc:682:execute$409.q_p ; - wire \$auto$rs_design_edit.cc:682:execute$409.dffre_out ; - (* src = "./rtl/primitive_example_design_6.v:8.8-8.11" *) - wire \$auto$rs_design_edit.cc:682:execute$409.q_n ; - wire \$auto$rs_design_edit.cc:682:execute$409.oddr_out ; - (* src = "./rtl/primitive_example_design_6.v:6.7-6.14" *) - wire \$auto$rs_design_edit.cc:682:execute$409.oddr_en ; - (* src = "./rtl/primitive_example_design_6.v:15.46-15.57" *) - wire \$auto$rs_design_edit.cc:682:execute$409.clk_buf_out ; - (* src = "./rtl/primitive_example_design_6.v:5.25-5.33" *) - wire \$auto$rs_design_edit.cc:682:execute$409.ibuf_oe3 ; - (* src = "./rtl/primitive_example_design_6.v:3.13-3.15" *) - wire [1:0] \$auto$rs_design_edit.cc:682:execute$409.in ; - (* src = "./rtl/primitive_example_design_6.v:5.7-5.15" *) - wire \$auto$rs_design_edit.cc:682:execute$409.ibuf_oe1 ; - (* src = "./rtl/primitive_example_design_6.v:5.34-5.42" *) - wire \$auto$rs_design_edit.cc:682:execute$409.ibuf_oe4 ; - wire dffre_out; - (* src = "./rtl/primitive_example_design_6.v:5.25-5.33" *) - (* src = "./rtl/primitive_example_design_6.v:5.25-5.33" *) - wire ibuf_oe3; - (* src = "./rtl/primitive_example_design_6.v:15.46-15.57" *) - wire clk_buf_out; - (* src = "./rtl/primitive_example_design_6.v:12.12-12.21" *) - wire [1:0] i_buf_out; - (* src = "./rtl/primitive_example_design_6.v:5.34-5.42" *) - (* src = "./rtl/primitive_example_design_6.v:5.34-5.42" *) - wire ibuf_oe4; - (* src = "./rtl/primitive_example_design_6.v:3.13-3.15" *) - (* src = "./rtl/primitive_example_design_6.v:3.13-3.15" *) - wire [1:0] in; - wire oddr_out; - (* src = "./rtl/primitive_example_design_6.v:7.8-7.11" *) - (* src = "./rtl/primitive_example_design_6.v:7.8-7.11" *) - wire q_p; - (* src = "./rtl/primitive_example_design_6.v:4.12-4.15" *) - (* src = "./rtl/primitive_example_design_6.v:4.12-4.15" *) - wire rst; - (* src = "./rtl/primitive_example_design_6.v:5.7-5.15" *) - (* src = "./rtl/primitive_example_design_6.v:5.7-5.15" *) - wire ibuf_oe1; - (* src = "./rtl/primitive_example_design_6.v:8.8-8.11" *) - (* src = "./rtl/primitive_example_design_6.v:8.8-8.11" *) - wire q_n; - (* src = "./rtl/primitive_example_design_6.v:4.7-4.10" *) - (* src = "./rtl/primitive_example_design_6.v:4.7-4.10" *) - wire clk; - (* src = "./rtl/primitive_example_design_6.v:5.16-5.24" *) - (* src = "./rtl/primitive_example_design_6.v:5.16-5.24" *) - wire ibuf_oe2; - (* src = "./rtl/primitive_example_design_6.v:6.7-6.14" *) - (* src = "./rtl/primitive_example_design_6.v:6.7-6.14" *) - wire oddr_en; - (* src = "./rtl/primitive_example_design_6.v:13.6-13.19" *) - wire rst_i_buf_out; - wire \$iopadmap$q_p ; - wire \$iopadmap$q_n ; - wire \$iopadmap$oddr_en ; - wire \$iopadmap$ibuf_oe4 ; - wire \$iopadmap$ibuf_oe3 ; - wire \$iopadmap$ibuf_oe2 ; - wire \$iopadmap$ibuf_oe1 ; - wire \$auto$clkbufmap.cc:263:execute$399 ; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_6.ibuf_oe1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.ibuf_oe1 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe1 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_6.ibuf_oe2 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.ibuf_oe2 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe2 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_6.ibuf_oe3 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.ibuf_oe3 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe3 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_6.ibuf_oe4 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.ibuf_oe4 ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe4 ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_6.oddr_en ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$409.oddr_en ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$oddr_en ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_6.q_n ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n ), - .O(\$auto$rs_design_edit.cc:682:execute$409.q_n ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$primitive_example_design_6.q_p ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p ), - .O(\$auto$rs_design_edit.cc:682:execute$409.q_p ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_6.v:15.7-15.59" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$409.clk_buf_inst ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe1 ), - .I(\$auto$rs_design_edit.cc:682:execute$409.clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$409.$auto$clkbufmap.cc:263:execute$399 ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_6.v:19.11-19.69" *) - O_BUFT_DS \$auto$rs_design_edit.cc:682:execute$409.o_buft_inst1 ( - .I(\$auto$rs_design_edit.cc:682:execute$409.in [0]), - .O_N(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_n ), - .O_P(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$q_p ), - .T(\$auto$rs_design_edit.cc:682:execute$409.dffre_out ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_6.v:21.7-21.60" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$409.ibuf_inst1 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe2 ), - .I(\$auto$rs_design_edit.cc:682:execute$409.in [0]), - .O(\$auto$rs_design_edit.cc:682:execute$409.i_buf_out [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_6.v:22.7-22.60" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$409.ibuf_inst2 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe3 ), - .I(\$auto$rs_design_edit.cc:682:execute$409.in [1]), - .O(\$auto$rs_design_edit.cc:682:execute$409.i_buf_out [1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_6.v:23.7-23.59" *) - I_BUF \$auto$rs_design_edit.cc:682:execute$409.ibuf_inst4 ( - .EN(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$ibuf_oe4 ), - .I(\$auto$rs_design_edit.cc:682:execute$409.rst ), - .O(\$auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./rtl/primitive_example_design_6.v:17.7-17.81" *) - O_DDR \$auto$rs_design_edit.cc:682:execute$409.iddr_ist1 ( - .C(\$auto$rs_design_edit.cc:682:execute$409.clk_buf_out ), - .D(\$auto$rs_design_edit.cc:682:execute$409.i_buf_out ), - .E(\$flatten$auto$rs_design_edit.cc:682:execute$409.$iopadmap$oddr_en ), - .Q(\$auto$rs_design_edit.cc:682:execute$409.oddr_out ), - .R(\$auto$rs_design_edit.cc:682:execute$409.rst ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$409.$auto$clkbufmap.cc:262:execute$398 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$409.$auto$clkbufmap.cc:263:execute$399 ), - .O(\$auto$rs_design_edit.cc:682:execute$409.clk_buf_out ) - ); - fabric_primitive_example_design_6 \$auto$rs_design_edit.cc:680:execute$408 ( - .clk_buf_out(clk_buf_out), - .dffre_out(dffre_out), - .oddr_out(oddr_out), - .rst_i_buf_out(rst_i_buf_out) - ); - assign \$auto$rs_design_edit.cc:682:execute$409.clk = clk; - assign clk_buf_out = \$auto$rs_design_edit.cc:682:execute$409.clk_buf_out ; - assign \$auto$rs_design_edit.cc:682:execute$409.dffre_out = dffre_out; - assign \$auto$rs_design_edit.cc:682:execute$409.ibuf_oe1 = ibuf_oe1; - assign \$auto$rs_design_edit.cc:682:execute$409.ibuf_oe2 = ibuf_oe2; - assign \$auto$rs_design_edit.cc:682:execute$409.ibuf_oe3 = ibuf_oe3; - assign \$auto$rs_design_edit.cc:682:execute$409.ibuf_oe4 = ibuf_oe4; - assign \$auto$rs_design_edit.cc:682:execute$409.in = in; - assign \$auto$rs_design_edit.cc:682:execute$409.oddr_en = oddr_en; - assign oddr_out = \$auto$rs_design_edit.cc:682:execute$409.oddr_out ; - assign q_n = \$auto$rs_design_edit.cc:682:execute$409.q_n ; - assign q_p = \$auto$rs_design_edit.cc:682:execute$409.q_p ; - assign \$auto$rs_design_edit.cc:682:execute$409.rst = rst; - assign rst_i_buf_out = \$auto$rs_design_edit.cc:682:execute$409.rst_i_buf_out ; -endmodule diff --git a/design_edit/Tests/primitive_example_design_6/primitive_example_design_6.ys b/design_edit/Tests/primitive_example_design_6/primitive_example_design_6.ys deleted file mode 100644 index 3b554172e..000000000 --- a/design_edit/Tests/primitive_example_design_6/primitive_example_design_6.ys +++ /dev/null @@ -1,19 +0,0 @@ -# Yosys synthesis script for O_SERDES_primitive_inst -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./rtl/primitive_example_design_6.v - - -# Technology mapping -hierarchy -top primitive_example_design_6 - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal delay -effort high -carry auto -new_tdp36k -max_lut 45408 -max_reg 90816 -max_device_dsp 176 -max_device_bram 176 -max_device_carry_length 528 -max_dsp 176 -max_bram 176 -max_carry_length 528 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -plugin -i design-edit -design_edit -tech genesis3 -json ./tmp/io_config.json -w ./tmp/wrapper_primitive_example_design_6_post_synth.v ./tmp/wrapper_primitive_example_design_6_post_synth.eblif -write_verilog -noexpr -nodec -norename -v ./tmp/primitive_example_design_6_post_synth.v -write_blif -param ./tmp/primitive_example_design_6_post_synth.eblif \ No newline at end of file diff --git a/design_edit/Tests/primitive_example_design_6/rtl/primitive_example_design_6.v b/design_edit/Tests/primitive_example_design_6/rtl/primitive_example_design_6.v deleted file mode 100644 index 827640931..000000000 --- a/design_edit/Tests/primitive_example_design_6/rtl/primitive_example_design_6.v +++ /dev/null @@ -1,27 +0,0 @@ -module primitive_example_design_6(clk,in,rst,q_p,q_n,oddr_en,ibuf_oe1,ibuf_oe2,ibuf_oe3,ibuf_oe4); - -input [1:0] in; -input clk, rst; -input ibuf_oe1,ibuf_oe2,ibuf_oe3,ibuf_oe4; -input oddr_en; -output q_p; -output q_n; - -wire [1:0] oddr_out; -wire [1:0] dffre_out; -wire [1:0] i_buf_out; -wire rst_i_buf_out; - -I_BUF clk_buf_inst (.I(clk),.EN(ibuf_oe1),.O(clk_buf_out)); - -O_DDR iddr_ist1 (.D(i_buf_out),.R(rst),.E(oddr_en),.C(clk_buf_out),.Q(oddr_out)); - -O_BUFT_DS o_buft_inst1 (.T(dffre_out),.I(in[0]),.O_N(q_n),.O_P(q_p)); - -I_BUF ibuf_inst1 (.I(in[0]),.EN(ibuf_oe2),.O(i_buf_out[0])); -I_BUF ibuf_inst2 (.I(in[1]),.EN(ibuf_oe3),.O(i_buf_out[1])); -I_BUF ibuf_inst4 (.I(rst),.EN(ibuf_oe4),.O(rst_i_buf_out)); - -DFFRE ff_inst1 (.D(oddr_out),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffre_out)); - -endmodule diff --git a/design_edit/Tests/primitive_example_design_6/synthesis/primitive_example_design_6_post_synth.eblif b/design_edit/Tests/primitive_example_design_6/synthesis/primitive_example_design_6_post_synth.eblif deleted file mode 100644 index 41e43f3c7..000000000 --- a/design_edit/Tests/primitive_example_design_6/synthesis/primitive_example_design_6_post_synth.eblif +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) - -.model primitive_example_design_6 -.inputs clk in[0] in[1] rst oddr_en ibuf_oe1 ibuf_oe2 ibuf_oe3 ibuf_oe4 -.outputs q_p q_n -.names $false -.names $true -1 -.names $undef -.subckt I_BUF EN=ibuf_oe1 I=clk O=clk_buf_out -.subckt DFFRE C=clk_buf_out D=oddr_out E=$true Q=dffre_out R=rst_i_buf_out -.subckt I_BUF EN=ibuf_oe2 I=in[0] O=i_buf_out[0] -.subckt I_BUF EN=ibuf_oe3 I=in[1] O=i_buf_out[1] -.subckt I_BUF EN=ibuf_oe4 I=rst O=rst_i_buf_out -.subckt O_DDR C=clk_buf_out D[0]=i_buf_out[0] D[1]=i_buf_out[1] E=oddr_en Q=oddr_out R=rst -.subckt O_BUFT_DS I=in[0] O_N=q_n O_P=q_p T=dffre_out -.end diff --git a/design_edit/Tests/primitive_example_design_6/synthesis/primitive_example_design_6_post_synth.v b/design_edit/Tests/primitive_example_design_6/synthesis/primitive_example_design_6_post_synth.v deleted file mode 100644 index fbd9ec16e..000000000 --- a/design_edit/Tests/primitive_example_design_6/synthesis/primitive_example_design_6_post_synth.v +++ /dev/null @@ -1,106 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 b6be8bb62, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module primitive_example_design_6(clk, in, rst, q_p, q_n, oddr_en, ibuf_oe1, ibuf_oe2, ibuf_oe3, ibuf_oe4); - input clk; - input ibuf_oe1; - input ibuf_oe2; - input ibuf_oe3; - input ibuf_oe4; - input [1:0] in; - input oddr_en; - output q_n; - output q_p; - input rst; - (* src = "./rtl/primitive_example_design_6.v:4.7-4.10" *) - (* src = "./rtl/primitive_example_design_6.v:4.7-4.10" *) - wire clk; - (* src = "./rtl/primitive_example_design_6.v:15.46-15.57" *) - wire clk_buf_out; - wire dffre_out; - (* src = "./rtl/primitive_example_design_6.v:12.12-12.21" *) - wire [1:0] i_buf_out; - (* src = "./rtl/primitive_example_design_6.v:5.7-5.15" *) - (* src = "./rtl/primitive_example_design_6.v:5.7-5.15" *) - wire ibuf_oe1; - (* src = "./rtl/primitive_example_design_6.v:5.16-5.24" *) - (* src = "./rtl/primitive_example_design_6.v:5.16-5.24" *) - wire ibuf_oe2; - (* src = "./rtl/primitive_example_design_6.v:5.25-5.33" *) - (* src = "./rtl/primitive_example_design_6.v:5.25-5.33" *) - wire ibuf_oe3; - (* src = "./rtl/primitive_example_design_6.v:5.34-5.42" *) - (* src = "./rtl/primitive_example_design_6.v:5.34-5.42" *) - wire ibuf_oe4; - (* src = "./rtl/primitive_example_design_6.v:3.13-3.15" *) - (* src = "./rtl/primitive_example_design_6.v:3.13-3.15" *) - wire [1:0] in; - (* src = "./rtl/primitive_example_design_6.v:6.7-6.14" *) - (* src = "./rtl/primitive_example_design_6.v:6.7-6.14" *) - wire oddr_en; - wire oddr_out; - (* src = "./rtl/primitive_example_design_6.v:8.8-8.11" *) - (* src = "./rtl/primitive_example_design_6.v:8.8-8.11" *) - wire q_n; - (* src = "./rtl/primitive_example_design_6.v:7.8-7.11" *) - (* src = "./rtl/primitive_example_design_6.v:7.8-7.11" *) - wire q_p; - (* src = "./rtl/primitive_example_design_6.v:4.12-4.15" *) - (* src = "./rtl/primitive_example_design_6.v:4.12-4.15" *) - wire rst; - (* src = "./rtl/primitive_example_design_6.v:13.6-13.19" *) - wire rst_i_buf_out; - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_6.v:15.7-15.59" *) - I_BUF clk_buf_inst ( - .EN(ibuf_oe1), - .I(clk), - .O(clk_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_6.v:25.7-25.87" *) - DFFRE ff_inst1 ( - .C(clk_buf_out), - .D(oddr_out), - .E(1'h1), - .Q(dffre_out), - .R(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_6.v:21.7-21.60" *) - I_BUF ibuf_inst1 ( - .EN(ibuf_oe2), - .I(in[0]), - .O(i_buf_out[0]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_6.v:22.7-22.60" *) - I_BUF ibuf_inst2 ( - .EN(ibuf_oe3), - .I(in[1]), - .O(i_buf_out[1]) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_6.v:23.7-23.59" *) - I_BUF ibuf_inst4 ( - .EN(ibuf_oe4), - .I(rst), - .O(rst_i_buf_out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_6.v:17.7-17.81" *) - O_DDR iddr_ist1 ( - .C(clk_buf_out), - .D(i_buf_out), - .E(oddr_en), - .Q(oddr_out), - .R(rst) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./rtl/primitive_example_design_6.v:19.11-19.69" *) - O_BUFT_DS o_buft_inst1 ( - .I(in[0]), - .O_N(q_n), - .O_P(q_p), - .T(dffre_out) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_7/Src/and2.v b/design_edit/Tests/primitive_example_design_7/Src/and2.v deleted file mode 100644 index 037d348e8..000000000 --- a/design_edit/Tests/primitive_example_design_7/Src/and2.v +++ /dev/null @@ -1,29 +0,0 @@ -`timescale 1ns / 1ps -//////////////////////////////////////////////////////// -// Rapid Silicon Raptor Example Design // -// and2_verilog // -// and2.v - Top-level file of simple 2-input AND gate // -//////////////////////////////////////////////////////// - -module and2 ( - input a, - input b, - input clk, - input reset, - output reg c = 1'b0 -); - - reg a_reg, b_reg = 1'b0; - - always@(posedge clk) - if (reset) begin - a_reg <= 1'b0; - b_reg <= 1'b0; - c <= 1'b0; - end else begin - a_reg <= a; - b_reg <= b; - c <= a_reg & b_reg; - end - -endmodule diff --git a/design_edit/Tests/primitive_example_design_7/Src/testbench_and2.v b/design_edit/Tests/primitive_example_design_7/Src/testbench_and2.v deleted file mode 100644 index 1e2e3bd7e..000000000 --- a/design_edit/Tests/primitive_example_design_7/Src/testbench_and2.v +++ /dev/null @@ -1,90 +0,0 @@ -`timescale 1ns / 1ps -///////////////////////////////////////////// -// Rapid Silicon Raptor Example Design // -// and2_verilog // -// testbench_and2.v - Testbench for design // -///////////////////////////////////////////// - -module testbench_and2; - - // Simulation parameters - parameter period = 10; - - // DUT inputs - reg a = 1'b0; - reg b = 1'b0; - reg clk = 1'b0; - reg reset = 1'b1; - - // DUT output - wire c; - - // Check signals - reg reset_delay = 1'b0; - reg [1:0] a_delay = 2'b00, b_delay = 2'b00; - wire a_delay_by_2 = a_delay[0]; - wire b_delay_by_2 = b_delay[0]; - integer error_cnt = 0; - - and2 DUT ( - .a(a), - .b(b), - .clk(clk), - .reset(reset), - .c(c) - ); - - // Clock - always - #period clk = ~clk; - - // Stimulus - initial begin - // Assert reset for 100 ns - #100; - @(posedge clk); - #1 reset = 1'b0; - repeat (2) begin - @(posedge clk); - #1 a = ~a; - @(posedge clk); - #1 b = ~b; - end - repeat (2) - @(posedge clk); - $display ("\n\nSimulation completed at simulation time %t with %d error(s).\n", $realtime, error_cnt); - $finish; - end - - // Self-chekcing - initial begin - $display(""); - // Wait 100 ns - #100; - forever begin - @(posedge clk); - #1 reset_delay = reset; - a_delay = {a, a_delay[1]}; - b_delay = {b, b_delay[1]}; - #(period-2); - if (reset_delay && (c != 1'b0)) begin - $display("\nError @ %t: Design in reset but output is not zero.", $realtime); - error_cnt = error_cnt + 1; - end else if (!reset_delay && (c != (a_delay[0] && b_delay[0]))) begin - $display("\nError @ %t: c=%b where a=%b and b=%b",$realtime, c, a_delay[0], b_delay[0]); - error_cnt = error_cnt + 1; - end else - $write("."); - end - end - - initial - $timeformat(-9,0," ns", 5); - - initial begin - $dumpfile("and2.vcd"); - $dumpvars(0,testbench_and2); - end - -endmodule - diff --git a/design_edit/Tests/primitive_example_design_7/constraints.sdc b/design_edit/Tests/primitive_example_design_7/constraints.sdc deleted file mode 100644 index 663874218..000000000 --- a/design_edit/Tests/primitive_example_design_7/constraints.sdc +++ /dev/null @@ -1,9 +0,0 @@ -# SDC file example - -# Setting a clock frequency of 200 MHz (5nS period) -create_clock -period 5 clk -set_input_delay -max 0 -clock clk [get_ports {a}] -set_input_delay -max 0 -clock clk [get_ports {b}] -set_input_delay -max 0 -clock clk [get_ports {reset}] -set_output_delay -max 0 -clock clk [get_ports {c}] - diff --git a/design_edit/Tests/primitive_example_design_7/gold/and2_wio_post_synth.eblif b/design_edit/Tests/primitive_example_design_7/gold/and2_wio_post_synth.eblif deleted file mode 100644 index f3b549f03..000000000 --- a/design_edit/Tests/primitive_example_design_7/gold/and2_wio_post_synth.eblif +++ /dev/null @@ -1,31 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model and2 -.inputs a b clk reset -.outputs c -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$499 D=$abc$221$li0_li0 E=$true Q=a_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$499 D=$abc$221$li1_li1 E=$true Q=b_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$499 D=$abc$221$li2_li2 E=$true Q=$iopadmap$c R=$true -.subckt LUT2 A[0]=$iopadmap$reset A[1]=$iopadmap$b Y=$abc$221$li1_li1 -.param INIT_VALUE 0100 -.subckt LUT3 A[0]=$iopadmap$reset A[1]=a_reg A[2]=b_reg Y=$abc$221$li2_li2 -.param INIT_VALUE 01000000 -.subckt LUT2 A[0]=$iopadmap$reset A[1]=$iopadmap$a Y=$abc$221$li0_li0 -.param INIT_VALUE 0100 -.subckt CLK_BUF I=$auto$clkbufmap.cc:263:execute$498 O=$auto$clkbufmap.cc:295:execute$499 -.subckt I_BUF EN=$true I=a O=$iopadmap$a -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=b O=$iopadmap$b -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$iopadmap$c O=c -.subckt I_BUF EN=$true I=clk O=$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=reset O=$iopadmap$reset -.param WEAK_KEEPER "NONE" -.names $iopadmap$clk $auto$clkbufmap.cc:263:execute$498 -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_7/gold/and2_wio_post_synth.v b/design_edit/Tests/primitive_example_design_7/gold/and2_wio_post_synth.v deleted file mode 100644 index b1bf99c8a..000000000 --- a/design_edit/Tests/primitive_example_design_7/gold/and2_wio_post_synth.v +++ /dev/null @@ -1,196 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module and2(a, b, clk, reset, c); - input a; - input b; - output c; - input clk; - input reset; - wire \$abc$221$li0_li0 ; - wire \$abc$221$li1_li1 ; - wire \$abc$221$li2_li2 ; - wire \$auto$clkbufmap.cc:263:execute$498 ; - wire \$auto$clkbufmap.cc:295:execute$499 ; - wire \$iopadmap$a ; - wire \$iopadmap$b ; - (* init = 1'h0 *) - wire \$iopadmap$c ; - wire \$iopadmap$clk ; - wire \$iopadmap$reset ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap500$auto$clkbufmap.cc:262:execute$497.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap500$auto$clkbufmap.cc:262:execute$497.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap501$iopadmap$and2.a.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap501$iopadmap$and2.a.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap501$iopadmap$and2.a.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap502$iopadmap$and2.c.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap502$iopadmap$and2.c.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap502$iopadmap$and2.c.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap503$iopadmap$and2.b.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap503$iopadmap$and2.b.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap503$iopadmap$and2.b.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap504$iopadmap$and2.reset.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap504$iopadmap$and2.reset.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap504$iopadmap$and2.reset.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap505$iopadmap$and2.clk.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap505$iopadmap$and2.clk.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap505$iopadmap$and2.clk.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.Y ; - (* src = "./Src/and2.v:9.9-9.10" *) - (* src = "./Src/and2.v:9.9-9.10" *) - wire a; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.7-16.12" *) - wire a_reg; - (* src = "./Src/and2.v:10.9-10.10" *) - (* src = "./Src/and2.v:10.9-10.10" *) - wire b; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.14-16.19" *) - wire b_reg; - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:13.14-13.15" *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:13.14-13.15" *) - wire c; - (* src = "./Src/and2.v:11.9-11.12" *) - (* src = "./Src/and2.v:11.9-11.12" *) - wire clk; - (* src = "./Src/and2.v:12.9-12.14" *) - (* src = "./Src/and2.v:12.9-12.14" *) - wire reset; - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$222 ( - .C(\$auto$clkbufmap.cc:295:execute$499 ), - .D(\$abc$221$li0_li0 ), - .E(1'h1), - .Q(a_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$223 ( - .C(\$auto$clkbufmap.cc:295:execute$499 ), - .D(\$abc$221$li1_li1 ), - .E(1'h1), - .Q(b_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$224 ( - .C(\$auto$clkbufmap.cc:295:execute$499 ), - .D(\$abc$221$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$494 ( - .A({ \$iopadmap$b , \$iopadmap$reset }), - .Y(\$abc$221$li1_li1 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$495 ( - .A({ b_reg, a_reg, \$iopadmap$reset }), - .Y(\$abc$221$li2_li2 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$496 ( - .A({ \$iopadmap$a , \$iopadmap$reset }), - .Y(\$abc$221$li0_li0 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$clkbufmap.cc:262:execute$497 ( - .I(\$auto$clkbufmap.cc:263:execute$498 ), - .O(\$auto$clkbufmap.cc:295:execute$499 ) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.a ( - .EN(1'h1), - .I(a), - .O(\$iopadmap$a ) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.b ( - .EN(1'h1), - .I(b), - .O(\$iopadmap$b ) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$and2.c ( - .I(\$iopadmap$c ), - .O(c) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.clk ( - .EN(1'h1), - .I(clk), - .O(\$iopadmap$clk ) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.reset ( - .EN(1'h1), - .I(reset), - .O(\$iopadmap$reset ) - ); - assign \$auto$clkbufmap.cc:263:execute$498 = \$iopadmap$clk ; -endmodule diff --git a/design_edit/Tests/primitive_example_design_7/gold/fab_and2_wio_post_synth.eblif b/design_edit/Tests/primitive_example_design_7/gold/fab_and2_wio_post_synth.eblif deleted file mode 100644 index b70ca64df..000000000 --- a/design_edit/Tests/primitive_example_design_7/gold/fab_and2_wio_post_synth.eblif +++ /dev/null @@ -1,19 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_and2 -.inputs $auto$clkbufmap.cc:295:execute$499 $iopadmap$reset $iopadmap$a $iopadmap$b -.outputs $iopadmap$c -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$499 D=$abc$221$li0_li0 E=$true Q=a_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$499 D=$abc$221$li1_li1 E=$true Q=b_reg R=$true -.subckt DFFRE C=$auto$clkbufmap.cc:295:execute$499 D=$abc$221$li2_li2 E=$true Q=$iopadmap$c R=$true -.subckt LUT2 A[0]=$iopadmap$reset A[1]=$iopadmap$b Y=$abc$221$li1_li1 -.param INIT_VALUE 0100 -.subckt LUT3 A[0]=$iopadmap$reset A[1]=a_reg A[2]=b_reg Y=$abc$221$li2_li2 -.param INIT_VALUE 01000000 -.subckt LUT2 A[0]=$iopadmap$reset A[1]=$iopadmap$a Y=$abc$221$li0_li0 -.param INIT_VALUE 0100 -.end diff --git a/design_edit/Tests/primitive_example_design_7/gold/fab_and2_wio_post_synth.v b/design_edit/Tests/primitive_example_design_7/gold/fab_and2_wio_post_synth.v deleted file mode 100644 index 9f1499f58..000000000 --- a/design_edit/Tests/primitive_example_design_7/gold/fab_and2_wio_post_synth.v +++ /dev/null @@ -1,125 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_and2(\$auto$clkbufmap.cc:295:execute$499 , \$iopadmap$reset , \$iopadmap$a , \$iopadmap$b , \$iopadmap$c ); - input \$iopadmap$b ; - output \$iopadmap$c ; - input \$iopadmap$reset ; - input \$iopadmap$a ; - input \$auto$clkbufmap.cc:295:execute$499 ; - wire \$iopadmap$b ; - (* init = 1'h0 *) - (* init = 1'h0 *) - wire \$iopadmap$c ; - wire \$iopadmap$clk ; - wire \$iopadmap$reset ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap500$auto$clkbufmap.cc:262:execute$497.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap500$auto$clkbufmap.cc:262:execute$497.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap501$iopadmap$and2.a.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap501$iopadmap$and2.a.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap501$iopadmap$and2.a.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap502$iopadmap$and2.c.C ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap502$iopadmap$and2.c.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap502$iopadmap$and2.c.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap503$iopadmap$and2.b.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap503$iopadmap$and2.b.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap503$iopadmap$and2.b.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap504$iopadmap$and2.reset.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap504$iopadmap$and2.reset.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap504$iopadmap$and2.reset.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap505$iopadmap$and2.clk.EN ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap505$iopadmap$and2.clk.I ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap505$iopadmap$and2.clk.O ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.Y ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.A ; - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.Y ; - wire \$iopadmap$a ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.7-16.12" *) - wire a_reg; - wire \$abc$221$li2_li2 ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.14-16.19" *) - wire b_reg; - wire \$auto$clkbufmap.cc:295:execute$499 ; - wire \$abc$221$li1_li1 ; - wire \$abc$221$li0_li0 ; - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$222 ( - .C(\$auto$clkbufmap.cc:295:execute$499 ), - .D(\$abc$221$li0_li0 ), - .E(1'h1), - .Q(a_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$223 ( - .C(\$auto$clkbufmap.cc:295:execute$499 ), - .D(\$abc$221$li1_li1 ), - .E(1'h1), - .Q(b_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$224 ( - .C(\$auto$clkbufmap.cc:295:execute$499 ), - .D(\$abc$221$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$494 ( - .A({ \$iopadmap$b , \$iopadmap$reset }), - .Y(\$abc$221$li1_li1 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$495 ( - .A({ b_reg, a_reg, \$iopadmap$reset }), - .Y(\$abc$221$li2_li2 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$496 ( - .A({ \$iopadmap$a , \$iopadmap$reset }), - .Y(\$abc$221$li0_li0 ) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_7/gold/io_config.json b/design_edit/Tests/primitive_example_design_7/gold/io_config.json deleted file mode 100644 index 5734287ee..000000000 --- a/design_edit/Tests/primitive_example_design_7/gold/io_config.json +++ /dev/null @@ -1,173 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\a (index=0, width=1, offset=0)", - " Detect input port \\b (index=0, width=1, offset=0)", - " Detect output port \\c (index=0, width=1, offset=0)", - " Detect input port \\clk (index=0, width=1, offset=0)", - " Detect input port \\reset (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF $iopadmap$and2.a", - " Cell port \\I is connected to input port \\a", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$and2.b", - " Cell port \\I is connected to input port \\b", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF $iopadmap$and2.c", - " Cell port \\O is connected to output port \\c", - " Get important connection of cell \\I_BUF $iopadmap$and2.clk", - " Cell port \\I is connected to input port \\clk", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF $iopadmap$and2.reset", - " Cell port \\I is connected to input port \\reset", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Trace Clock Buffer", - " Try \\I_BUF $iopadmap$and2.clk out connection: $iopadmap$clk", - " Connected $auto$clkbufmap.cc:262:execute$497", - " Additional Connection: $auto$clkbufmap.cc:263:execute$498", - " Assign location HR_3_0_0P (and properties) to Port a", - " Assign location HR_1_0_0P (and properties) to Port reset", - " Assign location HR_2_0_0P (and properties) to Port b", - " Assign location HP_2_0_0P (and properties) to Port clk", - " Assign location HR_5_0_0P (and properties) to Port c", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.a", - "linked_object" : "a", - "linked_objects" : { - "a" : { - "location" : "HR_3_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "a", - "O" : "$iopadmap$a" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.b", - "linked_object" : "b", - "linked_objects" : { - "b" : { - "location" : "HR_2_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "b", - "O" : "$iopadmap$b" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$and2.c", - "linked_object" : "c", - "linked_objects" : { - "c" : { - "location" : "HR_5_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$c", - "O" : "c" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.clk", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HP_2_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "clk", - "O" : "$iopadmap$clk" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk_#0", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HP_2_0_0P", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk", - "O" : "$auto$clkbufmap.cc:263:execute$498" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:262:execute$497", - "linked_object" : "clk", - "linked_objects" : { - "clk" : { - "location" : "HP_2_0_0P", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:263:execute$498", - "O" : "$auto$clkbufmap.cc:295:execute$499" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.reset", - "linked_object" : "reset", - "linked_objects" : { - "reset" : { - "location" : "HR_1_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "reset", - "O" : "$iopadmap$reset" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - } - ] -} diff --git a/design_edit/Tests/primitive_example_design_7/gold/wrapper_and2_wio_post_synth.eblif b/design_edit/Tests/primitive_example_design_7/gold/wrapper_and2_wio_post_synth.eblif deleted file mode 100644 index af263056b..000000000 --- a/design_edit/Tests/primitive_example_design_7/gold/wrapper_and2_wio_post_synth.eblif +++ /dev/null @@ -1,41 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model and2 -.inputs a b clk reset -.outputs c -.names $false -.names $true -1 -.names $undef -.subckt fabric_and2 $auto$clkbufmap.cc:295:execute$499=$auto$clkbufmap.cc:295:execute$499 $iopadmap$a=$iopadmap$a $iopadmap$b=$iopadmap$b $iopadmap$c=$iopadmap$c $iopadmap$reset=$iopadmap$reset -.subckt CLK_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$clk O=$flatten$auto$rs_design_edit.cc:682:execute$510.$auto$clkbufmap.cc:295:execute$499 -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$510.a O=$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$a -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$510.b O=$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$b -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$c O=$auto$rs_design_edit.cc:682:execute$510.c -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$510.clk O=$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$clk -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$510.reset O=$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$reset -.param WEAK_KEEPER "NONE" -.names $flatten$auto$rs_design_edit.cc:682:execute$510.$auto$clkbufmap.cc:295:execute$499 $auto$clkbufmap.cc:295:execute$499 -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$a $iopadmap$a -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$b $iopadmap$b -1 1 -.names $iopadmap$c $flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$c -1 1 -.names $flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$reset $iopadmap$reset -1 1 -.names a $auto$rs_design_edit.cc:682:execute$510.a -1 1 -.names b $auto$rs_design_edit.cc:682:execute$510.b -1 1 -.names $auto$rs_design_edit.cc:682:execute$510.c c -1 1 -.names clk $auto$rs_design_edit.cc:682:execute$510.clk -1 1 -.names reset $auto$rs_design_edit.cc:682:execute$510.reset -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_7/gold/wrapper_and2_wio_post_synth.v b/design_edit/Tests/primitive_example_design_7/gold/wrapper_and2_wio_post_synth.v deleted file mode 100644 index c8dca8e8b..000000000 --- a/design_edit/Tests/primitive_example_design_7/gold/wrapper_and2_wio_post_synth.v +++ /dev/null @@ -1,120 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module and2(a, b, clk, reset, c); - output c; - input b; - input a; - input clk; - input reset; - (* src = "./Src/and2.v:10.9-10.10" *) - wire \$auto$rs_design_edit.cc:682:execute$510.b ; - (* src = "./Src/and2.v:12.9-12.14" *) - wire \$auto$rs_design_edit.cc:682:execute$510.reset ; - (* src = "./Src/and2.v:11.9-11.12" *) - wire \$auto$rs_design_edit.cc:682:execute$510.clk ; - (* keep = 32'd1 *) - (* src = "./Src/and2.v:13.14-13.15" *) - wire \$auto$rs_design_edit.cc:682:execute$510.c ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$510.$auto$clkbufmap.cc:295:execute$499 ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$a ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$b ; - (* init = 1'h0 *) - wire \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$c ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$clk ; - wire \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$reset ; - (* src = "./Src/and2.v:9.9-9.10" *) - wire \$auto$rs_design_edit.cc:682:execute$510.a ; - wire \$iopadmap$reset ; - (* keep = 32'd1 *) - (* src = "./Src/and2.v:13.14-13.15" *) - (* keep = 32'd1 *) - (* src = "./Src/and2.v:13.14-13.15" *) - wire c; - (* init = 1'h0 *) - wire \$iopadmap$c ; - wire \$iopadmap$b ; - wire \$iopadmap$a ; - wire \$auto$clkbufmap.cc:295:execute$499 ; - (* src = "./Src/and2.v:10.9-10.10" *) - (* src = "./Src/and2.v:10.9-10.10" *) - wire b; - (* src = "./Src/and2.v:9.9-9.10" *) - (* src = "./Src/and2.v:9.9-9.10" *) - wire a; - (* src = "./Src/and2.v:11.9-11.12" *) - (* src = "./Src/and2.v:11.9-11.12" *) - wire clk; - (* src = "./Src/and2.v:12.9-12.14" *) - (* src = "./Src/and2.v:12.9-12.14" *) - wire reset; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$and2.a ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$510.a ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$a ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$and2.b ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$510.b ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$b ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$and2.c ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$c ), - .O(\$auto$rs_design_edit.cc:682:execute$510.c ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$and2.clk ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$510.clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$clk ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$and2.reset ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$510.reset ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$reset ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/cschai/github/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$flatten$auto$rs_design_edit.cc:682:execute$510.$auto$clkbufmap.cc:262:execute$497 ( - .I(\$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$clk ), - .O(\$flatten$auto$rs_design_edit.cc:682:execute$510.$auto$clkbufmap.cc:295:execute$499 ) - ); - fabric_and2 \$auto$rs_design_edit.cc:680:execute$509 ( - .\$auto$clkbufmap.cc:295:execute$499 (\$auto$clkbufmap.cc:295:execute$499 ), - .\$iopadmap$a (\$iopadmap$a ), - .\$iopadmap$b (\$iopadmap$b ), - .\$iopadmap$c (\$iopadmap$c ), - .\$iopadmap$reset (\$iopadmap$reset ) - ); - assign \$auto$clkbufmap.cc:295:execute$499 = \$flatten$auto$rs_design_edit.cc:682:execute$510.$auto$clkbufmap.cc:295:execute$499 ; - assign \$iopadmap$a = \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$a ; - assign \$iopadmap$b = \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$b ; - assign \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$c = \$iopadmap$c ; - assign \$iopadmap$reset = \$flatten$auto$rs_design_edit.cc:682:execute$510.$iopadmap$reset ; - assign \$auto$rs_design_edit.cc:682:execute$510.a = a; - assign \$auto$rs_design_edit.cc:682:execute$510.b = b; - assign c = \$auto$rs_design_edit.cc:682:execute$510.c ; - assign \$auto$rs_design_edit.cc:682:execute$510.clk = clk; - assign \$auto$rs_design_edit.cc:682:execute$510.reset = reset; -endmodule diff --git a/design_edit/Tests/primitive_example_design_7/pin_mapping.pin b/design_edit/Tests/primitive_example_design_7/pin_mapping.pin deleted file mode 100644 index 42097452f..000000000 --- a/design_edit/Tests/primitive_example_design_7/pin_mapping.pin +++ /dev/null @@ -1,14 +0,0 @@ -set_property mode Mode_BP_SDR_A_RX HR_3_0_0P -set_pin_loc a HR_3_0_0P - -set_property mode Mode_BP_SDR_A_RX HR_2_0_0P -set_pin_loc b HR_2_0_0P - -set_property mode Mode_BP_SDR_A_RX HR_1_0_0P -set_pin_loc reset HR_1_0_0P - -set_property mode Mode_BP_SDR_A_RX HP_2_0_0P -set_pin_loc clk HP_2_0_0P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_0P -set_pin_loc c HR_5_0_0P diff --git a/design_edit/Tests/primitive_example_design_7/primitive_example_design_7.ys b/design_edit/Tests/primitive_example_design_7/primitive_example_design_7.ys deleted file mode 100644 index cf07348f9..000000000 --- a/design_edit/Tests/primitive_example_design_7/primitive_example_design_7.ys +++ /dev/null @@ -1,25 +0,0 @@ - -# Yosys synthesis script for ${TOP_MODULE} -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./Src/and2.v - -# Technology mapping -hierarchy -auto-top - - - -plugin -i synth-rs - -synth_rs -tech genesis3 -de -goal mixed -effort high -carry auto -new_dsp19x2 -new_tdp36k -max_lut 34848 -max_reg 69696 -max_device_dsp 154 -max_device_bram 154 -max_device_carry_length 48 -max_dsp 154 -max_bram 154 -max_carry_length 48 -fsm_encoding onehot -de_max_threads -1 -write_rtlil design.rtlil -write_verilog -noexpr -nodec -norename -v ./tmp/and2_wio_post_synth.v -write_blif -param ./tmp/and2_wio_post_synth.eblif - -plugin -i design-edit -design_edit -tech genesis3 -sdc pin_mapping.pin -json ./tmp/io_config.json -w ./tmp//wrapper_and2_wio_post_synth.v ./tmp//wrapper_and2_wio_post_synth.eblif -write_verilog -noexpr -nodec -norename -v ./tmp/fab_and2_wio_post_synth.v -write_blif -param ./tmp/fab_and2_wio_post_synth.eblif - - \ No newline at end of file diff --git a/design_edit/Tests/primitive_example_design_8/Src/and2.v b/design_edit/Tests/primitive_example_design_8/Src/and2.v deleted file mode 100644 index e5cacbe09..000000000 --- a/design_edit/Tests/primitive_example_design_8/Src/and2.v +++ /dev/null @@ -1,216 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module and2(a, b, clk, reset, c, out); - input [1:0] clk; - input a; - input b; - output c; - output out; - input reset; - wire out; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap505$iopadmap$and2.reset.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap505$iopadmap$and2.reset.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap505$iopadmap$and2.reset.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap504$iopadmap$and2.c.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap504$iopadmap$and2.c.C ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap504$iopadmap$and2.c.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap503$iopadmap$and2.b.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap503$iopadmap$and2.b.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap503$iopadmap$and2.b.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap502$iopadmap$and2.a.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap502$iopadmap$and2.a.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap502$iopadmap$and2.a.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap501$iopadmap$and2.clk.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap501$iopadmap$and2.clk.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap501$iopadmap$and2.clk.O ; - wire [1:0] \$iopadmap$clk ; - (* src = "./Src/and2.v:11.9-11.12" *) - (* src = "./Src/and2.v:11.9-11.12" *) - wire [1:0] clk; - (* src = "./Src/and2.v:9.9-9.10" *) - (* src = "./Src/and2.v:9.9-9.10" *) - wire a; - (* src = "./Src/and2.v:10.9-10.10" *) - (* src = "./Src/and2.v:10.9-10.10" *) - wire b; - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:13.14-13.15" *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:13.14-13.15" *) - wire c; - (* src = "./Src/and2.v:12.9-12.14" *) - (* src = "./Src/and2.v:12.9-12.14" *) - wire reset; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap500$auto$clkbufmap.cc:261:execute$497.O ; - wire [1:0] \$auto$clkbufmap.cc:294:execute$499 ; - wire \$iopadmap$a ; - wire \$abc$221$li0_li0 ; - wire \$abc$221$li1_li1 ; - wire \$abc$221$li2_li2 ; - wire \$iopadmap$b ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.7-16.12" *) - wire a_reg; - (* init = 1'h0 *) - wire \$iopadmap$c ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.14-16.19" *) - wire b_reg; - wire \$iopadmap$reset ; - wire [1:0] \$auto$clkbufmap.cc:262:execute$498 ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap500$auto$clkbufmap.cc:261:execute$497.I ; - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$494 ( - .Y(\$abc$221$li2_li2 ), - .A({ b_reg, a_reg, \$iopadmap$reset }) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.b ( - .O(\$iopadmap$b ), - .EN(1'h1), - .I(b) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.a ( - .O(\$iopadmap$a ), - .EN(1'h1), - .I(a) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.clk ( - .O(\$iopadmap$clk[0] ), - .EN(1'h1), - .I(clk[0]) - ); - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.clk1 ( - .O(\$iopadmap$clk[1] ), - .EN(1'h1), - .I(clk[1]) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$and2.c ( - .O(c), - .I(\$iopadmap$c ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$clkbufmap.cc:261:execute$497 ( - .O(\$auto$clkbufmap.cc:294:execute$499[0] ), - .I(\$auto$clkbufmap.cc:262:execute$498[0] ) - ); - CLK_BUF \$auto$clkbufmap.cc:261:execute$4971 ( - .O(\$auto$clkbufmap.cc:294:execute$499[1] ), - .I(\$auto$clkbufmap.cc:262:execute$498[1] ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$222 ( - .C(\$auto$clkbufmap.cc:294:execute$499[0] ), - .D(\$abc$221$li0_li0 ), - .E(1'h1), - .Q(a_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$223 ( - .C(\$auto$clkbufmap.cc:294:execute$499[0] ), - .D(\$abc$221$li1_li1 ), - .E(1'h1), - .Q(b_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$224 ( - .C(\$auto$clkbufmap.cc:294:execute$499[0] ), - .D(\$abc$221$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$496 ( - .Y(\$abc$221$li0_li0 ), - .A({ \$iopadmap$a , \$iopadmap$reset }) - ); - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$4961 ( - .Y(out ), - .A({ \$iopadmap$a , \$auto$clkbufmap.cc:294:execute$499[1] }) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.reset ( - .O(\$iopadmap$reset ), - .EN(1'h1), - .I(reset) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$495 ( - .Y(\$abc$221$li1_li1 ), - .A({ \$iopadmap$b , \$iopadmap$reset }) - ); - assign \$auto$clkbufmap.cc:262:execute$498[0] = \$iopadmap$clk[0] ; - assign \$auto$clkbufmap.cc:262:execute$498[1] = \$iopadmap$clk[1] ; -endmodule diff --git a/design_edit/Tests/primitive_example_design_8/constraints.sdc b/design_edit/Tests/primitive_example_design_8/constraints.sdc deleted file mode 100644 index 663874218..000000000 --- a/design_edit/Tests/primitive_example_design_8/constraints.sdc +++ /dev/null @@ -1,9 +0,0 @@ -# SDC file example - -# Setting a clock frequency of 200 MHz (5nS period) -create_clock -period 5 clk -set_input_delay -max 0 -clock clk [get_ports {a}] -set_input_delay -max 0 -clock clk [get_ports {b}] -set_input_delay -max 0 -clock clk [get_ports {reset}] -set_output_delay -max 0 -clock clk [get_ports {c}] - diff --git a/design_edit/Tests/primitive_example_design_8/gold/fab_and2_wio_post_synth.eblif b/design_edit/Tests/primitive_example_design_8/gold/fab_and2_wio_post_synth.eblif deleted file mode 100644 index 76de09cd0..000000000 --- a/design_edit/Tests/primitive_example_design_8/gold/fab_and2_wio_post_synth.eblif +++ /dev/null @@ -1,21 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_and2 -.inputs \$iopadmap$a \$iopadmap$b \$iopadmap$reset \$auto$clkbufmap.cc:294:execute$499[0] \$auto$clkbufmap.cc:294:execute$499[1] -.outputs out \$iopadmap$c -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=\$auto$clkbufmap.cc:294:execute$499[0] D=\$abc$221$li0_li0 E=$true Q=a_reg R=$true -.subckt DFFRE C=\$auto$clkbufmap.cc:294:execute$499[0] D=\$abc$221$li1_li1 E=$true Q=b_reg R=$true -.subckt DFFRE C=\$auto$clkbufmap.cc:294:execute$499[0] D=\$abc$221$li2_li2 E=$true Q=\$iopadmap$c R=$true -.subckt LUT3 A[0]=\$iopadmap$reset A[1]=a_reg A[2]=b_reg Y=\$abc$221$li2_li2 -.param INIT_VALUE 01000000 -.subckt LUT2 A[0]=\$iopadmap$reset A[1]=\$iopadmap$b Y=\$abc$221$li1_li1 -.param INIT_VALUE 0100 -.subckt LUT2 A[0]=\$iopadmap$reset A[1]=\$iopadmap$a Y=\$abc$221$li0_li0 -.param INIT_VALUE 0100 -.subckt LUT2 A[0]=\$auto$clkbufmap.cc:294:execute$499[1] A[1]=\$iopadmap$a Y=out -.param INIT_VALUE 0100 -.end diff --git a/design_edit/Tests/primitive_example_design_8/gold/fab_and2_wio_post_synth.v b/design_edit/Tests/primitive_example_design_8/gold/fab_and2_wio_post_synth.v deleted file mode 100644 index f0d043125..000000000 --- a/design_edit/Tests/primitive_example_design_8/gold/fab_and2_wio_post_synth.v +++ /dev/null @@ -1,163 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_and2(out, \$iopadmap$a , \$iopadmap$b , \$iopadmap$c , \$iopadmap$reset , \$auto$clkbufmap.cc:294:execute$499[0] , \$auto$clkbufmap.cc:294:execute$499[1] ); - input \$auto$clkbufmap.cc:294:execute$499[0] ; - input \$auto$clkbufmap.cc:294:execute$499[1] ; - input \$iopadmap$a ; - input \$iopadmap$b ; - output \$iopadmap$c ; - input \$iopadmap$reset ; - output out; - (* src = "./Src/and2.v:148.8-148.46" *) - (* src = "./Src/and2.v:148.8-148.46" *) - wire \$auto$clkbufmap.cc:294:execute$499[0] ; - (* src = "./Src/and2.v:152.8-152.46" *) - (* src = "./Src/and2.v:152.8-152.46" *) - wire \$auto$clkbufmap.cc:294:execute$499[1] ; - (* src = "./Src/and2.v:74.8-74.20" *) - (* src = "./Src/and2.v:74.8-74.20" *) - wire \$iopadmap$a ; - (* src = "./Src/and2.v:78.8-78.20" *) - (* src = "./Src/and2.v:78.8-78.20" *) - wire \$iopadmap$b ; - (* init = 1'h0 *) - (* src = "./Src/and2.v:84.8-84.20" *) - (* init = 1'h0 *) - (* src = "./Src/and2.v:84.8-84.20" *) - wire \$iopadmap$c ; - (* src = "./Src/and2.v:53.14-53.28" *) - wire [1:0] \$iopadmap$clk ; - (* src = "./Src/and2.v:127.8-127.25" *) - wire \$iopadmap$clk[0] ; - (* src = "./Src/and2.v:134.8-134.25" *) - wire \$iopadmap$clk[1] ; - (* src = "./Src/and2.v:89.8-89.24" *) - (* src = "./Src/and2.v:89.8-89.24" *) - wire \$iopadmap$reset ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap500$auto$clkbufmap.cc:261:execute$497.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap500$auto$clkbufmap.cc:261:execute$497.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap501$iopadmap$and2.clk.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap501$iopadmap$and2.clk.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap501$iopadmap$and2.clk.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap502$iopadmap$and2.a.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap502$iopadmap$and2.a.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap502$iopadmap$and2.a.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap503$iopadmap$and2.b.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap503$iopadmap$and2.b.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap503$iopadmap$and2.b.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap504$iopadmap$and2.c.C ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap504$iopadmap$and2.c.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap504$iopadmap$and2.c.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap505$iopadmap$and2.reset.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap505$iopadmap$and2.reset.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap505$iopadmap$and2.reset.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.Y ; - (* src = "./Src/and2.v:90.14-90.49" *) - wire [1:0] \$auto$clkbufmap.cc:262:execute$498 ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.7-16.12" *) - wire a_reg; - (* src = "./Src/and2.v:77.8-77.25" *) - wire \$abc$221$li2_li2 ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.14-16.19" *) - wire b_reg; - (* src = "./Src/and2.v:73.14-73.49" *) - wire [1:0] \$auto$clkbufmap.cc:294:execute$499 ; - (* src = "./Src/and2.v:76.8-76.25" *) - wire \$abc$221$li1_li1 ; - (* src = "./Src/and2.v:8.10-8.13" *) - (* src = "./Src/and2.v:8.10-8.13" *) - wire out; - (* src = "./Src/and2.v:75.8-75.25" *) - wire \$abc$221$li0_li0 ; - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$223 ( - .C(\$auto$clkbufmap.cc:294:execute$499[0] ), - .D(\$abc$221$li1_li1 ), - .E(1'h1), - .Q(b_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$224 ( - .C(\$auto$clkbufmap.cc:294:execute$499[0] ), - .D(\$abc$221$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$494 ( - .A({ b_reg, a_reg, \$iopadmap$reset }), - .Y(\$abc$221$li2_li2 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$495 ( - .A({ \$iopadmap$b , \$iopadmap$reset }), - .Y(\$abc$221$li1_li1 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$496 ( - .A({ \$iopadmap$a , \$iopadmap$reset }), - .Y(\$abc$221$li0_li0 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./Src/and2.v:192.5-195.4" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$4961 ( - .A({ \$iopadmap$a , \$auto$clkbufmap.cc:294:execute$499[1] }), - .Y(out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$222 ( - .C(\$auto$clkbufmap.cc:294:execute$499[0] ), - .D(\$abc$221$li0_li0 ), - .E(1'h1), - .Q(a_reg), - .R(1'h1) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_8/gold/io_config.json b/design_edit/Tests/primitive_example_design_8/gold/io_config.json deleted file mode 100644 index 8937eb20e..000000000 --- a/design_edit/Tests/primitive_example_design_8/gold/io_config.json +++ /dev/null @@ -1,235 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\a (index=0, width=1, offset=0)", - " Detect input port \\b (index=0, width=1, offset=0)", - " Detect output port \\c (index=0, width=1, offset=0)", - " Detect input port \\clk (index=0, width=2, offset=0)", - " Detect input port \\clk (index=1, width=2, offset=0)", - " Detect output port \\out (index=0, width=1, offset=0)", - " Detect input port \\reset (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.a", - " Cell port \\I is connected to input port \\a", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.b", - " Cell port \\I is connected to input port \\b", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF \\$iopadmap$and2.c", - " Cell port \\O is connected to output port \\c", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.clk", - " Cell port \\I is connected to input port \\clk[0]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.clk1", - " Cell port \\I is connected to input port \\clk[1]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.reset", - " Cell port \\I is connected to input port \\reset", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Trace Clock Buffer", - " Try \\I_BUF \\$iopadmap$and2.clk out connection: \\$iopadmap$clk[0]", - " Connected \\$auto$clkbufmap.cc:261:execute$497", - " Additional Connection: \\$auto$clkbufmap.cc:262:execute$498[0]", - " Try \\I_BUF \\$iopadmap$and2.clk1 out connection: \\$iopadmap$clk[1]", - " Connected \\$auto$clkbufmap.cc:261:execute$4971", - " Additional Connection: \\$auto$clkbufmap.cc:262:execute$498[1]", - " Assign location HR_3_0_0P (and properties) to Port a", - " Assign location HR_1_0_0P (and properties) to Port reset", - " Assign location HR_2_0_0P (and properties) to Port b", - " Assign location HP_2_0_0P (and properties) to Port clk", - " Assign location HR_5_0_0P (and properties) to Port c", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.a", - "linked_object" : "a", - "linked_objects" : { - "a" : { - "location" : "HR_3_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "a", - "O" : "$iopadmap$a" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.b", - "linked_object" : "b", - "linked_objects" : { - "b" : { - "location" : "HR_2_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "b", - "O" : "$iopadmap$b" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$and2.c", - "linked_object" : "c", - "linked_objects" : { - "c" : { - "location" : "HR_5_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$c", - "O" : "c" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.clk", - "linked_object" : "clk[0]", - "linked_objects" : { - "clk[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "clk[0]", - "O" : "$iopadmap$clk[0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk[0]_#0", - "linked_object" : "clk[0]", - "linked_objects" : { - "clk[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk[0]", - "O" : "$auto$clkbufmap.cc:262:execute$498[0]" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:261:execute$497", - "linked_object" : "clk[0]", - "linked_objects" : { - "clk[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:262:execute$498[0]", - "O" : "$auto$clkbufmap.cc:294:execute$499[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.clk1", - "linked_object" : "clk[1]", - "linked_objects" : { - "clk[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "clk[1]", - "O" : "$iopadmap$clk[1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk[1]_#0", - "linked_object" : "clk[1]", - "linked_objects" : { - "clk[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$iopadmap$clk[1]", - "O" : "$auto$clkbufmap.cc:262:execute$498[1]" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:261:execute$4971", - "linked_object" : "clk[1]", - "linked_objects" : { - "clk[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "$auto$clkbufmap.cc:262:execute$498[1]", - "O" : "$auto$clkbufmap.cc:294:execute$499[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.reset", - "linked_object" : "reset", - "linked_objects" : { - "reset" : { - "location" : "HR_1_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "reset", - "O" : "$iopadmap$reset" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - } - ] -} diff --git a/design_edit/Tests/primitive_example_design_8/gold/wrapper_and2_wio_post_synth.eblif b/design_edit/Tests/primitive_example_design_8/gold/wrapper_and2_wio_post_synth.eblif deleted file mode 100644 index bebed4b31..000000000 --- a/design_edit/Tests/primitive_example_design_8/gold/wrapper_and2_wio_post_synth.eblif +++ /dev/null @@ -1,48 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model and2 -.inputs a b clk[0] clk[1] reset -.outputs c out -.names $false -.names $true -1 -.names $undef -.subckt fabric_and2 \$auto$clkbufmap.cc:294:execute$499[0]=\$auto$clkbufmap.cc:294:execute$499[0] \$auto$clkbufmap.cc:294:execute$499[1]=\$auto$clkbufmap.cc:294:execute$499[1] \$iopadmap$a=\$iopadmap$a \$iopadmap$b=\$iopadmap$b \$iopadmap$c=\$iopadmap$c \$iopadmap$reset=\$iopadmap$reset out=out -.subckt CLK_BUF I=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[0] O=$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[0] -.subckt CLK_BUF I=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[1] O=$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[1] -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.a O=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$a -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.b O=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$b -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$c O=$auto$rs_design_edit.cc:682:execute$2.c -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.clk[0] O=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[0] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.clk[1] O=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[1] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.reset O=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset -.param WEAK_KEEPER "NONE" -.names $auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[0] \$auto$clkbufmap.cc:294:execute$499[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[1] \$auto$clkbufmap.cc:294:execute$499[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.$iopadmap$a \$iopadmap$a -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.$iopadmap$b \$iopadmap$b -1 1 -.names \$iopadmap$c $auto$rs_design_edit.cc:682:execute$2.$iopadmap$c -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset \$iopadmap$reset -1 1 -.names a $auto$rs_design_edit.cc:682:execute$2.a -1 1 -.names b $auto$rs_design_edit.cc:682:execute$2.b -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.c c -1 1 -.names clk[0] $auto$rs_design_edit.cc:682:execute$2.clk[0] -1 1 -.names clk[1] $auto$rs_design_edit.cc:682:execute$2.clk[1] -1 1 -.names reset $auto$rs_design_edit.cc:682:execute$2.reset -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_8/gold/wrapper_and2_wio_post_synth.v b/design_edit/Tests/primitive_example_design_8/gold/wrapper_and2_wio_post_synth.v deleted file mode 100644 index c2ac29ab2..000000000 --- a/design_edit/Tests/primitive_example_design_8/gold/wrapper_and2_wio_post_synth.v +++ /dev/null @@ -1,159 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module and2(a, b, clk, reset, c, out); - input b; - output c; - input [1:0] clk; - output out; - input a; - input reset; - (* src = "./Src/and2.v:12.9-12.14" *) - wire \$auto$rs_design_edit.cc:682:execute$2.reset ; - (* src = "./Src/and2.v:9.9-9.10" *) - wire \$auto$rs_design_edit.cc:682:execute$2.a ; - (* src = "./Src/and2.v:11.9-11.12" *) - wire [1:0] \$auto$rs_design_edit.cc:682:execute$2.clk ; - (* src = "./Src/and2.v:89.8-89.24" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset ; - (* src = "./Src/and2.v:127.8-127.25" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[0] ; - (* src = "./Src/and2.v:134.8-134.25" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[1] ; - (* src = "./Src/and2.v:10.9-10.10" *) - wire \$auto$rs_design_edit.cc:682:execute$2.b ; - (* src = "./Src/and2.v:148.8-148.46" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[0] ; - (* src = "./Src/and2.v:152.8-152.46" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[1] ; - (* src = "./Src/and2.v:74.8-74.20" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$a ; - (* src = "./Src/and2.v:78.8-78.20" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$b ; - (* init = 1'h0 *) - (* src = "./Src/and2.v:84.8-84.20" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$c ; - (* keep = 32'd1 *) - (* src = "./Src/and2.v:13.14-13.15" *) - wire \$auto$rs_design_edit.cc:682:execute$2.c ; - (* init = 1'h0 *) - (* src = "./Src/and2.v:84.8-84.20" *) - wire \$iopadmap$c ; - (* src = "./Src/and2.v:78.8-78.20" *) - wire \$iopadmap$b ; - (* src = "./Src/and2.v:74.8-74.20" *) - wire \$iopadmap$a ; - (* src = "./Src/and2.v:152.8-152.46" *) - wire \$auto$clkbufmap.cc:294:execute$499[1] ; - (* src = "./Src/and2.v:148.8-148.46" *) - wire \$auto$clkbufmap.cc:294:execute$499[0] ; - (* src = "./Src/and2.v:10.9-10.10" *) - (* src = "./Src/and2.v:10.9-10.10" *) - wire b; - (* keep = 32'd1 *) - (* src = "./Src/and2.v:13.14-13.15" *) - (* keep = 32'd1 *) - (* src = "./Src/and2.v:13.14-13.15" *) - wire c; - (* src = "./Src/and2.v:11.9-11.12" *) - (* src = "./Src/and2.v:11.9-11.12" *) - wire [1:0] clk; - (* src = "./Src/and2.v:8.10-8.13" *) - (* src = "./Src/and2.v:8.10-8.13" *) - wire out; - (* src = "./Src/and2.v:9.9-9.10" *) - (* src = "./Src/and2.v:9.9-9.10" *) - wire a; - (* src = "./Src/and2.v:12.9-12.14" *) - (* src = "./Src/and2.v:12.9-12.14" *) - wire reset; - (* src = "./Src/and2.v:89.8-89.24" *) - wire \$iopadmap$reset ; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.a ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.a ), - .O(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$a ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.b ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.b ), - .O(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$b ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.c ( - .I(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$c ), - .O(\$auto$rs_design_edit.cc:682:execute$2.c ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.clk ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.clk [0]), - .O(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[0] ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./Src/and2.v:133.5-137.4" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.clk1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.clk [1]), - .O(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[1] ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.reset ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.reset ), - .O(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:261:execute$497 ( - .I(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[0] ), - .O(\$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[0] ) - ); - (* module_not_derived = 32'd1 *) - (* src = "./Src/and2.v:151.11-154.4" *) - CLK_BUF \$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:261:execute$4971 ( - .I(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$clk[1] ), - .O(\$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[1] ) - ); - fabric_and2 \$auto$rs_design_edit.cc:680:execute$1 ( - .\$auto$clkbufmap.cc:294:execute$499[0] (\$auto$clkbufmap.cc:294:execute$499[0] ), - .\$auto$clkbufmap.cc:294:execute$499[1] (\$auto$clkbufmap.cc:294:execute$499[1] ), - .\$iopadmap$a (\$iopadmap$a ), - .\$iopadmap$b (\$iopadmap$b ), - .\$iopadmap$c (\$iopadmap$c ), - .\$iopadmap$reset (\$iopadmap$reset ), - .out(out) - ); - assign \$auto$clkbufmap.cc:294:execute$499[0] = \$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[0] ; - assign \$auto$clkbufmap.cc:294:execute$499[1] = \$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:294:execute$499[1] ; - assign \$iopadmap$a = \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$a ; - assign \$iopadmap$b = \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$b ; - assign \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$c = \$iopadmap$c ; - assign \$iopadmap$reset = \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset ; - assign \$auto$rs_design_edit.cc:682:execute$2.a = a; - assign \$auto$rs_design_edit.cc:682:execute$2.b = b; - assign c = \$auto$rs_design_edit.cc:682:execute$2.c ; - assign \$auto$rs_design_edit.cc:682:execute$2.clk = clk; - assign \$auto$rs_design_edit.cc:682:execute$2.reset = reset; -endmodule diff --git a/design_edit/Tests/primitive_example_design_8/pin_mapping.pin b/design_edit/Tests/primitive_example_design_8/pin_mapping.pin deleted file mode 100644 index 42097452f..000000000 --- a/design_edit/Tests/primitive_example_design_8/pin_mapping.pin +++ /dev/null @@ -1,14 +0,0 @@ -set_property mode Mode_BP_SDR_A_RX HR_3_0_0P -set_pin_loc a HR_3_0_0P - -set_property mode Mode_BP_SDR_A_RX HR_2_0_0P -set_pin_loc b HR_2_0_0P - -set_property mode Mode_BP_SDR_A_RX HR_1_0_0P -set_pin_loc reset HR_1_0_0P - -set_property mode Mode_BP_SDR_A_RX HP_2_0_0P -set_pin_loc clk HP_2_0_0P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_0P -set_pin_loc c HR_5_0_0P diff --git a/design_edit/Tests/primitive_example_design_8/primitive_example_design_8.ys b/design_edit/Tests/primitive_example_design_8/primitive_example_design_8.ys deleted file mode 100644 index 0b4e6236a..000000000 --- a/design_edit/Tests/primitive_example_design_8/primitive_example_design_8.ys +++ /dev/null @@ -1,17 +0,0 @@ - -# Yosys synthesis script for ${TOP_MODULE} -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./Src/and2.v - -# Technology mapping -hierarchy -auto-top -write_rtlil design.rtlil - -plugin -i design-edit -design_edit -tech genesis3 -sdc pin_mapping.pin -json ./tmp/io_config.json -w ./tmp//wrapper_and2_wio_post_synth.v ./tmp//wrapper_and2_wio_post_synth.eblif -write_verilog -noexpr -nodec -norename -v ./tmp/fab_and2_wio_post_synth.v -write_blif -param ./tmp/fab_and2_wio_post_synth.eblif - - \ No newline at end of file diff --git a/design_edit/Tests/primitive_example_design_9/Src/and2.v b/design_edit/Tests/primitive_example_design_9/Src/and2.v deleted file mode 100644 index c68c1ecfb..000000000 --- a/design_edit/Tests/primitive_example_design_9/Src/and2.v +++ /dev/null @@ -1,215 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 07c42e625, gcc 11.1.0-1ubuntu1~20.04 -fPIC -Os) */ - -module and2(a, b, clk, reset, c, out); - input [1:0] clk; - input a; - input b; - output c; - output out; - input reset; - wire out; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap505$iopadmap$and2.reset.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap505$iopadmap$and2.reset.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap505$iopadmap$and2.reset.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap504$iopadmap$and2.c.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap504$iopadmap$and2.c.C ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap504$iopadmap$and2.c.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap503$iopadmap$and2.b.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap503$iopadmap$and2.b.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap503$iopadmap$and2.b.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap502$iopadmap$and2.a.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap502$iopadmap$and2.a.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap502$iopadmap$and2.a.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap501$iopadmap$and2.clk.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap501$iopadmap$and2.clk.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap501$iopadmap$and2.clk.O ; - wire [1:0] io_clk ; - (* src = "./Src/and2.v:11.9-11.12" *) - (* src = "./Src/and2.v:11.9-11.12" *) - wire [1:0] clk; - (* src = "./Src/and2.v:9.9-9.10" *) - (* src = "./Src/and2.v:9.9-9.10" *) - wire a; - (* src = "./Src/and2.v:10.9-10.10" *) - (* src = "./Src/and2.v:10.9-10.10" *) - wire b; - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:13.14-13.15" *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:13.14-13.15" *) - wire c; - (* src = "./Src/and2.v:12.9-12.14" *) - (* src = "./Src/and2.v:12.9-12.14" *) - wire reset; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap500$auto$clkbufmap.cc:261:execute$497.O ; - wire [1:0] intr_wire499 ; - wire \$iopadmap$a ; - wire \$abc$221$li0_li0 ; - wire \$abc$221$li1_li1 ; - wire \$abc$221$li2_li2 ; - wire \$iopadmap$b ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.7-16.12" *) - wire a_reg; - (* init = 1'h0 *) - wire \$iopadmap$c ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.14-16.19" *) - wire b_reg; - wire \$iopadmap$reset ; - wire [1:0] intr_wire498 ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap500$auto$clkbufmap.cc:261:execute$497.I ; - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$494 ( - .Y(\$abc$221$li2_li2 ), - .A({ b_reg, a_reg, \$iopadmap$reset }) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.b ( - .O(\$iopadmap$b ), - .EN(1'h1), - .I(b) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.a ( - .O(\$iopadmap$a ), - .EN(1'h1), - .I(a) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.clk ( - .O(io_clk[0] ), - .EN(1'h1), - .I(clk[0]) - ); - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.clk1 ( - .O(io_clk[1] ), - .EN(1'h1), - .I(clk[1]) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$iopadmap$and2.c ( - .O(c), - .I(\$iopadmap$c ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$clkbufmap.cc:261:execute$497 ( - .O(intr_wire499[0] ), - .I(intr_wire498[0] ) - ); - CLK_BUF \$auto$clkbufmap.cc:261:execute$4971 ( - .O(intr_wire499[1] ), - .I(intr_wire498[1] ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$222 ( - .C(intr_wire499[0] ), - .D(\$abc$221$li0_li0 ), - .E(1'h1), - .Q(a_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$223 ( - .C(intr_wire499[0] ), - .D(\$abc$221$li1_li1 ), - .E(1'h1), - .Q(b_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$224 ( - .C(intr_wire499[0] ), - .D(\$abc$221$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$496 ( - .Y(\$abc$221$li0_li0 ), - .A({ \$iopadmap$a , \$iopadmap$reset }) - ); - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$4961 ( - .Y(out ), - .A({ \$iopadmap$a , intr_wire499[1] }) - ); - (* keep = 32'h00000001 *) - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$iopadmap$and2.reset ( - .O(\$iopadmap$reset ), - .EN(1'h1), - .I(reset) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$495 ( - .Y(\$abc$221$li1_li1 ), - .A({ \$iopadmap$b , \$iopadmap$reset }) - ); - assign intr_wire498 = io_clk ; -endmodule diff --git a/design_edit/Tests/primitive_example_design_9/constraints.sdc b/design_edit/Tests/primitive_example_design_9/constraints.sdc deleted file mode 100644 index 663874218..000000000 --- a/design_edit/Tests/primitive_example_design_9/constraints.sdc +++ /dev/null @@ -1,9 +0,0 @@ -# SDC file example - -# Setting a clock frequency of 200 MHz (5nS period) -create_clock -period 5 clk -set_input_delay -max 0 -clock clk [get_ports {a}] -set_input_delay -max 0 -clock clk [get_ports {b}] -set_input_delay -max 0 -clock clk [get_ports {reset}] -set_output_delay -max 0 -clock clk [get_ports {c}] - diff --git a/design_edit/Tests/primitive_example_design_9/gold/fab_and2_wio_post_synth.eblif b/design_edit/Tests/primitive_example_design_9/gold/fab_and2_wio_post_synth.eblif deleted file mode 100644 index bd5cf5258..000000000 --- a/design_edit/Tests/primitive_example_design_9/gold/fab_and2_wio_post_synth.eblif +++ /dev/null @@ -1,21 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model fabric_and2 -.inputs intr_wire499[0] intr_wire499[1] \$iopadmap$a \$iopadmap$b \$iopadmap$reset -.outputs out \$iopadmap$c -.names $false -.names $true -1 -.names $undef -.subckt DFFRE C=intr_wire499[0] D=\$abc$221$li0_li0 E=$true Q=a_reg R=$true -.subckt DFFRE C=intr_wire499[0] D=\$abc$221$li1_li1 E=$true Q=b_reg R=$true -.subckt DFFRE C=intr_wire499[0] D=\$abc$221$li2_li2 E=$true Q=\$iopadmap$c R=$true -.subckt LUT3 A[0]=\$iopadmap$reset A[1]=a_reg A[2]=b_reg Y=\$abc$221$li2_li2 -.param INIT_VALUE 01000000 -.subckt LUT2 A[0]=\$iopadmap$reset A[1]=\$iopadmap$b Y=\$abc$221$li1_li1 -.param INIT_VALUE 0100 -.subckt LUT2 A[0]=\$iopadmap$reset A[1]=\$iopadmap$a Y=\$abc$221$li0_li0 -.param INIT_VALUE 0100 -.subckt LUT2 A[0]=intr_wire499[1] A[1]=\$iopadmap$a Y=out -.param INIT_VALUE 0100 -.end diff --git a/design_edit/Tests/primitive_example_design_9/gold/fab_and2_wio_post_synth.v b/design_edit/Tests/primitive_example_design_9/gold/fab_and2_wio_post_synth.v deleted file mode 100644 index 1eac1b9d0..000000000 --- a/design_edit/Tests/primitive_example_design_9/gold/fab_and2_wio_post_synth.v +++ /dev/null @@ -1,151 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module fabric_and2(out, intr_wire499, \$iopadmap$a , \$iopadmap$b , \$iopadmap$c , \$iopadmap$reset ); - input \$iopadmap$reset ; - input \$iopadmap$a ; - input \$iopadmap$b ; - output \$iopadmap$c ; - input [1:0] intr_wire499; - output out; - (* src = "./Src/and2.v:89.8-89.24" *) - (* src = "./Src/and2.v:89.8-89.24" *) - wire \$iopadmap$reset ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:10.12-10.13" *) - wire \$techmap500$auto$clkbufmap.cc:261:execute$497.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:11.12-11.13" *) - wire \$techmap500$auto$clkbufmap.cc:261:execute$497.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap501$iopadmap$and2.clk.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap501$iopadmap$and2.clk.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap501$iopadmap$and2.clk.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap502$iopadmap$and2.a.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap502$iopadmap$and2.a.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap502$iopadmap$and2.a.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap503$iopadmap$and2.b.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap503$iopadmap$and2.b.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap503$iopadmap$and2.b.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:38.16-38.17" *) - wire \$techmap504$iopadmap$and2.c.C ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:37.16-37.17" *) - wire \$techmap504$iopadmap$and2.c.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:39.16-39.17" *) - wire \$techmap504$iopadmap$and2.c.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:25.16-25.18" *) - wire \$techmap505$iopadmap$and2.reset.EN ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:24.16-24.17" *) - wire \$techmap505$iopadmap$and2.reset.I ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:26.16-26.17" *) - wire \$techmap505$iopadmap$and2.reset.O ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap506$abc$493$auto$blifparse.cc:515:parse_blif$495.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [1:0] \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap507$abc$493$auto$blifparse.cc:515:parse_blif$496.Y ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:12.23-12.24" *) - wire [2:0] \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.A ; - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:13.13-13.14" *) - wire \$techmap508$abc$493$auto$blifparse.cc:515:parse_blif$494.Y ; - (* src = "./Src/and2.v:74.8-74.20" *) - (* src = "./Src/and2.v:74.8-74.20" *) - wire \$iopadmap$a ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.7-16.12" *) - wire a_reg; - (* src = "./Src/and2.v:77.8-77.25" *) - wire \$abc$221$li2_li2 ; - (* init = 1'h0 *) - (* keep = 32'h00000001 *) - (* src = "./Src/and2.v:16.14-16.19" *) - wire b_reg; - (* src = "./Src/and2.v:78.8-78.20" *) - (* src = "./Src/and2.v:78.8-78.20" *) - wire \$iopadmap$b ; - (* src = "./Src/and2.v:76.8-76.25" *) - wire \$abc$221$li1_li1 ; - (* init = 1'h0 *) - (* src = "./Src/and2.v:84.8-84.20" *) - (* init = 1'h0 *) - (* src = "./Src/and2.v:84.8-84.20" *) - wire \$iopadmap$c ; - (* src = "./Src/and2.v:73.14-73.26" *) - (* src = "./Src/and2.v:73.14-73.26" *) - wire [1:0] intr_wire499; - (* src = "./Src/and2.v:53.14-53.20" *) - wire [1:0] io_clk; - (* src = "./Src/and2.v:8.10-8.13" *) - (* src = "./Src/and2.v:8.10-8.13" *) - wire out; - (* src = "./Src/and2.v:75.8-75.25" *) - wire \$abc$221$li0_li0 ; - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$223 ( - .C(intr_wire499[0]), - .D(\$abc$221$li1_li1 ), - .E(1'h1), - .Q(b_reg), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$224 ( - .C(intr_wire499[0]), - .D(\$abc$221$li2_li2 ), - .E(1'h1), - .Q(\$iopadmap$c ), - .R(1'h1) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:25.38-25.69" *) - LUT3 #( - .INIT_VALUE(8'h40) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$494 ( - .A({ b_reg, a_reg, \$iopadmap$reset }), - .Y(\$abc$221$li2_li2 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$495 ( - .A({ \$iopadmap$b , \$iopadmap$reset }), - .Y(\$abc$221$li1_li1 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/lut_map.v:21.38-21.69" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$496 ( - .A({ \$iopadmap$a , \$iopadmap$reset }), - .Y(\$abc$221$li0_li0 ) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "./Src/and2.v:192.5-195.4" *) - LUT2 #( - .INIT_VALUE(4'h4) - ) \$abc$493$auto$blifparse.cc:515:parse_blif$4961 ( - .A({ \$iopadmap$a , intr_wire499[1] }), - .Y(out) - ); - (* module_not_derived = 32'h00000001 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/ffs_map.v:10.11-10.70" *) - DFFRE \$abc$221$auto$blifparse.cc:362:parse_blif$222 ( - .C(intr_wire499[0]), - .D(\$abc$221$li0_li0 ), - .E(1'h1), - .Q(a_reg), - .R(1'h1) - ); -endmodule diff --git a/design_edit/Tests/primitive_example_design_9/gold/io_config.json b/design_edit/Tests/primitive_example_design_9/gold/io_config.json deleted file mode 100644 index 0cf121430..000000000 --- a/design_edit/Tests/primitive_example_design_9/gold/io_config.json +++ /dev/null @@ -1,235 +0,0 @@ -{ - "messages" : [ - "Start of IO Analysis", - " Get Ports", - " Detect input port \\a (index=0, width=1, offset=0)", - " Detect input port \\b (index=0, width=1, offset=0)", - " Detect output port \\c (index=0, width=1, offset=0)", - " Detect input port \\clk (index=0, width=2, offset=0)", - " Detect input port \\clk (index=1, width=2, offset=0)", - " Detect output port \\out (index=0, width=1, offset=0)", - " Detect input port \\reset (index=0, width=1, offset=0)", - " Get Port Primitives", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.a", - " Cell port \\I is connected to input port \\a", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.b", - " Cell port \\I is connected to input port \\b", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\O_BUF \\$iopadmap$and2.c", - " Cell port \\O is connected to output port \\c", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.clk", - " Cell port \\I is connected to input port \\clk[0]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.clk1", - " Cell port \\I is connected to input port \\clk[1]", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Get important connection of cell \\I_BUF \\$iopadmap$and2.reset", - " Cell port \\I is connected to input port \\reset", - " Parameter \\WEAK_KEEPER: \"NONE\"", - " Trace Clock Buffer", - " Try \\I_BUF \\$iopadmap$and2.clk out connection: \\io_clk[0]", - " Connected \\$auto$clkbufmap.cc:261:execute$497", - " Additional Connection: \\intr_wire498[0]", - " Try \\I_BUF \\$iopadmap$and2.clk1 out connection: \\io_clk[1]", - " Connected \\$auto$clkbufmap.cc:261:execute$4971", - " Additional Connection: \\intr_wire498[1]", - " Assign location HR_3_0_0P (and properties) to Port a", - " Assign location HR_1_0_0P (and properties) to Port reset", - " Assign location HR_2_0_0P (and properties) to Port b", - " Assign location HP_2_0_0P (and properties) to Port clk", - " Assign location HR_5_0_0P (and properties) to Port c", - "End of IO Analysis" - ], - "instances" : [ - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.a", - "linked_object" : "a", - "linked_objects" : { - "a" : { - "location" : "HR_3_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "a", - "O" : "$iopadmap$a" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.b", - "linked_object" : "b", - "linked_objects" : { - "b" : { - "location" : "HR_2_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "b", - "O" : "$iopadmap$b" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "O_BUF", - "name" : "$iopadmap$and2.c", - "linked_object" : "c", - "linked_objects" : { - "c" : { - "location" : "HR_5_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_TX" - } - } - }, - "connectivity" : { - "I" : "$iopadmap$c", - "O" : "c" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.clk", - "linked_object" : "clk[0]", - "linked_objects" : { - "clk[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "clk[0]", - "O" : "io_clk[0]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk[0]_#0", - "linked_object" : "clk[0]", - "linked_objects" : { - "clk[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "io_clk[0]", - "O" : "intr_wire498[0]" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:261:execute$497", - "linked_object" : "clk[0]", - "linked_objects" : { - "clk[0]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "intr_wire498[0]", - "O" : "intr_wire499[0]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.clk1", - "linked_object" : "clk[1]", - "linked_objects" : { - "clk[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "clk[1]", - "O" : "io_clk[1]" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - }, - { - "module" : "WIRE", - "name" : "AUTO_CLK_BUF_clk[1]_#0", - "linked_object" : "clk[1]", - "linked_objects" : { - "clk[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "io_clk[1]", - "O" : "intr_wire498[1]" - }, - "parameters" : { - } - }, - { - "module" : "CLK_BUF", - "name" : "$auto$clkbufmap.cc:261:execute$4971", - "linked_object" : "clk[1]", - "linked_objects" : { - "clk[1]" : { - "location" : "", - "properties" : { - } - } - }, - "connectivity" : { - "I" : "intr_wire498[1]", - "O" : "intr_wire499[1]" - }, - "parameters" : { - } - }, - { - "module" : "I_BUF", - "name" : "$iopadmap$and2.reset", - "linked_object" : "reset", - "linked_objects" : { - "reset" : { - "location" : "HR_1_0_0P", - "properties" : { - "mode" : "Mode_BP_SDR_A_RX" - } - } - }, - "connectivity" : { - "I" : "reset", - "O" : "$iopadmap$reset" - }, - "parameters" : { - "WEAK_KEEPER" : "NONE" - } - } - ] -} diff --git a/design_edit/Tests/primitive_example_design_9/gold/wrapper_and2_wio_post_synth.eblif b/design_edit/Tests/primitive_example_design_9/gold/wrapper_and2_wio_post_synth.eblif deleted file mode 100644 index f4426f252..000000000 --- a/design_edit/Tests/primitive_example_design_9/gold/wrapper_and2_wio_post_synth.eblif +++ /dev/null @@ -1,48 +0,0 @@ -# Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model and2 -.inputs a b clk[0] clk[1] reset -.outputs c out -.names $false -.names $true -1 -.names $undef -.subckt fabric_and2 \$iopadmap$a=\$iopadmap$a \$iopadmap$b=\$iopadmap$b \$iopadmap$c=\$iopadmap$c \$iopadmap$reset=\$iopadmap$reset intr_wire499[0]=intr_wire499[0] intr_wire499[1]=intr_wire499[1] out=out -.subckt CLK_BUF I=$auto$rs_design_edit.cc:682:execute$2.io_clk[0] O=$auto$rs_design_edit.cc:682:execute$2.intr_wire499[0] -.subckt CLK_BUF I=$auto$rs_design_edit.cc:682:execute$2.io_clk[1] O=$auto$rs_design_edit.cc:682:execute$2.intr_wire499[1] -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.a O=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$a -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.b O=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$b -.param WEAK_KEEPER "NONE" -.subckt O_BUF I=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$c O=$auto$rs_design_edit.cc:682:execute$2.c -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.clk[0] O=$auto$rs_design_edit.cc:682:execute$2.io_clk[0] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.clk[1] O=$auto$rs_design_edit.cc:682:execute$2.io_clk[1] -.param WEAK_KEEPER "NONE" -.subckt I_BUF EN=$true I=$auto$rs_design_edit.cc:682:execute$2.reset O=$auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset -.param WEAK_KEEPER "NONE" -.names $auto$rs_design_edit.cc:682:execute$2.$iopadmap$a \$iopadmap$a -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.$iopadmap$b \$iopadmap$b -1 1 -.names \$iopadmap$c $auto$rs_design_edit.cc:682:execute$2.$iopadmap$c -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset \$iopadmap$reset -1 1 -.names a $auto$rs_design_edit.cc:682:execute$2.a -1 1 -.names b $auto$rs_design_edit.cc:682:execute$2.b -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.c c -1 1 -.names clk[0] $auto$rs_design_edit.cc:682:execute$2.clk[0] -1 1 -.names clk[1] $auto$rs_design_edit.cc:682:execute$2.clk[1] -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.intr_wire499[0] intr_wire499[0] -1 1 -.names $auto$rs_design_edit.cc:682:execute$2.intr_wire499[1] intr_wire499[1] -1 1 -.names reset $auto$rs_design_edit.cc:682:execute$2.reset -1 1 -.end diff --git a/design_edit/Tests/primitive_example_design_9/gold/wrapper_and2_wio_post_synth.v b/design_edit/Tests/primitive_example_design_9/gold/wrapper_and2_wio_post_synth.v deleted file mode 100644 index 02efa7b8a..000000000 --- a/design_edit/Tests/primitive_example_design_9/gold/wrapper_and2_wio_post_synth.v +++ /dev/null @@ -1,151 +0,0 @@ -/* Generated by Yosys 0.18+10 (git sha1 8ecc445e4, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ - -module and2(a, b, clk, reset, c, out); - output out; - input reset; - output c; - input b; - input a; - input [1:0] clk; - (* src = "./Src/and2.v:9.9-9.10" *) - wire \$auto$rs_design_edit.cc:682:execute$2.a ; - (* keep = 32'd1 *) - (* src = "./Src/and2.v:13.14-13.15" *) - wire \$auto$rs_design_edit.cc:682:execute$2.c ; - (* src = "./Src/and2.v:11.9-11.12" *) - wire [1:0] \$auto$rs_design_edit.cc:682:execute$2.clk ; - (* src = "./Src/and2.v:74.8-74.20" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$a ; - (* src = "./Src/and2.v:78.8-78.20" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$b ; - (* init = 1'h0 *) - (* src = "./Src/and2.v:84.8-84.20" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$c ; - (* src = "./Src/and2.v:89.8-89.24" *) - wire \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset ; - (* src = "./Src/and2.v:73.14-73.26" *) - wire [1:0] \$auto$rs_design_edit.cc:682:execute$2.intr_wire499 ; - (* src = "./Src/and2.v:12.9-12.14" *) - wire \$auto$rs_design_edit.cc:682:execute$2.reset ; - (* src = "./Src/and2.v:10.9-10.10" *) - wire \$auto$rs_design_edit.cc:682:execute$2.b ; - (* src = "./Src/and2.v:53.14-53.20" *) - wire [1:0] \$auto$rs_design_edit.cc:682:execute$2.io_clk ; - (* src = "./Src/and2.v:8.10-8.13" *) - (* src = "./Src/and2.v:8.10-8.13" *) - wire out; - (* src = "./Src/and2.v:12.9-12.14" *) - (* src = "./Src/and2.v:12.9-12.14" *) - wire reset; - (* keep = 32'd1 *) - (* src = "./Src/and2.v:13.14-13.15" *) - (* keep = 32'd1 *) - (* src = "./Src/and2.v:13.14-13.15" *) - wire c; - (* src = "./Src/and2.v:73.14-73.26" *) - wire [1:0] intr_wire499; - (* src = "./Src/and2.v:89.8-89.24" *) - wire \$iopadmap$reset ; - (* init = 1'h0 *) - (* src = "./Src/and2.v:84.8-84.20" *) - wire \$iopadmap$c ; - (* src = "./Src/and2.v:78.8-78.20" *) - wire \$iopadmap$b ; - (* src = "./Src/and2.v:74.8-74.20" *) - wire \$iopadmap$a ; - (* src = "./Src/and2.v:10.9-10.10" *) - (* src = "./Src/and2.v:10.9-10.10" *) - wire b; - (* src = "./Src/and2.v:9.9-9.10" *) - (* src = "./Src/and2.v:9.9-9.10" *) - wire a; - (* src = "./Src/and2.v:11.9-11.12" *) - (* src = "./Src/and2.v:11.9-11.12" *) - wire [1:0] clk; - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.a ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.a ), - .O(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$a ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.b ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.b ), - .O(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$b ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:41.13-41.44" *) - O_BUF \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.c ( - .I(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$c ), - .O(\$auto$rs_design_edit.cc:682:execute$2.c ) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.clk ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.clk [0]), - .O(\$auto$rs_design_edit.cc:682:execute$2.io_clk [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./Src/and2.v:133.5-137.4" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.clk1 ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.clk [1]), - .O(\$auto$rs_design_edit.cc:682:execute$2.io_clk [1]) - ); - (* keep = 32'd1 *) - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:29.41-29.81" *) - I_BUF #( - .WEAK_KEEPER("NONE") - ) \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$and2.reset ( - .EN(1'h1), - .I(\$auto$rs_design_edit.cc:682:execute$2.reset ), - .O(\$auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset ) - ); - (* module_not_derived = 32'd1 *) - (* src = "/nfs_scratch/scratch/eda/behzad/pp/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis3/io_cell_final_map.v:14.13-14.45" *) - CLK_BUF \$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:261:execute$497 ( - .I(\$auto$rs_design_edit.cc:682:execute$2.io_clk [0]), - .O(\$auto$rs_design_edit.cc:682:execute$2.intr_wire499 [0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "./Src/and2.v:151.11-154.4" *) - CLK_BUF \$auto$rs_design_edit.cc:682:execute$2.$auto$clkbufmap.cc:261:execute$4971 ( - .I(\$auto$rs_design_edit.cc:682:execute$2.io_clk [1]), - .O(\$auto$rs_design_edit.cc:682:execute$2.intr_wire499 [1]) - ); - fabric_and2 \$auto$rs_design_edit.cc:680:execute$1 ( - .\$iopadmap$a (\$iopadmap$a ), - .\$iopadmap$b (\$iopadmap$b ), - .\$iopadmap$c (\$iopadmap$c ), - .\$iopadmap$reset (\$iopadmap$reset ), - .intr_wire499(intr_wire499), - .out(out) - ); - assign \$iopadmap$a = \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$a ; - assign \$iopadmap$b = \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$b ; - assign \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$c = \$iopadmap$c ; - assign \$iopadmap$reset = \$auto$rs_design_edit.cc:682:execute$2.$iopadmap$reset ; - assign \$auto$rs_design_edit.cc:682:execute$2.a = a; - assign \$auto$rs_design_edit.cc:682:execute$2.b = b; - assign c = \$auto$rs_design_edit.cc:682:execute$2.c ; - assign \$auto$rs_design_edit.cc:682:execute$2.clk = clk; - assign intr_wire499 = \$auto$rs_design_edit.cc:682:execute$2.intr_wire499 ; - assign \$auto$rs_design_edit.cc:682:execute$2.reset = reset; -endmodule diff --git a/design_edit/Tests/primitive_example_design_9/pin_mapping.pin b/design_edit/Tests/primitive_example_design_9/pin_mapping.pin deleted file mode 100644 index 42097452f..000000000 --- a/design_edit/Tests/primitive_example_design_9/pin_mapping.pin +++ /dev/null @@ -1,14 +0,0 @@ -set_property mode Mode_BP_SDR_A_RX HR_3_0_0P -set_pin_loc a HR_3_0_0P - -set_property mode Mode_BP_SDR_A_RX HR_2_0_0P -set_pin_loc b HR_2_0_0P - -set_property mode Mode_BP_SDR_A_RX HR_1_0_0P -set_pin_loc reset HR_1_0_0P - -set_property mode Mode_BP_SDR_A_RX HP_2_0_0P -set_pin_loc clk HP_2_0_0P - -set_property mode Mode_BP_SDR_A_TX HR_5_0_0P -set_pin_loc c HR_5_0_0P diff --git a/design_edit/Tests/primitive_example_design_9/primitive_example_design_9.ys b/design_edit/Tests/primitive_example_design_9/primitive_example_design_9.ys deleted file mode 100644 index 0b4e6236a..000000000 --- a/design_edit/Tests/primitive_example_design_9/primitive_example_design_9.ys +++ /dev/null @@ -1,17 +0,0 @@ - -# Yosys synthesis script for ${TOP_MODULE} -# Read source files -read_verilog -sv ../../../yosys-rs-plugin/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v -verilog_defines -read_verilog ./Src/and2.v - -# Technology mapping -hierarchy -auto-top -write_rtlil design.rtlil - -plugin -i design-edit -design_edit -tech genesis3 -sdc pin_mapping.pin -json ./tmp/io_config.json -w ./tmp//wrapper_and2_wio_post_synth.v ./tmp//wrapper_and2_wio_post_synth.eblif -write_verilog -noexpr -nodec -norename -v ./tmp/fab_and2_wio_post_synth.v -write_blif -param ./tmp/fab_and2_wio_post_synth.eblif - - \ No newline at end of file diff --git a/design_edit/src/netlist_checker.cc b/design_edit/src/netlist_checker.cc new file mode 100644 index 000000000..937aab670 --- /dev/null +++ b/design_edit/src/netlist_checker.cc @@ -0,0 +1,758 @@ +/** + * @file netlist_checker.cc + * @author Behzad Mehmood (behzadmehmood82@gmail.com) + * @author Manadher Kharroubi (manadher@gmail.com) + * @brief + * @version 0.1 + * @date 2024-09 + * + * @copyright Copyright (c) 2024 + */ +#include "netlist_checker.h" + +std::string NETLIST_CHECKER::escaped_id(const std::string &input) { + std::string result; + result.reserve(input.size()); + for (char c : input) { + if (c != '\\') { + result.push_back(c); + } + } + return result; +} + +void NETLIST_CHECKER::set_difference(const pool& set1, + const pool& set2) +{ + for (auto &bit : set1) + { + if (!set2.count(bit)) + { + diff.insert(bit); + } + } +} + +void NETLIST_CHECKER::write_checker_file() +{ + std::ofstream netlist_checker_file("netlist_checker.log"); + if (netlist_checker_file.is_open()) + { + netlist_checker_file << netlist_checker.str(); + netlist_checker_file.close(); + } + + netlist_checker.str(""); + netlist_checker.clear(); +} + +void NETLIST_CHECKER::gather_prims_data(Module* mod) +{ + for (auto cell : mod->cells()) + { + if (cell->type == RTLIL::escape_id("I_BUF") || + cell->type == RTLIL::escape_id("I_BUF_DS")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + for (SigBit bit : conn.second) + { + if (bit.wire != nullptr) + { + if (escaped_id(portName.str()) == "EN") + { + i_buf_ctrls.insert(bit); + } + } + } + } + } else if (cell->type == RTLIL::escape_id("O_BUFT") || + cell->type == RTLIL::escape_id("O_BUFT_DS")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + for (SigBit bit : conn.second) + { + if (bit.wire != nullptr) + { + if (escaped_id(portName.str()) == "T") + { + o_buf_ctrls.insert(bit); + } + } + } + } + } else if (cell->type == RTLIL::escape_id("FCLK_BUF")) + { + feedback_clocks++; + if(feedback_clocks > 8) + log_error("Feedback clock count exceeded, upto 8 feedback clocks are allowed.\n"); + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if(cell->input(portName)) + { + for (SigBit bit : conn.second) + { + if (bit.wire != nullptr) + { + fclk_buf_ins.insert(bit); + } + } + } + } + } else if (cell->type == RTLIL::escape_id("I_DELAY")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if(dly_controls.find(escaped_id(portName.str())) != dly_controls.end()) + { + if(cell->input(portName)) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) dly_in_ctrls.insert(bit); + } else if(cell->output(portName)) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) dly_out_ctrls.insert(bit); + } + } + } + } else if (cell->type == RTLIL::escape_id("O_DELAY")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if(dly_controls.find(escaped_id(portName.str())) != dly_controls.end()) + { + if(cell->input(portName)) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) dly_in_ctrls.insert(bit); + } else if(cell->output(portName)) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) dly_out_ctrls.insert(bit); + } + } + } + } else if (cell->type == RTLIL::escape_id("I_SERDES")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if(i_serdes_controls.find(escaped_id(portName.str())) != i_serdes_controls.end()) + { + if(cell->input(portName)) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) i_serdes_in_ctrls.insert(bit); + } else if(cell->output(portName)) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) i_serdes_out_ctrls.insert(bit); + } + } + } + } else if (cell->type == RTLIL::escape_id("O_SERDES")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if(o_serdes_controls.find(escaped_id(portName.str())) != o_serdes_controls.end()) + { + if(cell->input(portName)) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) o_serdes_in_ctrls.insert(bit); + } else if(cell->output(portName)) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) o_serdes_out_ctrls.insert(bit); + } + } + } + } else if (cell->type == RTLIL::escape_id("I_DDR") || + cell->type == RTLIL::escape_id("O_DDR")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if (portName == RTLIL::escape_id("R") || + portName == RTLIL::escape_id("E")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) ddr_ctrls.insert(bit); + } + } + } + } +} + +void NETLIST_CHECKER::check_idly_data_ins() +{ + netlist_checker << "\nChecking I_DELAY data inputs\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : i_dly_ins) + { + if (!i_buf_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is input data signal of I_DELAY and must be an I_BUF(DS) output\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_idly_data_outs() +{ + netlist_checker << "\nChecking I_DELAY data outputss\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : i_dly_outs) + { + if (!fab_ins.count(bit) && !i_serdes_ins.count(bit) && !i_ddr_ins.count(bit)) + { + netlist_checker << log_signal(bit) << " is output data signal of I_DELAY and must be a fabric/I_SERDES/I_DDR input\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_odly_data_outs() +{ + netlist_checker << "\nChecking O_DELAY data outputs\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : o_dly_outs) + { + if (!o_buf_ins.count(bit)) + { + netlist_checker << log_signal(bit) << " is output data signal of O_DELAY and must be an O_BUF(T/DS) input\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_odly_data_ins() +{ + netlist_checker << "\nChecking O_DELAY data inputss\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : o_dly_ins) + { + if (!fab_outs.count(bit) && !o_serdes_outs.count(bit) && !o_ddr_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is input data signal of O_DELAY and must be a fabric/O_SERDES/O_DDR output\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_dly_cntrls() +{ + netlist_checker << "\nChecking I_DELAY/O_DELAY control signals\n"; + netlist_checker << "================================================================\n"; + for (auto &bit : dly_in_ctrls) + { + if (!fab_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is an input control signal and must be a fabric output\n"; + netlist_error = true; + } + } + + for (auto &bit : dly_out_ctrls) + { + if (!fab_ins.count(bit)) + { + netlist_checker << log_signal(bit) << " is an output control signal and must be a fabric input\n"; + netlist_error = true; + } + } + netlist_checker << "================================================================\n"; +} + +void NETLIST_CHECKER::check_iddr_data_ins() +{ + netlist_checker << "\nChecking I_DDR data inputs\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : i_ddr_ins) + { + if (!i_dly_outs.count(bit) && !i_buf_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is input data signal of I_DDR and must be an I_BUF/I_DELAY output\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_oddr_data_outs() +{ + netlist_checker << "\nChecking O_DDR data outputss\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : o_ddr_outs) + { + if (!o_buf_ins.count(bit) && !o_dly_ins.count(bit)) + { + netlist_checker << log_signal(bit) << " is output data signal of O_DDR and must be an O_DELAY/O_BUF input\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_ddr_cntrls() +{ + netlist_checker << "\nChecking I_DDR/O_DDR control signals\n"; + netlist_checker << "================================================================\n"; + for (auto &bit : ddr_ctrls) + { + if (!fab_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is an input control signal and must be a fabric output\n"; + netlist_error = true; + } + } + + netlist_checker << "================================================================\n"; +} + +void NETLIST_CHECKER::check_iddr_data_outs() +{ + netlist_checker << "\nChecking I_DDR data outputs\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : i_ddr_outs) + { + if (!fab_ins.count(bit)) + { + netlist_checker << log_signal(bit) << " is output data signal of I_DDR and must be a fabric input\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_oddr_data_ins() +{ + netlist_checker << "\nChecking O_DDR data inputss\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : o_ddr_ins) + { + if (!fab_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is input data signal of O_DDR and must be a fabric output\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_iserdes_data_ins() +{ + netlist_checker << "\nChecking I_SERDES data inputs\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : i_serdes_ins) + { + if (!i_dly_outs.count(bit) && !i_buf_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is input data signal of I_SERDES and must be an I_BUF/I_DELAY output\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_iserdes_data_outs() +{ + netlist_checker << "\nChecking I_SERDES data outputs\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : i_serdes_outs) + { + if (!fab_ins.count(bit)) + { + netlist_checker << log_signal(bit) << " is output data signal of I_SERDES and must be a fabric input\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_oserdes_data_ins() +{ + netlist_checker << "\nChecking O_SERDES data inputss\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : o_serdes_ins) + { + if (!fab_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is input data signal of O_SERDES and must be a fabric output\n"; + netlist_error = true; + } + } +} + +void NETLIST_CHECKER::check_oserdes_data_outs() +{ + netlist_checker << "\nChecking O_SERDES data outputss\n"; + netlist_checker << "================================================================\n"; + + for (auto &bit : o_serdes_outs) + { + if (!o_buf_ins.count(bit) && !o_dly_ins.count(bit)) + { + netlist_checker << log_signal(bit) << " is output data signal of O_SERDES and must be an O_DELAY/O_BUF input\n"; + netlist_error = true; + } + } +} + + +void NETLIST_CHECKER::check_serdes_cntrls() +{ + netlist_checker << "\nChecking I_SERDES/O_SERDES control signals\n"; + netlist_checker << "================================================================\n"; + for (auto &bit : i_serdes_in_ctrls) + { + if (!fab_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is an input control signal and must be a fabric output\n"; + netlist_error = true; + } + } + + for (auto &bit : i_serdes_out_ctrls) + { + if (!fab_ins.count(bit)) + { + netlist_checker << log_signal(bit) << " is an output control signal and must be a fabric input\n"; + netlist_error = true; + } + } + + for (auto &bit : o_serdes_in_ctrls) + { + if (!fab_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is an input control signal and must be a fabric output\n"; + netlist_error = true; + } + } + + for (auto &bit : o_serdes_out_ctrls) + { + if (!fab_ins.count(bit)) + { + netlist_checker << log_signal(bit) << " is an output control signal and must be a fabric input\n"; + netlist_error = true; + } + } + netlist_checker << "================================================================\n"; +} + +void NETLIST_CHECKER::check_buf_cntrls() +{ + netlist_checker << "\nChecking Buffer control signals\n"; + netlist_checker << "================================================================\n"; + for (auto bit : i_buf_ctrls) + { + if (!fab_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is an input control signal and must be an output of fabric\n"; + netlist_error = true; + } + } + + for (auto bit : o_buf_ctrls) + { + if (!fab_outs.count(bit)) + { + netlist_checker << log_signal(bit) << " is an input control signal and must be an output of fabric\n"; + netlist_error = true; + } + } + netlist_checker << "================================================================\n"; +} + +void NETLIST_CHECKER::check_fclkbuf_conns() +{ + netlist_checker << "\nChecking FCLK_BUF connections\n"; + netlist_checker << "================================================================\n"; + set_difference(fclk_buf_ins, fab_outs); + if(!diff.empty()) + { + netlist_checker << "The following FCLK_BUF inputs are not fabric outputs\n"; + for (const auto &elem : diff) + { + netlist_checker << "FCLK_BUF_IN : " << log_signal(elem) << "\n"; + } + netlist_error = true; + diff.clear(); + } + netlist_checker << "================================================================\n"; +} + +void NETLIST_CHECKER::check_clkbuf_conns() +{ + set_difference(clk_buf_ins, i_buf_outs); + if(!diff.empty()) + { + netlist_checker << "================================================================\n"; + netlist_checker << "The following CLK_BUF inputs are not connected to I_BUF outputs\n"; + for (const auto &elem : diff) + { + netlist_checker << "CLK_BUF Input : " << log_signal(elem) << "\n"; + } + netlist_checker << "================================================================\n"; + netlist_error = true; + } + + diff.clear(); +} + +void NETLIST_CHECKER::check_buf_conns() +{ + netlist_checker << "Checking Buffer connections\n"; + if (design_inputs == i_buf_ins && design_outputs == o_buf_outs) + { + netlist_checker << "All IO connections are correct.\n"; + return; + } + + diff.clear(); + set_difference(design_inputs, i_buf_ins); + + if(!diff.empty()) + { + netlist_checker << "================================================================\n"; + netlist_checker << "The following inputs are not connected to I_BUFs\n"; + int i=0; + for (const auto &elem : diff) + { + i++; + netlist_checker << "Input : " << log_signal(elem) << "\n"; + } + netlist_checker << "================================================================\n"; + netlist_error = true; + } + + diff.clear(); + set_difference(i_buf_ins, design_inputs); + if(!diff.empty()) + { + netlist_checker << "================================================================\n"; + netlist_checker << "The following I_BUF inputs are not connected to the design inputs\n"; + for (const auto &elem : diff) + { + netlist_checker << "I_BUF Input : " << log_signal(elem) << "\n"; + } + netlist_checker << "================================================================\n"; + netlist_error = true; + } + + diff.clear(); + set_difference(design_outputs, o_buf_outs); + if(!diff.empty()) + { + netlist_checker << "================================================================\n"; + netlist_checker << "The following outputs are not connected to O_BUFs\n"; + for (const auto &elem : diff) + { + netlist_checker << "Output : " << log_signal(elem) << "\n"; + } + netlist_checker << "================================================================\n"; + netlist_error = true; + } + + diff.clear(); + set_difference(o_buf_outs, design_outputs); + if(!diff.empty()) + { + netlist_checker << "================================================================\n"; + netlist_checker << "The following O_BUF outputs are not connected to the design outputs\n"; + for (const auto &elem : diff) + { + netlist_checker << "O_BUF Output : " << log_signal(elem) << "\n"; + } + netlist_checker << "================================================================\n"; + netlist_error = true; + } + + diff.clear(); + return; +} + +void NETLIST_CHECKER::gather_bufs_data(Yosys::RTLIL::Module* orig_mod) +{ + for (auto cell : orig_mod->cells()) + { + string module_name = escaped_id(cell->type.str()); + if (std::find(prims.begin(), prims.end(), module_name) != prims.end()) + { + if (cell->type == RTLIL::escape_id("I_BUF") || + cell->type == RTLIL::escape_id("I_BUF_DS")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + for (SigBit bit : conn.second) + { + if (bit.wire != nullptr) + { + if (cell->input(portName) && (escaped_id(portName.str()) != "EN")) + i_buf_ins.insert(bit); + if (cell->output(portName)) i_buf_outs.insert(bit); + } + } + } + } else if (cell->type == RTLIL::escape_id("O_BUF") || + cell->type == RTLIL::escape_id("O_BUF_DS")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + for (SigBit bit : conn.second) + { + if (bit.wire != nullptr) + { + if(cell->output(portName)) o_buf_outs.insert(bit); + if (cell->input(portName)) o_buf_ins.insert(bit); + } + } + } + } else if (cell->type == RTLIL::escape_id("O_BUFT") || + cell->type == RTLIL::escape_id("O_BUFT_DS")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + for (SigBit bit : conn.second) + { + if (bit.wire != nullptr) + { + if(cell->output(portName)) o_buf_outs.insert(bit); + if (portName == RTLIL::escape_id("I")) o_buf_ins.insert(bit); + } + } + } + } else if (cell->type == RTLIL::escape_id("CLK_BUF")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if(cell->input(portName)) + { + for (SigBit bit : conn.second) + { + if (bit.wire != nullptr) + { + clk_buf_ins.insert(bit); + } + } + } + } + } else if (cell->type == RTLIL::escape_id("I_DELAY")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if (portName == RTLIL::escape_id("I")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) i_dly_ins.insert(bit); + } + if (portName == RTLIL::escape_id("O")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) i_dly_outs.insert(bit); + } + } + } else if (cell->type == RTLIL::escape_id("O_DELAY")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if (portName == RTLIL::escape_id("I")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) o_dly_ins.insert(bit); + } + if (portName == RTLIL::escape_id("O")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) o_dly_outs.insert(bit); + } + } + } else if (cell->type == RTLIL::escape_id("I_SERDES")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if (portName == RTLIL::escape_id("D")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) i_serdes_ins.insert(bit); + } + if (portName == RTLIL::escape_id("Q")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) i_serdes_outs.insert(bit); + } + } + } else if (cell->type == RTLIL::escape_id("O_SERDES")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if (portName == RTLIL::escape_id("D")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) o_serdes_ins.insert(bit); + } + if (portName == RTLIL::escape_id("Q")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) o_serdes_outs.insert(bit); + } + } + } else if (cell->type == RTLIL::escape_id("I_DDR")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if (portName == RTLIL::escape_id("D")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) i_ddr_ins.insert(bit); + } + if (portName == RTLIL::escape_id("Q")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) i_ddr_outs.insert(bit); + } + } + } else if (cell->type == RTLIL::escape_id("O_DDR")) + { + for (auto conn : cell->connections()) + { + IdString portName = conn.first; + if (portName == RTLIL::escape_id("D")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) o_ddr_ins.insert(bit); + } + if (portName == RTLIL::escape_id("Q")) + { + for (SigBit bit : conn.second) + if (bit.wire != nullptr) o_ddr_outs.insert(bit); + } + } + } + } + } +} diff --git a/design_edit/src/netlist_checker.h b/design_edit/src/netlist_checker.h new file mode 100644 index 000000000..80984d611 --- /dev/null +++ b/design_edit/src/netlist_checker.h @@ -0,0 +1,67 @@ +#ifndef NETLIST_CHECKER_H +#define NETLIST_CHECKER_H + +#include "backends/rtlil/rtlil_backend.h" +#include "kernel/celltypes.h" +#include "kernel/ff.h" +#include "kernel/ffinit.h" +#include "kernel/log.h" +#include "kernel/mem.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +using namespace RTLIL; + +struct NETLIST_CHECKER { + std::string escaped_id(const std::string &input); + void set_difference(const pool& set1, const pool& set2); + void write_checker_file(); + void gather_prims_data(Module* mod); + void gather_fabric_data(Module* mod); + void check_idly_data_ins(); + void check_idly_data_outs(); + void check_odly_data_outs(); + void check_odly_data_ins(); + void check_dly_cntrls(); + void check_ddr_cntrls(); + void check_iddr_data_outs(); + void check_iddr_data_ins(); + void check_oddr_data_ins(); + void check_oddr_data_outs(); + void check_iserdes_data_ins(); + void check_iserdes_data_outs(); + void check_oserdes_data_ins(); + void check_oserdes_data_outs(); + void check_serdes_cntrls(); + void check_buf_cntrls(); + void check_fclkbuf_conns(); + void check_clkbuf_conns(); + void check_buf_conns(); + void gather_bufs_data(Yosys::RTLIL::Module* orig_mod); + bool check_netlist(); + + int feedback_clocks = 0; + pool design_inputs, design_outputs; + std::unordered_set prims; + pool i_buf_ins, i_buf_outs, o_buf_outs, i_buf_ctrls, o_buf_ctrls; + pool clk_buf_ins, dly_in_ctrls, dly_out_ctrls; + pool fclk_buf_ins, fab_outs, fab_ins, o_buf_ins; + pool i_dly_ins, i_dly_outs, o_dly_ins, o_dly_outs; + pool i_serdes_ins, i_serdes_outs, o_serdes_ins, o_serdes_outs; + pool i_ddr_ins, i_ddr_outs, o_ddr_ins, o_ddr_outs; + pool i_serdes_in_ctrls, i_serdes_out_ctrls; + pool o_serdes_in_ctrls, o_serdes_out_ctrls, ddr_ctrls; + std::unordered_set i_serdes_controls = + {"RST", "BITSLIP_ADJ", "EN", "DATA_VALID", "DPA_LOCK", "DPA_ERROR", "PLL_LOCK"}; + std::unordered_set o_serdes_controls = + {"RST", "DATA_VALID", "OE_IN", "OE_OUT", "CHANNEL_BOND_SYNC_IN", "CHANNEL_BOND_SYNC_OUT", "PLL_LOCK"}; + std::unordered_set dly_controls = + {"DLY_LOAD", "DLY_ADJ", "DLY_INCDEC", "DLY_TAP_VALUE"}; + pool diff; + std::stringstream netlist_checker; + bool netlist_error = false; +}; + +#endif \ No newline at end of file diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index 2b756295a..0a8d1fd7f 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -20,6 +20,7 @@ #include "primitives_extractor.h" #include "rs_design_edit.h" #include "rs_primitive.h" +#include "netlist_checker.h" #include #include @@ -101,10 +102,6 @@ struct DesignEditRapidSilicon : public ScriptPass { pool unused_prim_outs; pool used_bits; pool orig_ins, orig_outs, fab_outs, fab_ins; - pool i_buf_ins, i_buf_outs, o_buf_outs; - pool clk_buf_ins; - pool fclk_buf_ins; - pool diff; RTLIL::Design *_design; RTLIL::Design *new_design = new RTLIL::Design; @@ -162,19 +159,6 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - void write_checker_file() - { - std::ofstream netlist_checker_file("netlist_checker.log"); - if (netlist_checker_file.is_open()) - { - netlist_checker_file << netlist_checker.str(); - netlist_checker_file.close(); - } - - netlist_checker.str(""); - netlist_checker.clear(); - } - std::string id(RTLIL::IdString internal_id) { const char *str = internal_id.c_str(); @@ -1286,18 +1270,6 @@ struct DesignEditRapidSilicon : public ScriptPass { float totalTime = duration.count() * 1e-9; std::cout << "[" << totalTime << " sec.]\n"; } - - void set_difference(const pool& set1, - const pool& set2) - { - for (auto &bit : set1) - { - if (!set2.count(bit)) - { - diff.insert(bit); - } - } - } void get_fabric_ios(Module* mod) { @@ -1321,110 +1293,6 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - void check_fclkbuf_conns() - { - netlist_checker << "\nChecking FCLK_BUF connections\n"; - netlist_checker << "================================================================\n"; - set_difference(fclk_buf_ins, fab_outs); - if(!diff.empty()) - { - netlist_checker << "The following fclk_buf_outputs are not fabric outputs\n"; - for (const auto &elem : diff) - { - netlist_checker << "FCLK_BUF_IN : " << log_signal(elem) << "\n"; - } - netlist_error = true; - diff.clear(); - } - netlist_checker << "================================================================\n"; - } - - void check_clkbuf_conns() - { - set_difference(clk_buf_ins, i_buf_outs); - if(!diff.empty()) - { - netlist_checker << "================================================================\n"; - netlist_checker << "The following CLK_BUF inputs are not connected to I_BUF outputs\n"; - for (const auto &elem : diff) - { - netlist_checker << "CLK_BUF Input : " << log_signal(elem) << "\n"; - } - netlist_checker << "================================================================\n"; - netlist_error = true; - } - - diff.clear(); - } - - void check_buf_conns() - { - netlist_checker << "Checking Buffer connections\n"; - if (orig_ins == i_buf_ins && orig_outs == o_buf_outs) - { - netlist_checker << "All IO connections are correct.\n"; - return; - } - - set_difference(orig_ins, i_buf_ins); - if(!diff.empty()) - { - netlist_checker << "================================================================\n"; - netlist_checker << "The following inputs are not connected to I_BUFs\n"; - for (const auto &elem : diff) - { - netlist_checker << "Input : " << log_signal(elem) << "\n"; - } - netlist_checker << "================================================================\n"; - netlist_error = true; - } - - diff.clear(); - set_difference(i_buf_ins, orig_ins); - if(!diff.empty()) - { - netlist_checker << "================================================================\n"; - netlist_checker << "The following I_BUF inputs are not connected to the design inputs\n"; - for (const auto &elem : diff) - { - netlist_checker << "I_BUF Input : " << log_signal(elem) << "\n"; - } - netlist_checker << "================================================================\n"; - netlist_error = true; - } - - diff.clear(); - set_difference(orig_outs, o_buf_outs); - if(!diff.empty()) - { - netlist_checker << "================================================================\n"; - netlist_checker << "The following outputs are not connected to O_BUFs\n"; - for (const auto &elem : diff) - { - netlist_checker << "Output : " << log_signal(elem) << "\n"; - } - netlist_checker << "================================================================\n"; - netlist_error = true; - } - - diff.clear(); - set_difference(o_buf_outs, orig_outs); - if(!diff.empty()) - { - netlist_checker << "================================================================\n"; - netlist_checker << "The following O_BUF outputs are not connected to the design outputs\n"; - for (const auto &elem : diff) - { - netlist_checker << "O_BUF Output : " << log_signal(elem) << "\n"; - } - netlist_checker << "================================================================\n"; - netlist_error = true; - } - - diff.clear(); - return; - } - static bool sigName(const RTLIL::SigSpec &sig, std::string &name) { if (!sig.is_chunk()) @@ -1636,6 +1504,8 @@ struct DesignEditRapidSilicon : public ScriptPass { auto start = high_resolution_clock::now(); auto start_time = start; + NETLIST_CHECKER checker; + checker.prims = primitives; log("Extracting primitives\n"); // Extract the primitive information (before anything is modified) PRIMITIVES_EXTRACTOR* extractor = new PRIMITIVES_EXTRACTOR(tech); @@ -1677,6 +1547,8 @@ struct DesignEditRapidSilicon : public ScriptPass { if (is_output) orig_outs.insert(bit); } } + checker.design_inputs = orig_ins; + checker.design_outputs = orig_outs; start = high_resolution_clock::now(); log("Gathering Wires Data\n"); @@ -1691,87 +1563,6 @@ struct DesignEditRapidSilicon : public ScriptPass { bool is_intf_prim = (soc_intf_prims.count(module_name) > 0) ? true : false; remove_prims.push_back(cell); - if (cell->type == RTLIL::escape_id("I_BUF") || - cell->type == RTLIL::escape_id("I_BUF_DS")) - { - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - for (SigBit bit : conn.second) - { - if (bit.wire != nullptr) - { - if (cell->input(portName) && - (remove_backslashes(portName.str()) != "EN")) i_buf_ins.insert(bit); - if (cell->output(portName)) i_buf_outs.insert(bit); - } - } - } - } else if (cell->type == RTLIL::escape_id("O_BUF") || - cell->type == RTLIL::escape_id("O_BUF_DS")) - { - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - for (SigBit bit : conn.second) - { - if (bit.wire != nullptr) - { - if(cell->output(portName)) o_buf_outs.insert(bit); - } - } - } - } else if (cell->type == RTLIL::escape_id("O_BUFT") || - cell->type == RTLIL::escape_id("O_BUFT_DS")) - { - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - for (SigBit bit : conn.second) - { - if (bit.wire != nullptr) - { - if(cell->output(portName)) o_buf_outs.insert(bit); - } - } - } - } else if (cell->type == RTLIL::escape_id("CLK_BUF")) - { - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - if(cell->input(portName)) - { - for (SigBit bit : conn.second) - { - if (bit.wire != nullptr) - { - clk_buf_ins.insert(bit); - } - } - } - } - } else if (cell->type == RTLIL::escape_id("FCLK_BUF")) - { - feedback_clocks++; - if(feedback_clocks > 8) - log_error("Feedback clock count exceeded, upto 8 feedback clocks are allowed.\n"); - for (auto conn : cell->connections()) - { - IdString portName = conn.first; - if(cell->input(portName)) - { - for (SigBit bit : conn.second) - { - if (bit.wire != nullptr) - { - fclk_buf_ins.insert(bit); - } - } - } - } - } - for (auto conn : cell->connections()) { IdString portName = conn.first; RTLIL::SigSpec actual = conn.second; @@ -1855,8 +1646,15 @@ struct DesignEditRapidSilicon : public ScriptPass { } } - check_buf_conns(); - check_clkbuf_conns(); + checker.gather_bufs_data(original_mod); + checker.check_buf_conns(); + checker.check_clkbuf_conns(); + checker.check_idly_data_ins(); + checker.check_odly_data_outs(); + checker.check_iserdes_data_ins(); + checker.check_oserdes_data_outs(); + checker.check_iddr_data_ins(); + checker.check_oddr_data_outs(); end = high_resolution_clock::now(); elapsed_time (start, end); @@ -1884,15 +1682,18 @@ struct DesignEditRapidSilicon : public ScriptPass { std::string wire_name = wire->name.str(); if (new_ins.find(wire_name) != new_ins.end()) { wire->port_input = true; + checker.fab_ins.insert(wire); continue; } if (new_outs.find(wire_name) != new_outs.end()) { wire->port_output = true; + checker.fab_outs.insert(wire); continue; } if (common_clks_resets.find(wire_name) != common_clks_resets.end()) { wire->port_input = true; + checker.fab_ins.insert(wire); continue; } if (interface_wires.find(wire_name) != interface_wires.end()) { @@ -1986,6 +1787,18 @@ struct DesignEditRapidSilicon : public ScriptPass { handle_dangling_outs(original_mod); end = high_resolution_clock::now(); elapsed_time (start, end); + checker.gather_prims_data(original_mod); + checker.check_buf_cntrls(); + checker.check_fclkbuf_conns(); + checker.check_odly_data_ins(); + checker.check_idly_data_outs(); + checker.check_dly_cntrls(); + checker.check_ddr_cntrls(); + checker.check_iddr_data_outs(); + checker.check_oddr_data_ins(); + checker.check_iserdes_data_outs(); + checker.check_oserdes_data_ins(); + checker.check_serdes_cntrls(); start = high_resolution_clock::now(); log("Deleting primitive cells and extra wires\n"); delete_cells(original_mod, remove_prims); @@ -2012,7 +1825,6 @@ struct DesignEditRapidSilicon : public ScriptPass { fixup_mod_ports(original_mod); get_fabric_ios(original_mod); - check_fclkbuf_conns(); remove_io_fab_prim(original_mod); @@ -2266,10 +2078,11 @@ struct DesignEditRapidSilicon : public ScriptPass { } } } + run_script(new_design); + checker.write_checker_file(); if (supported_tech) { - write_checker_file(); start = high_resolution_clock::now(); log("Dumping config.json\n"); // Dump entire wrap design using "config.json" naming (by default) @@ -2293,10 +2106,10 @@ struct DesignEditRapidSilicon : public ScriptPass { auto duration = duration_cast(end_time - start_time); float totalTime = duration.count() * 1e-9; std::cout << "Time elapsed in design editing : " << " [" << totalTime << " sec.]\n"; - if(netlist_error) - log_error("Netlist is illegal, check netlist_checker.log for more details.\n"); } delete extractor; + if (checker.netlist_error) + log_error("Netlist is illegal, check netlist_checker.log for more details.\n"); } void script() override { diff --git a/design_edit/src/rs_design_edit.h b/design_edit/src/rs_design_edit.h index 56e42e2bf..aafe6e132 100644 --- a/design_edit/src/rs_design_edit.h +++ b/design_edit/src/rs_design_edit.h @@ -82,9 +82,6 @@ std::string io_config_json; std::string sdc_file; bool sdc_passed = false; std::string tech; -std::stringstream netlist_checker; -bool netlist_error = false; -int feedback_clocks = 0; std::vector tokenizeString(const std::string &input); void processSdcFile(std::istream &input);