coreboot-TIMELESS-heads Thu Jan 1 00:00:00 UTC 1970 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d40,000cd2ac] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 5cf840 size 318c CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 5d2a40 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 done Enter amd_ht_init AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Forcing HT links to isochronous mode due to enabled IOMMU CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Exit amd_ht_init amd_ht_fixup amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Enabling IOMMU sb700_early_setup() CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 sb700_pmio_por_init() start_other_cores() NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c0009e 0x3c06644c FIDVID on BSP, APIC_id: 00 BSP fid = 0 NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. get_boot_apic_id: using 0 as APIC ID for node 0, core 0 get_boot_apic_id: using 1 as APIC ID for node 0, core 1 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 3 as APIC ID for node 0, core 3 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 5 as APIC ID for node 0, core 5 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 get_boot_apic_id: using 7 as APIC ID for node 0, core 7 get_boot_apic_id: using 8 as APIC ID for node 1, core 0 get_boot_apic_id: using 9 as APIC ID for node 1, core 1 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 11 as APIC ID for node 1, core 3 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 13 as APIC ID for node 1, core 5 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 get_boot_apic_id: using 15 as APIC ID for node 1, core 7 get_boot_apic_id: using 32 as APIC ID for node 2, core 0 get_boot_apic_id: using 33 as APIC ID for node 2, core 1 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 35 as APIC ID for node 2, core 3 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 37 as APIC ID for node 2, core 5 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 get_boot_apic_id: using 39 as APIC ID for node 2, core 7 get_boot_apic_id: using 40 as APIC ID for node 3, core 0 get_boot_apic_id: using 41 as APIC ID for node 3, core 1 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 43 as APIC ID for node 3, core 3 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 45 as APIC ID for node 3, core 5 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 get_boot_apic_id: using 47 as APIC ID for node 3, core 7 Wait for AP stage 1: ap_apicid = 1 readback = 1000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2 readback = 2000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 3 readback = 3000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 4 readback = 4000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 5 readback = 5000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 6 readback = 6000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 7 readback = 7000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 8 readback = 8000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 9 readback = 9000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = a readback = a000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = b readback = b000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = c readback = c000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = d readback = d000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = e readback = e000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = f readback = f000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 20 readback = 20000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 21 readback = 21000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 22 readback = 22000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 23 readback = 23000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 24 readback = 24000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 25 readback = 25000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 26 readback = 26000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 27 readback = 27000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 28 readback = 28000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 29 readback = 29000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2a readback = 2a000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2b readback = 2b000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2c readback = 2c000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2d readback = 2d000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2e readback = 2e000014 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2f readback = 2f000014 common_fid(packed) = 0 common_fid = 0 End FIDVIDMSR 0xc0010071 0x52c0009e 0x3c06644c sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode ...WARM RESET... soft_reset() called! ␀ coreboot-TIMELESS-heads Thu Jan 1 00:00:00 UTC 1970 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d40,000cd2ac] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0004 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 5cf840 size 318c CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 5d2a40 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 done Enter amd_ht_init AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Forcing HT links to isochronous mode due to enabled IOMMU CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Exit amd_ht_init amd_ht_fixup amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Enabling IOMMU sb700_early_setup() CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 sb700_pmio_por_init() start_other_cores() NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c0009e 0x3c025007 End FIDVIDMSR 0xc0010071 0x52c0009e 0x3c025007 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 ...WARM RESET... soft_reset() called! ␀ coreboot-TIMELESS-heads Thu Jan 1 00:00:00 UTC 1970 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d40,000cd2ac] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0004 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 5cf840 size 318c CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 5d2a40 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 done Enter amd_ht_init AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Forcing HT links to isochronous mode due to enabled IOMMU CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Exit amd_ht_init amd_ht_fixup amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475632 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 03000016 F3xDC: 05475634 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 03 sr5650_early_setup() get_cpu_rev EAX=0x600f12. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Enabling IOMMU sb700_early_setup() CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 sb700_pmio_por_init() start_other_cores() NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 init node: 02 cores: 07 pass 1 Start other core - nodeid: 02 cores: 07 get_boot_apic_id: using 34 as APIC ID for node 2, core 2 get_boot_apic_id: using 36 as APIC ID for node 2, core 4 get_boot_apic_id: using 38 as APIC ID for node 2, core 6 init node: 03 cores: 07 pass 1 Start other core - nodeid: 03 cores: 07 get_boot_apic_id: using 42 as APIC ID for node 3, core 2 get_boot_apic_id: using 44 as APIC ID for node 3, core 4 get_boot_apic_id: using 46 as APIC ID for node 3, core 6 started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21started get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22started get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23started get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24started get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25started get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26started get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27started get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29started get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astarted get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstarted get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstarted get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstarted get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estarted get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstarted Begin FIDVID MSR 0xc0010071 0x52c0009e 0x3c025007 End FIDVIDMSR 0xc0010071 0x52c0009e 0x3c025007 sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 stopped ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped get_boot_apic_id: using 33 as APIC ID for node 2, core 1 * AP 21stopped get_boot_apic_id: using 34 as APIC ID for node 2, core 2 * AP 22stopped get_boot_apic_id: using 35 as APIC ID for node 2, core 3 * AP 23stopped get_boot_apic_id: using 36 as APIC ID for node 2, core 4 * AP 24stopped get_boot_apic_id: using 37 as APIC ID for node 2, core 5 * AP 25stopped get_boot_apic_id: using 38 as APIC ID for node 2, core 6 * AP 26stopped get_boot_apic_id: using 39 as APIC ID for node 2, core 7 * AP 27stopped get_boot_apic_id: using 41 as APIC ID for node 3, core 1 * AP 29stopped get_boot_apic_id: using 42 as APIC ID for node 3, core 2 * AP 2astopped get_boot_apic_id: using 43 as APIC ID for node 3, core 3 * AP 2bstopped get_boot_apic_id: using 44 as APIC ID for node 3, core 4 * AP 2cstopped get_boot_apic_id: using 45 as APIC ID for node 3, core 5 * AP 2dstopped get_boot_apic_id: using 46 as APIC ID for node 3, core 6 * AP 2estopped get_boot_apic_id: using 47 as APIC ID for node 3, core 7 * AP 2fstopped fill_mem_ctrl() detected 4 nodes raminit_amdmct() raminit_amdmct begin: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 DIMMPresence: DIMMValid=8 DIMMPresence: DIMMPresent=8 DIMMPresence: RegDIMMPresent=8 DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=8 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=8 DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=8 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=0 DIMMPresence: MAload[0]=0 DIMMPresence: MAdimms[0]=0 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 DIMMPresence: DIMMValid=0 DIMMPresence: DIMMPresent=0 DIMMPresence: RegDIMMPresent=0 DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=0 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=0 DIMMPresence: MAload[0]=0 DIMMPresence: MAdimms[0]=0 DIMMPresence: DATAload[1]=0 DIMMPresence: MAload[1]=0 DIMMPresence: MAdimms[1]=0 DIMMPresence: Status 2000 DIMMPresence: ErrStatus 1 DIMMPresence: ErrCode 2 DIMMPresence: Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_preInitDCT CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 DIMMPresence: DIMMValid=4 DIMMPresence: DIMMPresent=4 DIMMPresence: RegDIMMPresent=4 DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=4 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=4 DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=4 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=0 DIMMPresence: MAload[1]=0 DIMMPresence: MAdimms[1]=0 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_preInitDCT CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 DIMMPresence: DIMMValid=0 DIMMPresence: DIMMPresent=0 DIMMPresence: RegDIMMPresent=0 DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=0 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=0 DIMMPresence: MAload[0]=0 DIMMPresence: MAdimms[0]=0 DIMMPresence: DATAload[1]=0 DIMMPresence: MAload[1]=0 DIMMPresence: MAdimms[1]=0 DIMMPresence: Status 2000 DIMMPresence: ErrStatus 1 DIMMPresence: ErrCode 2 DIMMPresence: Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 mctAutoInitMCT_D: DIMMSetVoltage CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 5 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 2 AutoCycTiming: Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 SPDCalcWidth: Status 2000 SPDCalcWidth: ErrStatus 1 SPDCalcWidth: ErrCode 2 SPDCalcWidth: Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 02 enable_spd_node2() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 5 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 00112222 mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramControlReg_Init_D: Start mct_DramControlReg_Init_D: F2xA8: 00000c00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00 mct_DramControlReg_Init_D: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 03 enable_spd_node3() mctAutoInitMCT_D: mct_initDCT CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 SPDCalcWidth: Status 2000 SPDCalcWidth: ErrStatus 1 SPDCalcWidth: ErrCode 2 SPDCalcWidth: Done mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 3ffffff BottomIO: c00000 Node: 00 base: 03 limit: 43fffff Node: 01 base: 00 limit: 00 Node: 02 base: 4400000 limit: 83fffff BottomIO: c00000 Node: 02 base: 4400003 limit: 83fffff Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 Copy dram map from Node 0 to Node 01 Copy dram map from Node 0 to Node 02 Copy dram map from Node 0 to Node 03 mctAutoInitMCT_D: mctHookAfterCPU mctAutoInitMCT_D: DQSTiming_D phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: training node 0 DCT 1 phyAssistedMemFnceTraining: done training node 0 DCT 1 phyAssistedMemFnceTraining: training node 2 DCT 0 phyAssistedMemFnceTraining: done training node 2 DCT 0 phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done activate_spd_rom() for node 00 enable_spd_node0() AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 DIMM 1 RttWr: 0 Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 initial seed: 0041 Lane 01 initial seed: 0041 Lane 02 initial seed: 0041 Lane 03 initial seed: 0041 Lane 04 initial seed: 0041 Lane 05 initial seed: 0041 Lane 06 initial seed: 0041 Lane 07 initial seed: 0041 Lane 08 initial seed: 0041 Lane 00 nibble 0 raw readback: 0042 Lane 00 nibble 0 adjusted value (pre nibble): 0042 Lane 00 nibble 0 adjusted value (post nibble): 0042 Lane 01 nibble 0 raw readback: 003e Lane 01 nibble 0 adjusted value (pre nibble): 003e Lane 01 nibble 0 adjusted value (post nibble): 003e Lane 02 nibble 0 raw readback: 003b Lane 02 nibble 0 adjusted value (pre nibble): 003b Lane 02 nibble 0 adjusted value (post nibble): 003b Lane 03 nibble 0 raw readback: 0038 Lane 03 nibble 0 adjusted value (pre nibble): 0038 Lane 03 nibble 0 adjusted value (post nibble): 0038 Lane 04 nibble 0 raw readback: 0030 Lane 04 nibble 0 adjusted value (pre nibble): 0030 Lane 04 nibble 0 adjusted value (post nibble): 0030 Lane 05 nibble 0 raw readback: 0033 Lane 05 nibble 0 adjusted value (pre nibble): 0033 Lane 05 nibble 0 adjusted value (post nibble): 0033 Lane 06 nibble 0 raw readback: 0035 Lane 06 nibble 0 adjusted value (pre nibble): 0035 Lane 06 nibble 0 adjusted value (post nibble): 0035 Lane 07 nibble 0 raw readback: 0039 Lane 07 nibble 0 adjusted value (pre nibble): 0039 Lane 07 nibble 0 adjusted value (post nibble): 0039 Lane 08 nibble 0 raw readback: 0031 Lane 08 nibble 0 adjusted value (pre nibble): 0031 Lane 08 nibble 0 adjusted value (post nibble): 0031 original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 DIMM 1 RttWr: 0 activate_spd_rom() for node 01 enable_spd_node1() activate_spd_rom() for node 02 enable_spd_node2() AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 DIMM 1 RttWr: 0 Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 initial seed: 0041 Lane 01 initial seed: 0041 Lane 02 initial seed: 0041 Lane 03 initial seed: 0041 Lane 04 initial seed: 0041 Lane 05 initial seed: 0041 Lane 06 initial seed: 0041 Lane 07 initial seed: 0041 Lane 08 initial seed: 0041 Lane 00 nibble 0 raw readback: 0044 Lane 00 nibble 0 adjusted value (pre nibble): 0044 Lane 00 nibble 0 adjusted value (post nibble): 0044 Lane 01 nibble 0 raw readback: 003d Lane 01 nibble 0 adjusted value (pre nibble): 003d Lane 01 nibble 0 adjusted value (post nibble): 003d Lane 02 nibble 0 raw readback: 003c Lane 02 nibble 0 adjusted value (pre nibble): 003c Lane 02 nibble 0 adjusted value (post nibble): 003c Lane 03 nibble 0 raw readback: 0039 Lane 03 nibble 0 adjusted value (pre nibble): 0039 Lane 03 nibble 0 adjusted value (post nibble): 0039 Lane 04 nibble 0 raw readback: 0031 Lane 04 nibble 0 adjusted value (pre nibble): 0031 Lane 04 nibble 0 adjusted value (post nibble): 0031 Lane 05 nibble 0 raw readback: 0035 Lane 05 nibble 0 adjusted value (pre nibble): 0035 Lane 05 nibble 0 adjusted value (post nibble): 0035 Lane 06 nibble 0 raw readback: 0038 Lane 06 nibble 0 adjusted value (pre nibble): 0038 Lane 06 nibble 0 adjusted value (post nibble): 0038 Lane 07 nibble 0 raw readback: 003a Lane 07 nibble 0 adjusted value (pre nibble): 003a Lane 07 nibble 0 adjusted value (post nibble): 003a Lane 08 nibble 0 raw readback: 0033 Lane 08 nibble 0 adjusted value (pre nibble): 0033 Lane 08 nibble 0 adjusted value (post nibble): 0033 original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 DIMM 1 RttWr: 0 activate_spd_rom() for node 03 enable_spd_node3() fam15_receiver_enable_training_seed: using seed: 004d fam15_receiver_enable_training_seed: using seed: 004d TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done fam15_receiver_enable_training_seed: using seed: 0054 fam15_receiver_enable_training_seed: using seed: 0054 TrainRcvrEn: Status 2005 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00000000 10112222 mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: training node 0 DCT 1 phyAssistedMemFnceTraining: done training node 0 DCT 1 phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00) fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 DIMM 1 RttWr: 0 Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 scaled delay: 0047 Lane 00 new seed: 0047 Lane 01 scaled delay: 0047 Lane 01 new seed: 0047 Lane 02 scaled delay: 0047 Lane 02 new seed: 0047 Lane 03 scaled delay: 0047 Lane 03 new seed: 0047 Lane 04 scaled delay: 0047 Lane 04 new seed: 0047 Lane 05 scaled delay: 0047 Lane 05 new seed: 0047 Lane 06 scaled delay: 0047 Lane 06 new seed: 0047 Lane 07 scaled delay: 0047 Lane 07 new seed: 0047 Lane 08 scaled delay: 0047 Lane 08 new seed: 0047 Lane 00 nibble 0 raw readback: 0049 Lane 00 nibble 0 adjusted value (pre nibble): 0049 Lane 00 nibble 0 adjusted value (post nibble): 0049 Lane 01 nibble 0 raw readback: 0044 Lane 01 nibble 0 adjusted value (pre nibble): 0044 Lane 01 nibble 0 adjusted value (post nibble): 0044 Lane 02 nibble 0 raw readback: 0041 Lane 02 nibble 0 adjusted value (pre nibble): 0041 Lane 02 nibble 0 adjusted value (post nibble): 0041 Lane 03 nibble 0 raw readback: 003e Lane 03 nibble 0 adjusted value (pre nibble): 003e Lane 03 nibble 0 adjusted value (post nibble): 003e Lane 04 nibble 0 raw readback: 0033 Lane 04 nibble 0 adjusted value (pre nibble): 0033 Lane 04 nibble 0 adjusted value (post nibble): 0033 Lane 05 nibble 0 raw readback: 0037 Lane 05 nibble 0 adjusted value (pre nibble): 0037 Lane 05 nibble 0 adjusted value (post nibble): 0037 Lane 06 nibble 0 raw readback: 003a Lane 06 nibble 0 adjusted value (pre nibble): 003a Lane 06 nibble 0 adjusted value (post nibble): 003a Lane 07 nibble 0 raw readback: 003d Lane 07 nibble 0 adjusted value (pre nibble): 003d Lane 07 nibble 0 adjusted value (post nibble): 003d Lane 08 nibble 0 raw readback: 0035 Lane 08 nibble 0 adjusted value (pre nibble): 0035 Lane 08 nibble 0 adjusted value (post nibble): 0035 original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480080 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680080 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000a ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00393c39 20112222 mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: training node 0 DCT 1 phyAssistedMemFnceTraining: done training node 0 DCT 1 phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00) fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088 DIMM 1 RttWr: 0 Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 scaled delay: 0056 Lane 00 new seed: 0056 Lane 01 scaled delay: 004f Lane 01 new seed: 004f Lane 02 scaled delay: 004b Lane 02 new seed: 004b Lane 03 scaled delay: 0047 Lane 03 new seed: 0047 Lane 04 scaled delay: 0039 Lane 04 new seed: 0039 Lane 05 scaled delay: 003e Lane 05 new seed: 003e Lane 06 scaled delay: 0042 Lane 06 new seed: 0042 Lane 07 scaled delay: 0046 Lane 07 new seed: 0046 Lane 08 scaled delay: 003b Lane 08 new seed: 003b Lane 00 nibble 0 raw readback: 0057 Lane 00 nibble 0 adjusted value (pre nibble): 0057 Lane 00 nibble 0 adjusted value (post nibble): 0057 Lane 01 nibble 0 raw readback: 0050 Lane 01 nibble 0 adjusted value (pre nibble): 0050 Lane 01 nibble 0 adjusted value (post nibble): 0050 Lane 02 nibble 0 raw readback: 004d Lane 02 nibble 0 adjusted value (pre nibble): 004d Lane 02 nibble 0 adjusted value (post nibble): 004d Lane 03 nibble 0 raw readback: 0049 Lane 03 nibble 0 adjusted value (pre nibble): 0049 Lane 03 nibble 0 adjusted value (post nibble): 0049 Lane 04 nibble 0 raw readback: 003c Lane 04 nibble 0 adjusted value (pre nibble): 003c Lane 04 nibble 0 adjusted value (post nibble): 003c Lane 05 nibble 0 raw readback: 0040 Lane 05 nibble 0 adjusted value (pre nibble): 0040 Lane 05 nibble 0 adjusted value (post nibble): 0040 Lane 06 nibble 0 raw readback: 0044 Lane 06 nibble 0 adjusted value (pre nibble): 0044 Lane 06 nibble 0 adjusted value (post nibble): 0044 Lane 07 nibble 0 raw readback: 0047 Lane 07 nibble 0 adjusted value (pre nibble): 0047 Lane 07 nibble 0 adjusted value (post nibble): 0047 Lane 08 nibble 0 raw readback: 003e Lane 08 nibble 0 adjusted value (pre nibble): 003e Lane 08 nibble 0 adjusted value (post nibble): 003e original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480088 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680088 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000e ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00373a37 30112222 mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: training node 0 DCT 1 phyAssistedMemFnceTraining: done training node 0 DCT 1 phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00) fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490 DIMM 1 RttWr: 2 Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 scaled delay: 0064 Lane 00 new seed: 0064 Lane 01 scaled delay: 005c Lane 01 new seed: 005c Lane 02 scaled delay: 0058 Lane 02 new seed: 0058 Lane 03 scaled delay: 0053 Lane 03 new seed: 0053 Lane 04 scaled delay: 0043 Lane 04 new seed: 0043 Lane 05 scaled delay: 0048 Lane 05 new seed: 0048 Lane 06 scaled delay: 004d Lane 06 new seed: 004d Lane 07 scaled delay: 0050 Lane 07 new seed: 0050 Lane 08 scaled delay: 0045 Lane 08 new seed: 0045 Lane 00 nibble 0 raw readback: 0026 Lane 00 nibble 0 adjusted value (pre nibble): 0066 Lane 00 nibble 0 adjusted value (post nibble): 0066 Lane 01 nibble 0 raw readback: 005f Lane 01 nibble 0 adjusted value (pre nibble): 005f Lane 01 nibble 0 adjusted value (post nibble): 005f Lane 02 nibble 0 raw readback: 005a Lane 02 nibble 0 adjusted value (pre nibble): 005a Lane 02 nibble 0 adjusted value (post nibble): 005a Lane 03 nibble 0 raw readback: 0055 Lane 03 nibble 0 adjusted value (pre nibble): 0055 Lane 03 nibble 0 adjusted value (post nibble): 0055 Lane 04 nibble 0 raw readback: 0044 Lane 04 nibble 0 adjusted value (pre nibble): 0044 Lane 04 nibble 0 adjusted value (post nibble): 0044 Lane 05 nibble 0 raw readback: 004a Lane 05 nibble 0 adjusted value (pre nibble): 004a Lane 05 nibble 0 adjusted value (post nibble): 004a Lane 06 nibble 0 raw readback: 004e Lane 06 nibble 0 adjusted value (pre nibble): 004e Lane 06 nibble 0 adjusted value (post nibble): 004e Lane 07 nibble 0 raw readback: 0052 Lane 07 nibble 0 adjusted value (pre nibble): 0052 Lane 07 nibble 0 adjusted value (post nibble): 0052 Lane 08 nibble 0 raw readback: 0045 Lane 08 nibble 0 adjusted value (pre nibble): 0045 Lane 08 nibble 0 adjusted value (post nibble): 0045 original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490 DIMM 1 RttWr: 2 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0012 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 1 timing/termination pattern 00363936 30112222 mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: training node 0 DCT 1 phyAssistedMemFnceTraining: done training node 0 DCT 1 phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00) fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 00 fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 0 mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00 SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 1 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 3 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 3 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 3 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098 DIMM 1 RttWr: 0 Programmed DCT 1 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 scaled delay: 0073 Lane 00 new seed: 0073 Lane 01 scaled delay: 006b Lane 01 new seed: 006b Lane 02 scaled delay: 0065 Lane 02 new seed: 0065 Lane 03 scaled delay: 005f Lane 03 new seed: 005f Lane 04 scaled delay: 004b Lane 04 new seed: 004b Lane 05 scaled delay: 0052 Lane 05 new seed: 0052 Lane 06 scaled delay: 0057 Lane 06 new seed: 0057 Lane 07 scaled delay: 005b Lane 07 new seed: 005b Lane 08 scaled delay: 004c Lane 08 new seed: 004c Lane 00 nibble 0 raw readback: 0034 Lane 00 nibble 0 adjusted value (pre nibble): 0074 Lane 00 nibble 0 adjusted value (post nibble): 0074 Lane 01 nibble 0 raw readback: 002a Lane 01 nibble 0 adjusted value (pre nibble): 006a Lane 01 nibble 0 adjusted value (post nibble): 006a Lane 02 nibble 0 raw readback: 0025 Lane 02 nibble 0 adjusted value (pre nibble): 0065 Lane 02 nibble 0 adjusted value (post nibble): 0065 Lane 03 nibble 0 raw readback: 005f Lane 03 nibble 0 adjusted value (pre nibble): 005f Lane 03 nibble 0 adjusted value (post nibble): 005f Lane 04 nibble 0 raw readback: 004b Lane 04 nibble 0 adjusted value (pre nibble): 004b Lane 04 nibble 0 adjusted value (post nibble): 004b Lane 05 nibble 0 raw readback: 0052 Lane 05 nibble 0 adjusted value (pre nibble): 0052 Lane 05 nibble 0 adjusted value (post nibble): 0052 Lane 06 nibble 0 raw readback: 0058 Lane 06 nibble 0 adjusted value (pre nibble): 0058 Lane 06 nibble 0 adjusted value (post nibble): 0058 Lane 07 nibble 0 raw readback: 005d Lane 07 nibble 0 adjusted value (pre nibble): 005d Lane 07 nibble 0 adjusted value (post nibble): 005d Lane 08 nibble 0 raw readback: 004e Lane 08 nibble 0 adjusted value (pre nibble): 004e Lane 08 nibble 0 adjusted value (post nibble): 004e original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 3 Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480098 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680098 DIMM 1 RttWr: 0 activate_spd_rom() for node 01 enable_spd_node1() activate_spd_rom() for node 02 enable_spd_node2() SetTargetFreq: Start SetTargetFreq: Node 2: New frequency code: 0006 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 10112222 mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: training node 2 DCT 0 phyAssistedMemFnceTraining: done training node 2 DCT 0 phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00) fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 DIMM 1 RttWr: 0 Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 scaled delay: 0047 Lane 00 new seed: 0047 Lane 01 scaled delay: 0047 Lane 01 new seed: 0047 Lane 02 scaled delay: 0047 Lane 02 new seed: 0047 Lane 03 scaled delay: 0047 Lane 03 new seed: 0047 Lane 04 scaled delay: 0047 Lane 04 new seed: 0047 Lane 05 scaled delay: 0047 Lane 05 new seed: 0047 Lane 06 scaled delay: 0047 Lane 06 new seed: 0047 Lane 07 scaled delay: 0047 Lane 07 new seed: 0047 Lane 08 scaled delay: 0047 Lane 08 new seed: 0047 Lane 00 nibble 0 raw readback: 004a Lane 00 nibble 0 adjusted value (pre nibble): 004a Lane 00 nibble 0 adjusted value (post nibble): 004a Lane 01 nibble 0 raw readback: 0043 Lane 01 nibble 0 adjusted value (pre nibble): 0043 Lane 01 nibble 0 adjusted value (post nibble): 0043 Lane 02 nibble 0 raw readback: 0041 Lane 02 nibble 0 adjusted value (pre nibble): 0041 Lane 02 nibble 0 adjusted value (post nibble): 0041 Lane 03 nibble 0 raw readback: 003e Lane 03 nibble 0 adjusted value (pre nibble): 003e Lane 03 nibble 0 adjusted value (post nibble): 003e Lane 04 nibble 0 raw readback: 0036 Lane 04 nibble 0 adjusted value (pre nibble): 0036 Lane 04 nibble 0 adjusted value (post nibble): 0036 Lane 05 nibble 0 raw readback: 003a Lane 05 nibble 0 adjusted value (pre nibble): 003a Lane 05 nibble 0 adjusted value (post nibble): 003a Lane 06 nibble 0 raw readback: 003c Lane 06 nibble 0 adjusted value (pre nibble): 003c Lane 06 nibble 0 adjusted value (post nibble): 003c Lane 07 nibble 0 raw readback: 003e Lane 07 nibble 0 adjusted value (pre nibble): 003e Lane 07 nibble 0 adjusted value (post nibble): 003e Lane 08 nibble 0 raw readback: 0036 Lane 08 nibble 0 adjusted value (pre nibble): 0036 Lane 08 nibble 0 adjusted value (post nibble): 0036 original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480080 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640042 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680080 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 2: New frequency code: 000a ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00393c39 20112222 mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: training node 2 DCT 0 phyAssistedMemFnceTraining: done training node 2 DCT 0 phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00) fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088 DIMM 1 RttWr: 0 Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 scaled delay: 0057 Lane 00 new seed: 0057 Lane 01 scaled delay: 004e Lane 01 new seed: 004e Lane 02 scaled delay: 004b Lane 02 new seed: 004b Lane 03 scaled delay: 0047 Lane 03 new seed: 0047 Lane 04 scaled delay: 003d Lane 04 new seed: 003d Lane 05 scaled delay: 0042 Lane 05 new seed: 0042 Lane 06 scaled delay: 0045 Lane 06 new seed: 0045 Lane 07 scaled delay: 0047 Lane 07 new seed: 0047 Lane 08 scaled delay: 003d Lane 08 new seed: 003d Lane 00 nibble 0 raw readback: 005a Lane 00 nibble 0 adjusted value (pre nibble): 005a Lane 00 nibble 0 adjusted value (post nibble): 005a Lane 01 nibble 0 raw readback: 0051 Lane 01 nibble 0 adjusted value (pre nibble): 0051 Lane 01 nibble 0 adjusted value (post nibble): 0051 Lane 02 nibble 0 raw readback: 004e Lane 02 nibble 0 adjusted value (pre nibble): 004e Lane 02 nibble 0 adjusted value (post nibble): 004e Lane 03 nibble 0 raw readback: 004a Lane 03 nibble 0 adjusted value (pre nibble): 004a Lane 03 nibble 0 adjusted value (post nibble): 004a Lane 04 nibble 0 raw readback: 003d Lane 04 nibble 0 adjusted value (pre nibble): 003d Lane 04 nibble 0 adjusted value (post nibble): 003d Lane 05 nibble 0 raw readback: 0042 Lane 05 nibble 0 adjusted value (pre nibble): 0042 Lane 05 nibble 0 adjusted value (post nibble): 0042 Lane 06 nibble 0 raw readback: 0046 Lane 06 nibble 0 adjusted value (pre nibble): 0046 Lane 06 nibble 0 adjusted value (post nibble): 0046 Lane 07 nibble 0 raw readback: 004b Lane 07 nibble 0 adjusted value (pre nibble): 004b Lane 07 nibble 0 adjusted value (post nibble): 004b Lane 08 nibble 0 raw readback: 0040 Lane 08 nibble 0 adjusted value (pre nibble): 0040 Lane 08 nibble 0 adjusted value (post nibble): 0040 original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480088 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680088 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 2: New frequency code: 000e ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00373a37 30112222 mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: training node 2 DCT 0 phyAssistedMemFnceTraining: done training node 2 DCT 0 phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00) fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490 DIMM 1 RttWr: 2 Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 scaled delay: 0068 Lane 00 new seed: 0068 Lane 01 scaled delay: 005d Lane 01 new seed: 005d Lane 02 scaled delay: 0059 Lane 02 new seed: 0059 Lane 03 scaled delay: 0054 Lane 03 new seed: 0054 Lane 04 scaled delay: 0044 Lane 04 new seed: 0044 Lane 05 scaled delay: 004a Lane 05 new seed: 004a Lane 06 scaled delay: 004f Lane 06 new seed: 004f Lane 07 scaled delay: 0055 Lane 07 new seed: 0055 Lane 08 scaled delay: 0048 Lane 08 new seed: 0048 Lane 00 nibble 0 raw readback: 0028 Lane 00 nibble 0 adjusted value (pre nibble): 0068 Lane 00 nibble 0 adjusted value (post nibble): 0068 Lane 01 nibble 0 raw readback: 005d Lane 01 nibble 0 adjusted value (pre nibble): 005d Lane 01 nibble 0 adjusted value (post nibble): 005d Lane 02 nibble 0 raw readback: 005a Lane 02 nibble 0 adjusted value (pre nibble): 005a Lane 02 nibble 0 adjusted value (post nibble): 005a Lane 03 nibble 0 raw readback: 0055 Lane 03 nibble 0 adjusted value (pre nibble): 0055 Lane 03 nibble 0 adjusted value (post nibble): 0055 Lane 04 nibble 0 raw readback: 0046 Lane 04 nibble 0 adjusted value (pre nibble): 0046 Lane 04 nibble 0 adjusted value (post nibble): 0046 Lane 05 nibble 0 raw readback: 004c Lane 05 nibble 0 adjusted value (pre nibble): 004c Lane 05 nibble 0 adjusted value (post nibble): 004c Lane 06 nibble 0 raw readback: 0050 Lane 06 nibble 0 adjusted value (pre nibble): 0050 Lane 06 nibble 0 adjusted value (post nibble): 0050 Lane 07 nibble 0 raw readback: 0055 Lane 07 nibble 0 adjusted value (pre nibble): 0055 Lane 07 nibble 0 adjusted value (post nibble): 0055 Lane 08 nibble 0 raw readback: 0048 Lane 08 nibble 0 adjusted value (pre nibble): 0048 Lane 08 nibble 0 adjusted value (post nibble): 0048 original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640006 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490 DIMM 1 RttWr: 2 SetTargetFreq: Start SetTargetFreq: Node 2: New frequency code: 0012 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00363936 30112222 mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: training node 2 DCT 0 phyAssistedMemFnceTraining: done training node 2 DCT 0 phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00) fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 00 fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 0 mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00 SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start Programmed DCT 0 ODT pattern 00000000 00000000 00000000 08020000 mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 3 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 3 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done AgesaHwWlPhase1: training nibble 0 DIMM 1 RttNom: 3 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098 DIMM 1 RttWr: 0 Programmed DCT 0 write levelling ODT pattern 00000002 from DIMM 1 data Lane 00 scaled delay: 0076 Lane 00 new seed: 0076 Lane 01 scaled delay: 0069 Lane 01 new seed: 0069 Lane 02 scaled delay: 0065 Lane 02 new seed: 0065 Lane 03 scaled delay: 005f Lane 03 new seed: 005f Lane 04 scaled delay: 004d Lane 04 new seed: 004d Lane 05 scaled delay: 0054 Lane 05 new seed: 0054 Lane 06 scaled delay: 0059 Lane 06 new seed: 0059 Lane 07 scaled delay: 005f Lane 07 new seed: 005f Lane 08 scaled delay: 004f Lane 08 new seed: 004f Lane 00 nibble 0 raw readback: 0037 Lane 00 nibble 0 adjusted value (pre nibble): 0077 Lane 00 nibble 0 adjusted value (post nibble): 0077 Lane 01 nibble 0 raw readback: 002b Lane 01 nibble 0 adjusted value (pre nibble): 006b Lane 01 nibble 0 adjusted value (post nibble): 006b Lane 02 nibble 0 raw readback: 0026 Lane 02 nibble 0 adjusted value (pre nibble): 0066 Lane 02 nibble 0 adjusted value (post nibble): 0066 Lane 03 nibble 0 raw readback: 0060 Lane 03 nibble 0 adjusted value (pre nibble): 0060 Lane 03 nibble 0 adjusted value (post nibble): 0060 Lane 04 nibble 0 raw readback: 004e Lane 04 nibble 0 adjusted value (pre nibble): 004e Lane 04 nibble 0 adjusted value (post nibble): 004e Lane 05 nibble 0 raw readback: 0055 Lane 05 nibble 0 adjusted value (pre nibble): 0055 Lane 05 nibble 0 adjusted value (post nibble): 0055 Lane 06 nibble 0 raw readback: 005b Lane 06 nibble 0 adjusted value (pre nibble): 005b Lane 06 nibble 0 adjusted value (post nibble): 005b Lane 07 nibble 0 raw readback: 0060 Lane 07 nibble 0 adjusted value (pre nibble): 0060 Lane 07 nibble 0 adjusted value (post nibble): 0060 Lane 08 nibble 0 raw readback: 0052 Lane 08 nibble 0 adjusted value (pre nibble): 0052 Lane 08 nibble 0 adjusted value (post nibble): 0052 original critical gross delay: 0 new critical gross delay: 0 DIMM 1 RttNom: 3 Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480098 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680098 DIMM 1 RttWr: 0 activate_spd_rom() for node 03 enable_spd_node3() fam15_receiver_enable_training_seed: using seed: 004d fam15_receiver_enable_training_seed: using seed: 004d TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done fam15_receiver_enable_training_seed: using seed: 0054 fam15_receiver_enable_training_seed: using seed: 0054 TrainRcvrEn: Status 2005 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSReceiverEnCyc: Status 2205 TrainDQSReceiverEnCyc: TrainErrors 4000 TrainDQSReceiverEnCyc: ErrStatus 4000 TrainDQSReceiverEnCyc: ErrCode 0 TrainDQSReceiverEnCyc: Done TrainDQSReceiverEnCyc: Status 2005 TrainDQSReceiverEnCyc: TrainErrors 4000 TrainDQSReceiverEnCyc: ErrStatus 4000 TrainDQSReceiverEnCyc: ErrCode 0 TrainDQSReceiverEnCyc: Done TrainMaxRdLatency: Status 2205 TrainMaxRdLatency: ErrStatus 4000 TrainMaxRdLatency: ErrCode 0 TrainMaxRdLatency: Done TrainMaxRdLatency: Status 2005 TrainMaxRdLatency: ErrStatus 4000 TrainMaxRdLatency: ErrCode 0 TrainMaxRdLatency: Done mctAutoInitMCT_D: :OtherTiming CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 InterleaveNodes_D: Status 2000 InterleaveNodes_D: ErrStatus 1 InterleaveNodes_D: ErrCode 2 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 2205 InterleaveChannels_D: ErrStatus 4000 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 1 InterleaveChannels_D: ErrCode 2 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 2005 InterleaveChannels_D: ErrStatus 4000 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 1 InterleaveChannels_D: ErrCode 2 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 ECC enabled on node: 00 DCTMemClr_Sync_D: Start DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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. DCTMemClr_Sync_D: Done ECC enabled on node: 02 DCTMemClr_Sync_D: Start DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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. DCTMemClr_Sync_D: Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 ECCInit: Node 00 ECCInit: Status 2205 ECCInit: ErrStatus 4000 ECCInit: ErrCode 0 ECCInit: Done ECCInit: Node 01 ECCInit: Status 2000 ECCInit: ErrStatus 1 ECCInit: ErrCode 2 ECCInit: Done ECCInit: Node 02 ECCInit: Status 2005 ECCInit: ErrStatus 4000 ECCInit: ErrCode 0 ECCInit: Done ECCInit: Node 03 ECCInit: Status 2000 ECCInit: ErrStatus 1 ECCInit: ErrCode 2 ECCInit: Done mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:c00000 CPUMemTyping: Bottom32bIO:c00000 CPUMemTyping: Bottom40bIO:8400000 mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 0 (interleaved: 0) set_up_cc6_storage_fam15: original (node 2) max_range_limit: 83fffffff DRAM limit: 43fffffff set_up_cc6_storage_fam15: new max_range_limit: 83effffff set_up_cc6_storage_fam15: Target node: 2 set_up_cc6_storage_fam15: Done set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 1 (interleaved: 0) set_up_cc6_storage_fam15: original (node 2) max_range_limit: 83fffffff DRAM limit: 7ffffff set_up_cc6_storage_fam15: new max_range_limit: 83effffff set_up_cc6_storage_fam15: Target node: 2 set_up_cc6_storage_fam15: Done set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 2 (interleaved: 0) set_up_cc6_storage_fam15: original (node 2) max_range_limit: 83fffffff DRAM limit: 83fffffff set_up_cc6_storage_fam15: new max_range_limit: 83effffff set_up_cc6_storage_fam15: Target node: 2 set_up_cc6_storage_fam15: Done set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 3 (interleaved: 0) set_up_cc6_storage_fam15: original (node 2) max_range_limit: 83fffffff DRAM limit: 7ffffff set_up_cc6_storage_fam15: new max_range_limit: 83effffff set_up_cc6_storage_fam15: Target node: 2 set_up_cc6_storage_fam15: Done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 mctAutoInitMCT_D Done: Global Status: 12 raminit_amdmct end: CBMEM: IMD: root @ b7fff000 254 entries. IMD: root @ b7ffec00 62 entries. amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 disable_spd() TPM initialization. TPM: Init Found TPM SLB9660 TT 1.2 by Infineon TPM: Open TPM: Startup TPM: command 0x99 returned 0x1e TPM: Error code 0x1e. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 3ff00 size 1572b CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 coreboot-TIMELESS-heads Thu Jan 1 00:00:00 UTC 1970 ramstage starting... Moving GDT to b7ffe9e0...ok Normal boot. BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 I2C: 00:54: enabled 1 I2C: 00:55: enabled 1 I2C: 00:56: enabled 1 I2C: 00:57: enabled 1 I2C: 00:2f: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.106: enabled 0 PNP: 002e.107: enabled 0 PNP: 002e.207: enabled 0 PNP: 002e.307: enabled 0 PNP: 002e.407: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.108: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.109: enabled 0 PNP: 002e.209: enabled 0 PNP: 002e.309: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PNP: 002e.c: enabled 0 PNP: 002e.d: enabled 0 PNP: 002e.f: enabled 0 PNP: 004e.0: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 1 PCI: 00:19.3: enabled 1 PCI: 00:19.4: enabled 1 PCI: 00:19.5: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1a.1: enabled 1 PCI: 00:1a.2: enabled 1 PCI: 00:1a.3: enabled 1 PCI: 00:1a.4: enabled 1 PCI: 00:1a.5: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1b.1: enabled 1 PCI: 00:1b.2: enabled 1 PCI: 00:1b.3: enabled 1 PCI: 00:1b.4: enabled 1 PCI: 00:1b.5: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 I2C: 00:54: enabled 1 I2C: 00:55: enabled 1 I2C: 00:56: enabled 1 I2C: 00:57: enabled 1 I2C: 00:2f: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.106: enabled 0 PNP: 002e.107: enabled 0 PNP: 002e.207: enabled 0 PNP: 002e.307: enabled 0 PNP: 002e.407: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.108: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.109: enabled 0 PNP: 002e.209: enabled 0 PNP: 002e.309: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PNP: 002e.c: enabled 0 PNP: 002e.d: enabled 0 PNP: 002e.f: enabled 0 PNP: 004e.0: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 1 PCI: 00:19.3: enabled 1 PCI: 00:19.4: enabled 1 PCI: 00:19.5: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1a.1: enabled 1 PCI: 00:1a.2: enabled 1 PCI: 00:1a.3: enabled 1 PCI: 00:1a.4: enabled 1 PCI: 00:1a.5: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1b.1: enabled 1 PCI: 00:1b.2: enabled 1 PCI: 00:1b.3: enabled 1 PCI: 00:1b.4: enabled 1 PCI: 00:1b.5: enabled 1 Mainboard KGPE-D16 Enable. dev=0x0012dfe0 mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000008 Root Device scanning... root_dev_scan_bus for Root Device setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000008 CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 PCI: 00:18.5 siblings=7 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled CPU: APIC: 06 enabled CPU: APIC: 07 enabled PCI: 00:19.5 siblings=7 CPU: APIC: 08 enabled CPU: APIC: 09 enabled CPU: APIC: 0a enabled CPU: APIC: 0b enabled CPU: APIC: 0c enabled CPU: APIC: 0d enabled CPU: APIC: 0e enabled CPU: APIC: 0f enabled PCI: 00:1a.5 siblings=7 CPU: APIC: 20 enabled CPU: APIC: 21 enabled CPU: APIC: 22 enabled CPU: APIC: 23 enabled CPU: APIC: 24 enabled CPU: APIC: 25 enabled CPU: APIC: 26 enabled CPU: APIC: 27 enabled PCI: 00:1b.5 siblings=7 CPU: APIC: 28 enabled CPU: APIC: 29 enabled CPU: APIC: 2a enabled CPU: APIC: 2b enabled CPU: APIC: 2c enabled CPU: APIC: 2d enabled CPU: APIC: 2e enabled CPU: APIC: 2f enabled scan_bus: scanning of bus CPU_CLUSTER: 0 took 104694 usecs DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1600] bus ops PCI: 00:18.0 [1022/1600] enabled PCI: 00:18.1 [1022/1601] enabled PCI: 00:18.2 [1022/1602] enabled PCI: 00:18.3 [1022/1603] ops PCI: 00:18.3 [1022/1603] enabled PCI: 00:18.4 [1022/1604] ops PCI: 00:18.4 [1022/1604] enabled PCI: 00:18.5 [1022/1605] ops PCI: 00:18.5 [1022/1605] enabled PCI: 00:19.0 [1022/1600] bus ops PCI: 00:19.0 [1022/1600] enabled PCI: 00:19.1 [1022/1601] enabled PCI: 00:19.2 [1022/1602] enabled PCI: 00:19.3 [1022/1603] ops PCI: 00:19.3 [1022/1603] enabled PCI: 00:19.4 [1022/1604] ops PCI: 00:19.4 [1022/1604] enabled PCI: 00:19.5 [1022/1605] ops PCI: 00:19.5 [1022/1605] enabled PCI: 00:1a.0 [1022/1600] bus ops PCI: 00:1a.0 [1022/1600] enabled PCI: 00:1a.1 [1022/1601] enabled PCI: 00:1a.2 [1022/1602] enabled PCI: 00:1a.3 [1022/1603] ops PCI: 00:1a.3 [1022/1603] enabled PCI: 00:1a.4 [1022/1604] ops PCI: 00:1a.4 [1022/1604] enabled PCI: 00:1a.5 [1022/1605] ops PCI: 00:1a.5 [1022/1605] enabled PCI: 00:1b.0 [1022/1600] bus ops PCI: 00:1b.0 [1022/1600] enabled PCI: 00:1b.1 [1022/1601] enabled PCI: 00:1b.2 [1022/1602] enabled PCI: 00:1b.3 [1022/1603] ops PCI: 00:1b.3 [1022/1603] enabled PCI: 00:1b.4 [1022/1604] ops PCI: 00:1b.4 [1022/1604] enabled PCI: 00:1b.5 [1022/1605] ops PCI: 00:1b.5 [1022/1605] enabled PCI: 00:18.0 scanning... do_hypertransport_scan_chain for bus 00 sr5650_enable: dev=00130900, VID_DID=0x5a101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x00130900, dev=0x00130360, port=0x8 PciePowerOffGppPorts() port 8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000010. NB_PCI_REG4C = 52042. Sysmem TOM = 0_c0000000 Sysmem TOM2 = 8_40000000 PCI: 00:00.0 [1002/5a10] ops PCI: 00:00.0 [1002/5a10] enabled Capability: type 0x08 @ 0xf0 flags: 0xa803 Capability: type 0x08 @ 0xf0 Capability: type 0x08 @ 0xc4 flags: 0x0280 PCI: 00:00.0 count: 0014 static_count: 0015 PCI: 00:00.0 [1002/5a10] enabled next_unitid: 0015 PCI: pci_scan_bus for bus 00 sr5650_enable: dev=00130900, VID_DID=0x5a101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x00130900, dev=0x00130360, port=0x8 PciePowerOffGppPorts() port 8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000010. NB_PCI_REG4C = 52042. Sysmem TOM = 0_c0000000 Sysmem TOM2 = 8_40000000 PCI: 00:00.0 [1002/5a10] enabled sr5650_enable: dev=00130860, VID_DID=0xffffffff Bus-0, Dev-0, Fun-1. PCI: Static device PCI: 00:00.1 not found, disabling it. sr5650_enable: dev=001307c0, VID_DID=0x5a231002 Bus-0, Dev-0, Fun-2. PCI: 00:00.2 [1002/5a23] ops PCI: 00:00.2 [1002/5a23] enabled sr5650_enable: dev=00130720, VID_DID=0xffffffff Bus-0, Dev-2,3, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x00130900, dev=0x00130720, port=0x2 PcieLinkTraining port=2:lc current state=2030400 sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=0 PciePowerOffGppPorts() port 2 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.0 subordinate bus PCI Express PCI: 00:02.0 [1002/5a16] enabled sr5650_enable: dev=00130680, VID_DID=0xffffffff Bus-0, Dev-2,3, Fun-0. enable=0 sr5650_enable: dev=001305e0, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x00130900, dev=0x001305e0, port=0x4 PcieLinkTraining port=4:lc current state=2030400 sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=0 PciePowerOffGppPorts() port 4 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:04.0 subordinate bus PCI Express PCI: 00:04.0 [1002/5a18] enabled sr5650_enable: dev=00130540, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 sr5650_enable: dev=001304a0, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 sr5650_enable: dev=00130400, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 sr5650_enable: dev=00130360, VID_DID=0xffffffff Bus-0, Dev-8, Fun-0. enable=0 disable_pcie_bar3 sr5650_enable: dev=001302c0, VID_DID=0xffffffff Bus-0, Dev-9, 10, Fun-0. enable=1 enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x00130900, dev=0x001302c0, port=0x9 PcieLinkTraining port=5:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=48 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:09.0 subordinate bus PCI Express PCI: 00:09.0 [1002/5a1c] enabled sr5650_enable: dev=00130220, VID_DID=0xffffffff Bus-0, Dev-9, 10, Fun-0. enable=1 enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x00130900, dev=0x00130220, port=0xa PcieLinkTraining port=6:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=50 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0a.0 subordinate bus PCI Express PCI: 00:0a.0 [1002/5a1d] enabled sr5650_enable: dev=00130180, VID_DID=0xffffffff Bus-0, Dev-11,12, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x00130900, dev=0x00130180, port=0xb PcieLinkTraining port=b:lc current state=2030400 sr5650_gpp_sb_init: port=0xb hw_port=0xb result=0 PciePowerOffGppPorts() port 11 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0b.0 subordinate bus PCI Express PCI: 00:0b.0 [1002/5a1f] enabled sr5650_enable: dev=001300e0, VID_DID=0xffffffff Bus-0, Dev-11,12, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x00130900, dev=0x001300e0, port=0xc PcieLinkTraining port=c:lc current state=2030400 sr5650_gpp_sb_init: port=0xc hw_port=0xc result=0 PciePowerOffGppPorts() port 12 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0c.0 subordinate bus PCI Express PCI: 00:0c.0 [1002/5a20] enabled sr5650_enable: dev=00130040, VID_DID=0xffffffff sr5650_gpp_sb_init: nb_dev=0x00130900, dev=0x00130040, port=0xd PcieLinkTraining port=d:lc current state=2030400 sr5650_gpp_sb_init: port=0xd hw_port=0xd result=0 PciePowerOffGppPorts() port 13 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0d.0 subordinate bus PCI Express PCI: 00:0d.0 [1002/5a1e] enabled sb7xx_51xx_enable() PCI: 00:11.0 [1002/4394] ops PCI: 00:11.0 [1002/4394] enabled sb7xx_51xx_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb7xx_51xx_enable() PCI: 00:12.1 [1002/4398] ops PCI: 00:12.1 [1002/4398] enabled sb7xx_51xx_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb7xx_51xx_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb7xx_51xx_enable() PCI: 00:13.1 [1002/4398] ops PCI: 00:13.1 [1002/4398] enabled sb7xx_51xx_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb7xx_51xx_enable() PCI: 00:14.0 [1002/4385] bus ops PCI: 00:14.0 [1002/4385] enabled sb7xx_51xx_enable() PCI: 00:14.1 [1002/439c] ops PCI: 00:14.1 [1002/439c] enabled sb7xx_51xx_enable() PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled sb7xx_51xx_enable() PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled sb7xx_51xx_enable() PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled sb7xx_51xx_enable() PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled PCI: 00:02.0 scanning... do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:02.0 took 5906 usecs PCI: 00:04.0 scanning... do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 02 scan_bus: scanning of bus PCI: 00:04.0 took 5853 usecs PCI: 00:09.0 scanning... do_pci_scan_bridge for PCI: 00:09.0 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/10d3] enabled Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled None Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Failed to enable LTR for dev = PCI: 03:00.0 scan_bus: scanning of bus PCI: 00:09.0 took 32131 usecs PCI: 00:0a.0 scanning... do_pci_scan_bridge for PCI: 00:0a.0 PCI: pci_scan_bus for bus 04 PCI: 04:00.0 [8086/10d3] enabled Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled None Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Failed to enable LTR for dev = PCI: 04:00.0 scan_bus: scanning of bus PCI: 00:0a.0 took 32129 usecs PCI: 00:0b.0 scanning... do_pci_scan_bridge for PCI: 00:0b.0 PCI: pci_scan_bus for bus 05 scan_bus: scanning of bus PCI: 00:0b.0 took 5854 usecs PCI: 00:0c.0 scanning... do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 06 scan_bus: scanning of bus PCI: 00:0c.0 took 5854 usecs PCI: 00:0d.0 scanning... do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 07 scan_bus: scanning of bus PCI: 00:0d.0 took 5854 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 bus: PCI: 00:14.0[0]->I2C: 01:50 enabled bus: PCI: 00:14.0[0]->I2C: 01:51 enabled bus: PCI: 00:14.0[0]->I2C: 01:52 enabled bus: PCI: 00:14.0[0]->I2C: 01:53 enabled bus: PCI: 00:14.0[0]->I2C: 01:54 enabled bus: PCI: 00:14.0[0]->I2C: 01:55 enabled bus: PCI: 00:14.0[0]->I2C: 01:56 enabled bus: PCI: 00:14.0[0]->I2C: 01:57 enabled bus: PCI: 00:14.0[0]->I2C: 01:2f enabled scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 30099 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.106 disabled PNP: 002e.107 disabled PNP: 002e.207 disabled PNP: 002e.307 disabled PNP: 002e.407 disabled PNP: 002e.8 disabled PNP: 002e.108 disabled PNP: 002e.9 disabled PNP: 002e.109 disabled PNP: 002e.209 disabled PNP: 002e.309 disabled PNP: 002e.a enabled PNP: 002e.b enabled PNP: 002e.c disabled PNP: 002e.d disabled PNP: 002e.f disabled PNP: 004e.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 37388 usecs PCI: 00:14.4 scanning... do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 08 sb7xx_51xx_enable() PCI: 08:01.0 [1a03/2000] ops PCI: 08:01.0 [1a03/2000] enabled sb7xx_51xx_enable() PCI: 08:02.0 [11c1/5811] enabled sb7xx_51xx_enable() PCI: Static device PCI: 08:03.0 not found, disabling it. scan_bus: scanning of bus PCI: 00:14.4 took 19594 usecs scan_bus: scanning of bus PCI: 00:18.0 took 1711665 usecs PCI: 00:19.0 scanning... scan_bus: scanning of bus PCI: 00:19.0 took 1633 usecs PCI: 00:1a.0 scanning... scan_bus: scanning of bus PCI: 00:1a.0 took 1633 usecs PCI: 00:1b.0 scanning... scan_bus: scanning of bus PCI: 00:1b.0 took 1633 usecs DOMAIN: 0000 passpw: enabled DOMAIN: 0000 passpw: enabled DOMAIN: 0000 passpw: enabled DOMAIN: 0000 passpw: enabled scan_bus: scanning of bus DOMAIN: 0000 took 1824033 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 1954003 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 2271658 exit 0 found VGA at PCI: 08:01.0 Setting up VGA for PCI: 08:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:14.4 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Reserving CC6 save segment base: 838000000 size: 08000000 DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 sr5690_read_resource: PCI: 00:00.0 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 PCI: 00:02.0 read_resources bus 1 link: 0 PCI: 00:02.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 2 link: 0 PCI: 00:04.0 read_resources bus 2 link: 0 done PCI: 00:09.0 read_resources bus 3 link: 0 PCI: 00:09.0 read_resources bus 3 link: 0 done PCI: 00:0a.0 read_resources bus 4 link: 0 PCI: 00:0a.0 read_resources bus 4 link: 0 done PCI: 00:0b.0 read_resources bus 5 link: 0 PCI: 00:0b.0 read_resources bus 5 link: 0 done PCI: 00:0c.0 read_resources bus 6 link: 0 PCI: 00:0c.0 read_resources bus 6 link: 0 done PCI: 00:0d.0 read_resources bus 7 link: 0 PCI: 00:0d.0 read_resources bus 7 link: 0 done PCI: 00:14.0 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources I2C: 01:54 missing read_resources I2C: 01:55 missing read_resources I2C: 01:56 missing read_resources I2C: 01:57 missing read_resources PCI: 00:14.0 read_resources bus 1 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:14.4 read_resources bus 8 link: 0 PCI: 00:14.4 read_resources bus 8 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 PCI: 00:18.4 read_resources bus 0 link: 0 PCI: 00:18.4 read_resources bus 0 link: 0 done PCI: 00:18.4 read_resources bus 0 link: 1 PCI: 00:18.4 read_resources bus 0 link: 1 done PCI: 00:18.4 read_resources bus 0 link: 2 PCI: 00:18.4 read_resources bus 0 link: 2 done PCI: 00:18.4 read_resources bus 0 link: 3 PCI: 00:18.4 read_resources bus 0 link: 3 done PCI: 00:19.0 read_resources bus 0 link: 3 PCI: 00:19.0 read_resources bus 0 link: 3 done PCI: 00:19.0 read_resources bus 0 link: 2 PCI: 00:19.0 read_resources bus 0 link: 2 done PCI: 00:19.0 read_resources bus 0 link: 0 PCI: 00:19.0 read_resources bus 0 link: 0 done PCI: 00:19.0 read_resources bus 0 link: 1 PCI: 00:19.0 read_resources bus 0 link: 1 done PCI: 00:19.4 read_resources bus 0 link: 0 PCI: 00:19.4 read_resources bus 0 link: 0 done PCI: 00:19.4 read_resources bus 0 link: 1 PCI: 00:19.4 read_resources bus 0 link: 1 done PCI: 00:19.4 read_resources bus 0 link: 2 PCI: 00:19.4 read_resources bus 0 link: 2 done PCI: 00:19.4 read_resources bus 0 link: 3 PCI: 00:19.4 read_resources bus 0 link: 3 done PCI: 00:1a.0 read_resources bus 0 link: 3 PCI: 00:1a.0 read_resources bus 0 link: 3 done PCI: 00:1a.0 read_resources bus 0 link: 2 PCI: 00:1a.0 read_resources bus 0 link: 2 done PCI: 00:1a.0 read_resources bus 0 link: 0 PCI: 00:1a.0 read_resources bus 0 link: 0 done PCI: 00:1a.0 read_resources bus 0 link: 1 PCI: 00:1a.0 read_resources bus 0 link: 1 done PCI: 00:1a.4 read_resources bus 0 link: 0 PCI: 00:1a.4 read_resources bus 0 link: 0 done PCI: 00:1a.4 read_resources bus 0 link: 1 PCI: 00:1a.4 read_resources bus 0 link: 1 done PCI: 00:1a.4 read_resources bus 0 link: 2 PCI: 00:1a.4 read_resources bus 0 link: 2 done PCI: 00:1a.4 read_resources bus 0 link: 3 PCI: 00:1a.4 read_resources bus 0 link: 3 done PCI: 00:1b.0 read_resources bus 0 link: 3 PCI: 00:1b.0 read_resources bus 0 link: 3 done PCI: 00:1b.0 read_resources bus 0 link: 2 PCI: 00:1b.0 read_resources bus 0 link: 2 done PCI: 00:1b.0 read_resources bus 0 link: 0 PCI: 00:1b.0 read_resources bus 0 link: 0 done PCI: 00:1b.0 read_resources bus 0 link: 1 PCI: 00:1b.0 read_resources bus 0 link: 1 done PCI: 00:1b.4 read_resources bus 0 link: 0 PCI: 00:1b.4 read_resources bus 0 link: 0 done PCI: 00:1b.4 read_resources bus 0 link: 1 PCI: 00:1b.4 read_resources bus 0 link: 1 done PCI: 00:1b.4 read_resources bus 0 link: 2 PCI: 00:1b.4 read_resources bus 0 link: 2 done PCI: 00:1b.4 read_resources bus 0 link: 3 PCI: 00:1b.4 read_resources bus 0 link: 3 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 APIC: 06 APIC: 07 APIC: 08 APIC: 09 APIC: 0a APIC: 0b APIC: 0c APIC: 0d APIC: 0e APIC: 0f APIC: 20 APIC: 21 APIC: 22 APIC: 23 APIC: 24 APIC: 25 APIC: 26 APIC: 27 APIC: 28 APIC: 29 APIC: 2a APIC: 2b APIC: 2c APIC: 2d APIC: 2e APIC: 2f DOMAIN: 0000 child on link 0 PCI: 00:18.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 DOMAIN: 0000 resource base 838000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:18.0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b8 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 child on link 0 PCI: 03:00.0 PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:0a.0 child on link 0 PCI: 04:00.0 PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0d.0 PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.1 PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74 PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90 PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 I2C: 01:54 I2C: 01:55 I2C: 01:56 I2C: 01:57 I2C: 01:2f PCI: 00:14.1 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.106 PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 PNP: 002e.107 PNP: 002e.207 PNP: 002e.307 PNP: 002e.407 PNP: 002e.8 PNP: 002e.108 PNP: 002e.9 PNP: 002e.109 PNP: 002e.209 PNP: 002e.309 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.d PNP: 002e.f PNP: 004e.0 PNP: 004e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 004e.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:14.4 child on link 0 PCI: 08:01.0 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 08:01.0 PCI: 08:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10 PCI: 08:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14 PCI: 08:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18 PCI: 08:02.0 PCI: 08:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 08:03.0 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:19.0 PCI: 00:19.1 PCI: 00:19.2 PCI: 00:19.3 PCI: 00:19.4 PCI: 00:19.5 PCI: 00:1a.0 PCI: 00:1a.1 PCI: 00:1a.2 PCI: 00:1a.3 PCI: 00:1a.4 PCI: 00:1a.5 PCI: 00:1b.0 PCI: 00:1b.1 PCI: 00:1b.2 PCI: 00:1b.3 PCI: 00:1b.4 PCI: 00:1b.5 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 03:00.0 18 * [0x0 - 0x1f] io PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 04:00.0 18 * [0x0 - 0x1f] io PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 08:01.0 18 * [0x0 - 0x7f] io PCI: 00:14.4 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:09.0 1c * [0x0 - 0xfff] io PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io PCI: 00:14.4 1c * [0x2000 - 0x2fff] io PCI: 00:11.0 20 * [0x3000 - 0x300f] io PCI: 00:14.1 20 * [0x3010 - 0x301f] io PCI: 00:11.0 10 * [0x3020 - 0x3027] io PCI: 00:11.0 18 * [0x3028 - 0x302f] io PCI: 00:14.1 10 * [0x3030 - 0x3037] io PCI: 00:14.1 18 * [0x3038 - 0x303f] io PCI: 00:11.0 14 * [0x3040 - 0x3043] io PCI: 00:11.0 1c * [0x3044 - 0x3047] io PCI: 00:14.1 14 * [0x3048 - 0x304b] io PCI: 00:14.1 1c * [0x304c - 0x304f] io PCI: 00:18.0 io: base: 3050 size: 4000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 110d8 * [0x0 - 0x3fff] io DOMAIN: 0000 io: base: 4000 size: 4000 align: 12 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 fc * [0x0 - 0xff] prefmem PCI: 00:18.0 prefmem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 08:01.0 10 * [0x0 - 0x7fffff] mem PCI: 08:01.0 14 * [0x800000 - 0x81ffff] mem PCI: 08:02.0 10 * [0x820000 - 0x820fff] mem PCI: 00:14.4 mem: base: 821000 size: 900000 align: 23 gran: 20 limit: ffffffff done PCI: 00:14.4 20 * [0x0 - 0x8fffff] mem PCI: 00:09.0 20 * [0x900000 - 0x9fffff] mem PCI: 00:0a.0 20 * [0xa00000 - 0xafffff] mem PCI: 00:00.2 44 * [0xb00000 - 0xb03fff] mem PCI: 00:14.2 10 * [0xb04000 - 0xb07fff] mem PCI: 00:12.0 10 * [0xb08000 - 0xb08fff] mem PCI: 00:12.1 10 * [0xb09000 - 0xb09fff] mem PCI: 00:13.0 10 * [0xb0a000 - 0xb0afff] mem PCI: 00:13.1 10 * [0xb0b000 - 0xb0bfff] mem PCI: 00:14.5 10 * [0xb0c000 - 0xb0cfff] mem PCI: 00:11.0 24 * [0xb0d000 - 0xb0d3ff] mem PCI: 00:12.2 10 * [0xb0e000 - 0xb0e0ff] mem PCI: 00:13.2 10 * [0xb0f000 - 0xb0f0ff] mem PCI: 00:14.3 a0 * [0xb10000 - 0xb10000] mem PCI: 00:18.0 mem: base: b10001 size: c00000 align: 23 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:18.0 110b8 * [0x4000000 - 0x4bfffff] mem PCI: 00:18.0 110b0 * [0x4c00000 - 0x4cfffff] prefmem DOMAIN: 0000 mem: base: 4d00000 size: 4d00000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed) constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed) constrain_resources: DOMAIN: 0000 08 base 838000000 limit 83fffffff mem (fixed) constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:14.0 b4 base fed00000 limit fed003ff mem (fixed) constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed) constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed) constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff800000 limit ffffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit ffffffff Setting resources... DOMAIN: 0000 io: base:1000 size:4000 align:12 gran:0 limit:ffff PCI: 00:18.0 110d8 * [0x1000 - 0x4fff] io DOMAIN: 0000 io: next_base: 5000 size: 4000 align: 12 gran: 0 done PCI: 00:18.0 io: base:1000 size:4000 align:12 gran:12 limit:4fff PCI: 00:09.0 1c * [0x1000 - 0x1fff] io PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io PCI: 00:14.4 1c * [0x3000 - 0x3fff] io PCI: 00:11.0 20 * [0x4000 - 0x400f] io PCI: 00:14.1 20 * [0x4010 - 0x401f] io PCI: 00:11.0 10 * [0x4020 - 0x4027] io PCI: 00:11.0 18 * [0x4028 - 0x402f] io PCI: 00:14.1 10 * [0x4030 - 0x4037] io PCI: 00:14.1 18 * [0x4038 - 0x403f] io PCI: 00:11.0 14 * [0x4040 - 0x4043] io PCI: 00:11.0 1c * [0x4044 - 0x4047] io PCI: 00:14.1 14 * [0x4048 - 0x404b] io PCI: 00:14.1 1c * [0x404c - 0x404f] io PCI: 00:18.0 io: next_base: 4050 size: 4000 align: 12 gran: 12 done PCI: 00:02.0 io: base:4fff size:0 align:12 gran:12 limit:4fff PCI: 00:02.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done PCI: 00:04.0 io: base:4fff size:0 align:12 gran:12 limit:4fff PCI: 00:04.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff PCI: 03:00.0 18 * [0x1000 - 0x101f] io PCI: 00:09.0 io: next_base: 1020 size: 1000 align: 12 gran: 12 done PCI: 00:0a.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff PCI: 04:00.0 18 * [0x2000 - 0x201f] io PCI: 00:0a.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done PCI: 00:0b.0 io: base:4fff size:0 align:12 gran:12 limit:4fff PCI: 00:0b.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done PCI: 00:0c.0 io: base:4fff size:0 align:12 gran:12 limit:4fff PCI: 00:0c.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done PCI: 00:0d.0 io: base:4fff size:0 align:12 gran:12 limit:4fff PCI: 00:0d.0 io: next_base: 4fff size: 0 align: 12 gran: 12 done PCI: 00:14.4 io: base:3000 size:1000 align:12 gran:12 limit:3fff PCI: 08:01.0 18 * [0x3000 - 0x307f] io PCI: 00:14.4 io: next_base: 3080 size: 1000 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f8000000 size:4d00000 align:26 gran:0 limit:ffffffff PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem PCI: 00:18.0 110b8 * [0xfc000000 - 0xfcbfffff] mem PCI: 00:18.0 110b0 * [0xfcc00000 - 0xfccfffff] prefmem DOMAIN: 0000 mem: next_base: fcd00000 size: 4d00000 align: 26 gran: 0 done PCI: 00:18.0 prefmem: base:fcc00000 size:100000 align:20 gran:20 limit:fccfffff PCI: 00:00.0 fc * [0xfcc00000 - 0xfcc000ff] prefmem PCI: 00:18.0 prefmem: next_base: fcc00100 size: 100000 align: 20 gran: 20 done PCI: 00:02.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:02.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:04.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:04.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:09.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:09.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:0a.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:0a.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:0b.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:0b.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:0c.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:0d.0 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 prefmem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:14.4 prefmem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 mem: base:fc000000 size:c00000 align:23 gran:20 limit:fcbfffff PCI: 00:14.4 20 * [0xfc000000 - 0xfc8fffff] mem PCI: 00:09.0 20 * [0xfc900000 - 0xfc9fffff] mem PCI: 00:0a.0 20 * [0xfca00000 - 0xfcafffff] mem PCI: 00:00.2 44 * [0xfcb00000 - 0xfcb03fff] mem PCI: 00:14.2 10 * [0xfcb04000 - 0xfcb07fff] mem PCI: 00:12.0 10 * [0xfcb08000 - 0xfcb08fff] mem PCI: 00:12.1 10 * [0xfcb09000 - 0xfcb09fff] mem PCI: 00:13.0 10 * [0xfcb0a000 - 0xfcb0afff] mem PCI: 00:13.1 10 * [0xfcb0b000 - 0xfcb0bfff] mem PCI: 00:14.5 10 * [0xfcb0c000 - 0xfcb0cfff] mem PCI: 00:11.0 24 * [0xfcb0d000 - 0xfcb0d3ff] mem PCI: 00:12.2 10 * [0xfcb0e000 - 0xfcb0e0ff] mem PCI: 00:13.2 10 * [0xfcb0f000 - 0xfcb0f0ff] mem PCI: 00:14.3 a0 * [0xfcb10000 - 0xfcb10000] mem PCI: 00:18.0 mem: next_base: fcb10001 size: c00000 align: 23 gran: 20 done PCI: 00:02.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff PCI: 00:02.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done PCI: 00:04.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff PCI: 00:04.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done PCI: 00:09.0 mem: base:fc900000 size:100000 align:20 gran:20 limit:fc9fffff PCI: 03:00.0 10 * [0xfc900000 - 0xfc91ffff] mem PCI: 03:00.0 1c * [0xfc920000 - 0xfc923fff] mem PCI: 00:09.0 mem: next_base: fc924000 size: 100000 align: 20 gran: 20 done PCI: 00:0a.0 mem: base:fca00000 size:100000 align:20 gran:20 limit:fcafffff PCI: 04:00.0 10 * [0xfca00000 - 0xfca1ffff] mem PCI: 04:00.0 1c * [0xfca20000 - 0xfca23fff] mem PCI: 00:0a.0 mem: next_base: fca24000 size: 100000 align: 20 gran: 20 done PCI: 00:0b.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff PCI: 00:0b.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff PCI: 00:0c.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff PCI: 00:0d.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 mem: base:fc000000 size:900000 align:23 gran:20 limit:fc8fffff PCI: 08:01.0 10 * [0xfc000000 - 0xfc7fffff] mem PCI: 08:01.0 14 * [0xfc800000 - 0xfc81ffff] mem PCI: 08:02.0 10 * [0xfc820000 - 0xfc820fff] mem PCI: 00:14.4 mem: next_base: fc821000 size: 900000 align: 23 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=00300000, basek=00400000, limitk=01100000 2: mmio_basek=00300000, basek=01100000, limitk=02100000 DOMAIN: 0000 assign_resources, bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem PCI: 00:18.0 110b0 <- [0x00fcc00000 - 0x00fccfffff] size 0x00100000 gran 0x14 prefmem PCI: 00:18.0 110b8 <- [0x00fc000000 - 0x00fcbfffff] size 0x00c00000 gran 0x14 mem PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000004fff] size 0x00004000 gran 0x0c io PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:00.0 sr5690_set_resources sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90 PCI: 00:00.0 fc <- [0x00fcc00000 - 0x00fcc000ff] size 0x00000100 gran 0x08 prefmem CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 PCI: 00:00.2 44 <- [0x00fcb00000 - 0x00fcb03fff] size 0x00004000 gran 0x0e mem PCI: 00:02.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:04.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:04.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:04.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:09.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:09.0 20 <- [0x00fc900000 - 0x00fc9fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x00fc900000 - 0x00fc91ffff] size 0x00020000 gran 0x11 mem PCI: 03:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io PCI: 03:00.0 1c <- [0x00fc920000 - 0x00fc923fff] size 0x00004000 gran 0x0e mem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io PCI: 00:0a.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:0a.0 20 <- [0x00fca00000 - 0x00fcafffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 00:0a.0 assign_resources, bus 4 link: 0 PCI: 04:00.0 10 <- [0x00fca00000 - 0x00fca1ffff] size 0x00020000 gran 0x11 mem PCI: 04:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 04:00.0 1c <- [0x00fca20000 - 0x00fca23fff] size 0x00004000 gran 0x0e mem PCI: 00:0a.0 assign_resources, bus 4 link: 0 PCI: 00:0b.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:0b.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:0b.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:0c.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 06 io PCI: 00:0c.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 06 prefmem PCI: 00:0c.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 06 mem PCI: 00:0d.0 1c <- [0x0000004fff - 0x0000004ffe] size 0x00000000 gran 0x0c bus 07 io PCI: 00:0d.0 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 07 prefmem PCI: 00:0d.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 07 mem PCI: 00:11.0 10 <- [0x0000004020 - 0x0000004027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000004040 - 0x0000004043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000004028 - 0x000000402f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000004044 - 0x0000004047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000004000 - 0x000000400f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00fcb0d000 - 0x00fcb0d3ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00fcb08000 - 0x00fcb08fff] size 0x00001000 gran 0x0c mem PCI: 00:12.1 10 <- [0x00fcb09000 - 0x00fcb09fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00fcb0e000 - 0x00fcb0e0ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00fcb0a000 - 0x00fcb0afff] size 0x00001000 gran 0x0c mem PCI: 00:13.1 10 <- [0x00fcb0b000 - 0x00fcb0bfff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00fcb0f000 - 0x00fcb0f0ff] size 0x00000100 gran 0x08 mem PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.1 10 <- [0x0000004030 - 0x0000004037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000004048 - 0x000000404b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000004038 - 0x000000403f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000404c - 0x000000404f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000004010 - 0x000000401f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00fcb04000 - 0x00fcb07fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 a0 <- [0x00fcb10000 - 0x00fcb10000] size 0x00000001 gran 0x00 mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.4 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 08 io PCI: 00:14.4 24 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 08 prefmem PCI: 00:14.4 20 <- [0x00fc000000 - 0x00fc8fffff] size 0x00900000 gran 0x14 bus 08 mem PCI: 00:14.4 assign_resources, bus 8 link: 0 PCI: 08:01.0 10 <- [0x00fc000000 - 0x00fc7fffff] size 0x00800000 gran 0x17 mem PCI: 08:01.0 14 <- [0x00fc800000 - 0x00fc81ffff] size 0x00020000 gran 0x11 mem PCI: 08:01.0 18 <- [0x0000003000 - 0x000000307f] size 0x00000080 gran 0x07 io PCI: 08:02.0 10 <- [0x00fc820000 - 0x00fc820fff] size 0x00001000 gran 0x0c mem PCI: 00:14.4 assign_resources, bus 8 link: 0 PCI: 00:14.5 10 <- [0x00fcb0c000 - 0x00fcb0cfff] size 0x00001000 gran 0x0c mem PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem PCI: 00:1a.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem PCI: 00:1b.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 APIC: 06 APIC: 07 APIC: 08 APIC: 09 APIC: 0a APIC: 0b APIC: 0c APIC: 0d APIC: 0e APIC: 0f APIC: 20 APIC: 21 APIC: 22 APIC: 23 APIC: 24 APIC: 25 APIC: 26 APIC: 27 APIC: 28 APIC: 29 APIC: 2a APIC: 2b APIC: 2c APIC: 2d APIC: 2e APIC: 2f DOMAIN: 0000 child on link 0 PCI: 00:18.0 DOMAIN: 0000 resource base 1000 size 4000 align 12 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f8000000 size 4d00000 align 26 gran 0 limit ffffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 DOMAIN: 0000 resource base 838000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 DOMAIN: 0000 resource base 100000000 size 340000000 align 0 gran 0 limit 0 flags e0004200 index 30 DOMAIN: 0000 resource base 440000000 size 400000000 align 0 gran 0 limit 0 flags e0004200 index 42 PCI: 00:18.0 PCI: 00:18.0 resource base fcc00000 size 100000 align 20 gran 20 limit fccfffff flags 60081200 index 110b0 PCI: 00:18.0 resource base fc000000 size c00000 align 23 gran 20 limit fcbfffff flags 60080200 index 110b8 PCI: 00:18.0 resource base 1000 size 4000 align 12 gran 12 limit 4fff flags 60080100 index 110d8 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8 PCI: 00:00.0 PCI: 00:00.0 resource base fcc00000 size 100 align 12 gran 8 limit fcc000ff flags 60001200 index fc PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.2 resource base fcb00000 size 4000 align 14 gran 14 limit fcb03fff flags 70000200 index 44 PCI: 00:02.0 PCI: 00:02.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c PCI: 00:02.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24 PCI: 00:02.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:04.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c PCI: 00:04.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24 PCI: 00:04.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 child on link 0 PCI: 03:00.0 PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c PCI: 00:09.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24 PCI: 00:09.0 resource base fc900000 size 100000 align 20 gran 20 limit fc9fffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base fc900000 size 20000 align 17 gran 17 limit fc91ffff flags 60000200 index 10 PCI: 03:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18 PCI: 03:00.0 resource base fc920000 size 4000 align 14 gran 14 limit fc923fff flags 60000200 index 1c PCI: 00:0a.0 child on link 0 PCI: 04:00.0 PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c PCI: 00:0a.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24 PCI: 00:0a.0 resource base fca00000 size 100000 align 20 gran 20 limit fcafffff flags 60080202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base fca00000 size 20000 align 17 gran 17 limit fca1ffff flags 60000200 index 10 PCI: 04:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18 PCI: 04:00.0 resource base fca20000 size 4000 align 14 gran 14 limit fca23fff flags 60000200 index 1c PCI: 00:0b.0 PCI: 00:0b.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c PCI: 00:0b.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24 PCI: 00:0b.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20 PCI: 00:0c.0 PCI: 00:0c.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c PCI: 00:0c.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24 PCI: 00:0c.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20 PCI: 00:0d.0 PCI: 00:0d.0 resource base 4fff size 0 align 12 gran 12 limit 4fff flags 60080102 index 1c PCI: 00:0d.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24 PCI: 00:0d.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20 PCI: 00:11.0 PCI: 00:11.0 resource base 4020 size 8 align 3 gran 3 limit 4027 flags 60000100 index 10 PCI: 00:11.0 resource base 4040 size 4 align 2 gran 2 limit 4043 flags 60000100 index 14 PCI: 00:11.0 resource base 4028 size 8 align 3 gran 3 limit 402f flags 60000100 index 18 PCI: 00:11.0 resource base 4044 size 4 align 2 gran 2 limit 4047 flags 60000100 index 1c PCI: 00:11.0 resource base 4000 size 10 align 4 gran 4 limit 400f flags 60000100 index 20 PCI: 00:11.0 resource base fcb0d000 size 400 align 12 gran 10 limit fcb0d3ff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base fcb08000 size 1000 align 12 gran 12 limit fcb08fff flags 60000200 index 10 PCI: 00:12.1 PCI: 00:12.1 resource base fcb09000 size 1000 align 12 gran 12 limit fcb09fff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base fcb0e000 size 100 align 12 gran 8 limit fcb0e0ff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base fcb0a000 size 1000 align 12 gran 12 limit fcb0afff flags 60000200 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base fcb0b000 size 1000 align 12 gran 12 limit fcb0bfff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base fcb0f000 size 100 align 12 gran 8 limit fcb0f0ff flags 60000200 index 10 PCI: 00:14.0 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74 PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90 PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 I2C: 01:54 I2C: 01:55 I2C: 01:56 I2C: 01:57 I2C: 01:2f PCI: 00:14.1 PCI: 00:14.1 resource base 4030 size 8 align 3 gran 3 limit 4037 flags 60000100 index 10 PCI: 00:14.1 resource base 4048 size 4 align 2 gran 2 limit 404b flags 60000100 index 14 PCI: 00:14.1 resource base 4038 size 8 align 3 gran 3 limit 403f flags 60000100 index 18 PCI: 00:14.1 resource base 404c size 4 align 2 gran 2 limit 404f flags 60000100 index 1c PCI: 00:14.1 resource base 4010 size 10 align 4 gran 4 limit 401f flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base fcb04000 size 4000 align 14 gran 14 limit fcb07fff flags 60000201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base fcb10000 size 1 align 12 gran 0 limit fcb10000 flags 60000200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 002e.106 PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 PNP: 002e.107 PNP: 002e.207 PNP: 002e.307 PNP: 002e.407 PNP: 002e.8 PNP: 002e.108 PNP: 002e.9 PNP: 002e.109 PNP: 002e.209 PNP: 002e.309 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.d PNP: 002e.f PNP: 004e.0 PNP: 004e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 004e.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:14.4 child on link 0 PCI: 08:01.0 PCI: 00:14.4 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c PCI: 00:14.4 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60081202 index 24 PCI: 00:14.4 resource base fc000000 size 900000 align 23 gran 20 limit fc8fffff flags 60080202 index 20 PCI: 08:01.0 PCI: 08:01.0 resource base fc000000 size 800000 align 23 gran 23 limit fc7fffff flags 60000200 index 10 PCI: 08:01.0 resource base fc800000 size 20000 align 17 gran 17 limit fc81ffff flags 60000200 index 14 PCI: 08:01.0 resource base 3000 size 80 align 7 gran 7 limit 307f flags 60000100 index 18 PCI: 08:01.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 08:02.0 PCI: 08:02.0 resource base fc820000 size 1000 align 12 gran 12 limit fc820fff flags 60000200 index 10 PCI: 08:03.0 PCI: 00:14.5 PCI: 00:14.5 resource base fcb0c000 size 1000 align 12 gran 12 limit fcb0cfff flags 60000200 index 10 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:19.0 PCI: 00:19.1 PCI: 00:19.2 PCI: 00:19.3 PCI: 00:19.4 PCI: 00:19.5 PCI: 00:1a.0 PCI: 00:1a.1 PCI: 00:1a.2 PCI: 00:1a.3 PCI: 00:1a.4 PCI: 00:1a.5 PCI: 00:1b.0 PCI: 00:1b.1 PCI: 00:1b.2 PCI: 00:1b.3 PCI: 00:1b.4 PCI: 00:1b.5 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 3149410 exit 0 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/8163 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/8163 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 subsystem <- 1043/8163 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 subsystem <- 1043/8163 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 PCI: 00:19.4 cmd <- 00 PCI: 00:19.5 cmd <- 00 PCI: 00:1a.0 cmd <- 00 PCI: 00:1a.1 subsystem <- 1043/8163 PCI: 00:1a.1 cmd <- 00 PCI: 00:1a.2 subsystem <- 1043/8163 PCI: 00:1a.2 cmd <- 00 PCI: 00:1a.3 cmd <- 00 PCI: 00:1a.4 cmd <- 00 PCI: 00:1a.5 cmd <- 00 PCI: 00:1b.0 cmd <- 00 PCI: 00:1b.1 subsystem <- 1043/8163 PCI: 00:1b.1 cmd <- 00 PCI: 00:1b.2 subsystem <- 1043/8163 PCI: 00:1b.2 cmd <- 00 PCI: 00:1b.3 cmd <- 00 PCI: 00:1b.4 cmd <- 00 PCI: 00:1b.5 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/8163 PCI: 00:00.0 cmd <- 02 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Initializing IOMMU PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 00 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 00 PCI: 00:09.0 bridge ctrl <- 0003 PCI: 00:09.0 cmd <- 07 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 07 PCI: 00:0b.0 bridge ctrl <- 0003 PCI: 00:0b.0 cmd <- 00 PCI: 00:0c.0 bridge ctrl <- 0003 PCI: 00:0c.0 cmd <- 00 PCI: 00:0d.0 bridge ctrl <- 0003 PCI: 00:0d.0 cmd <- 00 PCI: 00:11.0 subsystem <- 1043/8163 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1043/8163 PCI: 00:12.0 cmd <- 02 PCI: 00:12.1 subsystem <- 1043/8163 PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 subsystem <- 1043/8163 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1043/8163 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1043/8163 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1043/8163 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1043/8163 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1043/8163 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1043/8163 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1043/8163 PCI: 00:14.3 cmd <- 0f sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291 PCI: 00:14.4 bridge ctrl <- 000b PCI: 00:14.4 cmd <- 07 PCI: 00:14.5 subsystem <- 1043/8163 PCI: 00:14.5 cmd <- 02 PCI: 03:00.0 cmd <- 03 PCI: 04:00.0 cmd <- 03 PCI: 08:01.0 cmd <- 03 PCI: 08:02.0 subsystem <- 1043/8163 PCI: 08:02.0 cmd <- 02 done. BS: BS_DEV_ENABLE times (us): entry 0 run 190670 exit 0 Initializing devices... Root Device init ... Root Device init finished in 1381 usecs CPU_CLUSTER: 0 init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Enabling probe filter Enabling ATM mode CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 start_eip=0x00001000, code_size=0x00000031 CPU1: stack_base 00151000, stack_end 00151ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device 600f12 After Startup. CPU: family 15, model 01, stepping 02 CPU2: stack_base 00150000, stack_end 00150ff8 nodeid = 00, coreid = 01 Asserting INIT. Enabling cache Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Initializing CPU #2 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device 600f12 After Startup. CPU3: stack_base 0014f000, stack_end 0014fff8 CPU: family 15, model 01, stepping 02 Asserting INIT. Waiting for send to finish... +nodeid = 00, coreid = 02 Deasserting INIT. Waiting for send to finish... +Enabling cache #startup loops: 1. Sending STARTUP #1 to 3. After apic_write. CPU ID 0x80000001: 600f12 Startup point 1. Waiting for send to finish... +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB After Startup. CPU4: stack_base 0014e000, stack_end 0014eff8 Initializing CPU #3 Asserting INIT. MTRR: Physical address space: Waiting for send to finish... +CPU: vendor AMD device 600f12 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 Deasserting INIT. CPU: family 15, model 01, stepping 02 Waiting for send to finish... +nodeid = 00, coreid = 03 #startup loops: 1. Sending STARTUP #1 to 4. After apic_write. Enabling cache Startup point 1. 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 Waiting for send to finish... +0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 After Startup. CPU5: stack_base 0014d000, stack_end 0014dff8 0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0 Asserting INIT. 0x0000000100000000 - 0x0000000840000000 size 0x740000000 type 6 Waiting for send to finish... +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e Deasserting INIT. MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e Waiting for send to finish... +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e #startup loops: 1. Sending STARTUP #1 to 5. After apic_write. MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e Startup point 1. MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e Waiting for send to finish... +Initializing CPU #5 After Startup. CPU6: stack_base 0014c000, stack_end 0014cff8 MTRR: default type WB/UC MTRR counts: 1/2. MTRR: WB selected as default type. Asserting INIT. MTRR: 0 base 0x00000000c0000000 mask 0x0000ffffc0000000 type 0 Waiting for send to finish... + MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Deasserting INIT. Waiting for send to finish... +Setting up local APIC...#startup loops: 1. Sending STARTUP #1 to 6. apic_id: 0x02 done. After apic_write. CPU model: AMD Opteron(TM) Processor 6276 Startup point 1. Waiting for send to finish... siblings = 15, +Disabling SMM ASeg memory After Startup. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU7: stack_base 0014b000, stack_end 0014bff8 CPU #2 initialized Asserting INIT. Waiting for send to finish... +Setting up local APIC...Deasserting INIT. apic_id: 0x03 Waiting for send to finish... +done. #startup loops: 1. Sending STARTUP #1 to 7. CPU model: AMD Opteron(TM) Processor 6276 After apic_write. siblings = 15, Startup point 1. Waiting for send to finish... +Disabling SMM ASeg memory After Startup. CPU8: stack_base 0014a000, stack_end 0014aff8 CPU #3 initialized Asserting INIT. Waiting for send to finish... +Initializing CPU #6 Deasserting INIT. Waiting for send to finish... +CPU: vendor AMD device 600f12 #startup loops: 1. Sending STARTUP #1 to 8. After apic_write. CPU: vendor AMD device 600f12 Startup point 1. Waiting for send to finish... +CPU: family 15, model 01, stepping 02 After Startup. CPU9: stack_base 00149000, stack_end 00149ff8 Initializing CPU #7 Asserting INIT. Waiting for send to finish... +CPU: vendor AMD device 600f12 Deasserting INIT. Waiting for send to finish... +nodeid = 00, coreid = 05 #startup loops: 1. Sending STARTUP #1 to 9. After apic_write. Initializing CPU #4 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device 600f12 After Startup. CPU10: stack_base 00148000, stack_end 00148ff8 Enabling cache Asserting INIT. CPU: family 15, model 01, stepping 02 Waiting for send to finish... +nodeid = 00, coreid = 04 Deasserting INIT. CPU: family 15, model 01, stepping 02 Waiting for send to finish... +Initializing CPU #8 #startup loops: 1. Sending STARTUP #1 to 10. After apic_write. Initializing CPU #9 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device 600f12 After Startup. CPU11: stack_base 00147000, stack_end 00147ff8 CPU: family 15, model 01, stepping 02 Asserting INIT. Waiting for send to finish... +Enabling cache Deasserting INIT. Waiting for send to finish... +CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB #startup loops: 1. Sending STARTUP #1 to 11. After apic_write. MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 Startup point 1. Waiting for send to finish... +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e After Startup. MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e CPU12: stack_base 00146000, stack_end 00146ff8 nodeid = 00, coreid = 07 Asserting INIT. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Waiting for send to finish... +Enabled Deasserting INIT. Waiting for send to finish... +Setting up local APIC...#startup loops: 1. Sending STARTUP #1 to 12. After apic_write. apic_id: 0x04 done. Startup point 1. Waiting for send to finish... +CPU model: AMD Opteron(TM) Processor 6276 After Startup. siblings = 15, CPU13: stack_base 00145000, stack_end 00145ff8 Disabling SMM ASeg memory Asserting INIT. CPU #4 initialized Waiting for send to finish... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled + Deasserting INIT. Waiting for send to finish... Setting up local APIC...+ apic_id: 0x05 done. #startup loops: 1. Sending STARTUP #1 to 13. CPU model: AMD Opteron(TM) Processor 6276 After apic_write. siblings = 15, Startup point 1. Waiting for send to finish... +Disabling SMM ASeg memory After Startup. CPU #5 initialized CPU14: stack_base 00144000, stack_end 00144ff8 nodeid = 00, coreid = 06 Asserting INIT. Waiting for send to finish... +Initializing CPU #12 Deasserting INIT. Waiting for send to finish... +Enabling cache #startup loops: 1. Sending STARTUP #1 to 14. After apic_write. Enabling cache Startup point 1. Waiting for send to finish... CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +CPU: vendor AMD device 600f12 After Startup. MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e CPU15: stack_base 00143000, stack_end 00143ff8 MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e Asserting INIT. Waiting for send to finish... +Initializing CPU #10 Deasserting INIT. MTRR check Fixed MTRRs : Enabled Waiting for send to finish... Variable MTRRs: +Enabled #startup loops: 1. Sending STARTUP #1 to 15. After apic_write. Setting up local APIC...Startup point 1. Waiting for send to finish... apic_id: 0x06 done. +CPU model: AMD Opteron(TM) Processor 6276 After Startup. siblings = 15, CPU16: stack_base 00142000, stack_end 00142ff8 Disabling SMM ASeg memory Asserting INIT. MTRR check Fixed MTRRs : Enabled Waiting for send to finish... +Variable MTRRs: Deasserting INIT. CPU #6 initialized Waiting for send to finish... +Enabled #startup loops: 1. Sending STARTUP #1 to 32. After apic_write. Setting up local APIC...Startup point 1. Waiting for send to finish... + apic_id: 0x07 done. After Startup. CPU17: stack_base 00141000, stack_end 00141ff8 CPU model: AMD Opteron(TM) Processor 6276 Asserting INIT. siblings = 15, Waiting for send to finish... +Disabling SMM ASeg memory Deasserting INIT. CPU #7 initialized Waiting for send to finish... +Initializing CPU #16 #startup loops: 1. Sending STARTUP #1 to 33. After apic_write. CPU: vendor AMD device 600f12 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device 600f12 After Startup. CPU18: stack_base 00140000, stack_end 00140ff8 CPU: vendor AMD device 600f12 Asserting INIT. Waiting for send to finish... +CPU: family 15, model 01, stepping 02 Deasserting INIT. Waiting for send to finish... +nodeid = 01, coreid = 01 #startup loops: 1. Sending STARTUP #1 to 34. After apic_write. Initializing CPU #13 Startup point 1. Waiting for send to finish... +CPU: family 15, model 01, stepping 02 After Startup. CPU19: stack_base 0013f000, stack_end 0013fff8 Initializing CPU #18 Asserting INIT. Waiting for send to finish... +Enabling cache Deasserting INIT. Waiting for send to finish... +CPU: family 15, model 01, stepping 02 #startup loops: 1. Sending STARTUP #1 to 35. After apic_write. nodeid = 01, coreid = 00 Startup point 1. Waiting for send to finish... +Enabling cache After Startup. CPU20: stack_base 0013e000, stack_end 0013eff8 CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Asserting INIT. Waiting for send to finish... +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e Deasserting INIT. Waiting for send to finish... +nodeid = 01, coreid = 04 #startup loops: 1. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Sending STARTUP #1 to 36. After apic_write. Setting up local APIC...Startup point 1. Waiting for send to finish... + apic_id: 0x08 done. After Startup. CPU model: AMD Opteron(TM) Processor 6276 CPU21: stack_base 0013d000, stack_end 0013dff8 siblings = 15, Asserting INIT. Disabling SMM ASeg memory Waiting for send to finish... + MTRR check Fixed MTRRs : Enabled Deasserting INIT. CPU #8 initialized Waiting for send to finish... +Variable MTRRs: Enabled #startup loops: 1. Sending STARTUP #1 to 37. Setting up local APIC...After apic_write. apic_id: 0x09 done. Startup point 1. Waiting for send to finish... +CPU model: AMD Opteron(TM) Processor 6276 After Startup. siblings = 15, CPU22: stack_base 0013c000, stack_end 0013cff8 Disabling SMM ASeg memory Asserting INIT. CPU #9 initialized Waiting for send to finish... +CPU: family 15, model 01, stepping 02 Deasserting INIT. Waiting for send to finish... +Enabling cache #startup loops: 1. Sending STARTUP #1 to 38. After apic_write. CPU: vendor AMD device 600f12 CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Startup point 1. Waiting for send to finish... +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e After Startup. CPU23: stack_base 0013b000, stack_end 0013bff8 nodeid = 01, coreid = 02 Asserting INIT. CPU: family 15, model 01, stepping 02 MTRR check Waiting for send to finish... +nodeid = 01, coreid = 05 Deasserting INIT. Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for send to finish... +Enabling cache #startup loops: 1. Setting up local APIC...Sending STARTUP #1 to 39. apic_id: 0x0c done. After apic_write. CPU model: AMD Opteron(TM) Processor 6276 Startup point 1. Waiting for send to finish... +siblings = 15, After Startup. CPU24: stack_base 0013a000, stack_end 0013aff8 Disabling SMM ASeg memory Asserting INIT. CPU #12 initialized Waiting for send to finish... + MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Deasserting INIT. Waiting for send to finish... Setting up local APIC...+ apic_id: 0x0d done. #startup loops: 1. Sending STARTUP #1 to 40. CPU model: AMD Opteron(TM) Processor 6276 After apic_write. siblings = 15, Startup point 1. Disabling SMM ASeg memory Waiting for send to finish... +CPU #13 initialized After Startup. CPU25: stack_base 00139000, stack_end 00139ff8 Initializing CPU #24 Asserting INIT. Waiting for send to finish... +Enabling cache Deasserting INIT. Waiting for send to finish... +CPU: vendor AMD device 600f12 #startup loops: 1. Sending STARTUP #1 to 41. After apic_write. Initializing CPU #11 Startup point 1. Waiting for send to finish... +CPU ID 0x80000001: 600f12 After Startup. CPU26: stack_base 00138000, stack_end 00138ff8 CPU: vendor AMD device 600f12 Asserting INIT. CPU: family 15, model 01, stepping 02 Waiting for send to finish... +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Deasserting INIT. Waiting for send to finish... +CPU: vendor AMD device 600f12 #startup loops: 1. Sending STARTUP #1 to 42. After apic_write. nodeid = 01, coreid = 03 Startup point 1. Waiting for send to finish... +Enabling cache After Startup. CPU27: stack_base 00137000, stack_end 00137ff8 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e Asserting INIT. Waiting for send to finish... +Initializing CPU #25 Deasserting INIT. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for send to finish... +Setting up local APIC...#startup loops: 1. Sending STARTUP #1 to 43. apic_id: 0x0a done. After apic_write. CPU model: AMD Opteron(TM) Processor 6276 Startup point 1. Waiting for send to finish... +siblings = 15, After Startup. Disabling SMM ASeg memory CPU28: stack_base 00136000, stack_end 00136ff8 MTRR check Fixed MTRRs : Enabled Asserting INIT. Variable MTRRs: Waiting for send to finish... +CPU #10 initialized Deasserting INIT. Enabled Waiting for send to finish... +Setting up local APIC...#startup loops: 1. apic_id: 0x0b done. Sending STARTUP #1 to 44. CPU model: AMD Opteron(TM) Processor 6276 After apic_write. siblings = 15, Startup point 1. Disabling SMM ASeg memory Waiting for send to finish... +CPU #11 initialized After Startup. CPU29: stack_base 00135000, stack_end 00135ff8 Initializing CPU #28 Asserting INIT. Waiting for send to finish... +Initializing CPU #15 Deasserting INIT. Waiting for send to finish... +CPU: vendor AMD device 600f12 #startup loops: 1. Sending STARTUP #1 to 45. After apic_write. CPU: vendor AMD device 600f12 Startup point 1. Waiting for send to finish... +CPU: family 15, model 01, stepping 02 After Startup. CPU30: stack_base 00134000, stack_end 00134ff8 nodeid = 03, coreid = 04 Asserting INIT. Waiting for send to finish... +Initializing CPU #20 Deasserting INIT. Waiting for send to finish... +Initializing CPU #17 #startup loops: 1. Sending STARTUP #1 to 46. After apic_write. Initializing CPU #26 Startup point 1. Waiting for send to finish... +Initializing CPU #23 After Startup. CPU31: stack_base 00133000, stack_end 00133ff8 CPU: family 15, model 01, stepping 02 Asserting INIT. Waiting for send to finish... +Initializing CPU #30 Deasserting INIT. Waiting for send to finish... +CPU: vendor AMD device 600f12 #startup loops: 1. Sending STARTUP #1 to 47. After apic_write. Initializing CPU #27 Startup point 1. Waiting for send to finish... +CPU: family 15, model 01, stepping 02 After Startup. Initializing CPU #0 CPU: vendor AMD device 600f12 CPU: family 15, model 01, stepping 02 Initializing CPU #21 nodeid = 00, coreid = 00 Enabling cache Initializing CPU #31 CPU: family 15, model 01, stepping 02 CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB CPU: vendor AMD device 600f12 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e CPU: family 15, model 01, stepping 02 Initializing CPU #22 Enabling cache Initializing CPU #14 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled nodeid = 02, coreid = 02 Initializing CPU #29 Setting up local APIC...CPU: vendor AMD device 600f12 CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB apic_id: 0x00 done. nodeid = 01, coreid = 07 CPU model: AMD Opteron(TM) Processor 6276 nodeid = 03, coreid = 00 siblings = 15, CPU: family 15, model 01, stepping 02 Disabling SMM ASeg memory nodeid = 03, coreid = 05 CPU #0 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Enabling cache MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e Setting up local APIC...CPU_CLUSTER: 0 init finished in 1251055 usecs apic_id: 0x01 done. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled PCI: 00:18.0 init ... CPU model: AMD Opteron(TM) Processor 6276 Setting up local APIC...siblings = 15, apic_id: 0x2c done. PCI: 00:18.0 init finished in 6960 usecs CPU model: AMD Opteron(TM) Processor 6276 PCI: 00:18.1 init ... Disabling SMM ASeg memory PCI: 00:18.1 init finished in 4132 usecs siblings = 15, PCI: 00:18.2 init ... CPU #1 initialized Disabling SMM ASeg memory PCI: 00:18.2 init finished in 2391 usecs CPU #28 initialized PCI: 00:18.3 init ... NB: Function 3 Misc Control.. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' Setting up local APIC...CBFS: Found @ offset 2b340 size dc4 apic_id: 0x2d done. TPM: pcr 3 measure ff02b478 @ 3524: CPU model: AMD Opteron(TM) Processor 6276 a1615718siblings = 15, de98Disabling SMM ASeg memory d6d6CPU #29 initialized 19812c6b9fd3c3f5177bc137 CPU: vendor AMD device 600f12 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Enabling cache done. PCI: 00:18.3 init finished in 45976 usecs CPU: vendor AMD device 600f12 PCI: 00:18.4 init ... NB: Function 4 Link Control.. Enabling cache CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CPU: family 15, model 01, stepping 02 CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB a1615718de98d6d619812c6b9fd3c3f5177bc137 nodeid = 03, coreid = 01 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Enabling cache CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB CPU: vendor AMD device 600f12 CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: CPU: family 15, model 01, stepping 02 CPU: family 15, model 01, stepping 02 a1615718de98d6d619812c6b9fd3c3f5177bc137 nodeid = 01, coreid = 06 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Initializing CPU #19 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e done. CPU: vendor AMD device 600f12 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e PCI: 00:18.4 init finished in 111725 usecs CPU: vendor AMD device 600f12 PCI: 00:18.5 init ... NB: Function 5 Northbridge Control.. Enabling cache MTRR check done. PCI: 00:18.5 init finished in 8090 usecs CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB PCI: 00:19.0 init ... nodeid = 02, coreid = 07 Fixed MTRRs : Enabled Variable MTRRs: Enabled PCI: 00:19.0 init finished in 7828 usecs MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e PCI: 00:19.1 init ... CPU: vendor AMD device 600f12 PCI: 00:19.1 init finished in 30366 usecs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled PCI: 00:19.2 init ... Setting up local APIC...PCI: 00:19.2 init finished in 5629 usecs Setting up local APIC...PCI: 00:19.3 init ... NB: Function 3 Misc Control.. apic_id: 0x0e done. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CPU model: AMD Opteron(TM) Processor 6276 CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: siblings = 15, Enabling cache a1615718de98d6d619812cDisabling SMM ASeg memory 6b9fd3c3f5177bc137 CPU #14 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Setting up local APIC...done. apic_id: 0x0f done. PCI: 00:19.3 init finished in 44157 usecs CPU model: AMD Opteron(TM) Processor 6276 apic_id: 0x28 done. siblings = 15, CPU model: AMD Opteron(TM) Processor 6276 PCI: 00:19.4 init ... NB: Function 4 Link Control.. Disabling SMM ASeg memory CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CPU #15 initialized siblings = 15, CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: Disabling SMM ASeg memory CPU: vendor AMD device 600f12 a1615718CPU #24 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled de98d6d619812c6b9fd3c3f5177bc137 Setting up local APIC...src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 apic_id: 0x29 done. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CPU model: AMD Opteron(TM) Processor 6276 CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: siblings = 15, CPU: vendor AMD device 600f12 a1615718de98d6d619812c6b9fd3c3Disabling SMM ASeg memory f5177bc137 CPU #25 initialized src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CPU: family 15, model 01, stepping 02 done. nodeid = 03, coreid = 07 PCI: 00:19.4 init finished in 86759 usecs CPU: family 15, model 01, stepping 02 PCI: 00:19.5 init ... NB: Function 5 Northbridge Control.. nodeid = 02, coreid = 03 done. Enabling cache PCI: 00:19.5 init finished in 8296 usecs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled PCI: 00:1a.0 init ... PCI: 00:1a.0 init finished in 5630 usecs Setting up local APIC...PCI: 00:1a.1 init ... apic_id: 0x22 done. PCI: 00:1a.1 init finished in 2951 usecs CPU model: AMD Opteron(TM) Processor 6276 PCI: 00:1a.2 init ... siblings = 15, PCI: 00:1a.2 init finished in 4134 usecs Disabling SMM ASeg memory PCI: 00:1a.3 init ... NB: Function 3 Misc Control.. MTRR check Fixed MTRRs : Enabled Variable MTRRs: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' Enabled CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: CPU #18 initialized Setting up local APIC...a1 apic_id: 0x23 done. 61CPU model: AMD Opteron(TM) Processor 6276 57siblings = 15, 18Disabling SMM ASeg memory deCPU #19 initialized 98d6d619812c6b9fd3c3f5177bc137 CPU: vendor AMD device 600f12 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Enabling cache done. PCI: 00:1a.3 init finished in 47665 usecs CPU: family 15, model 01, stepping 02 PCI: 00:1a.4 init ... NB: Function 4 Link Control.. nodeid = 02, coreid = 06 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' nodeid = 02, coreid = 04 CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: CPU: vendor AMD device 600f12 a1615718de98d6d619812c6b9fd3c3f5177bc137 Enabling cache src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: Setting up local APIC...CPU: family 15, model 01, stepping 02 a1 apic_id: 0x26 done. 61CPU model: AMD Opteron(TM) Processor 6276 57siblings = 15, 18de98d6d6Disabling SMM ASeg memory 19812c6b MTRR check 9fFixed MTRRs : Enabled Variable MTRRs: Enabled d3c3 f5177bc137 Enabling cache src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Setting up local APIC...CPU #22 initialized done. apic_id: 0x27 done. PCI: 00:1a.4 init finished in 118933 usecs CPU model: AMD Opteron(TM) Processor 6276 PCI: 00:1a.5 init ... NB: Function 5 Northbridge Control.. siblings = 15, done. Disabling SMM ASeg memory PCI: 00:1a.5 init finished in 7847 usecs CPU #23 initialized PCI: 00:1b.0 init ... CPU: family 15, model 01, stepping 02 PCI: 00:1b.0 init finished in 2764 usecs nodeid = 02, coreid = 05 PCI: 00:1b.1 init ... Enabling cache PCI: 00:1b.1 init finished in 3082 usecs CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB PCI: 00:1b.2 init ... PCI: 00:1b.2 init finished in 7822 usecs MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e PCI: 00:1b.3 init ... NB: Function 3 Misc Control.. nodeid = 02, coreid = 01 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CBFS: Found @ offset 2b340 size dc4 Setting up local APIC...TPM: pcr 3 measure ff02b478 @ 3524: apic_id: 0x24 done. CPU: family 15, model 01, stepping 02 a16157CPU model: AMD Opteron(TM) Processor 6276 18desiblings = 15, 98Disabling SMM ASeg memory d6d619812c MTRR check 6bCPU #20 initialized 9fFixed MTRRs : Enabled Variable MTRRs: Enabled d3c3f5177bc137 Enabling cache src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Setting up local APIC...done. apic_id: 0x25 done. PCI: 00:1b.3 init finished in 81352 usecs CPU model: AMD Opteron(TM) Processor 6276 PCI: 00:1b.4 init ... siblings = 15, NB: Function 4 Link Control.. Disabling SMM ASeg memory CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CPU #21 initialized CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: CPU: family 15, model 01, stepping 02 a1615718de98d6d619812c6b9fd3c3f5177bc137 nodeid = 03, coreid = 03 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CPU: family 15, model 01, stepping 02 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' nodeid = 03, coreid = 06 CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: nodeid = 03, coreid = 02 a1615718de98d6d619812c6b9fd3c3f5177bc137 Enabling cache src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Enabling cache done. PCI: 00:1b.4 init finished in 70527 usecs CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB PCI: 00:1b.5 init ... NB: Function 5 Northbridge Control.. MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e done. PCI: 00:1b.5 init finished in 39505 usecs CPU: family 15, model 01, stepping 02 PCI: 00:00.0 init ... pcie_init in sr5650_ht.c MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled IOAPIC: Initializing IOAPIC at 0xfcc00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x01 Setting up local APIC...IOAPIC: Dumping registers apic_id: 0x2e done. reg 0x0000: 0x01000000 CPU model: AMD Opteron(TM) Processor 6276 reg 0x0001: 0x001f8021 siblings = 15, reg 0x0002: 0x00000000 Disabling SMM ASeg memory IOAPIC: 32 interrupts CPU #30 initialized IOAPIC: Enabling interrupts on FSB MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 Setting up local APIC...IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 apic_id: 0x2f done. IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 CPU model: AMD Opteron(TM) Processor 6276 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 siblings = 15, IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 Disabling SMM ASeg memory IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 CPU #31 initialized IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:00.0 init finished in 154185 usecs nodeid = 02, coreid = 00 PCI: 00:11.0 init ... Enabling cache CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB CBFS: Found @ offset 2b340 size dc4 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e TPM: pcr 3 measure ff02b478 @ 3524: Enabling cache Enabling cache a1615718 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB deSetting up local APIC...MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e apic_id: 0x20 done. 98CPU model: AMD Opteron(TM) Processor 6276 d6siblings = 15, d6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling SMM ASeg memory 19Setting up local APIC... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled apic_id: 0x2a done. 81CPU model: AMD Opteron(TM) Processor 6276 Setting up local APIC...CPU #16 initialized apic_id: 0x21 done. siblings = 15, CPU model: AMD Opteron(TM) Processor 6276 Disabling SMM ASeg memory siblings = 15, CPU #26 initialized Disabling SMM ASeg memory MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU #17 initialized 2c6bSetting up local APIC...9f apic_id: 0x2b done. d3CPU model: AMD Opteron(TM) Processor 6276 c3siblings = 15, f5Disabling SMM ASeg memory 17CPU #27 initialized 7bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 rev_id=15 sata_bar0=4020 sata_bar1=4040 sata_bar2=4028 sata_bar3=4044 sata_bar4=4000 sata_bar5=fcb0d000 ide_bar0=4030 ide_bar1=4048 ide_bar2=4038 ide_bar3=404c Maximum SATA port count supported by silicon: 6 SATA port 0 status = 0 No AHCI SATA drive on Slot0 SATA port 1 status = 0 No AHCI SATA drive on Slot1 SATA port 2 status = 0 No AHCI SATA drive on Slot2 SATA port 3 status = 23 drive detection done after 0 ms AHCI device 3 is ready after 1 tries SATA port 4 status = 0 No AHCI SATA drive on Slot4 SATA port 5 status = 0 No AHCI SATA drive on Slot5 PCI: 00:11.0 init finished in 227414 usecs PCI: 00:12.0 init ... PCI: 00:12.0 init finished in 1466 usecs PCI: 00:12.1 init ... PCI: 00:12.1 init finished in 1465 usecs PCI: 00:12.2 init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 usb2_bar0=0xfcb0e000 rpr 6.23, final dword=849e03c8 PCI: 00:12.2 init finished in 30927 usecs PCI: 00:13.0 init ... PCI: 00:13.0 init finished in 1466 usecs PCI: 00:13.1 init ... PCI: 00:13.1 init finished in 1465 usecs PCI: 00:13.2 init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 usb2_bar0=0xfcb0f000 rpr 6.23, final dword=849e03c8 PCI: 00:13.2 init finished in 30926 usecs PCI: 00:14.0 init ... sm_init(). IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: Dumping registers reg 0x0000: 0x00000000 reg 0x0001: 0x00178021 reg 0x0002: 0x00000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 WARNING: No CMOS option 'enable_legacy_usb'. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 set power "on" after power fail CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 ++++++++++no set NMI+++++ RTC Init sm_init() end PCI: 00:14.0 init finished in 182483 usecs PCI: 00:14.1 init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 PCI: 00:14.1 init finished in 27455 usecs PCI: 00:14.2 init ... base = 0xfcb04000 No codec! PCI: 00:14.2 init finished in 6222 usecs PCI: 00:14.3 init ... lpc_init PCI: 00:14.3 init finished in 2101 usecs PCI: 00:14.4 init ... PCI: 00:14.4 init finished in 1460 usecs PCI: 00:14.5 init ... PCI: 00:14.5 init finished in 1465 usecs PCI: 03:00.0 init ... PCI: 03:00.0 init finished in 1444 usecs PCI: 04:00.0 init ... PCI: 04:00.0 init finished in 1444 usecs smbus: PCI: 00:14.0[0]->I2C: 01:2f init ... Set SMBUS controller to channel 1 Found 64 pin W83795G Nuvoton H/W Monitor W83795G/ADG work in Thermal Cruise Mode Fan CTFS(celsius) TTTI(celsius) 1 80 80 2 80 80 3 80 80 4 80 80 5 80 80 6 80 80 DTS1 current value: 24 DTS2 current value: 31 DTS3 current value: 0 DTS4 current value: 0 DTS5 current value: 0 DTS6 current value: 0 DTS7 current value: 0 DTS8 current value: 0 Set SMBUS controller to channel 0 I2C: 01:2f init finished in 280413 usecs PNP: 002e.2 init ... PNP: 002e.2 init finished in 1380 usecs PNP: 002e.3 init ... PNP: 002e.3 init finished in 1382 usecs PNP: 002e.5 init ... w83667hg_a_init: Disable mouse controller.PNP: 002e.5 init finished in 4025 usecs PNP: 002e.a init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 set power on after power fail PNP: 002e.a init finished in 29191 usecs PNP: 002e.b init ... PNP: 002e.b init finished in 1382 usecs PCI: 08:01.0 init ... ASpeed AST2050: initializing video device ast_detect_chip: AST 1100 detected ast_detect_chip: VGA not enabled on entry, requesting chip POST ast_detect_chip: Analog VGA only ast_driver_load: dram -1974967296 0 32 00800000 ASpeed VGA text mode initialized PCI: 08:01.0 init finished in 33184 usecs PCI: 08:02.0 init ... PCI: 08:02.0 init finished in 1444 usecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:00.2: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 01:50: enabled 1 I2C: 01:51: enabled 1 I2C: 01:52: enabled 1 I2C: 01:53: enabled 1 I2C: 01:54: enabled 1 I2C: 01:55: enabled 1 I2C: 01:56: enabled 1 I2C: 01:57: enabled 1 I2C: 01:2f: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.106: enabled 0 PNP: 002e.107: enabled 0 PNP: 002e.207: enabled 0 PNP: 002e.307: enabled 0 PNP: 002e.407: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.108: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.109: enabled 0 PNP: 002e.209: enabled 0 PNP: 002e.309: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PNP: 002e.c: enabled 0 PNP: 002e.d: enabled 0 PNP: 002e.f: enabled 0 PNP: 004e.0: enabled 1 PCI: 00:14.4: enabled 1 PCI: 08:01.0: enabled 1 PCI: 08:02.0: enabled 1 PCI: 08:03.0: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 1 PCI: 00:19.3: enabled 1 PCI: 00:19.4: enabled 1 PCI: 00:19.5: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1a.1: enabled 1 PCI: 00:1a.2: enabled 1 PCI: 00:1a.3: enabled 1 PCI: 00:1a.4: enabled 1 PCI: 00:1a.5: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1b.1: enabled 1 PCI: 00:1b.2: enabled 1 PCI: 00:1b.3: enabled 1 PCI: 00:1b.4: enabled 1 PCI: 00:1b.5: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 05: enabled 1 APIC: 06: enabled 1 APIC: 07: enabled 1 APIC: 08: enabled 1 APIC: 09: enabled 1 APIC: 0a: enabled 1 APIC: 0b: enabled 1 APIC: 0c: enabled 1 APIC: 0d: enabled 1 APIC: 0e: enabled 1 APIC: 0f: enabled 1 APIC: 20: enabled 1 APIC: 21: enabled 1 APIC: 22: enabled 1 APIC: 23: enabled 1 APIC: 24: enabled 1 APIC: 25: enabled 1 APIC: 26: enabled 1 APIC: 27: enabled 1 APIC: 28: enabled 1 APIC: 29: enabled 1 APIC: 2a: enabled 1 APIC: 2b: enabled 1 APIC: 2c: enabled 1 APIC: 2d: enabled 1 APIC: 2e: enabled 1 APIC: 2f: enabled 1 PCI: 03:00.0: enabled 1 PCI: 04:00.0: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 3454717 exit 0 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 2516 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Writing IRQ routing tables to 0xf0000...done. Writing IRQ routing tables to 0xb7cbf000...done. PIRQ table: 48 bytes. Wrote the mp table end at: 000f0410 - 000f08ac Wrote the mp table end at: b7cbe010 - b7cbe4ac MP table: 1196 bytes. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 2c140 size 26a7 TPM: pcr 3 measure ff02c288 @ 9895: 46ab2e6a4c2f0da4d54a8051a31cbc14359654ce src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at b7c9a000. ACPI: * FACS ACPI: * DSDT ACPI: * FADT pm_base: 0x0800 ACPI: added table 1/32, length now 40 ACPI: * SSDT CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 processor_brand=AMD Opteron(TM) Processor 6276 Pstates algorithm ... Pstate_freq[0] = 2300MHz Pstate_power[0] = 6195mw Pstate_latency[0] = 5us Pstate_freq[1] = 2100MHz Pstate_power[1] = 5535mw Pstate_latency[1] = 5us Pstate_freq[2] = 1800MHz Pstate_power[2] = 4641mw Pstate_latency[2] = 5us Pstate_freq[3] = 1600MHz Pstate_power[3] = 4042mw Pstate_latency[3] = 5us Pstate_freq[4] = 1400MHz Pstate_power[4] = 3422mw Pstate_latency[4] = 5us PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 PSS: 2300MHz power 6195 control 0x0 status 0x0 PSS: 2100MHz power 5535 control 0x1 status 0x1 PSS: 1800MHz power 4641 control 0x2 status 0x2 PSS: 1600MHz power 4042 control 0x3 status 0x3 PSS: 1400MHz power 3422 control 0x4 status 0x4 \_SB.PCI0.LPC.TPM: LPC TPM PNP: 004e.0 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TCPA TCPA log created at b7c8a000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = b7ca0600 ACPI: * SRAT at b7ca0600 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f SRAT: lapic cpu_index=10, node_id=02, apic_id=20 SRAT: lapic cpu_index=11, node_id=02, apic_id=21 SRAT: lapic cpu_index=12, node_id=02, apic_id=22 SRAT: lapic cpu_index=13, node_id=02, apic_id=23 SRAT: lapic cpu_index=14, node_id=02, apic_id=24 SRAT: lapic cpu_index=15, node_id=02, apic_id=25 SRAT: lapic cpu_index=16, node_id=02, apic_id=26 SRAT: lapic cpu_index=17, node_id=02, apic_id=27 SRAT: lapic cpu_index=18, node_id=03, apic_id=28 SRAT: lapic cpu_index=19, node_id=03, apic_id=29 SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000 set_srat_mem: dev DOMAIN: 0000, res->index=0042 startk=01100000, sizek=01000000 ACPI: added table 6/32, length now 60 ACPI: * SLIT at b7ca08d0 ACPI: added table 7/32, length now 64 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 ACPI: * IVRS at b7ca0910 Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0x40 Capability: type 0x01 @ 0x44 ACPI: added table 8/32, length now 68 ACPI: * HPET ACPI: added table 9/32, length now 72 ACPI: * SRAT at b7ca0a00 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f SRAT: lapic cpu_index=10, node_id=02, apic_id=20 SRAT: lapic cpu_index=11, node_id=02, apic_id=21 SRAT: lapic cpu_index=12, node_id=02, apic_id=22 SRAT: lapic cpu_index=13, node_id=02, apic_id=23 SRAT: lapic cpu_index=14, node_id=02, apic_id=24 SRAT: lapic cpu_index=15, node_id=02, apic_id=25 SRAT: lapic cpu_index=16, node_id=02, apic_id=26 SRAT: lapic cpu_index=17, node_id=02, apic_id=27 SRAT: lapic cpu_index=18, node_id=03, apic_id=28 SRAT: lapic cpu_index=19, node_id=03, apic_id=29 SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000 set_srat_mem: dev DOMAIN: 0000, res->index=0042 startk=01100000, sizek=01000000 ACPI: added table 10/32, length now 76 ACPI: * SLIT at b7ca0cd0 ACPI: added table 11/32, length now 80 ACPI: * SRAT at b7ca0d10 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f SRAT: lapic cpu_index=10, node_id=02, apic_id=20 SRAT: lapic cpu_index=11, node_id=02, apic_id=21 SRAT: lapic cpu_index=12, node_id=02, apic_id=22 SRAT: lapic cpu_index=13, node_id=02, apic_id=23 SRAT: lapic cpu_index=14, node_id=02, apic_id=24 SRAT: lapic cpu_index=15, node_id=02, apic_id=25 SRAT: lapic cpu_index=16, node_id=02, apic_id=26 SRAT: lapic cpu_index=17, node_id=02, apic_id=27 SRAT: lapic cpu_index=18, node_id=03, apic_id=28 SRAT: lapic cpu_index=19, node_id=03, apic_id=29 SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000 set_srat_mem: dev DOMAIN: 0000, res->index=0042 startk=01100000, sizek=01000000 ACPI: added table 12/32, length now 84 ACPI: * SLIT at b7ca0fe0 ACPI: added table 13/32, length now 88 ACPI: * SRAT at b7ca1020 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f SRAT: lapic cpu_index=10, node_id=02, apic_id=20 SRAT: lapic cpu_index=11, node_id=02, apic_id=21 SRAT: lapic cpu_index=12, node_id=02, apic_id=22 SRAT: lapic cpu_index=13, node_id=02, apic_id=23 SRAT: lapic cpu_index=14, node_id=02, apic_id=24 SRAT: lapic cpu_index=15, node_id=02, apic_id=25 SRAT: lapic cpu_index=16, node_id=02, apic_id=26 SRAT: lapic cpu_index=17, node_id=02, apic_id=27 SRAT: lapic cpu_index=18, node_id=03, apic_id=28 SRAT: lapic cpu_index=19, node_id=03, apic_id=29 SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000 set_srat_mem: dev DOMAIN: 0000, res->index=0042 startk=01100000, sizek=01000000 ACPI: added table 14/32, length now 92 ACPI: * SLIT at b7ca12f0 ACPI: added table 15/32, length now 96 ACPI: done. ACPI tables: 29488 bytes. smbios_write_tables: b7c89000 Root Device (ASUS KGPE-D16) CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex) APIC: 00 (unknown) DOMAIN: 0000 (AMD Family 10h/15h Root Complex) PCI: 00:18.0 (AMD Family 10h/15h Northbridge) PCI: 00:00.0 (ATI SR5650) PCI: 00:00.1 (ATI SR5650) PCI: 00:00.2 (ATI SR5650) PCI: 00:02.0 (ATI SR5650) PCI: 00:03.0 (ATI SR5650) PCI: 00:04.0 (ATI SR5650) PCI: 00:05.0 (ATI SR5650) PCI: 00:06.0 (ATI SR5650) PCI: 00:07.0 (ATI SR5650) PCI: 00:08.0 (ATI SR5650) PCI: 00:09.0 (ATI SR5650) PCI: 00:0a.0 (ATI SR5650) PCI: 00:0b.0 (ATI SR5650) PCI: 00:0c.0 (ATI SR5650) PCI: 00:0d.0 (ATI SR5650) PCI: 00:11.0 (ATI SP5100) PCI: 00:12.0 (ATI SP5100) PCI: 00:12.1 (ATI SP5100) PCI: 00:12.2 (ATI SP5100) PCI: 00:13.0 (ATI SP5100) PCI: 00:13.1 (ATI SP5100) PCI: 00:13.2 (ATI SP5100) PCI: 00:14.0 (ATI SP5100) I2C: 01:50 (unknown) I2C: 01:51 (unknown) I2C: 01:52 (unknown) I2C: 01:53 (unknown) I2C: 01:54 (unknown) I2C: 01:55 (unknown) I2C: 01:56 (unknown) I2C: 01:57 (unknown) I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor) PCI: 00:14.1 (ATI SP5100) PCI: 00:14.2 (ATI SP5100) PCI: 00:14.3 (ATI SP5100) PNP: 002e.0 (WINBOND W83667HG-A Super I/O) PNP: 002e.1 (WINBOND W83667HG-A Super I/O) PNP: 002e.2 (WINBOND W83667HG-A Super I/O) PNP: 002e.3 (WINBOND W83667HG-A Super I/O) PNP: 002e.5 (WINBOND W83667HG-A Super I/O) PNP: 002e.106 (WINBOND W83667HG-A Super I/O) PNP: 002e.107 (WINBOND W83667HG-A Super I/O) PNP: 002e.207 (WINBOND W83667HG-A Super I/O) PNP: 002e.307 (WINBOND W83667HG-A Super I/O) PNP: 002e.407 (WINBOND W83667HG-A Super I/O) PNP: 002e.8 (WINBOND W83667HG-A Super I/O) PNP: 002e.108 (WINBOND W83667HG-A Super I/O) PNP: 002e.9 (WINBOND W83667HG-A Super I/O) PNP: 002e.109 (WINBOND W83667HG-A Super I/O) PNP: 002e.209 (WINBOND W83667HG-A Super I/O) PNP: 002e.309 (WINBOND W83667HG-A Super I/O) PNP: 002e.a (WINBOND W83667HG-A Super I/O) PNP: 002e.b (WINBOND W83667HG-A Super I/O) PNP: 002e.c (WINBOND W83667HG-A Super I/O) PNP: 002e.d (WINBOND W83667HG-A Super I/O) PNP: 002e.f (WINBOND W83667HG-A Super I/O) PNP: 004e.0 (LPC TPM) PCI: 00:14.4 (ATI SP5100) PCI: 08:01.0 (ATI SP5100) PCI: 08:02.0 (ATI SP5100) PCI: 08:03.0 (ATI SP5100) PCI: 00:14.5 (ATI SP5100) PCI: 00:18.1 (AMD Family 10h/15h Northbridge) PCI: 00:18.2 (AMD Family 10h/15h Northbridge) PCI: 00:18.3 (AMD Family 10h/15h Northbridge) PCI: 00:18.4 (AMD Family 10h/15h Northbridge) PCI: 00:18.5 (AMD Family 10h/15h Northbridge) PCI: 00:19.0 (AMD Family 10h/15h Northbridge) PCI: 00:19.1 (AMD Family 10h/15h Northbridge) PCI: 00:19.2 (AMD Family 10h/15h Northbridge) PCI: 00:19.3 (AMD Family 10h/15h Northbridge) PCI: 00:19.4 (AMD Family 10h/15h Northbridge) PCI: 00:19.5 (AMD Family 10h/15h Northbridge) PCI: 00:1a.0 (AMD Family 10h/15h Northbridge) PCI: 00:1a.1 (AMD Family 10h/15h Northbridge) PCI: 00:1a.2 (AMD Family 10h/15h Northbridge) PCI: 00:1a.3 (AMD Family 10h/15h Northbridge) PCI: 00:1a.4 (AMD Family 10h/15h Northbridge) PCI: 00:1a.5 (AMD Family 10h/15h Northbridge) PCI: 00:1b.0 (AMD Family 10h/15h Northbridge) PCI: 00:1b.1 (AMD Family 10h/15h Northbridge) PCI: 00:1b.2 (AMD Family 10h/15h Northbridge) PCI: 00:1b.3 (AMD Family 10h/15h Northbridge) PCI: 00:1b.4 (AMD Family 10h/15h Northbridge) PCI: 00:1b.5 (AMD Family 10h/15h Northbridge) APIC: 01 (unknown) APIC: 02 (unknown) APIC: 03 (unknown) APIC: 04 (unknown) APIC: 05 (unknown) APIC: 06 (unknown) APIC: 07 (unknown) APIC: 08 (unknown) APIC: 09 (unknown) APIC: 0a (unknown) APIC: 0b (unknown) APIC: 0c (unknown) APIC: 0d (unknown) APIC: 0e (unknown) APIC: 0f (unknown) APIC: 20 (unknown) APIC: 21 (unknown) APIC: 22 (unknown) APIC: 23 (unknown) APIC: 24 (unknown) APIC: 25 (unknown) APIC: 26 (unknown) APIC: 27 (unknown) APIC: 28 (unknown) APIC: 29 (unknown) APIC: 2a (unknown) APIC: 2b (unknown) APIC: 2c (unknown) APIC: 2d (unknown) APIC: 2e (unknown) APIC: 2f (unknown) PCI: 03:00.0 (unknown) PCI: 04:00.0 (unknown) SMBIOS tables: 519 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4812 Writing coreboot table at 0xb7cc0000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000bffff: RESERVED 3. 00000000000c0000-00000000b7c88fff: RAM 4. 00000000b7c89000-00000000b7ffffff: CONFIGURATION TABLES 5. 00000000b8000000-00000000bfffffff: RAM 6. 00000000c0000000-00000000cfffffff: RESERVED 7. 00000000fcb00000-00000000fcb03fff: RESERVED 8. 00000000feb00000-00000000feb00fff: RESERVED 9. 00000000fec00000-00000000fec00fff: RESERVED 10. 00000000fed00000-00000000fed00fff: RESERVED 11. 00000000fed40000-00000000fed44fff: RESERVED 12. 0000000100000000-0000000837ffffff: RAM 13. 0000000838000000-000000083fffffff: RESERVED Manufacturer: ef SF: Detected W25Q128 with sector size 0x1000, total 0x1000000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = ff000000 size = 1000000 #areas = 3 Wrote coreboot table at: b7cc0000, 0x1140 bytes, checksum 646c coreboot table: 4440 bytes. IMD ROOT 0. b7fff000 00001000 IMD SMALL 1. b7ffe000 00001000 CAR GLOBALS 2. b7ff3000 0000a6c0 CONSOLE 3. b7fd3000 00020000 AMDMEM INFO 4. b7fc9000 000093fc ACPI RESUME 5. b7cc8000 00301000 COREBOOT 6. b7cc0000 00008000 IRQ TABLE 7. b7cbf000 00001000 SMP TABLE 8. b7cbe000 00001000 ACPI 9. b7c9a000 00024000 TCPA LOG 10. b7c8a000 00010000 SMBIOS 11. b7c89000 00000800 IMD small region: IMD ROOT 0. b7ffec00 00000400 ROMSTAGE 1. b7ffebe0 00000004 GDT 2. b7ffe9e0 00000200 COREBOOTFWD 3. b7ffe9a0 00000028 Writing AMD DCT configuration to Flash CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 Manufacturer: ef SF: Detected W25Q128 with sector size 0x1000, total 0x1000000 SF: Successfully erased 32768 bytes @ 0x38000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2b340 size dc4 TPM: pcr 3 measure ff02b478 @ 3524: a1615718de98d6d619812c6b9fd3c3f5177bc137 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 BS: BS_WRITE_TABLES times (us): entry 0 run 2707014 exit 0 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 55680 size 57a16f Loading segment from ROM address 0xff0557b8 data (compression=0) New segment dstaddr 0x90000 memsize 0x1080 srcaddr 0xff055860 filesize 0x1080 Loading segment from ROM address 0xff0557d4 code (compression=0) New segment dstaddr 0x1000000 memsize 0x23e700 srcaddr 0xff0568e0 filesize 0x23e700 Loading segment from ROM address 0xff0557f0 code (compression=0) New segment dstaddr 0x40000 memsize 0xb1 srcaddr 0xff294fe0 filesize 0xb1 Loading segment from ROM address 0xff05580c data (compression=0) New segment dstaddr 0x91000 memsize 0x6 srcaddr 0xff295091 filesize 0x6 Loading segment from ROM address 0xff055828 data (compression=0) New segment dstaddr 0x4000000 memsize 0x33a890 srcaddr 0xff295097 filesize 0x33a890 Loading segment from ROM address 0xff055844 Entry Point 0x00040000 Bounce Buffer at bfdcf000, 2294304 bytes Loading Segment: addr: 0x0000000000090000 memsz: 0x0000000000001080 filesz: 0x0000000000001080 lb: [0x0000000000100000, 0x0000000000218110) Post relocation: addr: 0x0000000000090000 memsz: 0x0000000000001080 filesz: 0x0000000000001080 it's not compressed! [ 0x00090000, 00091080, 0x00091080) <- ff055860 dest 00090000, end 00091080, bouncebuffer bfdcf000 TPM: pcr 3 measure 00090000 @ 4224: 29740f0a34968f2e067bd77c847da3348848eb1a src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Loading Segment: addr: 0x0000000001000000 memsz: 0x000000000023e700 filesz: 0x000000000023e700 lb: [0x0000000000100000, 0x0000000000218110) Post relocation: addr: 0x0000000001000000 memsz: 0x000000000023e700 filesz: 0x000000000023e700 it's not compressed! [ 0x01000000, 0123e700, 0x0123e700) <- ff0568e0 dest 01000000, end 0123e700, bouncebuffer bfdcf000 TPM: pcr 3 measure 01000000 @ 2352896: 7900ab2bccfea1b0f1690e77874ac58e7c7ecc65 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Loading Segment: addr: 0x0000000000040000 memsz: 0x00000000000000b1 filesz: 0x00000000000000b1 lb: [0x0000000000100000, 0x0000000000218110) Post relocation: addr: 0x0000000000040000 memsz: 0x00000000000000b1 filesz: 0x00000000000000b1 it's not compressed! [ 0x00040000, 000400b1, 0x000400b1) <- ff294fe0 dest 00040000, end 000400b1, bouncebuffer bfdcf000 TPM: pcr 3 measure 00040000 @ 177: 42b5a23aae79b2f57de55635d5436d1f81713afa src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Loading Segment: addr: 0x0000000000091000 memsz: 0x0000000000000006 filesz: 0x0000000000000006 lb: [0x0000000000100000, 0x0000000000218110) Post relocation: addr: 0x0000000000091000 memsz: 0x0000000000000006 filesz: 0x0000000000000006 it's not compressed! [ 0x00091000, 00091006, 0x00091006) <- ff295091 dest 00091000, end 00091006, bouncebuffer bfdcf000 TPM: pcr 3 measure 00091000 @ 6: 7f3eb55225581465e1b6179c9616d5cedaf1e411 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Loading Segment: addr: 0x0000000004000000 memsz: 0x000000000033a890 filesz: 0x000000000033a890 lb: [0x0000000000100000, 0x0000000000218110) Post relocation: addr: 0x0000000004000000 memsz: 0x000000000033a890 filesz: 0x000000000033a890 it's not compressed! [ 0x04000000, 0433a890, 0x0433a890) <- ff295097 dest 04000000, end 0433a890, bouncebuffer bfdcf000 TPM: pcr 3 measure 04000000 @ 3385488: 950228d0bedcb74b5f594c15f5b8b5cdba552a17 src/drivers/pc80/tpm/tpm.c:514 unexpected TPM status 0xff src/drivers/pc80/tpm/tpm.c:702 failed sending data to TPM TPM: command 0x14 send/receive failed: 0x10000001 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 2610152 exit 0 Jumping to boot code at 00040000(b7cc0000) CPU0: stack: 00152000 - 00153000, lowest used address 0015294c, stack used: 1716 bytes entry = 0x00040000 lb_start = 0x00100000 lb_size = 0x00118110 buffer = 0xbfdcf000