diff --git a/asm/inline.rs b/asm/inline.rs
index 9150c9c3..5e2fbc10 100644
--- a/asm/inline.rs
+++ b/asm/inline.rs
@@ -52,13 +52,16 @@ pub unsafe fn __cpsie() {
 
 #[inline(always)]
 pub unsafe fn __delay(cyc: u32) {
-    // Use local labels to avoid R_ARM_THM_JUMP8 relocations which fail on thumbv6m.
+    // The loop will normally take 3 to 4 CPU cycles per iteration, but superscalar cores
+    // (eg. Cortex-M7) can potentially do it in 2, so we use that as the lower bound, since delaying
+    // for more cycles is okay.
+    let real_cyc = cyc / 2;
     asm!(
+        // Use local labels to avoid R_ARM_THM_JUMP8 relocations which fail on thumbv6m.
         "1:",
-        "nop",
         "subs {}, #1",
         "bne 1b",
-        in(reg) cyc
+        in(reg) real_cyc
     );
 }
 
diff --git a/bin/thumbv6m-none-eabi-lto.a b/bin/thumbv6m-none-eabi-lto.a
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diff --git a/bin/thumbv8m.main-none-eabi-lto.a b/bin/thumbv8m.main-none-eabi-lto.a
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diff --git a/bin/thumbv8m.main-none-eabihf-lto.a b/bin/thumbv8m.main-none-eabihf-lto.a
index cc627612..30c6ccc2 100644
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diff --git a/src/asm.rs b/src/asm.rs
index 297198b9..4dc1ab07 100644
--- a/src/asm.rs
+++ b/src/asm.rs
@@ -15,7 +15,7 @@ pub fn bkpt() {
     call_asm!(__bkpt());
 }
 
-/// Blocks the program for *at least* `n` instruction cycles
+/// Blocks the program for *at least* `cycles` CPU cycles.
 ///
 /// This is implemented in assembly so its execution time is independent of the optimization
 /// level, however it is dependent on the specific architecture and core configuration.
@@ -25,10 +25,8 @@ pub fn bkpt() {
 /// timer-less initialization of peripherals if and only if accurate timing is not essential. In
 /// any other case please use a more accurate method to produce a delay.
 #[inline]
-pub fn delay(n: u32) {
-    // NOTE(divide by 4) is easier to compute than `/ 3` because it's just a shift (`>> 2`).
-    let real_cyc = n / 4 + 1;
-    call_asm!(__delay(real_cyc: u32));
+pub fn delay(cycles: u32) {
+    call_asm!(__delay(cycles: u32));
 }
 
 /// A no-operation. Useful to prevent delay loops from being optimized away.