From c1b31afeeb14e00dc96bea88177c3bacd4715932 Mon Sep 17 00:00:00 2001 From: Ciara Loftus Date: Tue, 14 Oct 2025 08:45:12 +0000 Subject: [PATCH 1/6] net/intel: fix Rx vector capability detection The common function for detecting whether an rxq could use a vector rx path would automatically disqualify rx queues that had the timestamp offload enabled. This was incorrect behaviour because the iavf driver which uses this common function supports timestamp offload on its vector paths. Fix this by removing the conditional check for timestamp offload. Fixes: 9eb60580d155 ("net/intel: extract common Rx vector criteria") Cc: stable@dpdk.org Signed-off-by: Ciara Loftus Signed-off-by: 0-day Robot --- drivers/net/intel/common/rx.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/intel/common/rx.h b/drivers/net/intel/common/rx.h index 741808f5735..d3e4492ff17 100644 --- a/drivers/net/intel/common/rx.h +++ b/drivers/net/intel/common/rx.h @@ -235,9 +235,8 @@ ci_rxq_vec_capable(uint16_t nb_desc, uint16_t rx_free_thresh, uint64_t offloads) (nb_desc % rx_free_thresh) != 0) return false; - /* no driver supports timestamping or buffer split on vector path */ - if ((offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || - (offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT)) + /* no driver supports buffer split on vector path */ + if (offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) return false; return true; From c77993d4bed97bc40b9b2030deee362c0f653232 Mon Sep 17 00:00:00 2001 From: Ciara Loftus Date: Tue, 14 Oct 2025 08:45:13 +0000 Subject: [PATCH 2/6] net/iavf: fix Rx paths feature definitions Two rx paths had incorrect feature and offload definitions which led to incorrect path selections. Fix these. Remove timestamp offload from the list of offloads supported by paths that use the flexible rx descriptor. It is only available in the "offload" versions of those paths. Fixes: 91e3205d72d8 ("net/iavf: use common Rx path selection infrastructure") Cc: stable@dpdk.org Signed-off-by: Ciara Loftus Signed-off-by: 0-day Robot --- drivers/net/intel/iavf/iavf_rxtx.c | 5 +++-- drivers/net/intel/iavf/iavf_rxtx.h | 1 - 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/intel/iavf/iavf_rxtx.c b/drivers/net/intel/iavf/iavf_rxtx.c index 775fb4a66f4..67c73f9ad6f 100644 --- a/drivers/net/intel/iavf/iavf_rxtx.c +++ b/drivers/net/intel/iavf/iavf_rxtx.c @@ -3768,13 +3768,14 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = { {.scattered = true, .flex_desc = true, .bulk_alloc = true}}}, [IAVF_RX_AVX2_FLEX_RXD_OFFLOAD] = { iavf_recv_pkts_vec_avx2_flex_rxd_offload, "Vector AVX2 Flex Offload", - {IAVF_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256, + {IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS, RTE_VECT_SIMD_256, {.flex_desc = true, .bulk_alloc = true}}}, [IAVF_RX_AVX2_SCATTERED_FLEX_RXD_OFFLOAD] = { iavf_recv_scattered_pkts_vec_avx2_flex_rxd_offload, "Vector Scattered AVX2 Flex Offload", {IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, - RTE_VECT_SIMD_256, {.flex_desc = true, .bulk_alloc = true}}}, + RTE_VECT_SIMD_256, + {.scattered = true, .flex_desc = true, .bulk_alloc = true}}}, #ifdef CC_AVX512_SUPPORT [IAVF_RX_AVX512] = {iavf_recv_pkts_vec_avx512, "Vector AVX512", {IAVF_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512, {.bulk_alloc = true}}}, diff --git a/drivers/net/intel/iavf/iavf_rxtx.h b/drivers/net/intel/iavf/iavf_rxtx.h index 3f461efb288..44be29caf6c 100644 --- a/drivers/net/intel/iavf/iavf_rxtx.h +++ b/drivers/net/intel/iavf/iavf_rxtx.h @@ -83,7 +83,6 @@ /* vector paths that use the flex rx desc */ #define IAVF_RX_VECTOR_FLEX_OFFLOADS ( \ IAVF_RX_VECTOR_OFFLOADS | \ - RTE_ETH_RX_OFFLOAD_TIMESTAMP | \ RTE_ETH_RX_OFFLOAD_SECURITY) /* vector offload paths */ #define IAVF_RX_VECTOR_OFFLOAD_OFFLOADS ( \ From 89ef14b337fe9627806306e7d87dc759237f8a23 Mon Sep 17 00:00:00 2001 From: Ciara Loftus Date: Tue, 14 Oct 2025 08:45:14 +0000 Subject: [PATCH 3/6] net/iavf: fix Rx path selection for scalar flex bulk alloc The scalar bulk alloc rx burst function supports both legacy and flexible rx descriptors. The rx path selection infrastructure introduced in commit 91e3205d72d8 ("net/iavf: use common Rx path selection infrastructure") cannot define a path that supports both descriptor formats. To solve this problem, have two rx path definitions which both point to the same rx burst function but report different descriptor formats. This allows the rx path selection function to choose the correct path. Fixes: 91e3205d72d8 ("net/iavf: use common Rx path selection infrastructure") Cc: stable@dpdk.org Signed-off-by: Ciara Loftus Signed-off-by: 0-day Robot --- drivers/net/intel/iavf/iavf.h | 1 + drivers/net/intel/iavf/iavf_rxtx.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/net/intel/iavf/iavf.h b/drivers/net/intel/iavf/iavf.h index 435902fbc27..4e76162337b 100644 --- a/drivers/net/intel/iavf/iavf.h +++ b/drivers/net/intel/iavf/iavf.h @@ -327,6 +327,7 @@ enum iavf_rx_func_type { IAVF_RX_FLEX_RXD, IAVF_RX_SCATTERED_FLEX_RXD, IAVF_RX_BULK_ALLOC, + IAVF_RX_BULK_ALLOC_FLEX_RXD, IAVF_RX_SSE, IAVF_RX_SSE_SCATTERED, IAVF_RX_SSE_FLEX_RXD, diff --git a/drivers/net/intel/iavf/iavf_rxtx.c b/drivers/net/intel/iavf/iavf_rxtx.c index 67c73f9ad6f..bbf3a1737e1 100644 --- a/drivers/net/intel/iavf/iavf_rxtx.c +++ b/drivers/net/intel/iavf/iavf_rxtx.c @@ -3734,6 +3734,9 @@ static const struct ci_rx_path_info iavf_rx_path_infos[] = { {.scattered = true, .flex_desc = true}}}, [IAVF_RX_BULK_ALLOC] = {iavf_recv_pkts_bulk_alloc, "Scalar Bulk Alloc", {IAVF_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.bulk_alloc = true}}}, + [IAVF_RX_BULK_ALLOC_FLEX_RXD] = {iavf_recv_pkts_bulk_alloc, "Scalar Bulk Alloc Flex", + {IAVF_RX_SCALAR_FLEX_OFFLOADS, RTE_VECT_SIMD_DISABLED, + {.flex_desc = true, .bulk_alloc = true}}}, #ifdef RTE_ARCH_X86 [IAVF_RX_SSE] = {iavf_recv_pkts_vec, "Vector SSE", {IAVF_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}}, From 06bfac1424f9d3a3a1555605be326927ca6be807 Mon Sep 17 00:00:00 2001 From: Ciara Loftus Date: Tue, 14 Oct 2025 08:45:15 +0000 Subject: [PATCH 4/6] net/iavf: reformat the Rx path infos array In order to improve readability, reformat the rx path infos array. Signed-off-by: Ciara Loftus Signed-off-by: 0-day Robot --- drivers/net/intel/iavf/iavf_rxtx.c | 289 +++++++++++++++++++++-------- 1 file changed, 210 insertions(+), 79 deletions(-) diff --git a/drivers/net/intel/iavf/iavf_rxtx.c b/drivers/net/intel/iavf/iavf_rxtx.c index bbf3a1737e1..58d5747c40f 100644 --- a/drivers/net/intel/iavf/iavf_rxtx.c +++ b/drivers/net/intel/iavf/iavf_rxtx.c @@ -3720,99 +3720,230 @@ iavf_xmit_pkts_no_poll(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); static const struct ci_rx_path_info iavf_rx_path_infos[] = { - [IAVF_RX_DISABLED] = {iavf_recv_pkts_no_poll, "Disabled", - {IAVF_RX_NO_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.disabled = true}}}, - [IAVF_RX_DEFAULT] = {iavf_recv_pkts, "Scalar", - {IAVF_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED}}, - [IAVF_RX_SCATTERED] = {iavf_recv_scattered_pkts, "Scalar Scattered", - {IAVF_RX_SCALAR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, RTE_VECT_SIMD_DISABLED, - {.scattered = true}}}, - [IAVF_RX_FLEX_RXD] = {iavf_recv_pkts_flex_rxd, "Scalar Flex", - {IAVF_RX_SCALAR_FLEX_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.flex_desc = true}}}, - [IAVF_RX_SCATTERED_FLEX_RXD] = {iavf_recv_scattered_pkts_flex_rxd, "Scalar Scattered Flex", - {IAVF_RX_SCALAR_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, RTE_VECT_SIMD_DISABLED, - {.scattered = true, .flex_desc = true}}}, - [IAVF_RX_BULK_ALLOC] = {iavf_recv_pkts_bulk_alloc, "Scalar Bulk Alloc", - {IAVF_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.bulk_alloc = true}}}, - [IAVF_RX_BULK_ALLOC_FLEX_RXD] = {iavf_recv_pkts_bulk_alloc, "Scalar Bulk Alloc Flex", - {IAVF_RX_SCALAR_FLEX_OFFLOADS, RTE_VECT_SIMD_DISABLED, - {.flex_desc = true, .bulk_alloc = true}}}, + [IAVF_RX_DISABLED] = { + .pkt_burst = iavf_recv_pkts_no_poll, + .info = "Disabled", + .features = { + .rx_offloads = IAVF_RX_NO_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.disabled = true}}, + [IAVF_RX_DEFAULT] = { + .pkt_burst = iavf_recv_pkts, + .info = "Scalar", + .features = { + .rx_offloads = IAVF_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED}}, + [IAVF_RX_SCATTERED] = { + .pkt_burst = iavf_recv_scattered_pkts, + .info = "Scalar Scattered", + .features = { + .rx_offloads = IAVF_RX_SCALAR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.scattered = true}}, + [IAVF_RX_FLEX_RXD] = { + .pkt_burst = iavf_recv_pkts_flex_rxd, + .info = "Scalar Flex", + .features = { + .rx_offloads = IAVF_RX_SCALAR_FLEX_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.flex_desc = true}}, + [IAVF_RX_SCATTERED_FLEX_RXD] = { + .pkt_burst = iavf_recv_scattered_pkts_flex_rxd, + .info = "Scalar Scattered Flex", + .features = { + .rx_offloads = IAVF_RX_SCALAR_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.scattered = true, + .extra.flex_desc = true}}, + [IAVF_RX_BULK_ALLOC] = { + .pkt_burst = iavf_recv_pkts_bulk_alloc, + .info = "Scalar Bulk Alloc", + .features = { + .rx_offloads = IAVF_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.bulk_alloc = true}}, + [IAVF_RX_BULK_ALLOC_FLEX_RXD] = { + .pkt_burst = iavf_recv_pkts_bulk_alloc, + .info = "Scalar Bulk Alloc Flex", + .features = { + .rx_offloads = IAVF_RX_SCALAR_FLEX_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, #ifdef RTE_ARCH_X86 - [IAVF_RX_SSE] = {iavf_recv_pkts_vec, "Vector SSE", - {IAVF_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}}, - [IAVF_RX_SSE_SCATTERED] = {iavf_recv_scattered_pkts_vec, "Vector Scattered SSE", - {IAVF_RX_VECTOR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, RTE_VECT_SIMD_128, - {.scattered = true, .bulk_alloc = true}}}, - [IAVF_RX_SSE_FLEX_RXD] = {iavf_recv_pkts_vec_flex_rxd, "Vector Flex SSE", - {IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS, RTE_VECT_SIMD_128, - {.flex_desc = true, .bulk_alloc = true}}}, + [IAVF_RX_SSE] = { + .pkt_burst = iavf_recv_pkts_vec, + .info = "Vector SSE", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.bulk_alloc = true}}, + [IAVF_RX_SSE_SCATTERED] = { + .pkt_burst = iavf_recv_scattered_pkts_vec, + .info = "Vector Scattered SSE", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_128, + .extra.scattered = true, + .extra.bulk_alloc = true}}, + [IAVF_RX_SSE_FLEX_RXD] = { + .pkt_burst = iavf_recv_pkts_vec_flex_rxd, + .info = "Vector Flex SSE", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, [IAVF_RX_SSE_SCATTERED_FLEX_RXD] = { - iavf_recv_scattered_pkts_vec_flex_rxd, "Vector Scattered SSE Flex", - {IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, - RTE_VECT_SIMD_128, - {.scattered = true, .flex_desc = true, .bulk_alloc = true}}}, - [IAVF_RX_AVX2] = {iavf_recv_pkts_vec_avx2, "Vector AVX2", - {IAVF_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256, {.bulk_alloc = true}}}, - [IAVF_RX_AVX2_SCATTERED] = {iavf_recv_scattered_pkts_vec_avx2, "Vector Scattered AVX2", - {IAVF_RX_VECTOR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, RTE_VECT_SIMD_256, - {.scattered = true, .bulk_alloc = true}}}, - [IAVF_RX_AVX2_OFFLOAD] = {iavf_recv_pkts_vec_avx2_offload, "Vector AVX2 Offload", - {IAVF_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_256, {.bulk_alloc = true}}}, + .pkt_burst = iavf_recv_scattered_pkts_vec_flex_rxd, + .info = "Vector Scattered SSE Flex", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS | + RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_128, + .extra.scattered = true, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, + [IAVF_RX_AVX2] = { + .pkt_burst = iavf_recv_pkts_vec_avx2, + .info = "Vector AVX2", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.bulk_alloc = true}}, + [IAVF_RX_AVX2_SCATTERED] = { + .pkt_burst = iavf_recv_scattered_pkts_vec_avx2, + .info = "Vector Scattered AVX2", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_256, + .extra.scattered = true, + .extra.bulk_alloc = true}}, + [IAVF_RX_AVX2_OFFLOAD] = { + .pkt_burst = iavf_recv_pkts_vec_avx2_offload, + .info = "Vector AVX2 Offload", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.bulk_alloc = true}}, [IAVF_RX_AVX2_SCATTERED_OFFLOAD] = { - iavf_recv_scattered_pkts_vec_avx2_offload, "Vector Scattered AVX2 offload", - {IAVF_RX_VECTOR_OFFLOAD_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, RTE_VECT_SIMD_256, - {.scattered = true, .bulk_alloc = true}}}, - [IAVF_RX_AVX2_FLEX_RXD] = {iavf_recv_pkts_vec_avx2_flex_rxd, "Vector AVX2 Flex", - {IAVF_RX_VECTOR_FLEX_OFFLOADS, RTE_VECT_SIMD_256, - {.flex_desc = true, .bulk_alloc = true}}}, + .pkt_burst = iavf_recv_scattered_pkts_vec_avx2_offload, + .info = "Vector Scattered AVX2 Offload", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_256, + .extra.scattered = true, + .extra.bulk_alloc = true}}, + [IAVF_RX_AVX2_FLEX_RXD] = { + .pkt_burst = iavf_recv_pkts_vec_avx2_flex_rxd, + .info = "Vector AVX2 Flex", + .features = { + .rx_offloads = IAVF_RX_VECTOR_FLEX_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, [IAVF_RX_AVX2_SCATTERED_FLEX_RXD] = { - iavf_recv_scattered_pkts_vec_avx2_flex_rxd, "Vector Scattered AVX2 Flex", - {IAVF_RX_VECTOR_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, RTE_VECT_SIMD_256, - {.scattered = true, .flex_desc = true, .bulk_alloc = true}}}, + .pkt_burst = iavf_recv_scattered_pkts_vec_avx2_flex_rxd, + .info = "Vector Scattered AVX2 Flex", + .features = { + .rx_offloads = IAVF_RX_VECTOR_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_256, + .extra.scattered = true, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, [IAVF_RX_AVX2_FLEX_RXD_OFFLOAD] = { - iavf_recv_pkts_vec_avx2_flex_rxd_offload, "Vector AVX2 Flex Offload", - {IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS, RTE_VECT_SIMD_256, - {.flex_desc = true, .bulk_alloc = true}}}, + .pkt_burst = iavf_recv_pkts_vec_avx2_flex_rxd_offload, + .info = "Vector AVX2 Flex Offload", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, [IAVF_RX_AVX2_SCATTERED_FLEX_RXD_OFFLOAD] = { - iavf_recv_scattered_pkts_vec_avx2_flex_rxd_offload, - "Vector Scattered AVX2 Flex Offload", - {IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, - RTE_VECT_SIMD_256, - {.scattered = true, .flex_desc = true, .bulk_alloc = true}}}, + .pkt_burst = iavf_recv_scattered_pkts_vec_avx2_flex_rxd_offload, + .info = "Vector Scattered AVX2 Flex Offload", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS | + RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_256, + .extra.scattered = true, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, #ifdef CC_AVX512_SUPPORT - [IAVF_RX_AVX512] = {iavf_recv_pkts_vec_avx512, "Vector AVX512", - {IAVF_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512, {.bulk_alloc = true}}}, + [IAVF_RX_AVX512] = { + .pkt_burst = iavf_recv_pkts_vec_avx512, + .info = "Vector AVX512", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.bulk_alloc = true}}, [IAVF_RX_AVX512_SCATTERED] = { - iavf_recv_scattered_pkts_vec_avx512, "Vector Scattered AVX512", - {IAVF_RX_VECTOR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, RTE_VECT_SIMD_512, - {.scattered = true, .bulk_alloc = true}}}, - [IAVF_RX_AVX512_OFFLOAD] = {iavf_recv_pkts_vec_avx512_offload, "Vector AVX512 Offload", - {IAVF_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_512, {.bulk_alloc = true}}}, + .pkt_burst = iavf_recv_scattered_pkts_vec_avx512, + .info = "Vector Scattered AVX512", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_512, + .extra.scattered = true, + .extra.bulk_alloc = true}}, + [IAVF_RX_AVX512_OFFLOAD] = { + .pkt_burst = iavf_recv_pkts_vec_avx512_offload, + .info = "Vector AVX512 Offload", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.bulk_alloc = true}}, [IAVF_RX_AVX512_SCATTERED_OFFLOAD] = { - iavf_recv_scattered_pkts_vec_avx512_offload, "Vector Scattered AVX512 offload", - {IAVF_RX_VECTOR_OFFLOAD_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, RTE_VECT_SIMD_512, - {.scattered = true, .bulk_alloc = true}}}, - [IAVF_RX_AVX512_FLEX_RXD] = {iavf_recv_pkts_vec_avx512_flex_rxd, "Vector AVX512 Flex", - {IAVF_RX_VECTOR_FLEX_OFFLOADS, RTE_VECT_SIMD_512, - {.flex_desc = true, .bulk_alloc = true}}}, + .pkt_burst = iavf_recv_scattered_pkts_vec_avx512_offload, + .info = "Vector Scattered AVX512 Offload", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_512, + .extra.scattered = true, + .extra.bulk_alloc = true}}, + [IAVF_RX_AVX512_FLEX_RXD] = { + .pkt_burst = iavf_recv_pkts_vec_avx512_flex_rxd, + .info = "Vector AVX512 Flex", + .features = { + .rx_offloads = IAVF_RX_VECTOR_FLEX_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, [IAVF_RX_AVX512_SCATTERED_FLEX_RXD] = { - iavf_recv_scattered_pkts_vec_avx512_flex_rxd, "Vector Scattered AVX512 Flex", - {IAVF_RX_VECTOR_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, RTE_VECT_SIMD_512, - {.scattered = true, .flex_desc = true, .bulk_alloc = true}}}, + .pkt_burst = iavf_recv_scattered_pkts_vec_avx512_flex_rxd, + .info = "Vector Scattered AVX512 Flex", + .features = { + .rx_offloads = IAVF_RX_VECTOR_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_512, + .extra.scattered = true, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, [IAVF_RX_AVX512_FLEX_RXD_OFFLOAD] = { - iavf_recv_pkts_vec_avx512_flex_rxd_offload, "Vector AVX512 Flex Offload", - {IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS, RTE_VECT_SIMD_512, - {.flex_desc = true, .bulk_alloc = true}}}, + .pkt_burst = iavf_recv_pkts_vec_avx512_flex_rxd_offload, + .info = "Vector AVX512 Flex Offload", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, [IAVF_RX_AVX512_SCATTERED_FLEX_RXD_OFFLOAD] = { - iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload, - "Vector Scattered AVX512 Flex offload", - {IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS | RTE_ETH_RX_OFFLOAD_SCATTER, - RTE_VECT_SIMD_512, - {.scattered = true, .flex_desc = true, .bulk_alloc = true}}}, + .pkt_burst = iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload, + .info = "Vector Scattered AVX512 Flex Offload", + .features = { + .rx_offloads = IAVF_RX_VECTOR_OFFLOAD_FLEX_OFFLOADS | + RTE_ETH_RX_OFFLOAD_SCATTER, + .simd_width = RTE_VECT_SIMD_512, + .extra.scattered = true, + .extra.flex_desc = true, + .extra.bulk_alloc = true}}, #endif #elif defined RTE_ARCH_ARM - [IAVF_RX_SSE] = {iavf_recv_pkts_vec, "Vector Neon", - {IAVF_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}}, + [IAVF_RX_SSE] = { + .pkt_burst = iavf_recv_pkts_vec, + .info = "Vector Neon", + .features = { + .rx_offloads = IAVF_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.bulk_alloc = true}}, #endif }; From c850cc0e5052e8a7e42530953de53d62f0b6dd26 Mon Sep 17 00:00:00 2001 From: Ciara Loftus Date: Tue, 14 Oct 2025 08:45:16 +0000 Subject: [PATCH 5/6] net/i40e: reformat the Rx path infos array In order to improve readability, reformat the rx path infos array. Signed-off-by: Ciara Loftus Signed-off-by: 0-day Robot --- drivers/net/intel/i40e/i40e_rxtx.c | 126 ++++++++++++++++++++++------- 1 file changed, 95 insertions(+), 31 deletions(-) diff --git a/drivers/net/intel/i40e/i40e_rxtx.c b/drivers/net/intel/i40e/i40e_rxtx.c index 2bd09552252..c09696262da 100644 --- a/drivers/net/intel/i40e/i40e_rxtx.c +++ b/drivers/net/intel/i40e/i40e_rxtx.c @@ -3290,42 +3290,106 @@ i40e_recycle_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, } static const struct ci_rx_path_info i40e_rx_path_infos[] = { - [I40E_RX_DEFAULT] = { i40e_recv_pkts, "Scalar", - {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED}}, - [I40E_RX_SCATTERED] = { i40e_recv_scattered_pkts, "Scalar Scattered", - {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.scattered = true}}}, - [I40E_RX_BULK_ALLOC] = { i40e_recv_pkts_bulk_alloc, "Scalar Bulk Alloc", - {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.bulk_alloc = true}}}, + [I40E_RX_DEFAULT] = { + .pkt_burst = i40e_recv_pkts, + .info = "Scalar", + .features = { + .rx_offloads = I40E_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED}}, + [I40E_RX_SCATTERED] = { + .pkt_burst = i40e_recv_scattered_pkts, + .info = "Scalar Scattered", + .features = { + .rx_offloads = I40E_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.scattered = true}}, + [I40E_RX_BULK_ALLOC] = { + .pkt_burst = i40e_recv_pkts_bulk_alloc, + .info = "Scalar Bulk Alloc", + .features = { + .rx_offloads = I40E_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.bulk_alloc = true}}, #ifdef RTE_ARCH_X86 - [I40E_RX_SSE] = { i40e_recv_pkts_vec, "Vector SSE", - {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}}, - [I40E_RX_SSE_SCATTERED] = { i40e_recv_scattered_pkts_vec, "Vector SSE Scattered", - {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_128, - {.scattered = true, .bulk_alloc = true}}}, - [I40E_RX_AVX2] = { i40e_recv_pkts_vec_avx2, "Vector AVX2", - {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256, {.bulk_alloc = true}}}, - [I40E_RX_AVX2_SCATTERED] = { i40e_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered", - {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256, - {.scattered = true, .bulk_alloc = true}}}, + [I40E_RX_SSE] = { + .pkt_burst = i40e_recv_pkts_vec, + .info = "Vector SSE", + .features = { + .rx_offloads = I40E_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.bulk_alloc = true}}, + [I40E_RX_SSE_SCATTERED] = { + .pkt_burst = i40e_recv_scattered_pkts_vec, + .info = "Vector SSE Scattered", + .features = { + .rx_offloads = I40E_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.scattered = true, + .extra.bulk_alloc = true}}, + [I40E_RX_AVX2] = { + .pkt_burst = i40e_recv_pkts_vec_avx2, + .info = "Vector AVX2", + .features = { + .rx_offloads = I40E_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.bulk_alloc = true}}, + [I40E_RX_AVX2_SCATTERED] = { + .pkt_burst = i40e_recv_scattered_pkts_vec_avx2, + .info = "Vector AVX2 Scattered", + .features = { + .rx_offloads = I40E_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.scattered = true, + .extra.bulk_alloc = true}}, #ifdef CC_AVX512_SUPPORT - [I40E_RX_AVX512] = { i40e_recv_pkts_vec_avx512, "Vector AVX512", - {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512, {.bulk_alloc = true}}}, - [I40E_RX_AVX512_SCATTERED] = { i40e_recv_scattered_pkts_vec_avx512, - "Vector AVX512 Scattered", {I40E_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512, - {.scattered = true, .bulk_alloc = true}}}, + [I40E_RX_AVX512] = { + .pkt_burst = i40e_recv_pkts_vec_avx512, + .info = "Vector AVX512", + .features = { + .rx_offloads = I40E_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.bulk_alloc = true}}, + [I40E_RX_AVX512_SCATTERED] = { + .pkt_burst = i40e_recv_scattered_pkts_vec_avx512, + .info = "Vector AVX512 Scattered", + .features = { + .rx_offloads = I40E_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.scattered = true, + .extra.bulk_alloc = true}}, #endif #elif defined(RTE_ARCH_ARM64) - [I40E_RX_NEON] = { i40e_recv_pkts_vec, "Vector Neon", - {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}}, - [I40E_RX_NEON_SCATTERED] = { i40e_recv_scattered_pkts_vec, "Vector Neon Scattered", - {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_128, - {.scattered = true, .bulk_alloc = true}}}, + [I40E_RX_NEON] = { + .pkt_burst = i40e_recv_pkts_vec, + .info = "Vector Neon", + .features = { + .rx_offloads = I40E_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.bulk_alloc = true}}, + [I40E_RX_NEON_SCATTERED] = { + .pkt_burst = i40e_recv_scattered_pkts_vec, + .info = "Vector Neon Scattered", + .features = { + .rx_offloads = I40E_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.scattered = true, + .extra.bulk_alloc = true}}, #elif defined(RTE_ARCH_PPC_64) - [I40E_RX_ALTIVEC] = { i40e_recv_pkts_vec, "Vector AltiVec", - {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}}, - [I40E_RX_ALTIVEC_SCATTERED] = { i40e_recv_scattered_pkts_vec, "Vector AltiVec Scattered", - {I40E_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_128, - {.scattered = true, .bulk_alloc = true}}}, + [I40E_RX_ALTIVEC] = { + .pkt_burst = i40e_recv_pkts_vec, + .info = "Vector AltiVec", + .features = { + .rx_offloads = I40E_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.bulk_alloc = true}}, + [I40E_RX_ALTIVEC_SCATTERED] = { + .pkt_burst = i40e_recv_scattered_pkts_vec, + .info = "Vector AltiVec Scattered", + .features = { + .rx_offloads = I40E_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.scattered = true, + .extra.bulk_alloc = true}}, #endif }; From 5fbe7b0f351aa968b1398afec5115fb43eb19782 Mon Sep 17 00:00:00 2001 From: Ciara Loftus Date: Tue, 14 Oct 2025 08:45:17 +0000 Subject: [PATCH 6/6] net/ice: reformat the Rx path infos array In order to improve readability, reformat the rx path infos array. Signed-off-by: Ciara Loftus Signed-off-by: 0-day Robot --- drivers/net/intel/ice/ice_rxtx.c | 124 +++++++++++++++++++++++-------- 1 file changed, 93 insertions(+), 31 deletions(-) diff --git a/drivers/net/intel/ice/ice_rxtx.c b/drivers/net/intel/ice/ice_rxtx.c index 411b353417d..acc36ceb508 100644 --- a/drivers/net/intel/ice/ice_rxtx.c +++ b/drivers/net/intel/ice/ice_rxtx.c @@ -3667,41 +3667,103 @@ ice_xmit_pkts_simple(void *tx_queue, } static const struct ci_rx_path_info ice_rx_path_infos[] = { - [ICE_RX_DEFAULT] = {ice_recv_pkts, "Scalar", - {ICE_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED}}, - [ICE_RX_SCATTERED] = {ice_recv_scattered_pkts, "Scalar Scattered", - {ICE_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.scattered = true}}}, - [ICE_RX_BULK_ALLOC] = {ice_recv_pkts_bulk_alloc, "Scalar Bulk Alloc", - {ICE_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, {.bulk_alloc = true}}}, + [ICE_RX_DEFAULT] = { + .pkt_burst = ice_recv_pkts, + .info = "Scalar", + .features = { + .rx_offloads = ICE_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED}}, + [ICE_RX_SCATTERED] = { + .pkt_burst = ice_recv_scattered_pkts, + .info = "Scalar Scattered", + .features = { + .rx_offloads = ICE_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.scattered = true}}, + [ICE_RX_BULK_ALLOC] = { + .pkt_burst = ice_recv_pkts_bulk_alloc, + .info = "Scalar Bulk Alloc", + .features = { + .rx_offloads = ICE_RX_SCALAR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_DISABLED, + .extra.bulk_alloc = true}}, #ifdef RTE_ARCH_X86 - [ICE_RX_SSE] = {ice_recv_pkts_vec, "Vector SSE", - {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_128, {.bulk_alloc = true}}}, - [ICE_RX_SSE_SCATTERED] = {ice_recv_scattered_pkts_vec, "Vector SSE Scattered", - {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_128, - {.scattered = true, .bulk_alloc = true}}}, - [ICE_RX_AVX2] = {ice_recv_pkts_vec_avx2, "Vector AVX2", - {ICE_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256, {.bulk_alloc = true}}}, - [ICE_RX_AVX2_SCATTERED] = {ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered", - {ICE_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256, - {.scattered = true, .bulk_alloc = true}}}, - [ICE_RX_AVX2_OFFLOAD] = {ice_recv_pkts_vec_avx2_offload, "Offload Vector AVX2", - {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_256, {.bulk_alloc = true}}}, + [ICE_RX_SSE] = { + .pkt_burst = ice_recv_pkts_vec, + .info = "Vector SSE", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.bulk_alloc = true}}, + [ICE_RX_SSE_SCATTERED] = { + .pkt_burst = ice_recv_scattered_pkts_vec, + .info = "Vector SSE Scattered", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS, + .simd_width = RTE_VECT_SIMD_128, + .extra.scattered = true, + .extra.bulk_alloc = true}}, + [ICE_RX_AVX2] = { + .pkt_burst = ice_recv_pkts_vec_avx2, + .info = "Vector AVX2", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.bulk_alloc = true}}, + [ICE_RX_AVX2_SCATTERED] = { + .pkt_burst = ice_recv_scattered_pkts_vec_avx2, + .info = "Vector AVX2 Scattered", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.scattered = true, + .extra.bulk_alloc = true}}, + [ICE_RX_AVX2_OFFLOAD] = { + .pkt_burst = ice_recv_pkts_vec_avx2_offload, + .info = "Offload Vector AVX2", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.bulk_alloc = true}}, [ICE_RX_AVX2_SCATTERED_OFFLOAD] = { - ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered", - {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_256, - {.scattered = true, .bulk_alloc = true}}}, + .pkt_burst = ice_recv_scattered_pkts_vec_avx2_offload, + .info = "Offload Vector AVX2 Scattered", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS, + .simd_width = RTE_VECT_SIMD_256, + .extra.scattered = true, + .extra.bulk_alloc = true}}, #ifdef CC_AVX512_SUPPORT - [ICE_RX_AVX512] = {ice_recv_pkts_vec_avx512, "Vector AVX512", - {ICE_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512, {.bulk_alloc = true}}}, - [ICE_RX_AVX512_SCATTERED] = {ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered", - {ICE_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512, - {.scattered = true, .bulk_alloc = true}}}, - [ICE_RX_AVX512_OFFLOAD] = {ice_recv_pkts_vec_avx512_offload, "Offload Vector AVX512", - {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_512, {.bulk_alloc = true}}}, + [ICE_RX_AVX512] = { + .pkt_burst = ice_recv_pkts_vec_avx512, + .info = "Vector AVX512", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.bulk_alloc = true}}, + [ICE_RX_AVX512_SCATTERED] = { + .pkt_burst = ice_recv_scattered_pkts_vec_avx512, + .info = "Vector AVX512 Scattered", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.scattered = true, + .extra.bulk_alloc = true}}, + [ICE_RX_AVX512_OFFLOAD] = { + .pkt_burst = ice_recv_pkts_vec_avx512_offload, + .info = "Offload Vector AVX512", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.bulk_alloc = true}}, [ICE_RX_AVX512_SCATTERED_OFFLOAD] = { - ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered", - {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_512, - {.scattered = true, .bulk_alloc = true}}}, + .pkt_burst = ice_recv_scattered_pkts_vec_avx512_offload, + .info = "Offload Vector AVX512 Scattered", + .features = { + .rx_offloads = ICE_RX_VECTOR_OFFLOAD_OFFLOADS, + .simd_width = RTE_VECT_SIMD_512, + .extra.scattered = true, + .extra.bulk_alloc = true}}, #endif #endif };