diff --git a/drv/spartan7-loader/cosmo-seq/README.md b/drv/spartan7-loader/cosmo-seq/README.md index 0823cc02ec..339c476791 100644 --- a/drv/spartan7-loader/cosmo-seq/README.md +++ b/drv/spartan7-loader/cosmo-seq/README.md @@ -1,3 +1,3 @@ FPGA images and collateral are generated from: -[this sha](https://github.com/oxidecomputer/quartz/commit/0cf5b6cffba5bbf70db9b50b7301831e7697e8fb) -[release](https://api.github.com/repos/oxidecomputer/quartz/releases/220433638) \ No newline at end of file +[this sha](https://github.com/oxidecomputer/quartz/commit/76b99aaf164a4c04d9c88446522b132c0901ff6b) +[release](https://api.github.com/repos/oxidecomputer/quartz/releases/224921430) \ No newline at end of file diff --git a/drv/spartan7-loader/cosmo-seq/cosmo_seq.bz2 b/drv/spartan7-loader/cosmo-seq/cosmo_seq.bz2 index 21a220d97e..294f98bfa6 100644 Binary files a/drv/spartan7-loader/cosmo-seq/cosmo_seq.bz2 and b/drv/spartan7-loader/cosmo-seq/cosmo_seq.bz2 differ diff --git a/drv/spartan7-loader/cosmo-seq/cosmo_seq_top.json b/drv/spartan7-loader/cosmo-seq/cosmo_seq_top.json index f01e4b4ef8..1d583e1348 100644 --- a/drv/spartan7-loader/cosmo-seq/cosmo_seq_top.json +++ b/drv/spartan7-loader/cosmo-seq/cosmo_seq_top.json @@ -23,7 +23,7 @@ }, { "type": "addrmap", - "addr_span_bytes": 36, + "addr_span_bytes": 40, "inst_name": "espi", "orig_type_name": "espi_regs", "addr_offset": 512, @@ -56,8 +56,8 @@ { "type": "addrmap", "addr_span_bytes": 76, - "inst_name": "spd_proxy", - "orig_type_name": "spd_proxy_regs", + "inst_name": "dimms", + "orig_type_name": "dimm_regs", "addr_offset": 1536, "children": [] }, diff --git a/drv/spartan7-loader/cosmo-seq/dimm_regs.json b/drv/spartan7-loader/cosmo-seq/dimm_regs.json index ecfcf4e18d..275bf8634b 100644 --- a/drv/spartan7-loader/cosmo-seq/dimm_regs.json +++ b/drv/spartan7-loader/cosmo-seq/dimm_regs.json @@ -1,86 +1,13 @@ { "type": "addrmap", "addr_span_bytes": 76, - "inst_name": "spd_proxy_regs", + "inst_name": "dimm_regs", "addr_offset": 0, "children": [ - { - "type": "reg", - "inst_name": "spd_ctrl", - "addr_offset": 0, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "start", - "lsb": 0, - "msb": 0, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to initiate a SPD cache read. Cleared by hardware after the read is complete." - } - ] - }, - { - "type": "reg", - "inst_name": "fifo_ctrl", - "addr_offset": 4, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "tx_fifo_auto_inc", - "lsb": 6, - "msb": 6, - "reset": 1, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to one put TX FIFO in auto increment mode." - }, - { - "type": "field", - "inst_name": "tx_fifo_reset", - "lsb": 7, - "msb": 7, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to one to reset TX FIFO. Cleared by hardware after FIFO reset." - }, - { - "type": "field", - "inst_name": "rx_fifo_auto_inc", - "lsb": 14, - "msb": 14, - "reset": 1, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to one put RX FIFO in auto increment mode." - }, - { - "type": "field", - "inst_name": "rx_fifo_reset", - "lsb": 15, - "msb": 15, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to one to reset RX FIFO. Cleared by hardware after FIFO reset." - } - ] - }, { "type": "reg", "inst_name": "dimm_pcamp", - "addr_offset": 8, + "addr_offset": 0, "regwidth": 32, "min_accesswidth": 32, "children": [ @@ -221,7 +148,7 @@ { "type": "reg", "inst_name": "spd_present", - "addr_offset": 12, + "addr_offset": 4, "regwidth": 32, "min_accesswidth": 32, "children": [ @@ -362,7 +289,7 @@ { "type": "reg", "inst_name": "spd_select", - "addr_offset": 16, + "addr_offset": 8, "regwidth": 32, "min_accesswidth": 32, "children": [ @@ -500,10 +427,30 @@ } ] }, + { + "type": "reg", + "inst_name": "spd_ctrl", + "addr_offset": 12, + "regwidth": 32, + "min_accesswidth": 32, + "children": [ + { + "type": "field", + "inst_name": "start", + "lsb": 0, + "msb": 0, + "reset": 0, + "sw_access": "rw", + "se_onread": null, + "se_onwrite": null, + "desc": "Set to initiate a SPD cache read. Cleared by hardware after the read is complete." + } + ] + }, { "type": "reg", "inst_name": "spd_rd_ptr", - "addr_offset": 20, + "addr_offset": 16, "regwidth": 32, "min_accesswidth": 32, "children": [ @@ -523,7 +470,7 @@ { "type": "reg", "inst_name": "spd_rdata", - "addr_offset": 24, + "addr_offset": 20, "regwidth": 32, "min_accesswidth": 32, "children": [ @@ -540,6 +487,59 @@ } ] }, + { + "type": "reg", + "inst_name": "fifo_ctrl", + "addr_offset": 24, + "regwidth": 32, + "min_accesswidth": 32, + "children": [ + { + "type": "field", + "inst_name": "tx_fifo_auto_inc", + "lsb": 6, + "msb": 6, + "reset": 1, + "sw_access": "rw", + "se_onread": null, + "se_onwrite": null, + "desc": "Set to one put TX FIFO in auto increment mode." + }, + { + "type": "field", + "inst_name": "tx_fifo_reset", + "lsb": 7, + "msb": 7, + "reset": 0, + "sw_access": "rw", + "se_onread": null, + "se_onwrite": null, + "desc": "Set to one to reset TX FIFO. Cleared by hardware after FIFO reset." + }, + { + "type": "field", + "inst_name": "rx_fifo_auto_inc", + "lsb": 14, + "msb": 14, + "reset": 1, + "sw_access": "rw", + "se_onread": null, + "se_onwrite": null, + "desc": "Set to one put RX FIFO in auto increment mode." + }, + { + "type": "field", + "inst_name": "rx_fifo_reset", + "lsb": 15, + "msb": 15, + "reset": 0, + "sw_access": "rw", + "se_onread": null, + "se_onwrite": null, + "desc": "Set to one to reset RX FIFO. Cleared by hardware after FIFO reset." + } + ] + }, { "type": "reg", "inst_name": "bus0_cmd", diff --git a/drv/spartan7-loader/cosmo-seq/espi_regs.json b/drv/spartan7-loader/cosmo-seq/espi_regs.json index 8195427318..fb4d8585e9 100644 --- a/drv/spartan7-loader/cosmo-seq/espi_regs.json +++ b/drv/spartan7-loader/cosmo-seq/espi_regs.json @@ -1,6 +1,6 @@ { "type": "addrmap", - "addr_span_bytes": 36, + "addr_span_bytes": 40, "inst_name": "espi_regs", "addr_offset": 0, "children": [ @@ -238,6 +238,26 @@ "desc": "MSB is bit 31" } ] + }, + { + "type": "reg", + "inst_name": "post_code_count", + "addr_offset": 36, + "regwidth": 32, + "min_accesswidth": 32, + "children": [ + { + "type": "field", + "inst_name": "count", + "lsb": 0, + "msb": 31, + "reset": 0, + "sw_access": "rw", + "se_onread": null, + "se_onwrite": null, + "desc": "" + } + ] } ] } \ No newline at end of file diff --git a/drv/spartan7-loader/cosmo-seq/spd_proxy_regs.json b/drv/spartan7-loader/cosmo-seq/spd_proxy_regs.json deleted file mode 100644 index ab3f90a2c7..0000000000 --- a/drv/spartan7-loader/cosmo-seq/spd_proxy_regs.json +++ /dev/null @@ -1,478 +0,0 @@ -{ - "type": "addrmap", - "addr_span_bytes": 72, - "inst_name": "spd_proxy_regs", - "addr_offset": 0, - "children": [ - { - "type": "reg", - "inst_name": "spd_ctrl", - "addr_offset": 0, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "start", - "lsb": 0, - "msb": 0, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to initiate a SPD cache read. Cleared by hardware after the read is complete." - } - ] - }, - { - "type": "reg", - "inst_name": "fifo_ctrl", - "addr_offset": 4, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "tx_fifo_auto_inc", - "lsb": 6, - "msb": 6, - "reset": 1, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to one put TX FIFO in auto increment mode." - }, - { - "type": "field", - "inst_name": "tx_fifo_reset", - "lsb": 7, - "msb": 7, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to one to reset TX FIFO. Cleared by hardware after FIFO reset." - }, - { - "type": "field", - "inst_name": "rx_fifo_auto_inc", - "lsb": 14, - "msb": 14, - "reset": 1, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to one put RX FIFO in auto increment mode." - }, - { - "type": "field", - "inst_name": "rx_fifo_reset", - "lsb": 15, - "msb": 15, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to one to reset RX FIFO. Cleared by hardware after FIFO reset." - } - ] - }, - { - "type": "reg", - "inst_name": "spd_present", - "addr_offset": 8, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "bus0", - "lsb": 0, - "msb": 5, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "abcdef (a = lsb) spd ack'd" - }, - { - "type": "field", - "inst_name": "bus1", - "lsb": 8, - "msb": 13, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "ghijkl (g = lsb) spd ack'd" - } - ] - }, - { - "type": "reg", - "inst_name": "spd_select", - "addr_offset": 12, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "idx", - "lsb": 0, - "msb": 7, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Set to initiate a SPD cache read. Cleared by hardware after the read is complete." - } - ] - }, - { - "type": "reg", - "inst_name": "spd_rd_ptr", - "addr_offset": 16, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "addr", - "lsb": 0, - "msb": 7, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "in 32bit words, can write to move around 0-255 for 1024 bytes in 32bit words" - } - ] - }, - { - "type": "reg", - "inst_name": "spd_rdata", - "addr_offset": 20, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "data", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "in 32bit words" - } - ] - }, - { - "type": "reg", - "inst_name": "bus0_cmd", - "addr_offset": 24, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "len", - "lsb": 0, - "msb": 7, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "length of the payload in bytes" - }, - { - "type": "field", - "inst_name": "reg_addr", - "lsb": 8, - "msb": 15, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Register address" - }, - { - "type": "field", - "inst_name": "bus_addr", - "lsb": 16, - "msb": 22, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "i2c/i3c bus address" - }, - { - "type": "field", - "inst_name": "op", - "lsb": 24, - "msb": 25, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "READ=0b00, WRITE= 0b01, RANDOM=0b10" - } - ] - }, - { - "type": "reg", - "inst_name": "bus0_tx_wdata", - "addr_offset": 28, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "data", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "w", - "se_onread": null, - "se_onwrite": null, - "desc": "Writing stores data in fifo" - } - ] - }, - { - "type": "reg", - "inst_name": "bus0_tx_waddr", - "addr_offset": 32, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "addr", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "Live pointer in 32bit words to DPR" - } - ] - }, - { - "type": "reg", - "inst_name": "bus0_rx_raddr", - "addr_offset": 36, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "addr", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "Live pointer in 32bit words to DPR" - } - ] - }, - { - "type": "reg", - "inst_name": "bus0_rx_byte_count", - "addr_offset": 40, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "data", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "Byte count of data in RX FIFO" - } - ] - }, - { - "type": "reg", - "inst_name": "bus0_rx_rdata", - "addr_offset": 44, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "data", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "Note: in auto-inc mode. reading side-effects the data by moving the raddr pointer" - } - ] - }, - { - "type": "reg", - "inst_name": "bus1_cmd", - "addr_offset": 48, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "len", - "lsb": 0, - "msb": 7, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "length of the payload in bytes" - }, - { - "type": "field", - "inst_name": "reg_addr", - "lsb": 8, - "msb": 15, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "Register address" - }, - { - "type": "field", - "inst_name": "bus_addr", - "lsb": 16, - "msb": 22, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "i2c/i3c bus address" - }, - { - "type": "field", - "inst_name": "op", - "lsb": 24, - "msb": 25, - "reset": 0, - "sw_access": "rw", - "se_onread": null, - "se_onwrite": null, - "desc": "READ=0b00, WRITE= 0b01, RANDOM=0b10" - } - ] - }, - { - "type": "reg", - "inst_name": "bus1_tx_wdata", - "addr_offset": 52, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "data", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "w", - "se_onread": null, - "se_onwrite": null, - "desc": "Writing stores data in fifo" - } - ] - }, - { - "type": "reg", - "inst_name": "bus1_tx_waddr", - "addr_offset": 56, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "addr", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "Live pointer in 32bit words to DPR" - } - ] - }, - { - "type": "reg", - "inst_name": "bus1_rx_raddr", - "addr_offset": 60, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "addr", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "Live pointer in 32bit words to DPR" - } - ] - }, - { - "type": "reg", - "inst_name": "bus1_rx_byte_count", - "addr_offset": 64, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "data", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "Byte count of data in RX FIFO" - } - ] - }, - { - "type": "reg", - "inst_name": "bus1_rx_rdata", - "addr_offset": 68, - "regwidth": 32, - "min_accesswidth": 32, - "children": [ - { - "type": "field", - "inst_name": "data", - "lsb": 0, - "msb": 31, - "reset": 0, - "sw_access": "r", - "se_onread": null, - "se_onwrite": null, - "desc": "Note: in auto-inc mode. reading side-effects the data by moving the raddr pointer" - } - ] - } - ] -} \ No newline at end of file