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cosmo-seq: grab latest fpga #2092

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Merged
merged 1 commit into from
Jun 12, 2025
Merged

cosmo-seq: grab latest fpga #2092

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4 changes: 2 additions & 2 deletions drv/spartan7-loader/cosmo-seq/README.md
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
FPGA images and collateral are generated from:
[this sha](https://github.com/oxidecomputer/quartz/commit/0cf5b6cffba5bbf70db9b50b7301831e7697e8fb)
[release](https://api.github.com/repos/oxidecomputer/quartz/releases/220433638)
[this sha](https://github.com/oxidecomputer/quartz/commit/76b99aaf164a4c04d9c88446522b132c0901ff6b)
[release](https://api.github.com/repos/oxidecomputer/quartz/releases/224921430)
Binary file modified drv/spartan7-loader/cosmo-seq/cosmo_seq.bz2
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6 changes: 3 additions & 3 deletions drv/spartan7-loader/cosmo-seq/cosmo_seq_top.json
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@
},
{
"type": "addrmap",
"addr_span_bytes": 36,
"addr_span_bytes": 40,
"inst_name": "espi",
"orig_type_name": "espi_regs",
"addr_offset": 512,
Expand Down Expand Up @@ -56,8 +56,8 @@
{
"type": "addrmap",
"addr_span_bytes": 76,
"inst_name": "spd_proxy",
"orig_type_name": "spd_proxy_regs",
"inst_name": "dimms",
"orig_type_name": "dimm_regs",
"addr_offset": 1536,
"children": []
},
Expand Down
158 changes: 79 additions & 79 deletions drv/spartan7-loader/cosmo-seq/dimm_regs.json
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Original file line number Diff line number Diff line change
@@ -1,86 +1,13 @@
{
"type": "addrmap",
"addr_span_bytes": 76,
"inst_name": "spd_proxy_regs",
"inst_name": "dimm_regs",
"addr_offset": 0,
"children": [
{
"type": "reg",
"inst_name": "spd_ctrl",
"addr_offset": 0,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
{
"type": "field",
"inst_name": "start",
"lsb": 0,
"msb": 0,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to initiate a SPD cache read. Cleared by hardware after the read is complete."
}
]
},
{
"type": "reg",
"inst_name": "fifo_ctrl",
"addr_offset": 4,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
{
"type": "field",
"inst_name": "tx_fifo_auto_inc",
"lsb": 6,
"msb": 6,
"reset": 1,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to one put TX FIFO in auto increment mode."
},
{
"type": "field",
"inst_name": "tx_fifo_reset",
"lsb": 7,
"msb": 7,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to one to reset TX FIFO. Cleared by hardware after FIFO reset."
},
{
"type": "field",
"inst_name": "rx_fifo_auto_inc",
"lsb": 14,
"msb": 14,
"reset": 1,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to one put RX FIFO in auto increment mode."
},
{
"type": "field",
"inst_name": "rx_fifo_reset",
"lsb": 15,
"msb": 15,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to one to reset RX FIFO. Cleared by hardware after FIFO reset."
}
]
},
{
"type": "reg",
"inst_name": "dimm_pcamp",
"addr_offset": 8,
"addr_offset": 0,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand Down Expand Up @@ -221,7 +148,7 @@
{
"type": "reg",
"inst_name": "spd_present",
"addr_offset": 12,
"addr_offset": 4,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand Down Expand Up @@ -362,7 +289,7 @@
{
"type": "reg",
"inst_name": "spd_select",
"addr_offset": 16,
"addr_offset": 8,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand Down Expand Up @@ -500,10 +427,30 @@
}
]
},
{
"type": "reg",
"inst_name": "spd_ctrl",
"addr_offset": 12,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
{
"type": "field",
"inst_name": "start",
"lsb": 0,
"msb": 0,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to initiate a SPD cache read. Cleared by hardware after the read is complete."
}
]
},
{
"type": "reg",
"inst_name": "spd_rd_ptr",
"addr_offset": 20,
"addr_offset": 16,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand All @@ -523,7 +470,7 @@
{
"type": "reg",
"inst_name": "spd_rdata",
"addr_offset": 24,
"addr_offset": 20,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand All @@ -540,6 +487,59 @@
}
]
},
{
"type": "reg",
"inst_name": "fifo_ctrl",
"addr_offset": 24,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
{
"type": "field",
"inst_name": "tx_fifo_auto_inc",
"lsb": 6,
"msb": 6,
"reset": 1,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to one put TX FIFO in auto increment mode."
},
{
"type": "field",
"inst_name": "tx_fifo_reset",
"lsb": 7,
"msb": 7,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to one to reset TX FIFO. Cleared by hardware after FIFO reset."
},
{
"type": "field",
"inst_name": "rx_fifo_auto_inc",
"lsb": 14,
"msb": 14,
"reset": 1,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to one put RX FIFO in auto increment mode."
},
{
"type": "field",
"inst_name": "rx_fifo_reset",
"lsb": 15,
"msb": 15,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "Set to one to reset RX FIFO. Cleared by hardware after FIFO reset."
}
]
},
{
"type": "reg",
"inst_name": "bus0_cmd",
Expand Down
22 changes: 21 additions & 1 deletion drv/spartan7-loader/cosmo-seq/espi_regs.json
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{
"type": "addrmap",
"addr_span_bytes": 36,
"addr_span_bytes": 40,
"inst_name": "espi_regs",
"addr_offset": 0,
"children": [
Expand Down Expand Up @@ -238,6 +238,26 @@
"desc": "MSB is bit 31"
}
]
},
{
"type": "reg",
"inst_name": "post_code_count",
"addr_offset": 36,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
{
"type": "field",
"inst_name": "count",
"lsb": 0,
"msb": 31,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": ""
}
]
}
]
}
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