diff --git a/hdl/ip/bsv/CommonFunctions.bsv b/hdl/ip/bsv/CommonFunctions.bsv index b13aa07e..c0615826 100644 --- a/hdl/ip/bsv/CommonFunctions.bsv +++ b/hdl/ip/bsv/CommonFunctions.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/CommonInterfaces.bsv b/hdl/ip/bsv/CommonInterfaces.bsv index 296a4111..8f0c6ef0 100644 --- a/hdl/ip/bsv/CommonInterfaces.bsv +++ b/hdl/ip/bsv/CommonInterfaces.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/Countdown.bsv b/hdl/ip/bsv/Countdown.bsv index 3dca6b1d..a213043b 100644 --- a/hdl/ip/bsv/Countdown.bsv +++ b/hdl/ip/bsv/Countdown.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/Debouncer.bsv b/hdl/ip/bsv/Debouncer.bsv index 174b9266..26f0ccbf 100644 --- a/hdl/ip/bsv/Debouncer.bsv +++ b/hdl/ip/bsv/Debouncer.bsv @@ -1,4 +1,3 @@ -// Copyright 2023 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/Deserializer8b10b.bsv b/hdl/ip/bsv/Deserializer8b10b.bsv index 940a1b8f..e8a1eab0 100644 --- a/hdl/ip/bsv/Deserializer8b10b.bsv +++ b/hdl/ip/bsv/Deserializer8b10b.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/Encoding8b10b.bsv b/hdl/ip/bsv/Encoding8b10b.bsv index ce8c17ec..61f99130 100644 --- a/hdl/ip/bsv/Encoding8b10b.bsv +++ b/hdl/ip/bsv/Encoding8b10b.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public License, // v. 2.0. If a copy of the MPL was not distributed with this file, You can diff --git a/hdl/ip/bsv/I2C/I2CBitController.bsv b/hdl/ip/bsv/I2C/I2CBitController.bsv index 858e5a2e..9b29e131 100644 --- a/hdl/ip/bsv/I2C/I2CBitController.bsv +++ b/hdl/ip/bsv/I2C/I2CBitController.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/I2C/I2CCore.bsv b/hdl/ip/bsv/I2C/I2CCore.bsv index 7d47e4ea..f8a1e449 100644 --- a/hdl/ip/bsv/I2C/I2CCore.bsv +++ b/hdl/ip/bsv/I2C/I2CCore.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/I2C/test/I2CCoreTests.bsv b/hdl/ip/bsv/I2C/test/I2CCoreTests.bsv index a2598ff9..da034453 100644 --- a/hdl/ip/bsv/I2C/test/I2CCoreTests.bsv +++ b/hdl/ip/bsv/I2C/test/I2CCoreTests.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/I2C/test/I2CPeripheralModel.bsv b/hdl/ip/bsv/I2C/test/I2CPeripheralModel.bsv index 1c386d18..788e6814 100644 --- a/hdl/ip/bsv/I2C/test/I2CPeripheralModel.bsv +++ b/hdl/ip/bsv/I2C/test/I2CPeripheralModel.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/InitialReset.bsv b/hdl/ip/bsv/InitialReset.bsv index dd6b299f..c3248164 100644 --- a/hdl/ip/bsv/InitialReset.bsv +++ b/hdl/ip/bsv/InitialReset.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/InitialReset.v b/hdl/ip/bsv/InitialReset.v index ac68d96f..5d403041 100644 --- a/hdl/ip/bsv/InitialReset.v +++ b/hdl/ip/bsv/InitialReset.v @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/MDIO/MDIO.bsv b/hdl/ip/bsv/MDIO/MDIO.bsv index d8a9809f..a6dfe08e 100644 --- a/hdl/ip/bsv/MDIO/MDIO.bsv +++ b/hdl/ip/bsv/MDIO/MDIO.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/MDIO/test/MDIOPeripheralModel.bsv b/hdl/ip/bsv/MDIO/test/MDIOPeripheralModel.bsv index 9318c7b0..8443b78b 100644 --- a/hdl/ip/bsv/MDIO/test/MDIOPeripheralModel.bsv +++ b/hdl/ip/bsv/MDIO/test/MDIOPeripheralModel.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/MDIO/test/MDIOTests.bsv b/hdl/ip/bsv/MDIO/test/MDIOTests.bsv index bf3c8714..af281f22 100644 --- a/hdl/ip/bsv/MDIO/test/MDIOTests.bsv +++ b/hdl/ip/bsv/MDIO/test/MDIOTests.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/PLL.bsv b/hdl/ip/bsv/PLL.bsv index 3cb295bf..58e4c916 100644 --- a/hdl/ip/bsv/PLL.bsv +++ b/hdl/ip/bsv/PLL.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/SchmittReg.bsv b/hdl/ip/bsv/SchmittReg.bsv index 7a9cfe87..188ac66f 100644 --- a/hdl/ip/bsv/SchmittReg.bsv +++ b/hdl/ip/bsv/SchmittReg.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/Serializer8b10b.bsv b/hdl/ip/bsv/Serializer8b10b.bsv index 66a9a61b..d6614f51 100644 --- a/hdl/ip/bsv/Serializer8b10b.bsv +++ b/hdl/ip/bsv/Serializer8b10b.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/Strobe.bsv b/hdl/ip/bsv/Strobe.bsv index 6d5fab32..013edf65 100644 --- a/hdl/ip/bsv/Strobe.bsv +++ b/hdl/ip/bsv/Strobe.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/TestUtils.bsv b/hdl/ip/bsv/TestUtils.bsv index 5ec49106..627e7a7c 100644 --- a/hdl/ip/bsv/TestUtils.bsv +++ b/hdl/ip/bsv/TestUtils.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/WriteOnceReg.bsv b/hdl/ip/bsv/WriteOnceReg.bsv index 0c5217c5..bffac390 100644 --- a/hdl/ip/bsv/WriteOnceReg.bsv +++ b/hdl/ip/bsv/WriteOnceReg.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/examples/TestPatternVideoSource.bsv b/hdl/ip/bsv/examples/TestPatternVideoSource.bsv index 4697cb46..6c70685b 100644 --- a/hdl/ip/bsv/examples/TestPatternVideoSource.bsv +++ b/hdl/ip/bsv/examples/TestPatternVideoSource.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/examples/test_pattern_video_source.cc b/hdl/ip/bsv/examples/test_pattern_video_source.cc index 3815b465..885af902 100644 --- a/hdl/ip/bsv/examples/test_pattern_video_source.cc +++ b/hdl/ip/bsv/examples/test_pattern_video_source.cc @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/ignition/ignition_controller.rdl b/hdl/ip/bsv/ignition/ignition_controller.rdl index fc7a068b..a2ba0175 100644 --- a/hdl/ip/bsv/ignition/ignition_controller.rdl +++ b/hdl/ip/bsv/ignition/ignition_controller.rdl @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/ECP5.bsv b/hdl/ip/bsv/interfaces/ECP5.bsv index 494d5429..6d2afebc 100644 --- a/hdl/ip/bsv/interfaces/ECP5.bsv +++ b/hdl/ip/bsv/interfaces/ECP5.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/ECP5PLL.v b/hdl/ip/bsv/interfaces/ECP5PLL.v index 44abf65c..37b450f6 100644 --- a/hdl/ip/bsv/interfaces/ECP5PLL.v +++ b/hdl/ip/bsv/interfaces/ECP5PLL.v @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/ICE40.bsv b/hdl/ip/bsv/interfaces/ICE40.bsv index 9bcc6c2b..802aee97 100644 --- a/hdl/ip/bsv/interfaces/ICE40.bsv +++ b/hdl/ip/bsv/interfaces/ICE40.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/SPI.bsv b/hdl/ip/bsv/interfaces/SPI.bsv index 6c120418..5da991a0 100644 --- a/hdl/ip/bsv/interfaces/SPI.bsv +++ b/hdl/ip/bsv/interfaces/SPI.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/video/TMDS.bsv b/hdl/ip/bsv/interfaces/video/TMDS.bsv index d1c0f9ca..77c61ce7 100644 --- a/hdl/ip/bsv/interfaces/video/TMDS.bsv +++ b/hdl/ip/bsv/interfaces/video/TMDS.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/video/TestPatternGenerator.bsv b/hdl/ip/bsv/interfaces/video/TestPatternGenerator.bsv index 11e6c13c..a37d4776 100644 --- a/hdl/ip/bsv/interfaces/video/TestPatternGenerator.bsv +++ b/hdl/ip/bsv/interfaces/video/TestPatternGenerator.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/video/Timing.bsv b/hdl/ip/bsv/interfaces/video/Timing.bsv index 9418d601..ecd631f5 100644 --- a/hdl/ip/bsv/interfaces/video/Timing.bsv +++ b/hdl/ip/bsv/interfaces/video/Timing.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/video/Transmitter.bsv b/hdl/ip/bsv/interfaces/video/Transmitter.bsv index 81c89ab9..b1e65bfd 100644 --- a/hdl/ip/bsv/interfaces/video/Transmitter.bsv +++ b/hdl/ip/bsv/interfaces/video/Transmitter.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/video/video_source_validation.cc b/hdl/ip/bsv/interfaces/video/video_source_validation.cc index 62519620..5c2d51b8 100644 --- a/hdl/ip/bsv/interfaces/video/video_source_validation.cc +++ b/hdl/ip/bsv/interfaces/video/video_source_validation.cc @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/interfaces/video/video_source_validation.h b/hdl/ip/bsv/interfaces/video/video_source_validation.h index 4da5645c..759afe69 100644 --- a/hdl/ip/bsv/interfaces/video/video_source_validation.h +++ b/hdl/ip/bsv/interfaces/video/video_source_validation.h @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/power_rail/PowerRail.bsv b/hdl/ip/bsv/power_rail/PowerRail.bsv index f5501cb1..07249632 100644 --- a/hdl/ip/bsv/power_rail/PowerRail.bsv +++ b/hdl/ip/bsv/power_rail/PowerRail.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/test/Encoding8b10bTests.bsv b/hdl/ip/bsv/test/Encoding8b10bTests.bsv index 14e4c99d..8a5ee12b 100644 --- a/hdl/ip/bsv/test/Encoding8b10bTests.bsv +++ b/hdl/ip/bsv/test/Encoding8b10bTests.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/bsv/test_buck2/Countdown.bsv b/hdl/ip/bsv/test_buck2/Countdown.bsv index 3dca6b1d..a213043b 100644 --- a/hdl/ip/bsv/test_buck2/Countdown.bsv +++ b/hdl/ip/bsv/test_buck2/Countdown.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/ip/vhd/8b10b/helper_8b10b_pkg.vhd b/hdl/ip/vhd/8b10b/helper_8b10b_pkg.vhd index 662521a4..8b6be3b6 100644 --- a/hdl/ip/vhd/8b10b/helper_8b10b_pkg.vhd +++ b/hdl/ip/vhd/8b10b/helper_8b10b_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/arb_mux_demux/arbiter.vhd b/hdl/ip/vhd/arb_mux_demux/arbiter.vhd index 535e2ff5..d2ba8b6e 100644 --- a/hdl/ip/vhd/arb_mux_demux/arbiter.vhd +++ b/hdl/ip/vhd/arb_mux_demux/arbiter.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/arb_mux_demux/arbiter_pkg.vhd b/hdl/ip/vhd/arb_mux_demux/arbiter_pkg.vhd index f2151fa4..19025cf1 100644 --- a/hdl/ip/vhd/arb_mux_demux/arbiter_pkg.vhd +++ b/hdl/ip/vhd/arb_mux_demux/arbiter_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company --! Common shared information for arbiters package arbiter_pkg is diff --git a/hdl/ip/vhd/arb_mux_demux/sims/arbiter_sim_pkg.vhd b/hdl/ip/vhd/arb_mux_demux/sims/arbiter_sim_pkg.vhd index 904990a1..1a5e6587 100644 --- a/hdl/ip/vhd/arb_mux_demux/sims/arbiter_sim_pkg.vhd +++ b/hdl/ip/vhd/arb_mux_demux/sims/arbiter_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/arb_mux_demux/sims/arbiter_tb.vhd b/hdl/ip/vhd/arb_mux_demux/sims/arbiter_tb.vhd index 6c4aa2a6..18d193d4 100644 --- a/hdl/ip/vhd/arb_mux_demux/sims/arbiter_tb.vhd +++ b/hdl/ip/vhd/arb_mux_demux/sims/arbiter_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/arb_mux_demux/sims/arbiter_th.vhd b/hdl/ip/vhd/arb_mux_demux/sims/arbiter_th.vhd index 73ad7a73..9e298eef 100644 --- a/hdl/ip/vhd/arb_mux_demux/sims/arbiter_th.vhd +++ b/hdl/ip/vhd/arb_mux_demux/sims/arbiter_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/axi_blocks/axil8_resizer.vhd b/hdl/ip/vhd/axi_blocks/axil8_resizer.vhd index 965d2a27..f077b878 100644 --- a/hdl/ip/vhd/axi_blocks/axil8_resizer.vhd +++ b/hdl/ip/vhd/axi_blocks/axil8_resizer.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/axi_blocks/axil_common_pkg.vhd b/hdl/ip/vhd/axi_blocks/axil_common_pkg.vhd index e5dec3d0..aafd8110 100644 --- a/hdl/ip/vhd/axi_blocks/axil_common_pkg.vhd +++ b/hdl/ip/vhd/axi_blocks/axil_common_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/axi_blocks/axil_interconnect.vhd b/hdl/ip/vhd/axi_blocks/axil_interconnect.vhd index 15df1a78..2eb8b97f 100644 --- a/hdl/ip/vhd/axi_blocks/axil_interconnect.vhd +++ b/hdl/ip/vhd/axi_blocks/axil_interconnect.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/axi_blocks/axil_interconnect_2k8.vhd b/hdl/ip/vhd/axi_blocks/axil_interconnect_2k8.vhd index ce20da19..c2d6a247 100644 --- a/hdl/ip/vhd/axi_blocks/axil_interconnect_2k8.vhd +++ b/hdl/ip/vhd/axi_blocks/axil_interconnect_2k8.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/axi_blocks/axil_target_txn.vhd b/hdl/ip/vhd/axi_blocks/axil_target_txn.vhd index a4bb9a5d..44506bef 100644 --- a/hdl/ip/vhd/axi_blocks/axil_target_txn.vhd +++ b/hdl/ip/vhd/axi_blocks/axil_target_txn.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/axi_blocks/axilite_if_2k19_helper_pkg.vhd b/hdl/ip/vhd/axi_blocks/axilite_if_2k19_helper_pkg.vhd index f6cf719a..6fb36cfb 100644 --- a/hdl/ip/vhd/axi_blocks/axilite_if_2k19_helper_pkg.vhd +++ b/hdl/ip/vhd/axi_blocks/axilite_if_2k19_helper_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/axi_blocks/axilite_if_2k19_pkg.vhd b/hdl/ip/vhd/axi_blocks/axilite_if_2k19_pkg.vhd index 5ae85682..4a4e7034 100644 --- a/hdl/ip/vhd/axi_blocks/axilite_if_2k19_pkg.vhd +++ b/hdl/ip/vhd/axi_blocks/axilite_if_2k19_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/axi_blocks/axilite_if_2k8_pkg.vhd b/hdl/ip/vhd/axi_blocks/axilite_if_2k8_pkg.vhd index 7ca838a7..cc2c918d 100644 --- a/hdl/ip/vhd/axi_blocks/axilite_if_2k8_pkg.vhd +++ b/hdl/ip/vhd/axi_blocks/axilite_if_2k8_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/axi_blocks/axist_if_2k19_pkg.vhd b/hdl/ip/vhd/axi_blocks/axist_if_2k19_pkg.vhd index b1e97dc0..c06fefd5 100644 --- a/hdl/ip/vhd/axi_blocks/axist_if_2k19_pkg.vhd +++ b/hdl/ip/vhd/axi_blocks/axist_if_2k19_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/common/countdown/countdown.vhd b/hdl/ip/vhd/common/countdown/countdown.vhd index 757183c9..e080dd4a 100644 --- a/hdl/ip/vhd/common/countdown/countdown.vhd +++ b/hdl/ip/vhd/common/countdown/countdown.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- A general purpose counter block which counts down from a supplied `count` to zero. `done is not -- registered and will be asserted immediately when the internal count is at zero. Control priority diff --git a/hdl/ip/vhd/common/countdown/sims/countdown_tb.vhd b/hdl/ip/vhd/common/countdown/sims/countdown_tb.vhd index 27245e93..866bdc32 100644 --- a/hdl/ip/vhd/common/countdown/sims/countdown_tb.vhd +++ b/hdl/ip/vhd/common/countdown/sims/countdown_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/common/countdown/sims/countdown_th.vhd b/hdl/ip/vhd/common/countdown/sims/countdown_th.vhd index 46f6c3a3..cf7ad87f 100644 --- a/hdl/ip/vhd/common/countdown/sims/countdown_th.vhd +++ b/hdl/ip/vhd/common/countdown/sims/countdown_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/common/interfaces/tristate_if_pkg.vhd b/hdl/ip/vhd/common/interfaces/tristate_if_pkg.vhd index 78043e64..48ed63ed 100644 --- a/hdl/ip/vhd/common/interfaces/tristate_if_pkg.vhd +++ b/hdl/ip/vhd/common/interfaces/tristate_if_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- This package relies on the VHDL 2019 feature for "interfaces" diff --git a/hdl/ip/vhd/common/strobe/sims/strobe_tb.vhd b/hdl/ip/vhd/common/strobe/sims/strobe_tb.vhd index 4003f654..7a78f112 100644 --- a/hdl/ip/vhd/common/strobe/sims/strobe_tb.vhd +++ b/hdl/ip/vhd/common/strobe/sims/strobe_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/common/strobe/sims/strobe_th.vhd b/hdl/ip/vhd/common/strobe/sims/strobe_th.vhd index 020f5fdc..0959d968 100644 --- a/hdl/ip/vhd/common/strobe/sims/strobe_th.vhd +++ b/hdl/ip/vhd/common/strobe/sims/strobe_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/common/strobe/strobe.vhd b/hdl/ip/vhd/common/strobe/strobe.vhd index 04ca0a36..4b27adb4 100644 --- a/hdl/ip/vhd/common/strobe/strobe.vhd +++ b/hdl/ip/vhd/common/strobe/strobe.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- A small block that will generate a single `clk` pulse on `strobe` every `TICKS` cycles of `clk`. diff --git a/hdl/ip/vhd/common/utils/calc_pkg.vhd b/hdl/ip/vhd/common/utils/calc_pkg.vhd index de6a66d1..1eb7018a 100644 --- a/hdl/ip/vhd/common/utils/calc_pkg.vhd +++ b/hdl/ip/vhd/common/utils/calc_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/common/utils/sims/utilities_tb.vhd b/hdl/ip/vhd/common/utils/sims/utilities_tb.vhd index b80c66a5..4e67de44 100644 --- a/hdl/ip/vhd/common/utils/sims/utilities_tb.vhd +++ b/hdl/ip/vhd/common/utils/sims/utilities_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/common/utils/time_pkg.vhd b/hdl/ip/vhd/common/utils/time_pkg.vhd index 2374065a..22855e68 100644 --- a/hdl/ip/vhd/common/utils/time_pkg.vhd +++ b/hdl/ip/vhd/common/utils/time_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/common/utils/transforms_pkg.vhd b/hdl/ip/vhd/common/utils/transforms_pkg.vhd index 1373cacd..b2eb6033 100644 --- a/hdl/ip/vhd/common/utils/transforms_pkg.vhd +++ b/hdl/ip/vhd/common/utils/transforms_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/crc/crc8atm_8wide.vhd b/hdl/ip/vhd/crc/crc8atm_8wide.vhd index d5e055a0..2de2c318 100644 --- a/hdl/ip/vhd/crc/crc8atm_8wide.vhd +++ b/hdl/ip/vhd/crc/crc8atm_8wide.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/crc/crc8autostar_8wide.vhd b/hdl/ip/vhd/crc/crc8autostar_8wide.vhd index 3ba46167..dba568ca 100644 --- a/hdl/ip/vhd/crc/crc8autostar_8wide.vhd +++ b/hdl/ip/vhd/crc/crc8autostar_8wide.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/crc/crc_sim_pkg.vhd b/hdl/ip/vhd/crc/crc_sim_pkg.vhd index e7597620..6da6ea5f 100644 --- a/hdl/ip/vhd/crc/crc_sim_pkg.vhd +++ b/hdl/ip/vhd/crc/crc_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- As a reminder when making these: -- Highest term is xor'd with next input bit and result is fed back into the diff --git a/hdl/ip/vhd/espi/espi_spec_regs.rdl b/hdl/ip/vhd/espi/espi_spec_regs.rdl index 86f94dc6..e6629948 100644 --- a/hdl/ip/vhd/espi/espi_spec_regs.rdl +++ b/hdl/ip/vhd/espi/espi_spec_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2024 Oxide Computer Company // This is SystemRDL description of the sw-accesible registers in the Gimlet // Sequencer FPGA. diff --git a/hdl/ip/vhd/espi/espi_spec_regs.vhd b/hdl/ip/vhd/espi/espi_spec_regs.vhd index fe64ba78..b8ef0eab 100644 --- a/hdl/ip/vhd/espi/espi_spec_regs.vhd +++ b/hdl/ip/vhd/espi/espi_spec_regs.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/espi/espi_target_top.vhd b/hdl/ip/vhd/espi/espi_target_top.vhd index b52fdb22..15dea0a9 100644 --- a/hdl/ip/vhd/espi/espi_target_top.vhd +++ b/hdl/ip/vhd/espi/espi_target_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Top level of the eSPI target block. This block is responsible for -- basic synchronization of the eSPI signals, and instantiation of the diff --git a/hdl/ip/vhd/espi/flash_channel/flash_channel.vhd b/hdl/ip/vhd/espi/flash_channel/flash_channel.vhd index f3f10909..ea207062 100644 --- a/hdl/ip/vhd/espi/flash_channel/flash_channel.vhd +++ b/hdl/ip/vhd/espi/flash_channel/flash_channel.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- This block provides the transaction queueing and management for the flash -- channel. It is responsible for queueing up transactions, issuing commands to diff --git a/hdl/ip/vhd/espi/flash_channel/flash_channel_pkg.vhd b/hdl/ip/vhd/espi/flash_channel/flash_channel_pkg.vhd index 382db9c5..8f74038b 100644 --- a/hdl/ip/vhd/espi/flash_channel/flash_channel_pkg.vhd +++ b/hdl/ip/vhd/espi/flash_channel/flash_channel_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/espi/link_layer/alert_gen.vhd b/hdl/ip/vhd/espi/link_layer/alert_gen.vhd index 50931741..7ce92f69 100644 --- a/hdl/ip/vhd/espi/link_layer/alert_gen.vhd +++ b/hdl/ip/vhd/espi/link_layer/alert_gen.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- This block manages the state machine for the in-band alert mechanism. -- Logic in the slow domain monitors when an alert is needed and this block diff --git a/hdl/ip/vhd/espi/link_layer/cmd_sizer.vhd b/hdl/ip/vhd/espi/link_layer/cmd_sizer.vhd index 78603337..376e8d98 100644 --- a/hdl/ip/vhd/espi/link_layer/cmd_sizer.vhd +++ b/hdl/ip/vhd/espi/link_layer/cmd_sizer.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- In the fast domain, before we've done full packet parsing, we need -- some basic parsing to determine the size of the packet and when the diff --git a/hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd b/hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd index fd3670ad..07550362 100644 --- a/hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd +++ b/hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- This block allows an SP-interface to issue eSPI commands to the transaction -- layer and receive responses. It is used for debugging and testing purposes diff --git a/hdl/ip/vhd/espi/link_layer/link_layer.vhd b/hdl/ip/vhd/espi/link_layer/link_layer.vhd index 00b24bb2..c3517bb8 100644 --- a/hdl/ip/vhd/espi/link_layer/link_layer.vhd +++ b/hdl/ip/vhd/espi/link_layer/link_layer.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- The main qspi link layer block for this target, including the -- link-layer transaction management and FIFO interfaces to/from diff --git a/hdl/ip/vhd/espi/link_layer/link_layer_pkg.vhd b/hdl/ip/vhd/espi/link_layer/link_layer_pkg.vhd index e68cef0c..67399696 100644 --- a/hdl/ip/vhd/espi/link_layer/link_layer_pkg.vhd +++ b/hdl/ip/vhd/espi/link_layer/link_layer_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/espi/link_layer/qspi_link_layer_pkg.vhd b/hdl/ip/vhd/espi/link_layer/qspi_link_layer_pkg.vhd index 9986afef..6bf026bb 100644 --- a/hdl/ip/vhd/espi/link_layer/qspi_link_layer_pkg.vhd +++ b/hdl/ip/vhd/espi/link_layer/qspi_link_layer_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/espi/peripheral_channel/uart_channel_pkg.vhd b/hdl/ip/vhd/espi/peripheral_channel/uart_channel_pkg.vhd index afac2f4e..3e8f08c2 100644 --- a/hdl/ip/vhd/espi/peripheral_channel/uart_channel_pkg.vhd +++ b/hdl/ip/vhd/espi/peripheral_channel/uart_channel_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd b/hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd index 9c9f9e74..ea05fff2 100644 --- a/hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd +++ b/hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- This block provides the transaction queueing and management for the peripheral -- channel. It is responsible for queueing up transactions, issuing bytes to diff --git a/hdl/ip/vhd/espi/sims/espi_tb.vhd b/hdl/ip/vhd/espi/sims/espi_tb.vhd index cd17daa4..55b4392d 100644 --- a/hdl/ip/vhd/espi/sims/espi_tb.vhd +++ b/hdl/ip/vhd/espi/sims/espi_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/espi/sims/espi_tb_pkg.vhd b/hdl/ip/vhd/espi/sims/espi_tb_pkg.vhd index f1b3365b..793da338 100644 --- a/hdl/ip/vhd/espi/sims/espi_tb_pkg.vhd +++ b/hdl/ip/vhd/espi/sims/espi_tb_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- This package contains types and helper functions for building testbenches -- around the espi protocol. Functions and procedures in this block are "generic" diff --git a/hdl/ip/vhd/espi/sims/espi_th.vhd b/hdl/ip/vhd/espi/sims/espi_th.vhd index d3fd4708..61f3d3e6 100644 --- a/hdl/ip/vhd/espi/sims/espi_th.vhd +++ b/hdl/ip/vhd/espi/sims/espi_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/espi/sims/models/espi_controller_vc_pkg.vhd b/hdl/ip/vhd/espi/sims/models/espi_controller_vc_pkg.vhd index b99a7e92..a019582b 100644 --- a/hdl/ip/vhd/espi/sims/models/espi_controller_vc_pkg.vhd +++ b/hdl/ip/vhd/espi/sims/models/espi_controller_vc_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/espi/sims/models/espi_dbg_vc_pkg.vhd b/hdl/ip/vhd/espi/sims/models/espi_dbg_vc_pkg.vhd index ecd4f0a3..dcbef18b 100644 --- a/hdl/ip/vhd/espi/sims/models/espi_dbg_vc_pkg.vhd +++ b/hdl/ip/vhd/espi/sims/models/espi_dbg_vc_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/espi/sims/models/fake_flash_txn_mgr.vhd b/hdl/ip/vhd/espi/sims/models/fake_flash_txn_mgr.vhd index 3de7b6c9..47f678bc 100644 --- a/hdl/ip/vhd/espi/sims/models/fake_flash_txn_mgr.vhd +++ b/hdl/ip/vhd/espi/sims/models/fake_flash_txn_mgr.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- This is a fake flash transaction manager used to test the ESPI interface. -- Rather than pulling in a whole flash controller for sim, we just mock the diff --git a/hdl/ip/vhd/espi/sys_regs/espi_regs.rdl b/hdl/ip/vhd/espi/sys_regs/espi_regs.rdl index 73d93d05..bc548c2a 100644 --- a/hdl/ip/vhd/espi/sys_regs/espi_regs.rdl +++ b/hdl/ip/vhd/espi/sys_regs/espi_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2024 Oxide Computer Company // This is SystemRDL description of the sw-accessible registers in the Gimlet // Sequencer FPGA. diff --git a/hdl/ip/vhd/espi/sys_regs/espi_regs.vhd b/hdl/ip/vhd/espi/sys_regs/espi_regs.vhd index 5593c9ef..ab4ddab9 100644 --- a/hdl/ip/vhd/espi/sys_regs/espi_regs.vhd +++ b/hdl/ip/vhd/espi/sys_regs/espi_regs.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- SP-accessible registers for the eSPI block diff --git a/hdl/ip/vhd/espi/sys_regs/espi_spec_regs_view_pkg.vhd b/hdl/ip/vhd/espi/sys_regs/espi_spec_regs_view_pkg.vhd index 1eb4ed1a..1ce117a6 100644 --- a/hdl/ip/vhd/espi/sys_regs/espi_spec_regs_view_pkg.vhd +++ b/hdl/ip/vhd/espi/sys_regs/espi_spec_regs_view_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Composite record and views for exposing eSPI spec register -- values as a read-only interface in the sys_regs address space. diff --git a/hdl/ip/vhd/espi/sys_regs/sp5_post_code_pkg.vhd b/hdl/ip/vhd/espi/sys_regs/sp5_post_code_pkg.vhd index cd42ac2b..d3793cdd 100644 --- a/hdl/ip/vhd/espi/sys_regs/sp5_post_code_pkg.vhd +++ b/hdl/ip/vhd/espi/sys_regs/sp5_post_code_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2026 Oxide Computer Company -- Composite record and views for exposing eSPI spec register -- values as a read-only interface in the sys_regs address space. diff --git a/hdl/ip/vhd/espi/txn_layer/command_processor.vhd b/hdl/ip/vhd/espi/txn_layer/command_processor.vhd index e11f6f92..7504fc31 100644 --- a/hdl/ip/vhd/espi/txn_layer/command_processor.vhd +++ b/hdl/ip/vhd/espi/txn_layer/command_processor.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Main command parser and processing for the eSPI transaction layer. -- Pulls from a FIFO from the link layer or debug layer and processes diff --git a/hdl/ip/vhd/espi/txn_layer/espi_base_types_pkg.vhd b/hdl/ip/vhd/espi/txn_layer/espi_base_types_pkg.vhd index 6688f6e8..78a69676 100644 --- a/hdl/ip/vhd/espi/txn_layer/espi_base_types_pkg.vhd +++ b/hdl/ip/vhd/espi/txn_layer/espi_base_types_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/espi/txn_layer/espi_protocol_pkg.vhd b/hdl/ip/vhd/espi/txn_layer/espi_protocol_pkg.vhd index 3e12d985..43a858fa 100644 --- a/hdl/ip/vhd/espi/txn_layer/espi_protocol_pkg.vhd +++ b/hdl/ip/vhd/espi/txn_layer/espi_protocol_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/espi/txn_layer/link_to_txn_bridge.vhd b/hdl/ip/vhd/espi/txn_layer/link_to_txn_bridge.vhd index c841097c..4931270d 100644 --- a/hdl/ip/vhd/espi/txn_layer/link_to_txn_bridge.vhd +++ b/hdl/ip/vhd/espi/txn_layer/link_to_txn_bridge.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Provides clock-crossing between the link layer and transaction layer -- and provides the debug mux for disconnecting the link layer and using diff --git a/hdl/ip/vhd/espi/txn_layer/response_processor.vhd b/hdl/ip/vhd/espi/txn_layer/response_processor.vhd index 7dcabe82..01d74ec7 100644 --- a/hdl/ip/vhd/espi/txn_layer/response_processor.vhd +++ b/hdl/ip/vhd/espi/txn_layer/response_processor.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Determine and coordinate responses back to the link layer depending on the -- current command opcode and availablilty of data to send back. diff --git a/hdl/ip/vhd/espi/txn_layer/txn_layer_top.vhd b/hdl/ip/vhd/espi/txn_layer/txn_layer_top.vhd index 4b3a427a..54d119c4 100644 --- a/hdl/ip/vhd/espi/txn_layer/txn_layer_top.vhd +++ b/hdl/ip/vhd/espi/txn_layer/txn_layer_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Structural wrapper for the transaction layer and the various channel blocks diff --git a/hdl/ip/vhd/espi/vwire_channel/vwire_block.vhd b/hdl/ip/vhd/espi/vwire_channel/vwire_block.vhd index e8921c9a..e04d704a 100644 --- a/hdl/ip/vhd/espi/vwire_channel/vwire_block.vhd +++ b/hdl/ip/vhd/espi/vwire_channel/vwire_block.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- eSPI Virtual Wire Channel implementation -- While we do nothing with this today, the mask-rom in the SP5 diff --git a/hdl/ip/vhd/espi/vwire_channel/vwire_regs.rdl b/hdl/ip/vhd/espi/vwire_channel/vwire_regs.rdl index 3999ef14..c5c7c5bf 100644 --- a/hdl/ip/vhd/espi/vwire_channel/vwire_regs.rdl +++ b/hdl/ip/vhd/espi/vwire_channel/vwire_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2024 Oxide Computer Company // This is SystemRDL description of the sw-accesible registers in the Gimlet // Sequencer FPGA. diff --git a/hdl/ip/vhd/fifos/sims/fifos_sim_pkg.vhd b/hdl/ip/vhd/fifos/sims/fifos_sim_pkg.vhd index 7228437a..9e68a23b 100644 --- a/hdl/ip/vhd/fifos/sims/fifos_sim_pkg.vhd +++ b/hdl/ip/vhd/fifos/sims/fifos_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/fifos/sims/fifos_tb.vhd b/hdl/ip/vhd/fifos/sims/fifos_tb.vhd index 2311c462..a965d686 100644 --- a/hdl/ip/vhd/fifos/sims/fifos_tb.vhd +++ b/hdl/ip/vhd/fifos/sims/fifos_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/fifos/sims/fifos_th.vhd b/hdl/ip/vhd/fifos/sims/fifos_th.vhd index c11b75e7..0464b538 100644 --- a/hdl/ip/vhd/fifos/sims/fifos_th.vhd +++ b/hdl/ip/vhd/fifos/sims/fifos_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/fmc_if/model/stm32h7_fmc_model.vhd b/hdl/ip/vhd/fmc_if/model/stm32h7_fmc_model.vhd index dec61232..010b9ba0 100644 --- a/hdl/ip/vhd/fmc_if/model/stm32h7_fmc_model.vhd +++ b/hdl/ip/vhd/fmc_if/model/stm32h7_fmc_model.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company --! FMC controller model based on ST's RM0433 rev8 --! figures 115 and 116 for simulation of the diff --git a/hdl/ip/vhd/fmc_if/model/stm32h7_fmc_sim_pkg.vhd b/hdl/ip/vhd/fmc_if/model/stm32h7_fmc_sim_pkg.vhd index b9af1e61..405eb727 100644 --- a/hdl/ip/vhd/fmc_if/model/stm32h7_fmc_sim_pkg.vhd +++ b/hdl/ip/vhd/fmc_if/model/stm32h7_fmc_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company --! Bus master model based on ST's RM0433 --! figures 115 and 116 diff --git a/hdl/ip/vhd/fmc_if/sims/fmc_tb.vhd b/hdl/ip/vhd/fmc_if/sims/fmc_tb.vhd index bcffb3e5..2f3219f2 100644 --- a/hdl/ip/vhd/fmc_if/sims/fmc_tb.vhd +++ b/hdl/ip/vhd/fmc_if/sims/fmc_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/fmc_if/sims/fmc_tb_pkg.vhd b/hdl/ip/vhd/fmc_if/sims/fmc_tb_pkg.vhd index 11b5f58d..4d608672 100644 --- a/hdl/ip/vhd/fmc_if/sims/fmc_tb_pkg.vhd +++ b/hdl/ip/vhd/fmc_if/sims/fmc_tb_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company --! Bus master model based on ST's RM0433 --! figures 115 and 116 diff --git a/hdl/ip/vhd/fmc_if/sims/fmc_th.vhd b/hdl/ip/vhd/fmc_if/sims/fmc_th.vhd index df4e76c7..48ae6402 100644 --- a/hdl/ip/vhd/fmc_if/sims/fmc_th.vhd +++ b/hdl/ip/vhd/fmc_if/sims/fmc_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/fmc_if/stm32h7_fmc_target.vhd b/hdl/ip/vhd/fmc_if/stm32h7_fmc_target.vhd index 22a202e0..f23bbe9c 100644 --- a/hdl/ip/vhd/fmc_if/stm32h7_fmc_target.vhd +++ b/hdl/ip/vhd/fmc_if/stm32h7_fmc_target.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company --! This block provides an FMC target interface from the STM32H7's --! local bus, crosses clock domains into the FPGA's core logic diff --git a/hdl/ip/vhd/fmc_if/stm32h7_fmc_target_pkg.vhd b/hdl/ip/vhd/fmc_if/stm32h7_fmc_target_pkg.vhd index bff2c80a..9e9a1063 100644 --- a/hdl/ip/vhd/fmc_if/stm32h7_fmc_target_pkg.vhd +++ b/hdl/ip/vhd/fmc_if/stm32h7_fmc_target_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/common/i2c_common_pkg.vhd b/hdl/ip/vhd/i2c/common/i2c_common_pkg.vhd index 309ece94..4f9915be 100644 --- a/hdl/ip/vhd/i2c/common/i2c_common_pkg.vhd +++ b/hdl/ip/vhd/i2c/common/i2c_common_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/common/i2c_glitch_filter.vhd b/hdl/ip/vhd/i2c/common/i2c_glitch_filter.vhd index 1009a003..918b4f88 100644 --- a/hdl/ip/vhd/i2c/common/i2c_glitch_filter.vhd +++ b/hdl/ip/vhd/i2c/common/i2c_glitch_filter.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Simple i2c glitch filtering for targets I2C spec -- This block incurs a delay of 1 sync cycle and n filter cycles diff --git a/hdl/ip/vhd/i2c/controller/i2c_ctrl_top.vhd b/hdl/ip/vhd/i2c/controller/i2c_ctrl_top.vhd index 53749c7d..a4c4600c 100644 --- a/hdl/ip/vhd/i2c/controller/i2c_ctrl_top.vhd +++ b/hdl/ip/vhd/i2c/controller/i2c_ctrl_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/controller/link_layer/i2c_ctrl_link_layer.vhd b/hdl/ip/vhd/i2c/controller/link_layer/i2c_ctrl_link_layer.vhd index 2761f0fe..111afae7 100644 --- a/hdl/ip/vhd/i2c/controller/link_layer/i2c_ctrl_link_layer.vhd +++ b/hdl/ip/vhd/i2c/controller/link_layer/i2c_ctrl_link_layer.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- I2C Control Link Layer -- diff --git a/hdl/ip/vhd/i2c/controller/regs/i2c_ctrl_regs.rdl b/hdl/ip/vhd/i2c/controller/regs/i2c_ctrl_regs.rdl index d21dd6f9..5e47c2d5 100644 --- a/hdl/ip/vhd/i2c/controller/regs/i2c_ctrl_regs.rdl +++ b/hdl/ip/vhd/i2c/controller/regs/i2c_ctrl_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2024 Oxide Computer Company // This is a SystemRDL description of the SW-accessible registers for the I2C controller. addrmap i2c_ctrl_regs { diff --git a/hdl/ip/vhd/i2c/controller/regs/i2c_ctrl_regs.vhd b/hdl/ip/vhd/i2c/controller/regs/i2c_ctrl_regs.vhd index 38e7e1a8..3a52e8ec 100644 --- a/hdl/ip/vhd/i2c/controller/regs/i2c_ctrl_regs.vhd +++ b/hdl/ip/vhd/i2c/controller/regs/i2c_ctrl_regs.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- AXI-accessible registers for the I2C block diff --git a/hdl/ip/vhd/i2c/controller/txn_layer/i2c_ctrl_txn_layer.vhd b/hdl/ip/vhd/i2c/controller/txn_layer/i2c_ctrl_txn_layer.vhd index f79d8951..a067890d 100644 --- a/hdl/ip/vhd/i2c/controller/txn_layer/i2c_ctrl_txn_layer.vhd +++ b/hdl/ip/vhd/i2c/controller/txn_layer/i2c_ctrl_txn_layer.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- I2C Controller Transaction Layer -- diff --git a/hdl/ip/vhd/i2c/controller/txn_layer/sims/i2c_ctrl_txn_layer_tb.vhd b/hdl/ip/vhd/i2c/controller/txn_layer/sims/i2c_ctrl_txn_layer_tb.vhd index 471a81f6..845ee095 100644 --- a/hdl/ip/vhd/i2c/controller/txn_layer/sims/i2c_ctrl_txn_layer_tb.vhd +++ b/hdl/ip/vhd/i2c/controller/txn_layer/sims/i2c_ctrl_txn_layer_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/controller/txn_layer/sims/i2c_ctrl_txn_layer_th.vhd b/hdl/ip/vhd/i2c/controller/txn_layer/sims/i2c_ctrl_txn_layer_th.vhd index a403b37a..f686f493 100644 --- a/hdl/ip/vhd/i2c/controller/txn_layer/sims/i2c_ctrl_txn_layer_th.vhd +++ b/hdl/ip/vhd/i2c/controller/txn_layer/sims/i2c_ctrl_txn_layer_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_function.vhd b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_function.vhd index 695a5a5a..0f9afe1c 100644 --- a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_function.vhd +++ b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_function.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_pkg.vhd b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_pkg.vhd index c605014a..3f099f7a 100644 --- a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_pkg.vhd +++ b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_regs.rdl b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_regs.rdl index 0871a393..434eb98a 100644 --- a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_regs.rdl +++ b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // This is SystemRDL description of emulated i2c mux registers regfile pca9506_raw_regs #(longint unsigned SIZE = 8) { default regwidth = SIZE; diff --git a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_regs.vhd b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_regs.vhd index 3de59599..6fe2043d 100644 --- a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_regs.vhd +++ b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_regs.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_top.vhd b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_top.vhd index 4fbc2e15..7dfd127c 100644 --- a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_top.vhd +++ b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/pca9506_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- This provides an I/O expander sw-compatible with the PCA9506 memory map -- upper level logic will decide whether or not to use the tri-state signals diff --git a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_sim_pkg.vhd b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_sim_pkg.vhd index c4348dfb..05793550 100644 --- a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_sim_pkg.vhd +++ b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_tb.vhd b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_tb.vhd index 5b8c724b..2b94aa45 100644 --- a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_tb.vhd +++ b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_th.vhd b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_th.vhd index d75b4816..2186465f 100644 --- a/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_th.vhd +++ b/hdl/ip/vhd/i2c/io_expanders/PCA9506ish/sims/i2c_pca9506ish_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/muxes/PCA9545ish/emulated_pca9545_regs.rdl b/hdl/ip/vhd/i2c/muxes/PCA9545ish/emulated_pca9545_regs.rdl index d3718d11..b4892a19 100644 --- a/hdl/ip/vhd/i2c/muxes/PCA9545ish/emulated_pca9545_regs.rdl +++ b/hdl/ip/vhd/i2c/muxes/PCA9545ish/emulated_pca9545_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // This is SystemRDL description of emulated i2c mux registers addrmap emulated_pca9545_regs { diff --git a/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545_pkg.vhd b/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545_pkg.vhd index cd4edbd5..c4b54c0c 100644 --- a/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545_pkg.vhd +++ b/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_function.vhd b/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_function.vhd index fbbdd37e..6efa516e 100644 --- a/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_function.vhd +++ b/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_function.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- This block provides the logic and control register for the i2c mux -- as well as the response logic for interfacing with the i2c_target_phy block diff --git a/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_top.vhd b/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_top.vhd index 125cd03d..bbaf7b5f 100644 --- a/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_top.vhd +++ b/hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- This provides the digital portion of a 4 channel i2c mux, based on the software interface -- of a PCA9545. Currently no interrupts are supported as we don't need them so those diff --git a/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_sim_pkg.vhd b/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_sim_pkg.vhd index aa7e8acc..ee684e68 100644 --- a/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_sim_pkg.vhd +++ b/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_tb.vhd b/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_tb.vhd index aa940dba..277e9f37 100644 --- a/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_tb.vhd +++ b/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_th.vhd b/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_th.vhd index ae9f52c3..a8757bf6 100644 --- a/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_th.vhd +++ b/hdl/ip/vhd/i2c/muxes/PCA9545ish/sims/i2c_pca9545ish_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_function.vhd b/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_function.vhd index 19559680..eaadf532 100644 --- a/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_function.vhd +++ b/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_function.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- This block provides the logic and control register for the i2c mux -- as well as the response logic for interfacing with the i2c_target_phy block diff --git a/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_regs.rdl b/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_regs.rdl index 76d7c080..fa400f6f 100644 --- a/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_regs.rdl +++ b/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // This is SystemRDL description of emulated i2c mux registers addrmap oximux16_regs { diff --git a/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_top.vhd b/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_top.vhd index 48ed4f99..6f885e6b 100644 --- a/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_top.vhd +++ b/hdl/ip/vhd/i2c/muxes/oximux16/oximux16_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- This provides the digital portion of a 4 channel i2c mux, based on the software interface -- of a PCA9545. Currently no interrupts are supported as we don't need them so those diff --git a/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_sim_pkg.vhd b/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_sim_pkg.vhd index 276343b6..5034702b 100644 --- a/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_sim_pkg.vhd +++ b/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_tb.vhd b/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_tb.vhd index afa4d0e7..a076a04a 100644 --- a/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_tb.vhd +++ b/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_th.vhd b/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_th.vhd index e30c4824..01d164fb 100644 --- a/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_th.vhd +++ b/hdl/ip/vhd/i2c/muxes/oximux16/sims/oximux16_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/target/i2c_base_types_pkg.vhd b/hdl/ip/vhd/i2c/target/i2c_base_types_pkg.vhd index ef0996b1..3ae53e57 100644 --- a/hdl/ip/vhd/i2c/target/i2c_base_types_pkg.vhd +++ b/hdl/ip/vhd/i2c/target/i2c_base_types_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Shared base types for i2c components diff --git a/hdl/ip/vhd/i2c/target/i2c_phy_consolidator.vhd b/hdl/ip/vhd/i2c/target/i2c_phy_consolidator.vhd index 9b0e21bc..39fe2233 100644 --- a/hdl/ip/vhd/i2c/target/i2c_phy_consolidator.vhd +++ b/hdl/ip/vhd/i2c/target/i2c_phy_consolidator.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/target/i2c_target_phy.vhd b/hdl/ip/vhd/i2c/target/i2c_target_phy.vhd index 183b3943..7ce6faea 100644 --- a/hdl/ip/vhd/i2c/target/i2c_target_phy.vhd +++ b/hdl/ip/vhd/i2c/target/i2c_target_phy.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- This block provides an i2c-compliant "phy" for use with additional logic -- to create i2c target functions. It is intended to be generic and shareable diff --git a/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_sim_pkg.vhd b/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_sim_pkg.vhd index 66a44976..e060422a 100644 --- a/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_sim_pkg.vhd +++ b/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_tb.vhd b/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_tb.vhd index d258cb85..6be3348b 100644 --- a/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_tb.vhd +++ b/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_th.vhd b/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_th.vhd index f7379a87..de99eb31 100644 --- a/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_th.vhd +++ b/hdl/ip/vhd/i2c/target/sims/i2c_target_phy_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ice40primitives/ice40_pkg.vhd b/hdl/ip/vhd/ice40primitives/ice40_pkg.vhd index bd4b361f..9caf5e90 100644 --- a/hdl/ip/vhd/ice40primitives/ice40_pkg.vhd +++ b/hdl/ip/vhd/ice40primitives/ice40_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ignition/target/ibc_control.vhd b/hdl/ip/vhd/ignition/target/ibc_control.vhd index c725097e..c0e4fc43 100644 --- a/hdl/ip/vhd/ignition/target/ibc_control.vhd +++ b/hdl/ip/vhd/ignition/target/ibc_control.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Ignition is pretty simple. It can can turn on the IBC diff --git a/hdl/ip/vhd/ignition/target/ignition_io.vhd b/hdl/ip/vhd/ignition/target/ignition_io.vhd index 4d81ea59..ace7b8c3 100644 --- a/hdl/ip/vhd/ignition/target/ignition_io.vhd +++ b/hdl/ip/vhd/ignition/target/ignition_io.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ignition/target/ignition_pkg.vhd b/hdl/ip/vhd/ignition/target/ignition_pkg.vhd index 66de7395..f5e79322 100644 --- a/hdl/ip/vhd/ignition/target/ignition_pkg.vhd +++ b/hdl/ip/vhd/ignition/target/ignition_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ignition/target/ignition_status.vhd b/hdl/ip/vhd/ignition/target/ignition_status.vhd index 7914742a..c526585e 100644 --- a/hdl/ip/vhd/ignition/target/ignition_status.vhd +++ b/hdl/ip/vhd/ignition/target/ignition_status.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ignition/target/ignition_target_common.vhd b/hdl/ip/vhd/ignition/target/ignition_target_common.vhd index 616cf5b3..360e0587 100644 --- a/hdl/ip/vhd/ignition/target/ignition_target_common.vhd +++ b/hdl/ip/vhd/ignition/target/ignition_target_common.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ignition/target/rx_path/ignit_rx_pipe.vhd b/hdl/ip/vhd/ignition/target/rx_path/ignit_rx_pipe.vhd index 37867161..ff2917f6 100644 --- a/hdl/ip/vhd/ignition/target/rx_path/ignit_rx_pipe.vhd +++ b/hdl/ip/vhd/ignition/target/rx_path/ignit_rx_pipe.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/ignition/target/rx_path/pkt_parsing.vhd b/hdl/ip/vhd/ignition/target/rx_path/pkt_parsing.vhd index 4f1480f2..07bd4498 100644 --- a/hdl/ip/vhd/ignition/target/rx_path/pkt_parsing.vhd +++ b/hdl/ip/vhd/ignition/target/rx_path/pkt_parsing.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ignition/target/sims/ignition_controller_model.vhd b/hdl/ip/vhd/ignition/target/sims/ignition_controller_model.vhd index 4c788bba..92d8e107 100644 --- a/hdl/ip/vhd/ignition/target/sims/ignition_controller_model.vhd +++ b/hdl/ip/vhd/ignition/target/sims/ignition_controller_model.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- want to take a streaming interface with data (9bit, 8 data + control) -- generate IDLE sequences unless packets in-bound then send those diff --git a/hdl/ip/vhd/ignition/target/sims/ignition_sim_pkg.vhd b/hdl/ip/vhd/ignition/target/sims/ignition_sim_pkg.vhd index 1d6bd97e..dfb3c441 100644 --- a/hdl/ip/vhd/ignition/target/sims/ignition_sim_pkg.vhd +++ b/hdl/ip/vhd/ignition/target/sims/ignition_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ignition/target/sims/ignition_tgt_sim_tb.vhd b/hdl/ip/vhd/ignition/target/sims/ignition_tgt_sim_tb.vhd index 0163eec3..89e8f74c 100644 --- a/hdl/ip/vhd/ignition/target/sims/ignition_tgt_sim_tb.vhd +++ b/hdl/ip/vhd/ignition/target/sims/ignition_tgt_sim_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ignition/target/sims/ignition_tgt_sim_th.vhd b/hdl/ip/vhd/ignition/target/sims/ignition_tgt_sim_th.vhd index 467a2a08..ad717ad3 100644 --- a/hdl/ip/vhd/ignition/target/sims/ignition_tgt_sim_th.vhd +++ b/hdl/ip/vhd/ignition/target/sims/ignition_tgt_sim_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ignition/target/tx_path/ignition_tx.vhd b/hdl/ip/vhd/ignition/target/tx_path/ignition_tx.vhd index 46b6502c..3b8945c1 100644 --- a/hdl/ip/vhd/ignition/target/tx_path/ignition_tx.vhd +++ b/hdl/ip/vhd/ignition/target/tx_path/ignition_tx.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/info/info.vhd b/hdl/ip/vhd/info/info.vhd index 054cfaf8..ea816aa6 100644 --- a/hdl/ip/vhd/info/info.vhd +++ b/hdl/ip/vhd/info/info.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- 2019-compatible wrapper for basic board information registers diff --git a/hdl/ip/vhd/info/info_2k8.vhd b/hdl/ip/vhd/info/info_2k8.vhd index 1c59b163..ef64216e 100644 --- a/hdl/ip/vhd/info/info_2k8.vhd +++ b/hdl/ip/vhd/info/info_2k8.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Common register block for basic board information diff --git a/hdl/ip/vhd/info/info_regs.rdl b/hdl/ip/vhd/info/info_regs.rdl index 7236e666..e03c9855 100644 --- a/hdl/ip/vhd/info/info_regs.rdl +++ b/hdl/ip/vhd/info/info_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2024 Oxide Computer Company // This is SystemRDL description of the sw-accessible common board-info registers addrmap info_regs { diff --git a/hdl/ip/vhd/irq/irq_block.vhd b/hdl/ip/vhd/irq/irq_block.vhd index d67ed75e..fa1efe2a 100644 --- a/hdl/ip/vhd/irq/irq_block.vhd +++ b/hdl/ip/vhd/irq/irq_block.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2026 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ls_xcvr/aligner_10bk28_5.vhd b/hdl/ip/vhd/ls_xcvr/aligner_10bk28_5.vhd index 6646816e..653c868e 100644 --- a/hdl/ip/vhd/ls_xcvr/aligner_10bk28_5.vhd +++ b/hdl/ip/vhd/ls_xcvr/aligner_10bk28_5.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/ls_xcvr/ls_serdes.vhd b/hdl/ip/vhd/ls_xcvr/ls_serdes.vhd index 934467ea..d25e6e6a 100644 --- a/hdl/ip/vhd/ls_xcvr/ls_serdes.vhd +++ b/hdl/ip/vhd/ls_xcvr/ls_serdes.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/memories/mixed_width_simple_dpr.vhd b/hdl/ip/vhd/memories/mixed_width_simple_dpr.vhd index bba8b118..1da53d6e 100644 --- a/hdl/ip/vhd/memories/mixed_width_simple_dpr.vhd +++ b/hdl/ip/vhd/memories/mixed_width_simple_dpr.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/memories/sims/memories_sim_pkg.vhd b/hdl/ip/vhd/memories/sims/memories_sim_pkg.vhd index 88ba3ab1..32532697 100644 --- a/hdl/ip/vhd/memories/sims/memories_sim_pkg.vhd +++ b/hdl/ip/vhd/memories/sims/memories_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/memories/sims/memories_tb.vhd b/hdl/ip/vhd/memories/sims/memories_tb.vhd index 8b7d4492..61707973 100644 --- a/hdl/ip/vhd/memories/sims/memories_tb.vhd +++ b/hdl/ip/vhd/memories/sims/memories_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/memories/sims/memories_th.vhd b/hdl/ip/vhd/memories/sims/memories_th.vhd index 8be2410c..c6f6ace6 100644 --- a/hdl/ip/vhd/memories/sims/memories_th.vhd +++ b/hdl/ip/vhd/memories/sims/memories_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/pipeline/skidbuffer.vhd b/hdl/ip/vhd/pipeline/skidbuffer.vhd index 70369f23..00904582 100644 --- a/hdl/ip/vhd/pipeline/skidbuffer.vhd +++ b/hdl/ip/vhd/pipeline/skidbuffer.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- inspired by https://zipcpu.com/blog/2019/05/22/skidbuffer.html diff --git a/hdl/ip/vhd/sgpio/sgpio_shift_in.vhd b/hdl/ip/vhd/sgpio/sgpio_shift_in.vhd index b67555cc..d9da8aea 100644 --- a/hdl/ip/vhd/sgpio/sgpio_shift_in.vhd +++ b/hdl/ip/vhd/sgpio/sgpio_shift_in.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/sgpio/sgpio_shift_out.vhd b/hdl/ip/vhd/sgpio/sgpio_shift_out.vhd index 6309d30c..b70c5778 100644 --- a/hdl/ip/vhd/sgpio/sgpio_shift_out.vhd +++ b/hdl/ip/vhd/sgpio/sgpio_shift_out.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/sgpio/sgpio_top.vhd b/hdl/ip/vhd/sgpio/sgpio_top.vhd index 997cf355..c43f27a9 100644 --- a/hdl/ip/vhd/sgpio/sgpio_top.vhd +++ b/hdl/ip/vhd/sgpio/sgpio_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/sgpio/sims/sgpio_th.vhd b/hdl/ip/vhd/sgpio/sims/sgpio_th.vhd index dd4f9eab..baf35d7c 100644 --- a/hdl/ip/vhd/sgpio/sims/sgpio_th.vhd +++ b/hdl/ip/vhd/sgpio/sims/sgpio_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb.vhd b/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb.vhd index a54b501b..6a33ca3f 100644 --- a/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb.vhd +++ b/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb_pkg.vhd b/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb_pkg.vhd index 07f5c439..230d721a 100644 --- a/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb_pkg.vhd +++ b/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_th.vhd b/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_th.vhd index 178ddbd2..04d41f59 100644 --- a/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_th.vhd +++ b/hdl/ip/vhd/spi/axi_controller/sims/spi_axi_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi/axi_controller/spi_axi_controller_top.vhd b/hdl/ip/vhd/spi/axi_controller/spi_axi_controller_top.vhd index 94bffb7f..09a74359 100644 --- a/hdl/ip/vhd/spi/axi_controller/spi_axi_controller_top.vhd +++ b/hdl/ip/vhd/spi/axi_controller/spi_axi_controller_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Acting as a SPI peripheral, turn specially formed transactions into -- AXI-lite memory read/write transactions diff --git a/hdl/ip/vhd/spi/axi_controller/spi_axi_pkg.vhd b/hdl/ip/vhd/spi/axi_controller/spi_axi_pkg.vhd index 7a514af3..6f619536 100644 --- a/hdl/ip/vhd/spi/axi_controller/spi_axi_pkg.vhd +++ b/hdl/ip/vhd/spi/axi_controller/spi_axi_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi/axi_controller/spi_to_axi.vhd b/hdl/ip/vhd/spi/axi_controller/spi_to_axi.vhd index 410aff4c..bdb62ed7 100644 --- a/hdl/ip/vhd/spi/axi_controller/spi_to_axi.vhd +++ b/hdl/ip/vhd/spi/axi_controller/spi_to_axi.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Acting as a SPI peripheral, turn specially formed transactions into -- AXI-lite memory read/write transactions diff --git a/hdl/ip/vhd/spi/spi_target_phy/spi_target_phy.vhd b/hdl/ip/vhd/spi/spi_target_phy/spi_target_phy.vhd index ad2f6766..2a18c4eb 100644 --- a/hdl/ip/vhd/spi/spi_target_phy/spi_target_phy.vhd +++ b/hdl/ip/vhd/spi/spi_target_phy/spi_target_phy.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Simple SPI shifter PHY -- shifts on sclk edges (post synchronizer) when chipselect is asserted low diff --git a/hdl/ip/vhd/spi_nor_controller/espi_txn/espi_flash_txn_mgr.vhd b/hdl/ip/vhd/spi_nor_controller/espi_txn/espi_flash_txn_mgr.vhd index d6d28b85..644d49a7 100644 --- a/hdl/ip/vhd/spi_nor_controller/espi_txn/espi_flash_txn_mgr.vhd +++ b/hdl/ip/vhd/spi_nor_controller/espi_txn/espi_flash_txn_mgr.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2026 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/spi_nor_controller/link/spi_clk_gen.vhd b/hdl/ip/vhd/spi_nor_controller/link/spi_clk_gen.vhd index 7e99b67b..7106d45d 100644 --- a/hdl/ip/vhd/spi_nor_controller/link/spi_clk_gen.vhd +++ b/hdl/ip/vhd/spi_nor_controller/link/spi_clk_gen.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi_nor_controller/link/spi_link.vhd b/hdl/ip/vhd/spi_nor_controller/link/spi_link.vhd index 94d6fad4..8601ce60 100644 --- a/hdl/ip/vhd/spi_nor_controller/link/spi_link.vhd +++ b/hdl/ip/vhd/spi_nor_controller/link/spi_link.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi_nor_controller/mixed_width_adaptor.vhd b/hdl/ip/vhd/spi_nor_controller/mixed_width_adaptor.vhd index 3ea3f2a5..662e6405 100644 --- a/hdl/ip/vhd/spi_nor_controller/mixed_width_adaptor.vhd +++ b/hdl/ip/vhd/spi_nor_controller/mixed_width_adaptor.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_tb.vhd b/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_tb.vhd index 7a896eee..e6ccb827 100644 --- a/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_tb.vhd +++ b/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_tb_pkg.vhd b/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_tb_pkg.vhd index ba19b18e..8a02a190 100644 --- a/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_tb_pkg.vhd +++ b/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_tb_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_th.vhd b/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_th.vhd index 140530ff..bb3efb87 100644 --- a/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_th.vhd +++ b/hdl/ip/vhd/spi_nor_controller/sims/spi_nor_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi_nor_controller/spi_nor_pkg.vhd b/hdl/ip/vhd/spi_nor_controller/spi_nor_pkg.vhd index 264ca605..763bb08a 100644 --- a/hdl/ip/vhd/spi_nor_controller/spi_nor_pkg.vhd +++ b/hdl/ip/vhd/spi_nor_controller/spi_nor_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company; library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi_nor_controller/spi_nor_regs.rdl b/hdl/ip/vhd/spi_nor_controller/spi_nor_regs.rdl index 62b343c5..7f7bca6b 100644 --- a/hdl/ip/vhd/spi_nor_controller/spi_nor_regs.rdl +++ b/hdl/ip/vhd/spi_nor_controller/spi_nor_regs.rdl @@ -2,7 +2,6 @@ // License, v. 2.0. If a copy of the MPL was not distributed with this // file, You can obtain one at https://mozilla.org/MPL/2.0/. // -// Copyright 2024 Oxide Computer Company // // This is SystemRDL description of the sw-accesible registers in the // grapefruit dev board FPGA. diff --git a/hdl/ip/vhd/spi_nor_controller/spi_nor_regs.vhd b/hdl/ip/vhd/spi_nor_controller/spi_nor_regs.vhd index 0bbd81bc..2d7f4b0a 100644 --- a/hdl/ip/vhd/spi_nor_controller/spi_nor_regs.vhd +++ b/hdl/ip/vhd/spi_nor_controller/spi_nor_regs.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi_nor_controller/spi_nor_top.vhd b/hdl/ip/vhd/spi_nor_controller/spi_nor_top.vhd index 904beae0..507048ea 100644 --- a/hdl/ip/vhd/spi_nor_controller/spi_nor_top.vhd +++ b/hdl/ip/vhd/spi_nor_controller/spi_nor_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/spi_nor_controller/spi_txn/spi_txn_mgr.vhd b/hdl/ip/vhd/spi_nor_controller/spi_txn/spi_txn_mgr.vhd index 19866a2c..b6ff0f6e 100644 --- a/hdl/ip/vhd/spi_nor_controller/spi_txn/spi_txn_mgr.vhd +++ b/hdl/ip/vhd/spi_nor_controller/spi_txn/spi_txn_mgr.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/synchronizers/async_reset_bridge.vhd b/hdl/ip/vhd/synchronizers/async_reset_bridge.vhd index d3b3b62f..9a5bd083 100644 --- a/hdl/ip/vhd/synchronizers/async_reset_bridge.vhd +++ b/hdl/ip/vhd/synchronizers/async_reset_bridge.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/synchronizers/bacd.vhd b/hdl/ip/vhd/synchronizers/bacd.vhd index db172628..5394228d 100644 --- a/hdl/ip/vhd/synchronizers/bacd.vhd +++ b/hdl/ip/vhd/synchronizers/bacd.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/synchronizers/meta_sync.vhd b/hdl/ip/vhd/synchronizers/meta_sync.vhd index a7309bc5..c99ce004 100644 --- a/hdl/ip/vhd/synchronizers/meta_sync.vhd +++ b/hdl/ip/vhd/synchronizers/meta_sync.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/synchronizers/sims/synchronizers_tb.vhd b/hdl/ip/vhd/synchronizers/sims/synchronizers_tb.vhd index d546f000..8eeceab1 100644 --- a/hdl/ip/vhd/synchronizers/sims/synchronizers_tb.vhd +++ b/hdl/ip/vhd/synchronizers/sims/synchronizers_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/synchronizers/sims/synchronizers_th.vhd b/hdl/ip/vhd/synchronizers/sims/synchronizers_th.vhd index d9e1f5d6..fb4e8fe9 100644 --- a/hdl/ip/vhd/synchronizers/sims/synchronizers_th.vhd +++ b/hdl/ip/vhd/synchronizers/sims/synchronizers_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/synchronizers/tacd.vhd b/hdl/ip/vhd/synchronizers/tacd.vhd index db5482f0..7754faaf 100644 --- a/hdl/ip/vhd/synchronizers/tacd.vhd +++ b/hdl/ip/vhd/synchronizers/tacd.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/uart/base_uart/axi_st_uart.vhd b/hdl/ip/vhd/uart/base_uart/axi_st_uart.vhd index f2077e0b..206872f3 100644 --- a/hdl/ip/vhd/uart/base_uart/axi_st_uart.vhd +++ b/hdl/ip/vhd/uart/base_uart/axi_st_uart.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- A very simple UART that streams rx'd bytes out an axi streaming port -- and transmits bytes from an input axi streaming port, no buffering diff --git a/hdl/ip/vhd/uart/fifo_uart/axi_fifo_st_uart.vhd b/hdl/ip/vhd/uart/fifo_uart/axi_fifo_st_uart.vhd index 897dee34..d4e989c4 100644 --- a/hdl/ip/vhd/uart/fifo_uart/axi_fifo_st_uart.vhd +++ b/hdl/ip/vhd/uart/fifo_uart/axi_fifo_st_uart.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; diff --git a/hdl/ip/vhd/uart/sims/uart_tb.vhd b/hdl/ip/vhd/uart/sims/uart_tb.vhd index 433533d0..37dda4d3 100644 --- a/hdl/ip/vhd/uart/sims/uart_tb.vhd +++ b/hdl/ip/vhd/uart/sims/uart_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/uart/sims/uart_tb_pkg.vhd b/hdl/ip/vhd/uart/sims/uart_tb_pkg.vhd index 357da116..a011e2b4 100644 --- a/hdl/ip/vhd/uart/sims/uart_tb_pkg.vhd +++ b/hdl/ip/vhd/uart/sims/uart_tb_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/uart/sims/uart_th.vhd b/hdl/ip/vhd/uart/sims/uart_th.vhd index ad1c7a3d..d60efc74 100644 --- a/hdl/ip/vhd/uart/sims/uart_th.vhd +++ b/hdl/ip/vhd/uart/sims/uart_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/I2c_cmd/i2c_cmd_vc.vhd b/hdl/ip/vhd/vunit_components/I2c_cmd/i2c_cmd_vc.vhd index e8b401ca..b3862da8 100644 --- a/hdl/ip/vhd/vunit_components/I2c_cmd/i2c_cmd_vc.vhd +++ b/hdl/ip/vhd/vunit_components/I2c_cmd/i2c_cmd_vc.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/I2c_cmd/i2c_cmd_vc_pkg.vhd b/hdl/ip/vhd/vunit_components/I2c_cmd/i2c_cmd_vc_pkg.vhd index 37e6dd27..225d4540 100644 --- a/hdl/ip/vhd/vunit_components/I2c_cmd/i2c_cmd_vc_pkg.vhd +++ b/hdl/ip/vhd/vunit_components/I2c_cmd/i2c_cmd_vc_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/basic_stream/basic_sink.vhd b/hdl/ip/vhd/vunit_components/basic_stream/basic_sink.vhd index 45640cbf..2ecd49f2 100644 --- a/hdl/ip/vhd/vunit_components/basic_stream/basic_sink.vhd +++ b/hdl/ip/vhd/vunit_components/basic_stream/basic_sink.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- -- A basic sink for streamed data that can apply backpressure. diff --git a/hdl/ip/vhd/vunit_components/basic_stream/basic_source.vhd b/hdl/ip/vhd/vunit_components/basic_stream/basic_source.vhd index c17598b4..8122bd60 100644 --- a/hdl/ip/vhd/vunit_components/basic_stream/basic_source.vhd +++ b/hdl/ip/vhd/vunit_components/basic_stream/basic_source.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- -- A basic source of streamed data that respects backpressure. diff --git a/hdl/ip/vhd/vunit_components/basic_stream/basic_stream_pkg.vhd b/hdl/ip/vhd/vunit_components/basic_stream/basic_stream_pkg.vhd index f5da3085..06c5a141 100644 --- a/hdl/ip/vhd/vunit_components/basic_stream/basic_stream_pkg.vhd +++ b/hdl/ip/vhd/vunit_components/basic_stream/basic_stream_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/basic_stream/sims/th_basic_stream.vhd b/hdl/ip/vhd/vunit_components/basic_stream/sims/th_basic_stream.vhd index 62be7f09..db9ba94f 100644 --- a/hdl/ip/vhd/vunit_components/basic_stream/sims/th_basic_stream.vhd +++ b/hdl/ip/vhd/vunit_components/basic_stream/sims/th_basic_stream.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/gpio/gpio_msg_pkg.vhd b/hdl/ip/vhd/vunit_components/gpio/gpio_msg_pkg.vhd index 7845e81b..6a3b0d5e 100644 --- a/hdl/ip/vhd/vunit_components/gpio/gpio_msg_pkg.vhd +++ b/hdl/ip/vhd/vunit_components/gpio/gpio_msg_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/gpio/sim_gpio.vhd b/hdl/ip/vhd/vunit_components/gpio/sim_gpio.vhd index 4d6c156e..879ef2c1 100644 --- a/hdl/ip/vhd/vunit_components/gpio/sim_gpio.vhd +++ b/hdl/ip/vhd/vunit_components/gpio/sim_gpio.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/vunit_components/i2c_controller/i2c_ctrlr_vc.vhd b/hdl/ip/vhd/vunit_components/i2c_controller/i2c_ctrlr_vc.vhd index 84ec8186..fabe6794 100644 --- a/hdl/ip/vhd/vunit_components/i2c_controller/i2c_ctrlr_vc.vhd +++ b/hdl/ip/vhd/vunit_components/i2c_controller/i2c_ctrlr_vc.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/vunit_components/i2c_controller/i2c_ctrlr_vc_pkg.vhd b/hdl/ip/vhd/vunit_components/i2c_controller/i2c_ctrlr_vc_pkg.vhd index fbca2505..25f1a4e3 100644 --- a/hdl/ip/vhd/vunit_components/i2c_controller/i2c_ctrlr_vc_pkg.vhd +++ b/hdl/ip/vhd/vunit_components/i2c_controller/i2c_ctrlr_vc_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/i2c_target/i2c_target_vc.vhd b/hdl/ip/vhd/vunit_components/i2c_target/i2c_target_vc.vhd index 87f9de58..bd325a31 100644 --- a/hdl/ip/vhd/vunit_components/i2c_target/i2c_target_vc.vhd +++ b/hdl/ip/vhd/vunit_components/i2c_target/i2c_target_vc.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/i2c_target/i2c_target_vc_pkg.vhd b/hdl/ip/vhd/vunit_components/i2c_target/i2c_target_vc_pkg.vhd index be316e6a..c71b7f6c 100644 --- a/hdl/ip/vhd/vunit_components/i2c_target/i2c_target_vc_pkg.vhd +++ b/hdl/ip/vhd/vunit_components/i2c_target/i2c_target_vc_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_controller_vc.vhd b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_controller_vc.vhd index 1e9ccf0a..93b3824f 100644 --- a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_controller_vc.vhd +++ b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_controller_vc.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd index cf66887c..7b3fc022 100644 --- a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd +++ b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/ip/vhd/vunit_components/sim_gpio.vhd b/hdl/ip/vhd/vunit_components/sim_gpio.vhd index b82609cc..5aeae608 100644 --- a/hdl/ip/vhd/vunit_components/sim_gpio.vhd +++ b/hdl/ip/vhd/vunit_components/sim_gpio.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Note: Documentation can be rendered in VSCode using the TerosHDL -- plugin: https://terostechnology.github.io/terosHDLdoc/ diff --git a/hdl/projects/cosmo_hp/cosmo_hp_top.vhd b/hdl/projects/cosmo_hp/cosmo_hp_top.vhd index 1fd65606..f6b78ffa 100644 --- a/hdl/projects/cosmo_hp/cosmo_hp_top.vhd +++ b/hdl/projects/cosmo_hp/cosmo_hp_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Cosmo Ignition FPGA top targeting an ice40 HX8k diff --git a/hdl/projects/cosmo_hp/hp_subsystem/cem_hp_io_pkg.vhd b/hdl/projects/cosmo_hp/hp_subsystem/cem_hp_io_pkg.vhd index cf090cdf..51ea513a 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/cem_hp_io_pkg.vhd +++ b/hdl/projects/cosmo_hp/hp_subsystem/cem_hp_io_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_hp/hp_subsystem/cem_sync.vhd b/hdl/projects/cosmo_hp/hp_subsystem/cem_sync.vhd index d3508b3d..2ce44215 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/cem_sync.vhd +++ b/hdl/projects/cosmo_hp/hp_subsystem/cem_sync.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Take an array of records from each of the 10 CEMs and generate -- input synchronizers for each of them, and give back an output diff --git a/hdl/projects/cosmo_hp/hp_subsystem/hp_debug_regs.rdl b/hdl/projects/cosmo_hp/hp_subsystem/hp_debug_regs.rdl index a8907d7c..08d2815e 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/hp_debug_regs.rdl +++ b/hdl/projects/cosmo_hp/hp_subsystem/hp_debug_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // This is SystemRDL description of the sw-accessible common board-info registers addrmap hp_debug_regs { diff --git a/hdl/projects/cosmo_hp/hp_subsystem/hp_debug_regs.vhd b/hdl/projects/cosmo_hp/hp_subsystem/hp_debug_regs.vhd index 43b602a3..b54d4577 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/hp_debug_regs.vhd +++ b/hdl/projects/cosmo_hp/hp_subsystem/hp_debug_regs.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_hp/hp_subsystem/hp_logic.vhd b/hdl/projects/cosmo_hp/hp_subsystem/hp_logic.vhd index 7a9f0079..0df92675 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/hp_logic.vhd +++ b/hdl/projects/cosmo_hp/hp_subsystem/hp_logic.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_hp/hp_subsystem/hp_subystem_top.vhd b/hdl/projects/cosmo_hp/hp_subsystem/hp_subystem_top.vhd index 8775eca3..875c2efa 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/hp_subystem_top.vhd +++ b/hdl/projects/cosmo_hp/hp_subsystem/hp_subystem_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Cosmo Front Hot-plug FPGA targeting an ice40 HX8k diff --git a/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_hp_sim_tb.vhd b/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_hp_sim_tb.vhd index c6e82cc7..091bb884 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_hp_sim_tb.vhd +++ b/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_hp_sim_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_hp_sim_th.vhd b/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_hp_sim_th.vhd index 7ad2f2ba..b5d4c05d 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_hp_sim_th.vhd +++ b/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_hp_sim_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_model.vhd b/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_model.vhd index a5614c6f..ebf17773 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_model.vhd +++ b/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_model.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_sim_pkg.vhd b/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_sim_pkg.vhd index c8367680..9d893a2f 100644 --- a/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_sim_pkg.vhd +++ b/hdl/projects/cosmo_hp/hp_subsystem/sims/cem_sim_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_ignition/cosmo_ignition_a_top.vhd b/hdl/projects/cosmo_ignition/cosmo_ignition_a_top.vhd index e284df8a..735aa16d 100644 --- a/hdl/projects/cosmo_ignition/cosmo_ignition_a_top.vhd +++ b/hdl/projects/cosmo_ignition/cosmo_ignition_a_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Cosmo Front Hot-plug FPGA targeting an ice40 HX8k diff --git a/hdl/projects/cosmo_ignition/cosmo_ignition_top.vhd b/hdl/projects/cosmo_ignition/cosmo_ignition_top.vhd index e56dba21..943f08b0 100644 --- a/hdl/projects/cosmo_ignition/cosmo_ignition_top.vhd +++ b/hdl/projects/cosmo_ignition/cosmo_ignition_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Cosmo Front Hot-plug FPGA targeting an ice40 HX8k diff --git a/hdl/projects/cosmo_seq/black_box_entities/cosmo_pll.vhd b/hdl/projects/cosmo_seq/black_box_entities/cosmo_pll.vhd index 727c5828..762f1503 100644 --- a/hdl/projects/cosmo_seq/black_box_entities/cosmo_pll.vhd +++ b/hdl/projects/cosmo_seq/black_box_entities/cosmo_pll.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- A no synth, no sim, black entity to make analysis happy diff --git a/hdl/projects/cosmo_seq/board_support/board_support_top.vhd b/hdl/projects/cosmo_seq/board_support/board_support_top.vhd index a5c35043..6141d7ae 100644 --- a/hdl/projects/cosmo_seq/board_support/board_support_top.vhd +++ b/hdl/projects/cosmo_seq/board_support/board_support_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/board_support/reset_sync.vhd b/hdl/projects/cosmo_seq/board_support/reset_sync.vhd index 596cb0c2..959766b3 100644 --- a/hdl/projects/cosmo_seq/board_support/reset_sync.vhd +++ b/hdl/projects/cosmo_seq/board_support/reset_sync.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; diff --git a/hdl/projects/cosmo_seq/chip2chip_if/chip2chip_top.vhd b/hdl/projects/cosmo_seq/chip2chip_if/chip2chip_top.vhd index eed96b8f..b6f6413f 100644 --- a/hdl/projects/cosmo_seq/chip2chip_if/chip2chip_top.vhd +++ b/hdl/projects/cosmo_seq/chip2chip_if/chip2chip_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/cosmo_seq_top.vhd b/hdl/projects/cosmo_seq/cosmo_seq_top.vhd index c63ee302..9cce248a 100644 --- a/hdl/projects/cosmo_seq/cosmo_seq_top.vhd +++ b/hdl/projects/cosmo_seq/cosmo_seq_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Cosmo Sequencer FPGA targeting the Spartan-7 diff --git a/hdl/projects/cosmo_seq/debug_module/debug_header.vhd b/hdl/projects/cosmo_seq/debug_module/debug_header.vhd index 083780e4..e4afdfd5 100644 --- a/hdl/projects/cosmo_seq/debug_module/debug_header.vhd +++ b/hdl/projects/cosmo_seq/debug_module/debug_header.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; diff --git a/hdl/projects/cosmo_seq/debug_module/debug_module_top.vhd b/hdl/projects/cosmo_seq/debug_module/debug_module_top.vhd index 8cf2ba44..3f53c0b4 100644 --- a/hdl/projects/cosmo_seq/debug_module/debug_module_top.vhd +++ b/hdl/projects/cosmo_seq/debug_module/debug_module_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; diff --git a/hdl/projects/cosmo_seq/debug_module/debug_regs.rdl b/hdl/projects/cosmo_seq/debug_module/debug_regs.rdl index 4939be0b..0c0893c7 100644 --- a/hdl/projects/cosmo_seq/debug_module/debug_regs.rdl +++ b/hdl/projects/cosmo_seq/debug_module/debug_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // This is SystemRDL description of the sw-accessible registers in the Cosmo // Debug Control FPGA block. diff --git a/hdl/projects/cosmo_seq/sequencer/a1_a0_seq.vhd b/hdl/projects/cosmo_seq/sequencer/a1_a0_seq.vhd index e4f88f43..f3dbcb84 100644 --- a/hdl/projects/cosmo_seq/sequencer/a1_a0_seq.vhd +++ b/hdl/projects/cosmo_seq/sequencer/a1_a0_seq.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/nic_seq.vhd b/hdl/projects/cosmo_seq/sequencer/nic_seq.vhd index d2882e96..8e0fad8f 100644 --- a/hdl/projects/cosmo_seq/sequencer/nic_seq.vhd +++ b/hdl/projects/cosmo_seq/sequencer/nic_seq.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/seq_sync.vhd b/hdl/projects/cosmo_seq/sequencer/seq_sync.vhd index 81526153..18902dc6 100644 --- a/hdl/projects/cosmo_seq/sequencer/seq_sync.vhd +++ b/hdl/projects/cosmo_seq/sequencer/seq_sync.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sequencer_io_pkg.vhd b/hdl/projects/cosmo_seq/sequencer/sequencer_io_pkg.vhd index afb3ec37..7e8ecd4f 100644 --- a/hdl/projects/cosmo_seq/sequencer/sequencer_io_pkg.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sequencer_io_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sequencer_regs.rdl b/hdl/projects/cosmo_seq/sequencer/sequencer_regs.rdl index 56e226f4..dbd0768f 100644 --- a/hdl/projects/cosmo_seq/sequencer/sequencer_regs.rdl +++ b/hdl/projects/cosmo_seq/sequencer/sequencer_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // This is SystemRDL description of the sw-accessible registers in the Cosmo // Sequencer FPGA block. diff --git a/hdl/projects/cosmo_seq/sequencer/sequencer_regs.vhd b/hdl/projects/cosmo_seq/sequencer/sequencer_regs.vhd index aa7ceefe..a9b39114 100644 --- a/hdl/projects/cosmo_seq/sequencer/sequencer_regs.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sequencer_regs.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sims/cascade_rail_model.vhd b/hdl/projects/cosmo_seq/sequencer/sims/cascade_rail_model.vhd index 08eb58fe..af2aeb3f 100644 --- a/hdl/projects/cosmo_seq/sequencer/sims/cascade_rail_model.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sims/cascade_rail_model.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sims/nic_model.vhd b/hdl/projects/cosmo_seq/sequencer/sims/nic_model.vhd index f7d332b3..d23075c0 100644 --- a/hdl/projects/cosmo_seq/sequencer/sims/nic_model.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sims/nic_model.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sims/nic_model_msg_pkg.vhd b/hdl/projects/cosmo_seq/sequencer/sims/nic_model_msg_pkg.vhd index d993846a..a35a3a27 100644 --- a/hdl/projects/cosmo_seq/sequencer/sims/nic_model_msg_pkg.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sims/nic_model_msg_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sims/rail_model.vhd b/hdl/projects/cosmo_seq/sequencer/sims/rail_model.vhd index 1fa46ec1..276b6a80 100644 --- a/hdl/projects/cosmo_seq/sequencer/sims/rail_model.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sims/rail_model.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sims/rail_model_msg_pkg.vhd b/hdl/projects/cosmo_seq/sequencer/sims/rail_model_msg_pkg.vhd index 90214248..38d87b1f 100644 --- a/hdl/projects/cosmo_seq/sequencer/sims/rail_model_msg_pkg.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sims/rail_model_msg_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_tb.vhd b/hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_tb.vhd index ba1e2f54..da9f3181 100644 --- a/hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_tb.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_tb.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_th.vhd b/hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_th.vhd index 6c28006d..553d6317 100644 --- a/hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_th.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_th.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sims/sp5_sim.vhd b/hdl/projects/cosmo_seq/sequencer/sims/sp5_sim.vhd index b0ac5e57..0695fe9a 100644 --- a/hdl/projects/cosmo_seq/sequencer/sims/sp5_sim.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sims/sp5_sim.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sequencer/sp5_sequencer.vhd b/hdl/projects/cosmo_seq/sequencer/sp5_sequencer.vhd index 6b03caae..9b0b91ec 100644 --- a/hdl/projects/cosmo_seq/sequencer/sp5_sequencer.vhd +++ b/hdl/projects/cosmo_seq/sequencer/sp5_sequencer.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sp5_espi_flash_subsystem/sp5_espi_flash_subsystem.vhd b/hdl/projects/cosmo_seq/sp5_espi_flash_subsystem/sp5_espi_flash_subsystem.vhd index 59f4b090..daa6d7df 100644 --- a/hdl/projects/cosmo_seq/sp5_espi_flash_subsystem/sp5_espi_flash_subsystem.vhd +++ b/hdl/projects/cosmo_seq/sp5_espi_flash_subsystem/sp5_espi_flash_subsystem.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sp5_hotplug_subsystem/perst_oneshot.vhd b/hdl/projects/cosmo_seq/sp5_hotplug_subsystem/perst_oneshot.vhd index 803d57fd..2a335786 100644 --- a/hdl/projects/cosmo_seq/sp5_hotplug_subsystem/perst_oneshot.vhd +++ b/hdl/projects/cosmo_seq/sp5_hotplug_subsystem/perst_oneshot.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sp5_hotplug_subsystem/sp5_hotplug_subsystem.vhd b/hdl/projects/cosmo_seq/sp5_hotplug_subsystem/sp5_hotplug_subsystem.vhd index 04f922ca..266108bd 100644 --- a/hdl/projects/cosmo_seq/sp5_hotplug_subsystem/sp5_hotplug_subsystem.vhd +++ b/hdl/projects/cosmo_seq/sp5_hotplug_subsystem/sp5_hotplug_subsystem.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Cosmo Sequencer FPGA targeting the Spartan-7 diff --git a/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd b/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd index 644d5273..ddacb006 100644 --- a/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd +++ b/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd b/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd index 0d8b7662..859cf58d 100644 --- a/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd +++ b/hdl/projects/cosmo_seq/sp5_uart_subsystem/sp5_uart_subsystem_pkg.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_regs.rdl b/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_regs.rdl index cc931787..4acab0a3 100644 --- a/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_regs.rdl +++ b/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // This is SystemRDL description of the sw-accessible registers in the Cosmo // Sequencer FPGA block. diff --git a/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_subsystem.vhd b/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_subsystem.vhd index d5ac93aa..893d3fa4 100644 --- a/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_subsystem.vhd +++ b/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_subsystem.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- Cosmo Sequencer FPGA targeting the Spartan-7 diff --git a/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_subsystem_regs.vhd b/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_subsystem_regs.vhd index f22475a0..946ef3fd 100644 --- a/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_subsystem_regs.vhd +++ b/hdl/projects/cosmo_seq/sp_i2c_subsystem/sp_i2c_subsystem_regs.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company library ieee; use ieee.std_logic_1164.all; diff --git a/hdl/projects/ecp5_evn/Board.bsv b/hdl/projects/ecp5_evn/Board.bsv index 07c39007..54692879 100644 --- a/hdl/projects/ecp5_evn/Board.bsv +++ b/hdl/projects/ecp5_evn/Board.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/gimlet/sequencer/Fans.bsv b/hdl/projects/gimlet/sequencer/Fans.bsv index c97e8ab1..86437699 100644 --- a/hdl/projects/gimlet/sequencer/Fans.bsv +++ b/hdl/projects/gimlet/sequencer/Fans.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company package Fans; diff --git a/hdl/projects/gimlet/sequencer/GimletSeqTop.bsv b/hdl/projects/gimlet/sequencer/GimletSeqTop.bsv index 547dba4d..cabad12f 100644 --- a/hdl/projects/gimlet/sequencer/GimletSeqTop.bsv +++ b/hdl/projects/gimlet/sequencer/GimletSeqTop.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company package GimletSeqTop; diff --git a/hdl/projects/gimlet/sequencer/gimlet_seq_fpga_regs.rdl b/hdl/projects/gimlet/sequencer/gimlet_seq_fpga_regs.rdl index f79776f1..8ca10559 100755 --- a/hdl/projects/gimlet/sequencer/gimlet_seq_fpga_regs.rdl +++ b/hdl/projects/gimlet/sequencer/gimlet_seq_fpga_regs.rdl @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // This is SystemRDL description of the sw-accesible registers in the Gimlet // Sequencer FPGA. diff --git a/hdl/projects/grapefruit/base_regs/gfruit_regs.rdl b/hdl/projects/grapefruit/base_regs/gfruit_regs.rdl index 435a728a..d736ea75 100644 --- a/hdl/projects/grapefruit/base_regs/gfruit_regs.rdl +++ b/hdl/projects/grapefruit/base_regs/gfruit_regs.rdl @@ -2,7 +2,6 @@ // License, v. 2.0. If a copy of the MPL was not distributed with this // file, You can obtain one at https://mozilla.org/MPL/2.0/. // -// Copyright 2024 Oxide Computer Company // // This is SystemRDL description of the sw-accesible registers in the // grapefruit dev board FPGA. diff --git a/hdl/projects/grapefruit/base_regs/registers.vhd b/hdl/projects/grapefruit/base_regs/registers.vhd index 2c014ca4..b7a28d9d 100644 --- a/hdl/projects/grapefruit/base_regs/registers.vhd +++ b/hdl/projects/grapefruit/base_regs/registers.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; diff --git a/hdl/projects/grapefruit/black_box_entities/gfruit_pll.vhd b/hdl/projects/grapefruit/black_box_entities/gfruit_pll.vhd index 8fb2c0a5..e80c67a6 100644 --- a/hdl/projects/grapefruit/black_box_entities/gfruit_pll.vhd +++ b/hdl/projects/grapefruit/black_box_entities/gfruit_pll.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2025 Oxide Computer Company -- A no synth, no sim, black entity to make analysis happy diff --git a/hdl/projects/grapefruit/grapefruit_top.vhd b/hdl/projects/grapefruit/grapefruit_top.vhd index 6c6c27b8..7447a74d 100644 --- a/hdl/projects/grapefruit/grapefruit_top.vhd +++ b/hdl/projects/grapefruit/grapefruit_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; diff --git a/hdl/projects/grapefruit/integration/drivers/espi_dbg.py b/hdl/projects/grapefruit/integration/drivers/espi_dbg.py index 6047b83f..99082184 100644 --- a/hdl/projects/grapefruit/integration/drivers/espi_dbg.py +++ b/hdl/projects/grapefruit/integration/drivers/espi_dbg.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company from crc import Calculator, Crc8 diff --git a/hdl/projects/grapefruit/integration/drivers/spi_nor.py b/hdl/projects/grapefruit/integration/drivers/spi_nor.py index 0bb73afb..9c922bef 100644 --- a/hdl/projects/grapefruit/integration/drivers/spi_nor.py +++ b/hdl/projects/grapefruit/integration/drivers/spi_nor.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import time op_page_program = 0x02 diff --git a/hdl/projects/grapefruit/sgpio/gfruit_sgpio.rdl b/hdl/projects/grapefruit/sgpio/gfruit_sgpio.rdl index eb70f7df..aa62b77e 100644 --- a/hdl/projects/grapefruit/sgpio/gfruit_sgpio.rdl +++ b/hdl/projects/grapefruit/sgpio/gfruit_sgpio.rdl @@ -2,7 +2,6 @@ // License, v. 2.0. If a copy of the MPL was not distributed with this // file, You can obtain one at https://mozilla.org/MPL/2.0/. // -// Copyright 2024 Oxide Computer Company // // This is SystemRDL description of the sw-accesible registers in the // grapefruit dev board FPGA. diff --git a/hdl/projects/grapefruit/sgpio/gfruit_sgpio.vhd b/hdl/projects/grapefruit/sgpio/gfruit_sgpio.vhd index 61cb464e..802d0767 100644 --- a/hdl/projects/grapefruit/sgpio/gfruit_sgpio.vhd +++ b/hdl/projects/grapefruit/sgpio/gfruit_sgpio.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company -- Grapefruit is meant to serve as a BMC replacement in AMD's Ruby -- reference platform for cosmo dev. As such, there are some functions diff --git a/hdl/projects/grapefruit/sgpio/gfruit_sgpio_regs.rdl b/hdl/projects/grapefruit/sgpio/gfruit_sgpio_regs.rdl index 5d9d0f1b..29b4ffdd 100644 --- a/hdl/projects/grapefruit/sgpio/gfruit_sgpio_regs.rdl +++ b/hdl/projects/grapefruit/sgpio/gfruit_sgpio_regs.rdl @@ -2,7 +2,6 @@ // License, v. 2.0. If a copy of the MPL was not distributed with this // file, You can obtain one at https://mozilla.org/MPL/2.0/. // -// Copyright 2024 Oxide Computer Company // // This is SystemRDL description of the sw-accesible registers in the // grapefruit dev board FPGA. diff --git a/hdl/projects/grapefruit/sgpio/sgpio_regs.vhd b/hdl/projects/grapefruit/sgpio/sgpio_regs.vhd index fadbc60e..e226d17a 100644 --- a/hdl/projects/grapefruit/sgpio/sgpio_regs.vhd +++ b/hdl/projects/grapefruit/sgpio/sgpio_regs.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2024 Oxide Computer Company library ieee; diff --git a/hdl/projects/icestick/Board.bsv b/hdl/projects/icestick/Board.bsv index 21a9ff86..b6d9fe82 100644 --- a/hdl/projects/icestick/Board.bsv +++ b/hdl/projects/icestick/Board.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/icestick/Examples.bsv b/hdl/projects/icestick/Examples.bsv index c692d4cf..551a3457 100644 --- a/hdl/projects/icestick/Examples.bsv +++ b/hdl/projects/icestick/Examples.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/ignitionlet/Examples.bsv b/hdl/projects/ignitionlet/Examples.bsv index 2ed85c23..4a2b7057 100644 --- a/hdl/projects/ignitionlet/Examples.bsv +++ b/hdl/projects/ignitionlet/Examples.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/minibar/MinibarController.bsv b/hdl/projects/minibar/MinibarController.bsv index d375a6fe..d098d7cd 100644 --- a/hdl/projects/minibar/MinibarController.bsv +++ b/hdl/projects/minibar/MinibarController.bsv @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/minibar/MinibarMiscRegs.bsv b/hdl/projects/minibar/MinibarMiscRegs.bsv index c009a1c2..f040649a 100644 --- a/hdl/projects/minibar/MinibarMiscRegs.bsv +++ b/hdl/projects/minibar/MinibarMiscRegs.bsv @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/minibar/MinibarPcie.bsv b/hdl/projects/minibar/MinibarPcie.bsv index 67e52a7e..4ea83c71 100644 --- a/hdl/projects/minibar/MinibarPcie.bsv +++ b/hdl/projects/minibar/MinibarPcie.bsv @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/minibar/MinibarSpiServer.bsv b/hdl/projects/minibar/MinibarSpiServer.bsv index ef79ae0e..fac1c62a 100644 --- a/hdl/projects/minibar/MinibarSpiServer.bsv +++ b/hdl/projects/minibar/MinibarSpiServer.bsv @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/minibar/MinibarTop.bsv b/hdl/projects/minibar/MinibarTop.bsv index 1520e1ef..b0298129 100644 --- a/hdl/projects/minibar/MinibarTop.bsv +++ b/hdl/projects/minibar/MinibarTop.bsv @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/minibar/minibar_controller.rdl b/hdl/projects/minibar/minibar_controller.rdl index 01ca0261..d07cca0b 100644 --- a/hdl/projects/minibar/minibar_controller.rdl +++ b/hdl/projects/minibar/minibar_controller.rdl @@ -1,4 +1,3 @@ -// Copyright 2025 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/observer_ignition/observer_ignition_top.vhd b/hdl/projects/observer_ignition/observer_ignition_top.vhd index 91f669ee..3d10ae35 100644 --- a/hdl/projects/observer_ignition/observer_ignition_top.vhd +++ b/hdl/projects/observer_ignition/observer_ignition_top.vhd @@ -2,7 +2,6 @@ -- License, v. 2.0. If a copy of the MPL was not distributed with this -- file, You can obtain one at https://mozilla.org/MPL/2.0/. -- --- Copyright 2026 Oxide Computer Company -- Observer power shelf controller FPGA targeting an ice40 HX8k diff --git a/hdl/projects/sidecar/mainboard/PCIeEndpointController.bsv b/hdl/projects/sidecar/mainboard/PCIeEndpointController.bsv index 250a78ce..8b87a5ab 100644 --- a/hdl/projects/sidecar/mainboard/PCIeEndpointController.bsv +++ b/hdl/projects/sidecar/mainboard/PCIeEndpointController.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/mainboard/SidecarMainboardMiscSequencers.bsv b/hdl/projects/sidecar/mainboard/SidecarMainboardMiscSequencers.bsv index ad280f73..80c8c39b 100644 --- a/hdl/projects/sidecar/mainboard/SidecarMainboardMiscSequencers.bsv +++ b/hdl/projects/sidecar/mainboard/SidecarMainboardMiscSequencers.bsv @@ -1,4 +1,3 @@ -// Copyright 2023 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/mainboard/Tofino2Sequencer.bsv b/hdl/projects/sidecar/mainboard/Tofino2Sequencer.bsv index 7c6cf42a..2a35c9ae 100644 --- a/hdl/projects/sidecar/mainboard/Tofino2Sequencer.bsv +++ b/hdl/projects/sidecar/mainboard/Tofino2Sequencer.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/mainboard/sidecar_mainboard_controller.rdl b/hdl/projects/sidecar/mainboard/sidecar_mainboard_controller.rdl index 6428b33e..56957ad4 100644 --- a/hdl/projects/sidecar/mainboard/sidecar_mainboard_controller.rdl +++ b/hdl/projects/sidecar/mainboard/sidecar_mainboard_controller.rdl @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/mainboard/test/Tofino2SequencerTests.bsv b/hdl/projects/sidecar/mainboard/test/Tofino2SequencerTests.bsv index d5de1350..4cfb8d73 100644 --- a/hdl/projects/sidecar/mainboard/test/Tofino2SequencerTests.bsv +++ b/hdl/projects/sidecar/mainboard/test/Tofino2SequencerTests.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/QSFPModule/QsfpModuleController.bsv b/hdl/projects/sidecar/qsfp_x32/QSFPModule/QsfpModuleController.bsv index 0dfa6b3c..342f8287 100644 --- a/hdl/projects/sidecar/qsfp_x32/QSFPModule/QsfpModuleController.bsv +++ b/hdl/projects/sidecar/qsfp_x32/QSFPModule/QsfpModuleController.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/QSFPModule/QsfpModulesTop.bsv b/hdl/projects/sidecar/qsfp_x32/QSFPModule/QsfpModulesTop.bsv index d39526a7..5fa8b9e9 100644 --- a/hdl/projects/sidecar/qsfp_x32/QSFPModule/QsfpModulesTop.bsv +++ b/hdl/projects/sidecar/qsfp_x32/QSFPModule/QsfpModulesTop.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/QSFPModule/qsfp_modules_top.rdl b/hdl/projects/sidecar/qsfp_x32/QSFPModule/qsfp_modules_top.rdl index b6374b2c..e2928a1f 100644 --- a/hdl/projects/sidecar/qsfp_x32/QSFPModule/qsfp_modules_top.rdl +++ b/hdl/projects/sidecar/qsfp_x32/QSFPModule/qsfp_modules_top.rdl @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/QSFPModule/test/QsfpModuleControllerTests.bsv b/hdl/projects/sidecar/qsfp_x32/QSFPModule/test/QsfpModuleControllerTests.bsv index b6276d37..c2c72d2b 100644 --- a/hdl/projects/sidecar/qsfp_x32/QSFPModule/test/QsfpModuleControllerTests.bsv +++ b/hdl/projects/sidecar/qsfp_x32/QSFPModule/test/QsfpModuleControllerTests.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/QsfpX32Controller.bsv b/hdl/projects/sidecar/qsfp_x32/QsfpX32Controller.bsv index bfac507b..b1536574 100644 --- a/hdl/projects/sidecar/qsfp_x32/QsfpX32Controller.bsv +++ b/hdl/projects/sidecar/qsfp_x32/QsfpX32Controller.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerSpiServer.bsv b/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerSpiServer.bsv index 24a7c8e5..5b9df6d3 100644 --- a/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerSpiServer.bsv +++ b/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerSpiServer.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerTop.bsv b/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerTop.bsv index 058a710a..e1997cf6 100644 --- a/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerTop.bsv +++ b/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerTop.bsv @@ -1,791 +1,790 @@ -// Copyright 2022 Oxide Computer Company -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at https://mozilla.org/MPL/2.0/. -package QsfpX32ControllerTop; - -// BSV Core -import Clocks::*; -import Connectable::*; -import GetPut::*; -import StmtFSM::*; -import TriState::*; -import Vector::*; - -// Oxide -import Bidirection::*; -import Blinky::*; -import I2CCommon::*; -import I2CCore::*; -import I2CBitController::*; -import IOSync::*; -import SPI::*; -import Strobe::*; -import PowerRail::*; - -import MDIO::*; - -// QSFP -import QsfpModuleController::*; -import QsfpModulesTop::*; -import QsfpX32Controller::*; -import QsfpX32ControllerTopRegs::*; -import VSC8562::*; - -(* always_enabled *) -interface QsfpControllerTop; - // - // QSFP Ports - // - method Bool fpga_to_qsfp_en_0; - method Bit#(1) fpga_to_qsfp_lpmode_0; - method Bit#(1) fpga_to_qsfp_reset_l_0; - (* prefix = "" *) method Action qsfp_to_fpga_pg_0(Bool qsfp_to_fpga_pg_0); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_0(Bit#(1) qsfp_to_fpga_irq_l_0); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_0(Bit#(1) qsfp_to_fpga_present_l_0); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_0; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_0; - - method Bool fpga_to_qsfp_en_1; - method Bit#(1) fpga_to_qsfp_lpmode_1; - method Bit#(1) fpga_to_qsfp_reset_l_1; - (* prefix = "" *) method Action qsfp_to_fpga_pg_1(Bool qsfp_to_fpga_pg_1); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_1(Bit#(1) qsfp_to_fpga_irq_l_1); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_1(Bit#(1) qsfp_to_fpga_present_l_1); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_1; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_1; - - method Bool fpga_to_qsfp_en_2; - method Bit#(1) fpga_to_qsfp_lpmode_2; - method Bit#(1) fpga_to_qsfp_reset_l_2; - (* prefix = "" *) method Action qsfp_to_fpga_pg_2(Bool qsfp_to_fpga_pg_2); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_2(Bit#(1) qsfp_to_fpga_irq_l_2); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_2(Bit#(1) qsfp_to_fpga_present_l_2); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_2; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_2; - - method Bool fpga_to_qsfp_en_3; - method Bit#(1) fpga_to_qsfp_lpmode_3; - method Bit#(1) fpga_to_qsfp_reset_l_3; - (* prefix = "" *) method Action qsfp_to_fpga_pg_3(Bool qsfp_to_fpga_pg_3); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_3(Bit#(1) qsfp_to_fpga_irq_l_3); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_3(Bit#(1) qsfp_to_fpga_present_l_3); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_3; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_3; - - method Bool fpga_to_qsfp_en_4; - method Bit#(1) fpga_to_qsfp_lpmode_4; - method Bit#(1) fpga_to_qsfp_reset_l_4; - (* prefix = "" *) method Action qsfp_to_fpga_pg_4(Bool qsfp_to_fpga_pg_4); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_4(Bit#(1) qsfp_to_fpga_irq_l_4); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_4(Bit#(1) qsfp_to_fpga_present_l_4); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_4; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_4; - - method Bool fpga_to_qsfp_en_5; - method Bit#(1) fpga_to_qsfp_lpmode_5; - method Bit#(1) fpga_to_qsfp_reset_l_5; - (* prefix = "" *) method Action qsfp_to_fpga_pg_5(Bool qsfp_to_fpga_pg_5); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_5(Bit#(1) qsfp_to_fpga_irq_l_5); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_5(Bit#(1) qsfp_to_fpga_present_l_5); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_5; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_5; - - method Bool fpga_to_qsfp_en_6; - method Bit#(1) fpga_to_qsfp_lpmode_6; - method Bit#(1) fpga_to_qsfp_reset_l_6; - (* prefix = "" *) method Action qsfp_to_fpga_pg_6(Bool qsfp_to_fpga_pg_6); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_6(Bit#(1) qsfp_to_fpga_irq_l_6); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_6(Bit#(1) qsfp_to_fpga_present_l_6); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_6; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_6; - - method Bool fpga_to_qsfp_en_7; - method Bit#(1) fpga_to_qsfp_lpmode_7; - method Bit#(1) fpga_to_qsfp_reset_l_7; - (* prefix = "" *) method Action qsfp_to_fpga_pg_7(Bool qsfp_to_fpga_pg_7); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_7(Bit#(1) qsfp_to_fpga_irq_l_7); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_7(Bit#(1) qsfp_to_fpga_present_l_7); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_7; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_7; - - method Bool fpga_to_qsfp_en_8; - method Bit#(1) fpga_to_qsfp_lpmode_8; - method Bit#(1) fpga_to_qsfp_reset_l_8; - (* prefix = "" *) method Action qsfp_to_fpga_pg_8(Bool qsfp_to_fpga_pg_8); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_8(Bit#(1) qsfp_to_fpga_irq_l_8); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_8(Bit#(1) qsfp_to_fpga_present_l_8); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_8; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_8; - - method Bool fpga_to_qsfp_en_9; - method Bit#(1) fpga_to_qsfp_lpmode_9; - method Bit#(1) fpga_to_qsfp_reset_l_9; - (* prefix = "" *) method Action qsfp_to_fpga_pg_9(Bool qsfp_to_fpga_pg_9); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_9(Bit#(1) qsfp_to_fpga_irq_l_9); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_9(Bit#(1) qsfp_to_fpga_present_l_9); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_9; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_9; - - method Bool fpga_to_qsfp_en_10; - method Bit#(1) fpga_to_qsfp_lpmode_10; - method Bit#(1) fpga_to_qsfp_reset_l_10; - (* prefix = "" *) method Action qsfp_to_fpga_pg_10(Bool qsfp_to_fpga_pg_10); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_10(Bit#(1) qsfp_to_fpga_irq_l_10); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_10(Bit#(1) qsfp_to_fpga_present_l_10); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_10; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_10; - - method Bool fpga_to_qsfp_en_11; - method Bit#(1) fpga_to_qsfp_lpmode_11; - method Bit#(1) fpga_to_qsfp_reset_l_11; - (* prefix = "" *) method Action qsfp_to_fpga_pg_11(Bool qsfp_to_fpga_pg_11); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_11(Bit#(1) qsfp_to_fpga_irq_l_11); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_11(Bit#(1) qsfp_to_fpga_present_l_11); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_11; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_11; - - method Bool fpga_to_qsfp_en_12; - method Bit#(1) fpga_to_qsfp_lpmode_12; - method Bit#(1) fpga_to_qsfp_reset_l_12; - (* prefix = "" *) method Action qsfp_to_fpga_pg_12(Bool qsfp_to_fpga_pg_12); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_12(Bit#(1) qsfp_to_fpga_irq_l_12); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_12(Bit#(1) qsfp_to_fpga_present_l_12); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_12; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_12; - - method Bool fpga_to_qsfp_en_13; - method Bit#(1) fpga_to_qsfp_lpmode_13; - method Bit#(1) fpga_to_qsfp_reset_l_13; - (* prefix = "" *) method Action qsfp_to_fpga_pg_13(Bool qsfp_to_fpga_pg_13); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_13(Bit#(1) qsfp_to_fpga_irq_l_13); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_13(Bit#(1) qsfp_to_fpga_present_l_13); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_13; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_13; - - method Bool fpga_to_qsfp_en_14; - method Bit#(1) fpga_to_qsfp_lpmode_14; - method Bit#(1) fpga_to_qsfp_reset_l_14; - (* prefix = "" *) method Action qsfp_to_fpga_pg_14(Bool qsfp_to_fpga_pg_14); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_14(Bit#(1) qsfp_to_fpga_irq_l_14); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_14(Bit#(1) qsfp_to_fpga_present_l_14); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_14; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_14; - - method Bool fpga_to_qsfp_en_15; - method Bit#(1) fpga_to_qsfp_lpmode_15; - method Bit#(1) fpga_to_qsfp_reset_l_15; - (* prefix = "" *) method Action qsfp_to_fpga_pg_15(Bool qsfp_to_fpga_pg_15); - (* prefix = "" *) method Action qsfp_to_fpga_irq_l_15(Bit#(1) qsfp_to_fpga_irq_l_15); - (* prefix = "" *) method Action qsfp_to_fpga_present_l_15(Bit#(1) qsfp_to_fpga_present_l_15); - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_15; - interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_15; - - // - // SPI Peripheral - // - - method Bit#(1) spi_main_to_fpga_miso_r(); - (* prefix = "" *) method Action spi_main_to_fpga_cs1_l(Bit#(1) spi_main_to_fpga_cs1_l); - (* prefix = "" *) method Action spi_main_to_fpga_sck(Bit#(1) spi_main_to_fpga_sck); - (* prefix = "" *) method Action spi_main_to_fpga_mosi(Bit#(1) spi_main_to_fpga_mosi); - - // - // Power - // - - method Bit#(1) fpga_to_vr_v3p3_qsfp_en(); - (* prefix = "" *) method Action vr_v3p3_qsfp_to_fpga_pg(Bit#(1) vr_v3p3_qsfp_to_fpga_pg); - (* prefix = "" *) method Action pmbus_v3p3_qsfp_to_fpga_alert(Bit#(1) pmbus_v3p3_qsfp_to_fpga_alert); - - // - // PHY - // - - method Bool fpga_to_vr_phy_en(); - (* prefix = "" *) method Action vr_v1p0_phy_to_fpga_pg(Bool vr_v1p0_phy_to_fpga_pg); - (* prefix = "" *) method Action vr_v2p5_phy_to_fpga_pg(Bool vr_v2p5_phy_to_fpga_pg); - method Bit#(1) fpga_to_phy_refclk_en(); - method Bit#(1) fpga_to_phy_coma_mode(); - method Bit#(1) fpga_to_phy_reset_l(); - method Bit#(1) miim_fpga_to_phy_mdc(); - (* prefix = "" *) method Action miim_phy_to_fpga_mdint_l(Bit#(1) miim_phy_to_fpga_mdint_l); - interface Inout#(Bit#(1)) miim_fpga_to_phy_mdio; - - // - // Miscellaneous - // - - method Bit#(1) fpga_to_main_irq_r_l(); - method Bit#(1) fpga_led(); - method Bit#(1) fpga_to_leds0_reset_l(); - method Bit#(1) fpga_to_leds0_oe_l(); - method Bit#(8) debug_fpga_io(); - (* prefix = "" *) method Action fpga_app_id_r(Bit#(1) fpga_app_id_r); - (* prefix = "" *) method Action fpga_board_ver(Bit#(5) fpga_board_ver); -endinterface - -function Inout#(Bit#(1)) inout_from_tristate(TriState#(Bit#(1)) tristate) = tristate.io; - -(* default_clock_osc="clk_50m_fpga", - default_reset="gpio_to_fpga_design_reset_l" *) -module mkQsfpX32ControllerTop (QsfpControllerTop); - // Synchronize the default reset to the default clock - Clock cur_clk <- exposeCurrentClock(); - Reset reset_synced <- mkAsyncResetFromCR(2, cur_clk); - - QsfpX32Controller controller <- - mkQsfpX32Controller(defaultValue, reset_by reset_synced); - - // - // QSFP Ports - // - - // P0 - ReadOnly#(Bool) qsfp0_hsc_en <- mkOutputSyncFor(controller.qsfp[0].power_en); - ReadOnly#(Bit#(1)) qsfp0_lpmode <- mkOutputSyncFor(controller.qsfp[0].lpmode); - ReadOnly#(Bit#(1)) qsfp0_resetl <- mkOutputSyncFor(controller.qsfp[0].resetl); - InputReg#(Bool, 2) qsfp0_hsc_pg <- mkInputSyncFor(controller.qsfp[0].power_good); - InputReg#(Bit#(1), 2) qsfp0_intl <- mkInputSyncFor(controller.qsfp[0].intl); - InputReg#(Bit#(1), 2) qsfp0_modprsl <- mkInputSyncFor(controller.qsfp[0].modprsl); - ReadOnly#(Bool) qsfp0_scl_out_en <- mkOutputSyncFor(controller.qsfp[0].scl.out_en); - ReadOnly#(Bit#(1)) qsfp0_scl_out <- mkOutputSyncFor(controller.qsfp[0].scl.out); - InputReg#(Bit#(1), 2) qsfp0_scl_in <- mkInputSyncFor(controller.qsfp[0].scl.in); - TriState#(Bit#(1)) qsfp0_scl <- mkTriState(qsfp0_scl_out_en, qsfp0_scl_out); - mkConnection(sync(qsfp0_scl_in), qsfp0_scl._read); - ReadOnly#(Bool) qsfp0_sda_out_en <- mkOutputSyncFor(controller.qsfp[0].sda.out_en); - ReadOnly#(Bit#(1)) qsfp0_sda_out <- mkOutputSyncFor(controller.qsfp[0].sda.out); - InputReg#(Bit#(1), 2) qsfp0_sda_in <- mkInputSyncFor(controller.qsfp[0].sda.in); - TriState#(Bit#(1)) qsfp0_sda <- mkTriState(qsfp0_sda_out_en, qsfp0_sda_out); - mkConnection(sync(qsfp0_sda_in), qsfp0_sda._read); - - // P1 - ReadOnly#(Bool) qsfp1_hsc_en <- mkOutputSyncFor(controller.qsfp[1].power_en); - ReadOnly#(Bit#(1)) qsfp1_lpmode <- mkOutputSyncFor(controller.qsfp[1].lpmode); - ReadOnly#(Bit#(1)) qsfp1_resetl <- mkOutputSyncFor(controller.qsfp[1].resetl); - InputReg#(Bool, 2) qsfp1_hsc_pg <- mkInputSyncFor(controller.qsfp[1].power_good); - InputReg#(Bit#(1), 2) qsfp1_intl <- mkInputSyncFor(controller.qsfp[1].intl); - InputReg#(Bit#(1), 2) qsfp1_modprsl <- mkInputSyncFor(controller.qsfp[1].modprsl); - ReadOnly#(Bool) qsfp1_scl_out_en <- mkOutputSyncFor(controller.qsfp[1].scl.out_en); - ReadOnly#(Bit#(1)) qsfp1_scl_out <- mkOutputSyncFor(controller.qsfp[1].scl.out); - InputReg#(Bit#(1), 2) qsfp1_scl_in <- mkInputSyncFor(controller.qsfp[1].scl.in); - TriState#(Bit#(1)) qsfp1_scl <- mkTriState(qsfp1_scl_out_en, qsfp1_scl_out); - mkConnection(sync(qsfp1_scl_in), qsfp1_scl._read); - ReadOnly#(Bool) qsfp1_sda_out_en <- mkOutputSyncFor(controller.qsfp[1].sda.out_en); - ReadOnly#(Bit#(1)) qsfp1_sda_out <- mkOutputSyncFor(controller.qsfp[1].sda.out); - InputReg#(Bit#(1), 2) qsfp1_sda_in <- mkInputSyncFor(controller.qsfp[1].sda.in); - TriState#(Bit#(1)) qsfp1_sda <- mkTriState(qsfp1_sda_out_en, qsfp1_sda_out); - mkConnection(sync(qsfp1_sda_in), qsfp1_sda._read); - - // P2 - ReadOnly#(Bool) qsfp2_hsc_en <- mkOutputSyncFor(controller.qsfp[2].power_en); - ReadOnly#(Bit#(1)) qsfp2_lpmode <- mkOutputSyncFor(controller.qsfp[2].lpmode); - ReadOnly#(Bit#(1)) qsfp2_resetl <- mkOutputSyncFor(controller.qsfp[2].resetl); - InputReg#(Bool, 2) qsfp2_hsc_pg <- mkInputSyncFor(controller.qsfp[2].power_good); - InputReg#(Bit#(1), 2) qsfp2_intl <- mkInputSyncFor(controller.qsfp[2].intl); - InputReg#(Bit#(1), 2) qsfp2_modprsl <- mkInputSyncFor(controller.qsfp[2].modprsl); - ReadOnly#(Bool) qsfp2_scl_out_en <- mkOutputSyncFor(controller.qsfp[2].scl.out_en); - ReadOnly#(Bit#(1)) qsfp2_scl_out <- mkOutputSyncFor(controller.qsfp[2].scl.out); - InputReg#(Bit#(1), 2) qsfp2_scl_in <- mkInputSyncFor(controller.qsfp[2].scl.in); - TriState#(Bit#(1)) qsfp2_scl <- mkTriState(qsfp2_scl_out_en, qsfp2_scl_out); - mkConnection(sync(qsfp2_scl_in), qsfp2_scl._read); - ReadOnly#(Bool) qsfp2_sda_out_en <- mkOutputSyncFor(controller.qsfp[2].sda.out_en); - ReadOnly#(Bit#(1)) qsfp2_sda_out <- mkOutputSyncFor(controller.qsfp[2].sda.out); - InputReg#(Bit#(1), 2) qsfp2_sda_in <- mkInputSyncFor(controller.qsfp[2].sda.in); - TriState#(Bit#(1)) qsfp2_sda <- mkTriState(qsfp2_sda_out_en, qsfp2_sda_out); - mkConnection(sync(qsfp2_sda_in), qsfp2_sda._read); - - // P3 - ReadOnly#(Bool) qsfp3_hsc_en <- mkOutputSyncFor(controller.qsfp[3].power_en); - ReadOnly#(Bit#(1)) qsfp3_lpmode <- mkOutputSyncFor(controller.qsfp[3].lpmode); - ReadOnly#(Bit#(1)) qsfp3_resetl <- mkOutputSyncFor(controller.qsfp[3].resetl); - InputReg#(Bool, 2) qsfp3_hsc_pg <- mkInputSyncFor(controller.qsfp[3].power_good); - InputReg#(Bit#(1), 2) qsfp3_intl <- mkInputSyncFor(controller.qsfp[3].intl); - InputReg#(Bit#(1), 2) qsfp3_modprsl <- mkInputSyncFor(controller.qsfp[3].modprsl); - ReadOnly#(Bool) qsfp3_scl_out_en <- mkOutputSyncFor(controller.qsfp[3].scl.out_en); - ReadOnly#(Bit#(1)) qsfp3_scl_out <- mkOutputSyncFor(controller.qsfp[3].scl.out); - InputReg#(Bit#(1), 2) qsfp3_scl_in <- mkInputSyncFor(controller.qsfp[3].scl.in); - TriState#(Bit#(1)) qsfp3_scl <- mkTriState(qsfp3_scl_out_en, qsfp3_scl_out); - mkConnection(sync(qsfp3_scl_in), qsfp3_scl._read); - ReadOnly#(Bool) qsfp3_sda_out_en <- mkOutputSyncFor(controller.qsfp[3].sda.out_en); - ReadOnly#(Bit#(1)) qsfp3_sda_out <- mkOutputSyncFor(controller.qsfp[3].sda.out); - InputReg#(Bit#(1), 2) qsfp3_sda_in <- mkInputSyncFor(controller.qsfp[3].sda.in); - TriState#(Bit#(1)) qsfp3_sda <- mkTriState(qsfp3_sda_out_en, qsfp3_sda_out); - mkConnection(sync(qsfp3_sda_in), qsfp3_sda._read); - - // P4 - ReadOnly#(Bool) qsfp4_hsc_en <- mkOutputSyncFor(controller.qsfp[4].power_en); - ReadOnly#(Bit#(1)) qsfp4_lpmode <- mkOutputSyncFor(controller.qsfp[4].lpmode); - ReadOnly#(Bit#(1)) qsfp4_resetl <- mkOutputSyncFor(controller.qsfp[4].resetl); - InputReg#(Bool, 2) qsfp4_hsc_pg <- mkInputSyncFor(controller.qsfp[4].power_good); - InputReg#(Bit#(1), 2) qsfp4_intl <- mkInputSyncFor(controller.qsfp[4].intl); - InputReg#(Bit#(1), 2) qsfp4_modprsl <- mkInputSyncFor(controller.qsfp[4].modprsl); - ReadOnly#(Bool) qsfp4_scl_out_en <- mkOutputSyncFor(controller.qsfp[4].scl.out_en); - ReadOnly#(Bit#(1)) qsfp4_scl_out <- mkOutputSyncFor(controller.qsfp[4].scl.out); - InputReg#(Bit#(1), 2) qsfp4_scl_in <- mkInputSyncFor(controller.qsfp[4].scl.in); - TriState#(Bit#(1)) qsfp4_scl <- mkTriState(qsfp4_scl_out_en, qsfp4_scl_out); - mkConnection(sync(qsfp4_scl_in), qsfp4_scl._read); - ReadOnly#(Bool) qsfp4_sda_out_en <- mkOutputSyncFor(controller.qsfp[4].sda.out_en); - ReadOnly#(Bit#(1)) qsfp4_sda_out <- mkOutputSyncFor(controller.qsfp[4].sda.out); - InputReg#(Bit#(1), 2) qsfp4_sda_in <- mkInputSyncFor(controller.qsfp[4].sda.in); - TriState#(Bit#(1)) qsfp4_sda <- mkTriState(qsfp4_sda_out_en, qsfp4_sda_out); - mkConnection(sync(qsfp4_sda_in), qsfp4_sda._read); - - // P5 - ReadOnly#(Bool) qsfp5_hsc_en <- mkOutputSyncFor(controller.qsfp[5].power_en); - ReadOnly#(Bit#(1)) qsfp5_lpmode <- mkOutputSyncFor(controller.qsfp[5].lpmode); - ReadOnly#(Bit#(1)) qsfp5_resetl <- mkOutputSyncFor(controller.qsfp[5].resetl); - InputReg#(Bool, 2) qsfp5_hsc_pg <- mkInputSyncFor(controller.qsfp[5].power_good); - InputReg#(Bit#(1), 2) qsfp5_intl <- mkInputSyncFor(controller.qsfp[5].intl); - InputReg#(Bit#(1), 2) qsfp5_modprsl <- mkInputSyncFor(controller.qsfp[5].modprsl); - ReadOnly#(Bool) qsfp5_scl_out_en <- mkOutputSyncFor(controller.qsfp[5].scl.out_en); - ReadOnly#(Bit#(1)) qsfp5_scl_out <- mkOutputSyncFor(controller.qsfp[5].scl.out); - InputReg#(Bit#(1), 2) qsfp5_scl_in <- mkInputSyncFor(controller.qsfp[5].scl.in); - TriState#(Bit#(1)) qsfp5_scl <- mkTriState(qsfp5_scl_out_en, qsfp5_scl_out); - mkConnection(sync(qsfp5_scl_in), qsfp5_scl._read); - ReadOnly#(Bool) qsfp5_sda_out_en <- mkOutputSyncFor(controller.qsfp[5].sda.out_en); - ReadOnly#(Bit#(1)) qsfp5_sda_out <- mkOutputSyncFor(controller.qsfp[5].sda.out); - InputReg#(Bit#(1), 2) qsfp5_sda_in <- mkInputSyncFor(controller.qsfp[5].sda.in); - TriState#(Bit#(1)) qsfp5_sda <- mkTriState(qsfp5_sda_out_en, qsfp5_sda_out); - mkConnection(sync(qsfp5_sda_in), qsfp5_sda._read); - - // P6 - ReadOnly#(Bool) qsfp6_hsc_en <- mkOutputSyncFor(controller.qsfp[6].power_en); - ReadOnly#(Bit#(1)) qsfp6_lpmode <- mkOutputSyncFor(controller.qsfp[6].lpmode); - ReadOnly#(Bit#(1)) qsfp6_resetl <- mkOutputSyncFor(controller.qsfp[6].resetl); - InputReg#(Bool, 2) qsfp6_hsc_pg <- mkInputSyncFor(controller.qsfp[6].power_good); - InputReg#(Bit#(1), 2) qsfp6_intl <- mkInputSyncFor(controller.qsfp[6].intl); - InputReg#(Bit#(1), 2) qsfp6_modprsl <- mkInputSyncFor(controller.qsfp[6].modprsl); - ReadOnly#(Bool) qsfp6_scl_out_en <- mkOutputSyncFor(controller.qsfp[6].scl.out_en); - ReadOnly#(Bit#(1)) qsfp6_scl_out <- mkOutputSyncFor(controller.qsfp[6].scl.out); - InputReg#(Bit#(1), 2) qsfp6_scl_in <- mkInputSyncFor(controller.qsfp[6].scl.in); - TriState#(Bit#(1)) qsfp6_scl <- mkTriState(qsfp6_scl_out_en, qsfp6_scl_out); - mkConnection(sync(qsfp6_scl_in), qsfp6_scl._read); - ReadOnly#(Bool) qsfp6_sda_out_en <- mkOutputSyncFor(controller.qsfp[6].sda.out_en); - ReadOnly#(Bit#(1)) qsfp6_sda_out <- mkOutputSyncFor(controller.qsfp[6].sda.out); - InputReg#(Bit#(1), 2) qsfp6_sda_in <- mkInputSyncFor(controller.qsfp[6].sda.in); - TriState#(Bit#(1)) qsfp6_sda <- mkTriState(qsfp6_sda_out_en, qsfp6_sda_out); - mkConnection(sync(qsfp6_sda_in), qsfp6_sda._read); - - // P7 - ReadOnly#(Bool) qsfp7_hsc_en <- mkOutputSyncFor(controller.qsfp[7].power_en); - ReadOnly#(Bit#(1)) qsfp7_lpmode <- mkOutputSyncFor(controller.qsfp[7].lpmode); - ReadOnly#(Bit#(1)) qsfp7_resetl <- mkOutputSyncFor(controller.qsfp[7].resetl); - InputReg#(Bool, 2) qsfp7_hsc_pg <- mkInputSyncFor(controller.qsfp[7].power_good); - InputReg#(Bit#(1), 2) qsfp7_intl <- mkInputSyncFor(controller.qsfp[7].intl); - InputReg#(Bit#(1), 2) qsfp7_modprsl <- mkInputSyncFor(controller.qsfp[7].modprsl); - ReadOnly#(Bool) qsfp7_scl_out_en <- mkOutputSyncFor(controller.qsfp[7].scl.out_en); - ReadOnly#(Bit#(1)) qsfp7_scl_out <- mkOutputSyncFor(controller.qsfp[7].scl.out); - InputReg#(Bit#(1), 2) qsfp7_scl_in <- mkInputSyncFor(controller.qsfp[7].scl.in); - TriState#(Bit#(1)) qsfp7_scl <- mkTriState(qsfp7_scl_out_en, qsfp7_scl_out); - mkConnection(sync(qsfp7_scl_in), qsfp7_scl._read); - ReadOnly#(Bool) qsfp7_sda_out_en <- mkOutputSyncFor(controller.qsfp[7].sda.out_en); - ReadOnly#(Bit#(1)) qsfp7_sda_out <- mkOutputSyncFor(controller.qsfp[7].sda.out); - InputReg#(Bit#(1), 2) qsfp7_sda_in <- mkInputSyncFor(controller.qsfp[7].sda.in); - TriState#(Bit#(1)) qsfp7_sda <- mkTriState(qsfp7_sda_out_en, qsfp7_sda_out); - mkConnection(sync(qsfp7_sda_in), qsfp7_sda._read); - - // P8 - ReadOnly#(Bool) qsfp8_hsc_en <- mkOutputSyncFor(controller.qsfp[8].power_en); - ReadOnly#(Bit#(1)) qsfp8_lpmode <- mkOutputSyncFor(controller.qsfp[8].lpmode); - ReadOnly#(Bit#(1)) qsfp8_resetl <- mkOutputSyncFor(controller.qsfp[8].resetl); - InputReg#(Bool, 2) qsfp8_hsc_pg <- mkInputSyncFor(controller.qsfp[8].power_good); - InputReg#(Bit#(1), 2) qsfp8_intl <- mkInputSyncFor(controller.qsfp[8].intl); - InputReg#(Bit#(1), 2) qsfp8_modprsl <- mkInputSyncFor(controller.qsfp[8].modprsl); - ReadOnly#(Bool) qsfp8_scl_out_en <- mkOutputSyncFor(controller.qsfp[8].scl.out_en); - ReadOnly#(Bit#(1)) qsfp8_scl_out <- mkOutputSyncFor(controller.qsfp[8].scl.out); - InputReg#(Bit#(1), 2) qsfp8_scl_in <- mkInputSyncFor(controller.qsfp[8].scl.in); - TriState#(Bit#(1)) qsfp8_scl <- mkTriState(qsfp8_scl_out_en, qsfp8_scl_out); - mkConnection(sync(qsfp8_scl_in), qsfp8_scl._read); - ReadOnly#(Bool) qsfp8_sda_out_en <- mkOutputSyncFor(controller.qsfp[8].sda.out_en); - ReadOnly#(Bit#(1)) qsfp8_sda_out <- mkOutputSyncFor(controller.qsfp[8].sda.out); - InputReg#(Bit#(1), 2) qsfp8_sda_in <- mkInputSyncFor(controller.qsfp[8].sda.in); - TriState#(Bit#(1)) qsfp8_sda <- mkTriState(qsfp8_sda_out_en, qsfp8_sda_out); - mkConnection(sync(qsfp8_sda_in), qsfp8_sda._read); - - // P9 - ReadOnly#(Bool) qsfp9_hsc_en <- mkOutputSyncFor(controller.qsfp[9].power_en); - ReadOnly#(Bit#(1)) qsfp9_lpmode <- mkOutputSyncFor(controller.qsfp[9].lpmode); - ReadOnly#(Bit#(1)) qsfp9_resetl <- mkOutputSyncFor(controller.qsfp[9].resetl); - InputReg#(Bool, 2) qsfp9_hsc_pg <- mkInputSyncFor(controller.qsfp[9].power_good); - InputReg#(Bit#(1), 2) qsfp9_intl <- mkInputSyncFor(controller.qsfp[9].intl); - InputReg#(Bit#(1), 2) qsfp9_modprsl <- mkInputSyncFor(controller.qsfp[9].modprsl); - ReadOnly#(Bool) qsfp9_scl_out_en <- mkOutputSyncFor(controller.qsfp[9].scl.out_en); - ReadOnly#(Bit#(1)) qsfp9_scl_out <- mkOutputSyncFor(controller.qsfp[9].scl.out); - InputReg#(Bit#(1), 2) qsfp9_scl_in <- mkInputSyncFor(controller.qsfp[9].scl.in); - TriState#(Bit#(1)) qsfp9_scl <- mkTriState(qsfp9_scl_out_en, qsfp9_scl_out); - mkConnection(sync(qsfp9_scl_in), qsfp9_scl._read); - ReadOnly#(Bool) qsfp9_sda_out_en <- mkOutputSyncFor(controller.qsfp[9].sda.out_en); - ReadOnly#(Bit#(1)) qsfp9_sda_out <- mkOutputSyncFor(controller.qsfp[9].sda.out); - InputReg#(Bit#(1), 2) qsfp9_sda_in <- mkInputSyncFor(controller.qsfp[9].sda.in); - TriState#(Bit#(1)) qsfp9_sda <- mkTriState(qsfp9_sda_out_en, qsfp9_sda_out); - mkConnection(sync(qsfp9_sda_in), qsfp9_sda._read); - - // P10 - ReadOnly#(Bool) qsfp10_hsc_en <- mkOutputSyncFor(controller.qsfp[10].power_en); - ReadOnly#(Bit#(1)) qsfp10_lpmode <- mkOutputSyncFor(controller.qsfp[10].lpmode); - ReadOnly#(Bit#(1)) qsfp10_resetl <- mkOutputSyncFor(controller.qsfp[10].resetl); - InputReg#(Bool, 2) qsfp10_hsc_pg <- mkInputSyncFor(controller.qsfp[10].power_good); - InputReg#(Bit#(1), 2) qsfp10_intl <- mkInputSyncFor(controller.qsfp[10].intl); - InputReg#(Bit#(1), 2) qsfp10_modprsl<- mkInputSyncFor(controller.qsfp[10].modprsl); - ReadOnly#(Bool) qsfp10_scl_out_en <- mkOutputSyncFor(controller.qsfp[10].scl.out_en); - ReadOnly#(Bit#(1)) qsfp10_scl_out <- mkOutputSyncFor(controller.qsfp[10].scl.out); - InputReg#(Bit#(1), 2) qsfp10_scl_in <- mkInputSyncFor(controller.qsfp[10].scl.in); - TriState#(Bit#(1)) qsfp10_scl <- mkTriState(qsfp10_scl_out_en, qsfp10_scl_out); - mkConnection(sync(qsfp10_scl_in), qsfp10_scl._read); - ReadOnly#(Bool) qsfp10_sda_out_en <- mkOutputSyncFor(controller.qsfp[10].sda.out_en); - ReadOnly#(Bit#(1)) qsfp10_sda_out <- mkOutputSyncFor(controller.qsfp[10].sda.out); - InputReg#(Bit#(1), 2) qsfp10_sda_in <- mkInputSyncFor(controller.qsfp[10].sda.in); - TriState#(Bit#(1)) qsfp10_sda <- mkTriState(qsfp10_sda_out_en, qsfp10_sda_out); - mkConnection(sync(qsfp10_sda_in), qsfp10_sda._read); - - // P11 - ReadOnly#(Bool) qsfp11_hsc_en <- mkOutputSyncFor(controller.qsfp[11].power_en); - ReadOnly#(Bit#(1)) qsfp11_lpmode <- mkOutputSyncFor(controller.qsfp[11].lpmode); - ReadOnly#(Bit#(1)) qsfp11_resetl <- mkOutputSyncFor(controller.qsfp[11].resetl); - InputReg#(Bool, 2) qsfp11_hsc_pg <- mkInputSyncFor(controller.qsfp[11].power_good); - InputReg#(Bit#(1), 2) qsfp11_intl <- mkInputSyncFor(controller.qsfp[11].intl); - InputReg#(Bit#(1), 2) qsfp11_modprsl<- mkInputSyncFor(controller.qsfp[11].modprsl); - ReadOnly#(Bool) qsfp11_scl_out_en <- mkOutputSyncFor(controller.qsfp[11].scl.out_en); - ReadOnly#(Bit#(1)) qsfp11_scl_out <- mkOutputSyncFor(controller.qsfp[11].scl.out); - InputReg#(Bit#(1), 2) qsfp11_scl_in <- mkInputSyncFor(controller.qsfp[11].scl.in); - TriState#(Bit#(1)) qsfp11_scl <- mkTriState(qsfp11_scl_out_en, qsfp11_scl_out); - mkConnection(sync(qsfp11_scl_in), qsfp11_scl._read); - ReadOnly#(Bool) qsfp11_sda_out_en <- mkOutputSyncFor(controller.qsfp[11].sda.out_en); - ReadOnly#(Bit#(1)) qsfp11_sda_out <- mkOutputSyncFor(controller.qsfp[11].sda.out); - InputReg#(Bit#(1), 2) qsfp11_sda_in <- mkInputSyncFor(controller.qsfp[11].sda.in); - TriState#(Bit#(1)) qsfp11_sda <- mkTriState(qsfp11_sda_out_en, qsfp11_sda_out); - mkConnection(sync(qsfp11_sda_in), qsfp11_sda._read); - - // P12 - ReadOnly#(Bool) qsfp12_hsc_en <- mkOutputSyncFor(controller.qsfp[12].power_en); - ReadOnly#(Bit#(1)) qsfp12_lpmode <- mkOutputSyncFor(controller.qsfp[12].lpmode); - ReadOnly#(Bit#(1)) qsfp12_resetl <- mkOutputSyncFor(controller.qsfp[12].resetl); - InputReg#(Bool, 2) qsfp12_hsc_pg <- mkInputSyncFor(controller.qsfp[12].power_good); - InputReg#(Bit#(1), 2) qsfp12_intl <- mkInputSyncFor(controller.qsfp[12].intl); - InputReg#(Bit#(1), 2) qsfp12_modprsl<- mkInputSyncFor(controller.qsfp[12].modprsl); - ReadOnly#(Bool) qsfp12_scl_out_en <- mkOutputSyncFor(controller.qsfp[12].scl.out_en); - ReadOnly#(Bit#(1)) qsfp12_scl_out <- mkOutputSyncFor(controller.qsfp[12].scl.out); - InputReg#(Bit#(1), 2) qsfp12_scl_in <- mkInputSyncFor(controller.qsfp[12].scl.in); - TriState#(Bit#(1)) qsfp12_scl <- mkTriState(qsfp12_scl_out_en, qsfp12_scl_out); - mkConnection(sync(qsfp12_scl_in), qsfp12_scl._read); - ReadOnly#(Bool) qsfp12_sda_out_en <- mkOutputSyncFor(controller.qsfp[12].sda.out_en); - ReadOnly#(Bit#(1)) qsfp12_sda_out <- mkOutputSyncFor(controller.qsfp[12].sda.out); - InputReg#(Bit#(1), 2) qsfp12_sda_in <- mkInputSyncFor(controller.qsfp[12].sda.in); - TriState#(Bit#(1)) qsfp12_sda <- mkTriState(qsfp12_sda_out_en, qsfp12_sda_out); - mkConnection(sync(qsfp12_sda_in), qsfp12_sda._read); - - // P13 - ReadOnly#(Bool) qsfp13_hsc_en <- mkOutputSyncFor(controller.qsfp[13].power_en); - ReadOnly#(Bit#(1)) qsfp13_lpmode <- mkOutputSyncFor(controller.qsfp[13].lpmode); - ReadOnly#(Bit#(1)) qsfp13_resetl <- mkOutputSyncFor(controller.qsfp[13].resetl); - InputReg#(Bool, 2) qsfp13_hsc_pg <- mkInputSyncFor(controller.qsfp[13].power_good); - InputReg#(Bit#(1), 2) qsfp13_intl <- mkInputSyncFor(controller.qsfp[13].intl); - InputReg#(Bit#(1), 2) qsfp13_modprsl<- mkInputSyncFor(controller.qsfp[13].modprsl); - ReadOnly#(Bool) qsfp13_scl_out_en <- mkOutputSyncFor(controller.qsfp[13].scl.out_en); - ReadOnly#(Bit#(1)) qsfp13_scl_out <- mkOutputSyncFor(controller.qsfp[13].scl.out); - InputReg#(Bit#(1), 2) qsfp13_scl_in <- mkInputSyncFor(controller.qsfp[13].scl.in); - TriState#(Bit#(1)) qsfp13_scl <- mkTriState(qsfp13_scl_out_en, qsfp13_scl_out); - mkConnection(sync(qsfp13_scl_in), qsfp13_scl._read); - ReadOnly#(Bool) qsfp13_sda_out_en <- mkOutputSyncFor(controller.qsfp[13].sda.out_en); - ReadOnly#(Bit#(1)) qsfp13_sda_out <- mkOutputSyncFor(controller.qsfp[13].sda.out); - InputReg#(Bit#(1), 2) qsfp13_sda_in <- mkInputSyncFor(controller.qsfp[13].sda.in); - TriState#(Bit#(1)) qsfp13_sda <- mkTriState(qsfp13_sda_out_en, qsfp13_sda_out); - mkConnection(sync(qsfp13_sda_in), qsfp13_sda._read); - - // P14 - ReadOnly#(Bool) qsfp14_hsc_en <- mkOutputSyncFor(controller.qsfp[14].power_en); - ReadOnly#(Bit#(1)) qsfp14_lpmode <- mkOutputSyncFor(controller.qsfp[14].lpmode); - ReadOnly#(Bit#(1)) qsfp14_resetl <- mkOutputSyncFor(controller.qsfp[14].resetl); - InputReg#(Bool, 2) qsfp14_hsc_pg <- mkInputSyncFor(controller.qsfp[14].power_good); - InputReg#(Bit#(1), 2) qsfp14_intl <- mkInputSyncFor(controller.qsfp[14].intl); - InputReg#(Bit#(1), 2) qsfp14_modprsl<- mkInputSyncFor(controller.qsfp[14].modprsl); - ReadOnly#(Bool) qsfp14_scl_out_en <- mkOutputSyncFor(controller.qsfp[14].scl.out_en); - ReadOnly#(Bit#(1)) qsfp14_scl_out <- mkOutputSyncFor(controller.qsfp[14].scl.out); - InputReg#(Bit#(1), 2) qsfp14_scl_in <- mkInputSyncFor(controller.qsfp[14].scl.in); - TriState#(Bit#(1)) qsfp14_scl <- mkTriState(qsfp14_scl_out_en, qsfp14_scl_out); - mkConnection(sync(qsfp14_scl_in), qsfp14_scl._read); - ReadOnly#(Bool) qsfp14_sda_out_en <- mkOutputSyncFor(controller.qsfp[14].sda.out_en); - ReadOnly#(Bit#(1)) qsfp14_sda_out <- mkOutputSyncFor(controller.qsfp[14].sda.out); - InputReg#(Bit#(1), 2) qsfp14_sda_in <- mkInputSyncFor(controller.qsfp[14].sda.in); - TriState#(Bit#(1)) qsfp14_sda <- mkTriState(qsfp14_sda_out_en, qsfp14_sda_out); - mkConnection(sync(qsfp14_sda_in), qsfp14_sda._read); - - // P15 - ReadOnly#(Bool) qsfp15_hsc_en <- mkOutputSyncFor(controller.qsfp[15].power_en); - ReadOnly#(Bit#(1)) qsfp15_lpmode <- mkOutputSyncFor(controller.qsfp[15].lpmode); - ReadOnly#(Bit#(1)) qsfp15_resetl <- mkOutputSyncFor(controller.qsfp[15].resetl); - InputReg#(Bool, 2) qsfp15_hsc_pg <- mkInputSyncFor(controller.qsfp[15].power_good); - InputReg#(Bit#(1), 2) qsfp15_intl <- mkInputSyncFor(controller.qsfp[15].intl); - InputReg#(Bit#(1), 2) qsfp15_modprsl<- mkInputSyncFor(controller.qsfp[15].modprsl); - ReadOnly#(Bool) qsfp15_scl_out_en <- mkOutputSyncFor(controller.qsfp[15].scl.out_en); - ReadOnly#(Bit#(1)) qsfp15_scl_out <- mkOutputSyncFor(controller.qsfp[15].scl.out); - InputReg#(Bit#(1), 2) qsfp15_scl_in <- mkInputSyncFor(controller.qsfp[15].scl.in); - TriState#(Bit#(1)) qsfp15_scl <- mkTriState(qsfp15_scl_out_en, qsfp15_scl_out); - mkConnection(sync(qsfp15_scl_in), qsfp15_scl._read); - ReadOnly#(Bool) qsfp15_sda_out_en <- mkOutputSyncFor(controller.qsfp[15].sda.out_en); - ReadOnly#(Bit#(1)) qsfp15_sda_out <- mkOutputSyncFor(controller.qsfp[15].sda.out); - InputReg#(Bit#(1), 2) qsfp15_sda_in <- mkInputSyncFor(controller.qsfp[15].sda.in); - TriState#(Bit#(1)) qsfp15_sda <- mkTriState(qsfp15_sda_out_en, qsfp15_sda_out); - mkConnection(sync(qsfp15_sda_in), qsfp15_sda._read); - - // - // SPI Peripheral - // - - InputReg#(Bit#(1), 2) csn <- mkInputSyncFor(controller.spi.csn); - InputReg#(Bit#(1), 2) sclk <- mkInputSyncFor(controller.spi.sclk); - InputReg#(Bit#(1), 2) copi <- mkInputSyncFor(controller.spi.copi); - ReadOnly#(Bit#(1)) cipo <- mkOutputSyncFor(controller.spi.cipo); - - // - // Power - // - - // - // PHY - // - ReadOnly#(Bool) phy_vr_en <- mkOutputSyncFor(controller.vsc8562.v1p0.en); - InputReg#(Bool, 2) phy_v1p0_pg <- mkInputSyncFor(controller.vsc8562.v1p0.pg); - InputReg#(Bool, 2) phy_v2p5_pg <- mkInputSyncFor(controller.vsc8562.v2p5.pg); - - ReadOnly#(Bit#(1)) phy_coma_mode <- mkOutputSyncFor(controller.vsc8562.coma_mode); - ReadOnly#(Bit#(1)) phy_refclk_en <- mkOutputSyncFor(controller.vsc8562.refclk_en); - ReadOnly#(Bit#(1)) phy_reset_ <- mkOutputSyncFor(controller.vsc8562.reset_); - - ReadOnly#(Bit#(1)) phy_mdc <- mkOutputSyncFor(controller.vsc8562.smi.mdc); - InputReg#(Bit#(1), 2) phy_mdint <- mkInputSyncFor(controller.vsc8562.mdint); - ReadOnly#(Bool) phy_mdio_out_en <- mkOutputSyncFor(controller.vsc8562.smi.mdio.out_en); - ReadOnly#(Bit#(1)) phy_mdio_out <- mkOutputSyncFor(controller.vsc8562.smi.mdio.out); - InputReg#(Bit#(1), 2) phy_mdio_in <- mkInputSyncFor(controller.vsc8562.smi.mdio.in); - TriState#(Bit#(1)) phy_mdio <- mkTriState(phy_mdio_out_en, phy_mdio_out); - mkConnection(sync(phy_mdio_in), phy_mdio._read); - - // - // Miscellaneous - // - ReadOnly#(Bit#(1)) fpga_led_blinky <- mkOutputSyncFor(controller.blinky.led[0]); - InputReg#(Bit#(1), 2) fpga_app_id <- mkInputSyncFor(controller.top.fpga_app_id); - ReadOnly#(Bit#(1)) led_reset <- mkOutputSyncFor(controller.top.led_controller_reset); - ReadOnly#(Bit#(1)) led_oe <- mkOutputSyncFor(controller.top.led_controller_output_en); - InputReg#(Bit#(1), 2) pmbus_v3p3_alert <- mkInputSync(); - InputReg#(Bit#(1), 2) vr_v3p3_pg <- mkInputSync(); - InputReg#(Bit#(5), 2) fpga_board_ver_in <- mkInputSyncFor(controller.top.fpga_board_ver); - - // - // Wire design out to the device pins - // - - // - // QSFP Ports - // - method fpga_to_qsfp_en_0 = qsfp0_hsc_en; - method fpga_to_qsfp_lpmode_0 = qsfp0_lpmode; - method fpga_to_qsfp_reset_l_0 = qsfp0_resetl; - method qsfp_to_fpga_pg_0 = sync(qsfp0_hsc_pg); - method qsfp_to_fpga_irq_l_0 = sync(qsfp0_intl); - method qsfp_to_fpga_present_l_0 = sync(qsfp0_modprsl); - interface i2c_fpga_to_qsfp_scl_0 = qsfp0_scl.io; - interface i2c_fpga_to_qsfp_sda_0 = qsfp0_sda.io; - - method fpga_to_qsfp_en_1 = qsfp1_hsc_en; - method fpga_to_qsfp_lpmode_1 = qsfp1_lpmode; - method fpga_to_qsfp_reset_l_1 = qsfp1_resetl; - method qsfp_to_fpga_pg_1 = sync(qsfp1_hsc_pg); - method qsfp_to_fpga_irq_l_1 = sync(qsfp1_intl); - method qsfp_to_fpga_present_l_1 = sync(qsfp1_modprsl); - interface i2c_fpga_to_qsfp_scl_1 = qsfp1_scl.io; - interface i2c_fpga_to_qsfp_sda_1 = qsfp1_sda.io; - - method fpga_to_qsfp_en_2 = qsfp2_hsc_en; - method fpga_to_qsfp_lpmode_2 = qsfp2_lpmode; - method fpga_to_qsfp_reset_l_2 = qsfp2_resetl; - method qsfp_to_fpga_pg_2 = sync(qsfp2_hsc_pg); - method qsfp_to_fpga_irq_l_2 = sync(qsfp2_intl); - method qsfp_to_fpga_present_l_2 = sync(qsfp2_modprsl); - interface i2c_fpga_to_qsfp_scl_2 = qsfp2_scl.io; - interface i2c_fpga_to_qsfp_sda_2 = qsfp2_sda.io; - - method fpga_to_qsfp_en_3 = qsfp3_hsc_en; - method fpga_to_qsfp_lpmode_3 = qsfp3_lpmode; - method fpga_to_qsfp_reset_l_3 = qsfp3_resetl; - method qsfp_to_fpga_pg_3 = sync(qsfp3_hsc_pg); - method qsfp_to_fpga_irq_l_3 = sync(qsfp3_intl); - method qsfp_to_fpga_present_l_3 = sync(qsfp3_modprsl); - interface i2c_fpga_to_qsfp_scl_3 = qsfp3_scl.io; - interface i2c_fpga_to_qsfp_sda_3 = qsfp3_sda.io; - - method fpga_to_qsfp_en_4 = qsfp4_hsc_en; - method fpga_to_qsfp_lpmode_4 = qsfp4_lpmode; - method fpga_to_qsfp_reset_l_4 = qsfp4_resetl; - method qsfp_to_fpga_pg_4 = sync(qsfp4_hsc_pg); - method qsfp_to_fpga_irq_l_4 = sync(qsfp4_intl); - method qsfp_to_fpga_present_l_4 = sync(qsfp4_modprsl); - interface i2c_fpga_to_qsfp_scl_4 = qsfp4_scl.io; - interface i2c_fpga_to_qsfp_sda_4 = qsfp4_sda.io; - - method fpga_to_qsfp_en_5 = qsfp5_hsc_en; - method fpga_to_qsfp_lpmode_5 = qsfp5_lpmode; - method fpga_to_qsfp_reset_l_5 = qsfp5_resetl; - method qsfp_to_fpga_pg_5 = sync(qsfp5_hsc_pg); - method qsfp_to_fpga_irq_l_5 = sync(qsfp5_intl); - method qsfp_to_fpga_present_l_5 = sync(qsfp5_modprsl); - interface i2c_fpga_to_qsfp_scl_5 = qsfp5_scl.io; - interface i2c_fpga_to_qsfp_sda_5 = qsfp5_sda.io; - - method fpga_to_qsfp_en_6 = qsfp6_hsc_en; - method fpga_to_qsfp_lpmode_6 = qsfp6_lpmode; - method fpga_to_qsfp_reset_l_6 = qsfp6_resetl; - method qsfp_to_fpga_pg_6 = sync(qsfp6_hsc_pg); - method qsfp_to_fpga_irq_l_6 = sync(qsfp6_intl); - method qsfp_to_fpga_present_l_6 = sync(qsfp6_modprsl); - interface i2c_fpga_to_qsfp_scl_6 = qsfp6_scl.io; - interface i2c_fpga_to_qsfp_sda_6 = qsfp6_sda.io; - - method fpga_to_qsfp_en_7 = qsfp7_hsc_en; - method fpga_to_qsfp_lpmode_7 = qsfp7_lpmode; - method fpga_to_qsfp_reset_l_7 = qsfp7_resetl; - method qsfp_to_fpga_pg_7 = sync(qsfp7_hsc_pg); - method qsfp_to_fpga_irq_l_7 = sync(qsfp7_intl); - method qsfp_to_fpga_present_l_7 = sync(qsfp7_modprsl); - interface i2c_fpga_to_qsfp_scl_7 = qsfp7_scl.io; - interface i2c_fpga_to_qsfp_sda_7 = qsfp7_sda.io; - - method fpga_to_qsfp_en_8 = qsfp8_hsc_en; - method fpga_to_qsfp_lpmode_8 = qsfp8_lpmode; - method fpga_to_qsfp_reset_l_8 = qsfp8_resetl; - method qsfp_to_fpga_pg_8 = sync(qsfp8_hsc_pg); - method qsfp_to_fpga_irq_l_8 = sync(qsfp8_intl); - method qsfp_to_fpga_present_l_8 = sync(qsfp8_modprsl); - interface i2c_fpga_to_qsfp_scl_8 = qsfp8_scl.io; - interface i2c_fpga_to_qsfp_sda_8 = qsfp8_sda.io; - - method fpga_to_qsfp_en_9 = qsfp9_hsc_en; - method fpga_to_qsfp_lpmode_9 = qsfp9_lpmode; - method fpga_to_qsfp_reset_l_9 = qsfp9_resetl; - method qsfp_to_fpga_pg_9 = sync(qsfp9_hsc_pg); - method qsfp_to_fpga_irq_l_9 = sync(qsfp9_intl); - method qsfp_to_fpga_present_l_9 = sync(qsfp9_modprsl); - interface i2c_fpga_to_qsfp_scl_9 = qsfp9_scl.io; - interface i2c_fpga_to_qsfp_sda_9 = qsfp9_sda.io; - - method fpga_to_qsfp_en_10 = qsfp10_hsc_en; - method fpga_to_qsfp_lpmode_10 = qsfp10_lpmode; - method fpga_to_qsfp_reset_l_10 = qsfp10_resetl; - method qsfp_to_fpga_pg_10 = sync(qsfp10_hsc_pg); - method qsfp_to_fpga_irq_l_10 = sync(qsfp10_intl); - method qsfp_to_fpga_present_l_10 = sync(qsfp10_modprsl); - interface i2c_fpga_to_qsfp_scl_10 = qsfp10_scl.io; - interface i2c_fpga_to_qsfp_sda_10 = qsfp10_sda.io; - - method fpga_to_qsfp_en_11 = qsfp11_hsc_en; - method fpga_to_qsfp_lpmode_11 = qsfp11_lpmode; - method fpga_to_qsfp_reset_l_11 = qsfp11_resetl; - method qsfp_to_fpga_pg_11 = sync(qsfp11_hsc_pg); - method qsfp_to_fpga_irq_l_11 = sync(qsfp11_intl); - method qsfp_to_fpga_present_l_11 = sync(qsfp11_modprsl); - interface i2c_fpga_to_qsfp_scl_11 = qsfp11_scl.io; - interface i2c_fpga_to_qsfp_sda_11 = qsfp11_sda.io; - - method fpga_to_qsfp_en_12 = qsfp12_hsc_en; - method fpga_to_qsfp_lpmode_12 = qsfp12_lpmode; - method fpga_to_qsfp_reset_l_12 = qsfp12_resetl; - method qsfp_to_fpga_pg_12 = sync(qsfp12_hsc_pg); - method qsfp_to_fpga_irq_l_12 = sync(qsfp12_intl); - method qsfp_to_fpga_present_l_12 = sync(qsfp12_modprsl); - interface i2c_fpga_to_qsfp_scl_12 = qsfp12_scl.io; - interface i2c_fpga_to_qsfp_sda_12 = qsfp12_sda.io; - - method fpga_to_qsfp_en_13 = qsfp13_hsc_en; - method fpga_to_qsfp_lpmode_13 = qsfp13_lpmode; - method fpga_to_qsfp_reset_l_13 = qsfp13_resetl; - method qsfp_to_fpga_pg_13 = sync(qsfp13_hsc_pg); - method qsfp_to_fpga_irq_l_13 = sync(qsfp13_intl); - method qsfp_to_fpga_present_l_13 = sync(qsfp13_modprsl); - interface i2c_fpga_to_qsfp_scl_13 = qsfp13_scl.io; - interface i2c_fpga_to_qsfp_sda_13 = qsfp13_sda.io; - - method fpga_to_qsfp_en_14 = qsfp14_hsc_en; - method fpga_to_qsfp_lpmode_14 = qsfp14_lpmode; - method fpga_to_qsfp_reset_l_14 = qsfp14_resetl; - method qsfp_to_fpga_pg_14 = sync(qsfp14_hsc_pg); - method qsfp_to_fpga_irq_l_14 = sync(qsfp14_intl); - method qsfp_to_fpga_present_l_14 = sync(qsfp14_modprsl); - interface i2c_fpga_to_qsfp_scl_14 = qsfp14_scl.io; - interface i2c_fpga_to_qsfp_sda_14 = qsfp14_sda.io; - - method fpga_to_qsfp_en_15 = qsfp15_hsc_en; - method fpga_to_qsfp_lpmode_15 = qsfp15_lpmode; - method fpga_to_qsfp_reset_l_15 = qsfp15_resetl; - method qsfp_to_fpga_pg_15 = sync(qsfp15_hsc_pg); - method qsfp_to_fpga_irq_l_15 = sync(qsfp15_intl); - method qsfp_to_fpga_present_l_15 = sync(qsfp15_modprsl); - interface i2c_fpga_to_qsfp_scl_15 = qsfp15_scl.io; - interface i2c_fpga_to_qsfp_sda_15 = qsfp15_sda.io; - - // - // SPI Peripheral - // - - method spi_main_to_fpga_cs1_l = sync(csn); - method spi_main_to_fpga_sck = sync(sclk); - method spi_main_to_fpga_mosi = sync(copi); - method spi_main_to_fpga_miso_r = cipo; - - // - // Power - // - - // - // PHY - // - - method fpga_to_vr_phy_en = phy_vr_en; - method vr_v1p0_phy_to_fpga_pg = sync(phy_v1p0_pg); - method vr_v2p5_phy_to_fpga_pg = sync(phy_v2p5_pg); - - method fpga_to_phy_refclk_en; - // The PHY oscillator on Rev B and C boards has an errata for its EN - // pin, causing it on occasion to misbehave when enabled (much) later - // after PoR. On these boards always enable the output irrespective of - // sequencer state. - if (fpga_board_ver_in == 'h1 || fpga_board_ver_in == 'h2) begin - return 1; - end else begin - return phy_refclk_en; - end - endmethod - method fpga_to_phy_coma_mode = phy_coma_mode; - method fpga_to_phy_reset_l = ~phy_reset_; - - method miim_fpga_to_phy_mdc = phy_mdc; - method miim_phy_to_fpga_mdint_l = sync_inverted(phy_mdint); - interface miim_fpga_to_phy_mdio = phy_mdio.io; - - // - // Miscellaneous - // - - method Bit#(1) fpga_to_vr_v3p3_qsfp_en = 1; - method vr_v3p3_qsfp_to_fpga_pg = sync(vr_v3p3_pg); - method pmbus_v3p3_qsfp_to_fpga_alert = sync(pmbus_v3p3_alert); - - method Bit#(1) fpga_to_main_irq_r_l = 1; - method Bit#(1) fpga_led = fpga_led_blinky; - method Bit#(1) fpga_to_leds0_reset_l = ~led_reset; - method Bit#(1) fpga_to_leds0_oe_l = ~led_oe; - method fpga_app_id_r = sync(fpga_app_id); - method Bit#(8) debug_fpga_io = { - qsfp3_sda._read, // Bit 7, J31 pin 10 - qsfp3_scl._read, // Bit 6, J31 pin 9 - qsfp2_sda._read, // Bit 5, J31 pin 8 - qsfp2_scl._read, // Bit 4, J31 pin 7 - qsfp1_sda._read, // Bit 3, J31 pin 4 - qsfp1_scl._read, // Bit 2, J31 pin 3 - qsfp0_sda._read, // Bit 1, J31 pin 2 - qsfp0_scl._read}; // Bit 0, J31 pin 1 - method fpga_board_ver = sync(fpga_board_ver_in); -endmodule - -endpackage: QsfpX32ControllerTop +// +// This Source Code Form is subject to the terms of the Mozilla Public +// License, v. 2.0. If a copy of the MPL was not distributed with this +// file, You can obtain one at https://mozilla.org/MPL/2.0/. +package QsfpX32ControllerTop; + +// BSV Core +import Clocks::*; +import Connectable::*; +import GetPut::*; +import StmtFSM::*; +import TriState::*; +import Vector::*; + +// Oxide +import Bidirection::*; +import Blinky::*; +import I2CCommon::*; +import I2CCore::*; +import I2CBitController::*; +import IOSync::*; +import SPI::*; +import Strobe::*; +import PowerRail::*; + +import MDIO::*; + +// QSFP +import QsfpModuleController::*; +import QsfpModulesTop::*; +import QsfpX32Controller::*; +import QsfpX32ControllerTopRegs::*; +import VSC8562::*; + +(* always_enabled *) +interface QsfpControllerTop; + // + // QSFP Ports + // + method Bool fpga_to_qsfp_en_0; + method Bit#(1) fpga_to_qsfp_lpmode_0; + method Bit#(1) fpga_to_qsfp_reset_l_0; + (* prefix = "" *) method Action qsfp_to_fpga_pg_0(Bool qsfp_to_fpga_pg_0); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_0(Bit#(1) qsfp_to_fpga_irq_l_0); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_0(Bit#(1) qsfp_to_fpga_present_l_0); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_0; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_0; + + method Bool fpga_to_qsfp_en_1; + method Bit#(1) fpga_to_qsfp_lpmode_1; + method Bit#(1) fpga_to_qsfp_reset_l_1; + (* prefix = "" *) method Action qsfp_to_fpga_pg_1(Bool qsfp_to_fpga_pg_1); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_1(Bit#(1) qsfp_to_fpga_irq_l_1); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_1(Bit#(1) qsfp_to_fpga_present_l_1); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_1; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_1; + + method Bool fpga_to_qsfp_en_2; + method Bit#(1) fpga_to_qsfp_lpmode_2; + method Bit#(1) fpga_to_qsfp_reset_l_2; + (* prefix = "" *) method Action qsfp_to_fpga_pg_2(Bool qsfp_to_fpga_pg_2); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_2(Bit#(1) qsfp_to_fpga_irq_l_2); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_2(Bit#(1) qsfp_to_fpga_present_l_2); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_2; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_2; + + method Bool fpga_to_qsfp_en_3; + method Bit#(1) fpga_to_qsfp_lpmode_3; + method Bit#(1) fpga_to_qsfp_reset_l_3; + (* prefix = "" *) method Action qsfp_to_fpga_pg_3(Bool qsfp_to_fpga_pg_3); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_3(Bit#(1) qsfp_to_fpga_irq_l_3); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_3(Bit#(1) qsfp_to_fpga_present_l_3); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_3; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_3; + + method Bool fpga_to_qsfp_en_4; + method Bit#(1) fpga_to_qsfp_lpmode_4; + method Bit#(1) fpga_to_qsfp_reset_l_4; + (* prefix = "" *) method Action qsfp_to_fpga_pg_4(Bool qsfp_to_fpga_pg_4); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_4(Bit#(1) qsfp_to_fpga_irq_l_4); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_4(Bit#(1) qsfp_to_fpga_present_l_4); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_4; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_4; + + method Bool fpga_to_qsfp_en_5; + method Bit#(1) fpga_to_qsfp_lpmode_5; + method Bit#(1) fpga_to_qsfp_reset_l_5; + (* prefix = "" *) method Action qsfp_to_fpga_pg_5(Bool qsfp_to_fpga_pg_5); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_5(Bit#(1) qsfp_to_fpga_irq_l_5); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_5(Bit#(1) qsfp_to_fpga_present_l_5); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_5; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_5; + + method Bool fpga_to_qsfp_en_6; + method Bit#(1) fpga_to_qsfp_lpmode_6; + method Bit#(1) fpga_to_qsfp_reset_l_6; + (* prefix = "" *) method Action qsfp_to_fpga_pg_6(Bool qsfp_to_fpga_pg_6); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_6(Bit#(1) qsfp_to_fpga_irq_l_6); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_6(Bit#(1) qsfp_to_fpga_present_l_6); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_6; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_6; + + method Bool fpga_to_qsfp_en_7; + method Bit#(1) fpga_to_qsfp_lpmode_7; + method Bit#(1) fpga_to_qsfp_reset_l_7; + (* prefix = "" *) method Action qsfp_to_fpga_pg_7(Bool qsfp_to_fpga_pg_7); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_7(Bit#(1) qsfp_to_fpga_irq_l_7); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_7(Bit#(1) qsfp_to_fpga_present_l_7); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_7; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_7; + + method Bool fpga_to_qsfp_en_8; + method Bit#(1) fpga_to_qsfp_lpmode_8; + method Bit#(1) fpga_to_qsfp_reset_l_8; + (* prefix = "" *) method Action qsfp_to_fpga_pg_8(Bool qsfp_to_fpga_pg_8); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_8(Bit#(1) qsfp_to_fpga_irq_l_8); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_8(Bit#(1) qsfp_to_fpga_present_l_8); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_8; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_8; + + method Bool fpga_to_qsfp_en_9; + method Bit#(1) fpga_to_qsfp_lpmode_9; + method Bit#(1) fpga_to_qsfp_reset_l_9; + (* prefix = "" *) method Action qsfp_to_fpga_pg_9(Bool qsfp_to_fpga_pg_9); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_9(Bit#(1) qsfp_to_fpga_irq_l_9); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_9(Bit#(1) qsfp_to_fpga_present_l_9); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_9; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_9; + + method Bool fpga_to_qsfp_en_10; + method Bit#(1) fpga_to_qsfp_lpmode_10; + method Bit#(1) fpga_to_qsfp_reset_l_10; + (* prefix = "" *) method Action qsfp_to_fpga_pg_10(Bool qsfp_to_fpga_pg_10); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_10(Bit#(1) qsfp_to_fpga_irq_l_10); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_10(Bit#(1) qsfp_to_fpga_present_l_10); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_10; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_10; + + method Bool fpga_to_qsfp_en_11; + method Bit#(1) fpga_to_qsfp_lpmode_11; + method Bit#(1) fpga_to_qsfp_reset_l_11; + (* prefix = "" *) method Action qsfp_to_fpga_pg_11(Bool qsfp_to_fpga_pg_11); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_11(Bit#(1) qsfp_to_fpga_irq_l_11); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_11(Bit#(1) qsfp_to_fpga_present_l_11); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_11; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_11; + + method Bool fpga_to_qsfp_en_12; + method Bit#(1) fpga_to_qsfp_lpmode_12; + method Bit#(1) fpga_to_qsfp_reset_l_12; + (* prefix = "" *) method Action qsfp_to_fpga_pg_12(Bool qsfp_to_fpga_pg_12); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_12(Bit#(1) qsfp_to_fpga_irq_l_12); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_12(Bit#(1) qsfp_to_fpga_present_l_12); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_12; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_12; + + method Bool fpga_to_qsfp_en_13; + method Bit#(1) fpga_to_qsfp_lpmode_13; + method Bit#(1) fpga_to_qsfp_reset_l_13; + (* prefix = "" *) method Action qsfp_to_fpga_pg_13(Bool qsfp_to_fpga_pg_13); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_13(Bit#(1) qsfp_to_fpga_irq_l_13); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_13(Bit#(1) qsfp_to_fpga_present_l_13); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_13; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_13; + + method Bool fpga_to_qsfp_en_14; + method Bit#(1) fpga_to_qsfp_lpmode_14; + method Bit#(1) fpga_to_qsfp_reset_l_14; + (* prefix = "" *) method Action qsfp_to_fpga_pg_14(Bool qsfp_to_fpga_pg_14); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_14(Bit#(1) qsfp_to_fpga_irq_l_14); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_14(Bit#(1) qsfp_to_fpga_present_l_14); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_14; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_14; + + method Bool fpga_to_qsfp_en_15; + method Bit#(1) fpga_to_qsfp_lpmode_15; + method Bit#(1) fpga_to_qsfp_reset_l_15; + (* prefix = "" *) method Action qsfp_to_fpga_pg_15(Bool qsfp_to_fpga_pg_15); + (* prefix = "" *) method Action qsfp_to_fpga_irq_l_15(Bit#(1) qsfp_to_fpga_irq_l_15); + (* prefix = "" *) method Action qsfp_to_fpga_present_l_15(Bit#(1) qsfp_to_fpga_present_l_15); + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_scl_15; + interface Inout#(Bit#(1)) i2c_fpga_to_qsfp_sda_15; + + // + // SPI Peripheral + // + + method Bit#(1) spi_main_to_fpga_miso_r(); + (* prefix = "" *) method Action spi_main_to_fpga_cs1_l(Bit#(1) spi_main_to_fpga_cs1_l); + (* prefix = "" *) method Action spi_main_to_fpga_sck(Bit#(1) spi_main_to_fpga_sck); + (* prefix = "" *) method Action spi_main_to_fpga_mosi(Bit#(1) spi_main_to_fpga_mosi); + + // + // Power + // + + method Bit#(1) fpga_to_vr_v3p3_qsfp_en(); + (* prefix = "" *) method Action vr_v3p3_qsfp_to_fpga_pg(Bit#(1) vr_v3p3_qsfp_to_fpga_pg); + (* prefix = "" *) method Action pmbus_v3p3_qsfp_to_fpga_alert(Bit#(1) pmbus_v3p3_qsfp_to_fpga_alert); + + // + // PHY + // + + method Bool fpga_to_vr_phy_en(); + (* prefix = "" *) method Action vr_v1p0_phy_to_fpga_pg(Bool vr_v1p0_phy_to_fpga_pg); + (* prefix = "" *) method Action vr_v2p5_phy_to_fpga_pg(Bool vr_v2p5_phy_to_fpga_pg); + method Bit#(1) fpga_to_phy_refclk_en(); + method Bit#(1) fpga_to_phy_coma_mode(); + method Bit#(1) fpga_to_phy_reset_l(); + method Bit#(1) miim_fpga_to_phy_mdc(); + (* prefix = "" *) method Action miim_phy_to_fpga_mdint_l(Bit#(1) miim_phy_to_fpga_mdint_l); + interface Inout#(Bit#(1)) miim_fpga_to_phy_mdio; + + // + // Miscellaneous + // + + method Bit#(1) fpga_to_main_irq_r_l(); + method Bit#(1) fpga_led(); + method Bit#(1) fpga_to_leds0_reset_l(); + method Bit#(1) fpga_to_leds0_oe_l(); + method Bit#(8) debug_fpga_io(); + (* prefix = "" *) method Action fpga_app_id_r(Bit#(1) fpga_app_id_r); + (* prefix = "" *) method Action fpga_board_ver(Bit#(5) fpga_board_ver); +endinterface + +function Inout#(Bit#(1)) inout_from_tristate(TriState#(Bit#(1)) tristate) = tristate.io; + +(* default_clock_osc="clk_50m_fpga", + default_reset="gpio_to_fpga_design_reset_l" *) +module mkQsfpX32ControllerTop (QsfpControllerTop); + // Synchronize the default reset to the default clock + Clock cur_clk <- exposeCurrentClock(); + Reset reset_synced <- mkAsyncResetFromCR(2, cur_clk); + + QsfpX32Controller controller <- + mkQsfpX32Controller(defaultValue, reset_by reset_synced); + + // + // QSFP Ports + // + + // P0 + ReadOnly#(Bool) qsfp0_hsc_en <- mkOutputSyncFor(controller.qsfp[0].power_en); + ReadOnly#(Bit#(1)) qsfp0_lpmode <- mkOutputSyncFor(controller.qsfp[0].lpmode); + ReadOnly#(Bit#(1)) qsfp0_resetl <- mkOutputSyncFor(controller.qsfp[0].resetl); + InputReg#(Bool, 2) qsfp0_hsc_pg <- mkInputSyncFor(controller.qsfp[0].power_good); + InputReg#(Bit#(1), 2) qsfp0_intl <- mkInputSyncFor(controller.qsfp[0].intl); + InputReg#(Bit#(1), 2) qsfp0_modprsl <- mkInputSyncFor(controller.qsfp[0].modprsl); + ReadOnly#(Bool) qsfp0_scl_out_en <- mkOutputSyncFor(controller.qsfp[0].scl.out_en); + ReadOnly#(Bit#(1)) qsfp0_scl_out <- mkOutputSyncFor(controller.qsfp[0].scl.out); + InputReg#(Bit#(1), 2) qsfp0_scl_in <- mkInputSyncFor(controller.qsfp[0].scl.in); + TriState#(Bit#(1)) qsfp0_scl <- mkTriState(qsfp0_scl_out_en, qsfp0_scl_out); + mkConnection(sync(qsfp0_scl_in), qsfp0_scl._read); + ReadOnly#(Bool) qsfp0_sda_out_en <- mkOutputSyncFor(controller.qsfp[0].sda.out_en); + ReadOnly#(Bit#(1)) qsfp0_sda_out <- mkOutputSyncFor(controller.qsfp[0].sda.out); + InputReg#(Bit#(1), 2) qsfp0_sda_in <- mkInputSyncFor(controller.qsfp[0].sda.in); + TriState#(Bit#(1)) qsfp0_sda <- mkTriState(qsfp0_sda_out_en, qsfp0_sda_out); + mkConnection(sync(qsfp0_sda_in), qsfp0_sda._read); + + // P1 + ReadOnly#(Bool) qsfp1_hsc_en <- mkOutputSyncFor(controller.qsfp[1].power_en); + ReadOnly#(Bit#(1)) qsfp1_lpmode <- mkOutputSyncFor(controller.qsfp[1].lpmode); + ReadOnly#(Bit#(1)) qsfp1_resetl <- mkOutputSyncFor(controller.qsfp[1].resetl); + InputReg#(Bool, 2) qsfp1_hsc_pg <- mkInputSyncFor(controller.qsfp[1].power_good); + InputReg#(Bit#(1), 2) qsfp1_intl <- mkInputSyncFor(controller.qsfp[1].intl); + InputReg#(Bit#(1), 2) qsfp1_modprsl <- mkInputSyncFor(controller.qsfp[1].modprsl); + ReadOnly#(Bool) qsfp1_scl_out_en <- mkOutputSyncFor(controller.qsfp[1].scl.out_en); + ReadOnly#(Bit#(1)) qsfp1_scl_out <- mkOutputSyncFor(controller.qsfp[1].scl.out); + InputReg#(Bit#(1), 2) qsfp1_scl_in <- mkInputSyncFor(controller.qsfp[1].scl.in); + TriState#(Bit#(1)) qsfp1_scl <- mkTriState(qsfp1_scl_out_en, qsfp1_scl_out); + mkConnection(sync(qsfp1_scl_in), qsfp1_scl._read); + ReadOnly#(Bool) qsfp1_sda_out_en <- mkOutputSyncFor(controller.qsfp[1].sda.out_en); + ReadOnly#(Bit#(1)) qsfp1_sda_out <- mkOutputSyncFor(controller.qsfp[1].sda.out); + InputReg#(Bit#(1), 2) qsfp1_sda_in <- mkInputSyncFor(controller.qsfp[1].sda.in); + TriState#(Bit#(1)) qsfp1_sda <- mkTriState(qsfp1_sda_out_en, qsfp1_sda_out); + mkConnection(sync(qsfp1_sda_in), qsfp1_sda._read); + + // P2 + ReadOnly#(Bool) qsfp2_hsc_en <- mkOutputSyncFor(controller.qsfp[2].power_en); + ReadOnly#(Bit#(1)) qsfp2_lpmode <- mkOutputSyncFor(controller.qsfp[2].lpmode); + ReadOnly#(Bit#(1)) qsfp2_resetl <- mkOutputSyncFor(controller.qsfp[2].resetl); + InputReg#(Bool, 2) qsfp2_hsc_pg <- mkInputSyncFor(controller.qsfp[2].power_good); + InputReg#(Bit#(1), 2) qsfp2_intl <- mkInputSyncFor(controller.qsfp[2].intl); + InputReg#(Bit#(1), 2) qsfp2_modprsl <- mkInputSyncFor(controller.qsfp[2].modprsl); + ReadOnly#(Bool) qsfp2_scl_out_en <- mkOutputSyncFor(controller.qsfp[2].scl.out_en); + ReadOnly#(Bit#(1)) qsfp2_scl_out <- mkOutputSyncFor(controller.qsfp[2].scl.out); + InputReg#(Bit#(1), 2) qsfp2_scl_in <- mkInputSyncFor(controller.qsfp[2].scl.in); + TriState#(Bit#(1)) qsfp2_scl <- mkTriState(qsfp2_scl_out_en, qsfp2_scl_out); + mkConnection(sync(qsfp2_scl_in), qsfp2_scl._read); + ReadOnly#(Bool) qsfp2_sda_out_en <- mkOutputSyncFor(controller.qsfp[2].sda.out_en); + ReadOnly#(Bit#(1)) qsfp2_sda_out <- mkOutputSyncFor(controller.qsfp[2].sda.out); + InputReg#(Bit#(1), 2) qsfp2_sda_in <- mkInputSyncFor(controller.qsfp[2].sda.in); + TriState#(Bit#(1)) qsfp2_sda <- mkTriState(qsfp2_sda_out_en, qsfp2_sda_out); + mkConnection(sync(qsfp2_sda_in), qsfp2_sda._read); + + // P3 + ReadOnly#(Bool) qsfp3_hsc_en <- mkOutputSyncFor(controller.qsfp[3].power_en); + ReadOnly#(Bit#(1)) qsfp3_lpmode <- mkOutputSyncFor(controller.qsfp[3].lpmode); + ReadOnly#(Bit#(1)) qsfp3_resetl <- mkOutputSyncFor(controller.qsfp[3].resetl); + InputReg#(Bool, 2) qsfp3_hsc_pg <- mkInputSyncFor(controller.qsfp[3].power_good); + InputReg#(Bit#(1), 2) qsfp3_intl <- mkInputSyncFor(controller.qsfp[3].intl); + InputReg#(Bit#(1), 2) qsfp3_modprsl <- mkInputSyncFor(controller.qsfp[3].modprsl); + ReadOnly#(Bool) qsfp3_scl_out_en <- mkOutputSyncFor(controller.qsfp[3].scl.out_en); + ReadOnly#(Bit#(1)) qsfp3_scl_out <- mkOutputSyncFor(controller.qsfp[3].scl.out); + InputReg#(Bit#(1), 2) qsfp3_scl_in <- mkInputSyncFor(controller.qsfp[3].scl.in); + TriState#(Bit#(1)) qsfp3_scl <- mkTriState(qsfp3_scl_out_en, qsfp3_scl_out); + mkConnection(sync(qsfp3_scl_in), qsfp3_scl._read); + ReadOnly#(Bool) qsfp3_sda_out_en <- mkOutputSyncFor(controller.qsfp[3].sda.out_en); + ReadOnly#(Bit#(1)) qsfp3_sda_out <- mkOutputSyncFor(controller.qsfp[3].sda.out); + InputReg#(Bit#(1), 2) qsfp3_sda_in <- mkInputSyncFor(controller.qsfp[3].sda.in); + TriState#(Bit#(1)) qsfp3_sda <- mkTriState(qsfp3_sda_out_en, qsfp3_sda_out); + mkConnection(sync(qsfp3_sda_in), qsfp3_sda._read); + + // P4 + ReadOnly#(Bool) qsfp4_hsc_en <- mkOutputSyncFor(controller.qsfp[4].power_en); + ReadOnly#(Bit#(1)) qsfp4_lpmode <- mkOutputSyncFor(controller.qsfp[4].lpmode); + ReadOnly#(Bit#(1)) qsfp4_resetl <- mkOutputSyncFor(controller.qsfp[4].resetl); + InputReg#(Bool, 2) qsfp4_hsc_pg <- mkInputSyncFor(controller.qsfp[4].power_good); + InputReg#(Bit#(1), 2) qsfp4_intl <- mkInputSyncFor(controller.qsfp[4].intl); + InputReg#(Bit#(1), 2) qsfp4_modprsl <- mkInputSyncFor(controller.qsfp[4].modprsl); + ReadOnly#(Bool) qsfp4_scl_out_en <- mkOutputSyncFor(controller.qsfp[4].scl.out_en); + ReadOnly#(Bit#(1)) qsfp4_scl_out <- mkOutputSyncFor(controller.qsfp[4].scl.out); + InputReg#(Bit#(1), 2) qsfp4_scl_in <- mkInputSyncFor(controller.qsfp[4].scl.in); + TriState#(Bit#(1)) qsfp4_scl <- mkTriState(qsfp4_scl_out_en, qsfp4_scl_out); + mkConnection(sync(qsfp4_scl_in), qsfp4_scl._read); + ReadOnly#(Bool) qsfp4_sda_out_en <- mkOutputSyncFor(controller.qsfp[4].sda.out_en); + ReadOnly#(Bit#(1)) qsfp4_sda_out <- mkOutputSyncFor(controller.qsfp[4].sda.out); + InputReg#(Bit#(1), 2) qsfp4_sda_in <- mkInputSyncFor(controller.qsfp[4].sda.in); + TriState#(Bit#(1)) qsfp4_sda <- mkTriState(qsfp4_sda_out_en, qsfp4_sda_out); + mkConnection(sync(qsfp4_sda_in), qsfp4_sda._read); + + // P5 + ReadOnly#(Bool) qsfp5_hsc_en <- mkOutputSyncFor(controller.qsfp[5].power_en); + ReadOnly#(Bit#(1)) qsfp5_lpmode <- mkOutputSyncFor(controller.qsfp[5].lpmode); + ReadOnly#(Bit#(1)) qsfp5_resetl <- mkOutputSyncFor(controller.qsfp[5].resetl); + InputReg#(Bool, 2) qsfp5_hsc_pg <- mkInputSyncFor(controller.qsfp[5].power_good); + InputReg#(Bit#(1), 2) qsfp5_intl <- mkInputSyncFor(controller.qsfp[5].intl); + InputReg#(Bit#(1), 2) qsfp5_modprsl <- mkInputSyncFor(controller.qsfp[5].modprsl); + ReadOnly#(Bool) qsfp5_scl_out_en <- mkOutputSyncFor(controller.qsfp[5].scl.out_en); + ReadOnly#(Bit#(1)) qsfp5_scl_out <- mkOutputSyncFor(controller.qsfp[5].scl.out); + InputReg#(Bit#(1), 2) qsfp5_scl_in <- mkInputSyncFor(controller.qsfp[5].scl.in); + TriState#(Bit#(1)) qsfp5_scl <- mkTriState(qsfp5_scl_out_en, qsfp5_scl_out); + mkConnection(sync(qsfp5_scl_in), qsfp5_scl._read); + ReadOnly#(Bool) qsfp5_sda_out_en <- mkOutputSyncFor(controller.qsfp[5].sda.out_en); + ReadOnly#(Bit#(1)) qsfp5_sda_out <- mkOutputSyncFor(controller.qsfp[5].sda.out); + InputReg#(Bit#(1), 2) qsfp5_sda_in <- mkInputSyncFor(controller.qsfp[5].sda.in); + TriState#(Bit#(1)) qsfp5_sda <- mkTriState(qsfp5_sda_out_en, qsfp5_sda_out); + mkConnection(sync(qsfp5_sda_in), qsfp5_sda._read); + + // P6 + ReadOnly#(Bool) qsfp6_hsc_en <- mkOutputSyncFor(controller.qsfp[6].power_en); + ReadOnly#(Bit#(1)) qsfp6_lpmode <- mkOutputSyncFor(controller.qsfp[6].lpmode); + ReadOnly#(Bit#(1)) qsfp6_resetl <- mkOutputSyncFor(controller.qsfp[6].resetl); + InputReg#(Bool, 2) qsfp6_hsc_pg <- mkInputSyncFor(controller.qsfp[6].power_good); + InputReg#(Bit#(1), 2) qsfp6_intl <- mkInputSyncFor(controller.qsfp[6].intl); + InputReg#(Bit#(1), 2) qsfp6_modprsl <- mkInputSyncFor(controller.qsfp[6].modprsl); + ReadOnly#(Bool) qsfp6_scl_out_en <- mkOutputSyncFor(controller.qsfp[6].scl.out_en); + ReadOnly#(Bit#(1)) qsfp6_scl_out <- mkOutputSyncFor(controller.qsfp[6].scl.out); + InputReg#(Bit#(1), 2) qsfp6_scl_in <- mkInputSyncFor(controller.qsfp[6].scl.in); + TriState#(Bit#(1)) qsfp6_scl <- mkTriState(qsfp6_scl_out_en, qsfp6_scl_out); + mkConnection(sync(qsfp6_scl_in), qsfp6_scl._read); + ReadOnly#(Bool) qsfp6_sda_out_en <- mkOutputSyncFor(controller.qsfp[6].sda.out_en); + ReadOnly#(Bit#(1)) qsfp6_sda_out <- mkOutputSyncFor(controller.qsfp[6].sda.out); + InputReg#(Bit#(1), 2) qsfp6_sda_in <- mkInputSyncFor(controller.qsfp[6].sda.in); + TriState#(Bit#(1)) qsfp6_sda <- mkTriState(qsfp6_sda_out_en, qsfp6_sda_out); + mkConnection(sync(qsfp6_sda_in), qsfp6_sda._read); + + // P7 + ReadOnly#(Bool) qsfp7_hsc_en <- mkOutputSyncFor(controller.qsfp[7].power_en); + ReadOnly#(Bit#(1)) qsfp7_lpmode <- mkOutputSyncFor(controller.qsfp[7].lpmode); + ReadOnly#(Bit#(1)) qsfp7_resetl <- mkOutputSyncFor(controller.qsfp[7].resetl); + InputReg#(Bool, 2) qsfp7_hsc_pg <- mkInputSyncFor(controller.qsfp[7].power_good); + InputReg#(Bit#(1), 2) qsfp7_intl <- mkInputSyncFor(controller.qsfp[7].intl); + InputReg#(Bit#(1), 2) qsfp7_modprsl <- mkInputSyncFor(controller.qsfp[7].modprsl); + ReadOnly#(Bool) qsfp7_scl_out_en <- mkOutputSyncFor(controller.qsfp[7].scl.out_en); + ReadOnly#(Bit#(1)) qsfp7_scl_out <- mkOutputSyncFor(controller.qsfp[7].scl.out); + InputReg#(Bit#(1), 2) qsfp7_scl_in <- mkInputSyncFor(controller.qsfp[7].scl.in); + TriState#(Bit#(1)) qsfp7_scl <- mkTriState(qsfp7_scl_out_en, qsfp7_scl_out); + mkConnection(sync(qsfp7_scl_in), qsfp7_scl._read); + ReadOnly#(Bool) qsfp7_sda_out_en <- mkOutputSyncFor(controller.qsfp[7].sda.out_en); + ReadOnly#(Bit#(1)) qsfp7_sda_out <- mkOutputSyncFor(controller.qsfp[7].sda.out); + InputReg#(Bit#(1), 2) qsfp7_sda_in <- mkInputSyncFor(controller.qsfp[7].sda.in); + TriState#(Bit#(1)) qsfp7_sda <- mkTriState(qsfp7_sda_out_en, qsfp7_sda_out); + mkConnection(sync(qsfp7_sda_in), qsfp7_sda._read); + + // P8 + ReadOnly#(Bool) qsfp8_hsc_en <- mkOutputSyncFor(controller.qsfp[8].power_en); + ReadOnly#(Bit#(1)) qsfp8_lpmode <- mkOutputSyncFor(controller.qsfp[8].lpmode); + ReadOnly#(Bit#(1)) qsfp8_resetl <- mkOutputSyncFor(controller.qsfp[8].resetl); + InputReg#(Bool, 2) qsfp8_hsc_pg <- mkInputSyncFor(controller.qsfp[8].power_good); + InputReg#(Bit#(1), 2) qsfp8_intl <- mkInputSyncFor(controller.qsfp[8].intl); + InputReg#(Bit#(1), 2) qsfp8_modprsl <- mkInputSyncFor(controller.qsfp[8].modprsl); + ReadOnly#(Bool) qsfp8_scl_out_en <- mkOutputSyncFor(controller.qsfp[8].scl.out_en); + ReadOnly#(Bit#(1)) qsfp8_scl_out <- mkOutputSyncFor(controller.qsfp[8].scl.out); + InputReg#(Bit#(1), 2) qsfp8_scl_in <- mkInputSyncFor(controller.qsfp[8].scl.in); + TriState#(Bit#(1)) qsfp8_scl <- mkTriState(qsfp8_scl_out_en, qsfp8_scl_out); + mkConnection(sync(qsfp8_scl_in), qsfp8_scl._read); + ReadOnly#(Bool) qsfp8_sda_out_en <- mkOutputSyncFor(controller.qsfp[8].sda.out_en); + ReadOnly#(Bit#(1)) qsfp8_sda_out <- mkOutputSyncFor(controller.qsfp[8].sda.out); + InputReg#(Bit#(1), 2) qsfp8_sda_in <- mkInputSyncFor(controller.qsfp[8].sda.in); + TriState#(Bit#(1)) qsfp8_sda <- mkTriState(qsfp8_sda_out_en, qsfp8_sda_out); + mkConnection(sync(qsfp8_sda_in), qsfp8_sda._read); + + // P9 + ReadOnly#(Bool) qsfp9_hsc_en <- mkOutputSyncFor(controller.qsfp[9].power_en); + ReadOnly#(Bit#(1)) qsfp9_lpmode <- mkOutputSyncFor(controller.qsfp[9].lpmode); + ReadOnly#(Bit#(1)) qsfp9_resetl <- mkOutputSyncFor(controller.qsfp[9].resetl); + InputReg#(Bool, 2) qsfp9_hsc_pg <- mkInputSyncFor(controller.qsfp[9].power_good); + InputReg#(Bit#(1), 2) qsfp9_intl <- mkInputSyncFor(controller.qsfp[9].intl); + InputReg#(Bit#(1), 2) qsfp9_modprsl <- mkInputSyncFor(controller.qsfp[9].modprsl); + ReadOnly#(Bool) qsfp9_scl_out_en <- mkOutputSyncFor(controller.qsfp[9].scl.out_en); + ReadOnly#(Bit#(1)) qsfp9_scl_out <- mkOutputSyncFor(controller.qsfp[9].scl.out); + InputReg#(Bit#(1), 2) qsfp9_scl_in <- mkInputSyncFor(controller.qsfp[9].scl.in); + TriState#(Bit#(1)) qsfp9_scl <- mkTriState(qsfp9_scl_out_en, qsfp9_scl_out); + mkConnection(sync(qsfp9_scl_in), qsfp9_scl._read); + ReadOnly#(Bool) qsfp9_sda_out_en <- mkOutputSyncFor(controller.qsfp[9].sda.out_en); + ReadOnly#(Bit#(1)) qsfp9_sda_out <- mkOutputSyncFor(controller.qsfp[9].sda.out); + InputReg#(Bit#(1), 2) qsfp9_sda_in <- mkInputSyncFor(controller.qsfp[9].sda.in); + TriState#(Bit#(1)) qsfp9_sda <- mkTriState(qsfp9_sda_out_en, qsfp9_sda_out); + mkConnection(sync(qsfp9_sda_in), qsfp9_sda._read); + + // P10 + ReadOnly#(Bool) qsfp10_hsc_en <- mkOutputSyncFor(controller.qsfp[10].power_en); + ReadOnly#(Bit#(1)) qsfp10_lpmode <- mkOutputSyncFor(controller.qsfp[10].lpmode); + ReadOnly#(Bit#(1)) qsfp10_resetl <- mkOutputSyncFor(controller.qsfp[10].resetl); + InputReg#(Bool, 2) qsfp10_hsc_pg <- mkInputSyncFor(controller.qsfp[10].power_good); + InputReg#(Bit#(1), 2) qsfp10_intl <- mkInputSyncFor(controller.qsfp[10].intl); + InputReg#(Bit#(1), 2) qsfp10_modprsl<- mkInputSyncFor(controller.qsfp[10].modprsl); + ReadOnly#(Bool) qsfp10_scl_out_en <- mkOutputSyncFor(controller.qsfp[10].scl.out_en); + ReadOnly#(Bit#(1)) qsfp10_scl_out <- mkOutputSyncFor(controller.qsfp[10].scl.out); + InputReg#(Bit#(1), 2) qsfp10_scl_in <- mkInputSyncFor(controller.qsfp[10].scl.in); + TriState#(Bit#(1)) qsfp10_scl <- mkTriState(qsfp10_scl_out_en, qsfp10_scl_out); + mkConnection(sync(qsfp10_scl_in), qsfp10_scl._read); + ReadOnly#(Bool) qsfp10_sda_out_en <- mkOutputSyncFor(controller.qsfp[10].sda.out_en); + ReadOnly#(Bit#(1)) qsfp10_sda_out <- mkOutputSyncFor(controller.qsfp[10].sda.out); + InputReg#(Bit#(1), 2) qsfp10_sda_in <- mkInputSyncFor(controller.qsfp[10].sda.in); + TriState#(Bit#(1)) qsfp10_sda <- mkTriState(qsfp10_sda_out_en, qsfp10_sda_out); + mkConnection(sync(qsfp10_sda_in), qsfp10_sda._read); + + // P11 + ReadOnly#(Bool) qsfp11_hsc_en <- mkOutputSyncFor(controller.qsfp[11].power_en); + ReadOnly#(Bit#(1)) qsfp11_lpmode <- mkOutputSyncFor(controller.qsfp[11].lpmode); + ReadOnly#(Bit#(1)) qsfp11_resetl <- mkOutputSyncFor(controller.qsfp[11].resetl); + InputReg#(Bool, 2) qsfp11_hsc_pg <- mkInputSyncFor(controller.qsfp[11].power_good); + InputReg#(Bit#(1), 2) qsfp11_intl <- mkInputSyncFor(controller.qsfp[11].intl); + InputReg#(Bit#(1), 2) qsfp11_modprsl<- mkInputSyncFor(controller.qsfp[11].modprsl); + ReadOnly#(Bool) qsfp11_scl_out_en <- mkOutputSyncFor(controller.qsfp[11].scl.out_en); + ReadOnly#(Bit#(1)) qsfp11_scl_out <- mkOutputSyncFor(controller.qsfp[11].scl.out); + InputReg#(Bit#(1), 2) qsfp11_scl_in <- mkInputSyncFor(controller.qsfp[11].scl.in); + TriState#(Bit#(1)) qsfp11_scl <- mkTriState(qsfp11_scl_out_en, qsfp11_scl_out); + mkConnection(sync(qsfp11_scl_in), qsfp11_scl._read); + ReadOnly#(Bool) qsfp11_sda_out_en <- mkOutputSyncFor(controller.qsfp[11].sda.out_en); + ReadOnly#(Bit#(1)) qsfp11_sda_out <- mkOutputSyncFor(controller.qsfp[11].sda.out); + InputReg#(Bit#(1), 2) qsfp11_sda_in <- mkInputSyncFor(controller.qsfp[11].sda.in); + TriState#(Bit#(1)) qsfp11_sda <- mkTriState(qsfp11_sda_out_en, qsfp11_sda_out); + mkConnection(sync(qsfp11_sda_in), qsfp11_sda._read); + + // P12 + ReadOnly#(Bool) qsfp12_hsc_en <- mkOutputSyncFor(controller.qsfp[12].power_en); + ReadOnly#(Bit#(1)) qsfp12_lpmode <- mkOutputSyncFor(controller.qsfp[12].lpmode); + ReadOnly#(Bit#(1)) qsfp12_resetl <- mkOutputSyncFor(controller.qsfp[12].resetl); + InputReg#(Bool, 2) qsfp12_hsc_pg <- mkInputSyncFor(controller.qsfp[12].power_good); + InputReg#(Bit#(1), 2) qsfp12_intl <- mkInputSyncFor(controller.qsfp[12].intl); + InputReg#(Bit#(1), 2) qsfp12_modprsl<- mkInputSyncFor(controller.qsfp[12].modprsl); + ReadOnly#(Bool) qsfp12_scl_out_en <- mkOutputSyncFor(controller.qsfp[12].scl.out_en); + ReadOnly#(Bit#(1)) qsfp12_scl_out <- mkOutputSyncFor(controller.qsfp[12].scl.out); + InputReg#(Bit#(1), 2) qsfp12_scl_in <- mkInputSyncFor(controller.qsfp[12].scl.in); + TriState#(Bit#(1)) qsfp12_scl <- mkTriState(qsfp12_scl_out_en, qsfp12_scl_out); + mkConnection(sync(qsfp12_scl_in), qsfp12_scl._read); + ReadOnly#(Bool) qsfp12_sda_out_en <- mkOutputSyncFor(controller.qsfp[12].sda.out_en); + ReadOnly#(Bit#(1)) qsfp12_sda_out <- mkOutputSyncFor(controller.qsfp[12].sda.out); + InputReg#(Bit#(1), 2) qsfp12_sda_in <- mkInputSyncFor(controller.qsfp[12].sda.in); + TriState#(Bit#(1)) qsfp12_sda <- mkTriState(qsfp12_sda_out_en, qsfp12_sda_out); + mkConnection(sync(qsfp12_sda_in), qsfp12_sda._read); + + // P13 + ReadOnly#(Bool) qsfp13_hsc_en <- mkOutputSyncFor(controller.qsfp[13].power_en); + ReadOnly#(Bit#(1)) qsfp13_lpmode <- mkOutputSyncFor(controller.qsfp[13].lpmode); + ReadOnly#(Bit#(1)) qsfp13_resetl <- mkOutputSyncFor(controller.qsfp[13].resetl); + InputReg#(Bool, 2) qsfp13_hsc_pg <- mkInputSyncFor(controller.qsfp[13].power_good); + InputReg#(Bit#(1), 2) qsfp13_intl <- mkInputSyncFor(controller.qsfp[13].intl); + InputReg#(Bit#(1), 2) qsfp13_modprsl<- mkInputSyncFor(controller.qsfp[13].modprsl); + ReadOnly#(Bool) qsfp13_scl_out_en <- mkOutputSyncFor(controller.qsfp[13].scl.out_en); + ReadOnly#(Bit#(1)) qsfp13_scl_out <- mkOutputSyncFor(controller.qsfp[13].scl.out); + InputReg#(Bit#(1), 2) qsfp13_scl_in <- mkInputSyncFor(controller.qsfp[13].scl.in); + TriState#(Bit#(1)) qsfp13_scl <- mkTriState(qsfp13_scl_out_en, qsfp13_scl_out); + mkConnection(sync(qsfp13_scl_in), qsfp13_scl._read); + ReadOnly#(Bool) qsfp13_sda_out_en <- mkOutputSyncFor(controller.qsfp[13].sda.out_en); + ReadOnly#(Bit#(1)) qsfp13_sda_out <- mkOutputSyncFor(controller.qsfp[13].sda.out); + InputReg#(Bit#(1), 2) qsfp13_sda_in <- mkInputSyncFor(controller.qsfp[13].sda.in); + TriState#(Bit#(1)) qsfp13_sda <- mkTriState(qsfp13_sda_out_en, qsfp13_sda_out); + mkConnection(sync(qsfp13_sda_in), qsfp13_sda._read); + + // P14 + ReadOnly#(Bool) qsfp14_hsc_en <- mkOutputSyncFor(controller.qsfp[14].power_en); + ReadOnly#(Bit#(1)) qsfp14_lpmode <- mkOutputSyncFor(controller.qsfp[14].lpmode); + ReadOnly#(Bit#(1)) qsfp14_resetl <- mkOutputSyncFor(controller.qsfp[14].resetl); + InputReg#(Bool, 2) qsfp14_hsc_pg <- mkInputSyncFor(controller.qsfp[14].power_good); + InputReg#(Bit#(1), 2) qsfp14_intl <- mkInputSyncFor(controller.qsfp[14].intl); + InputReg#(Bit#(1), 2) qsfp14_modprsl<- mkInputSyncFor(controller.qsfp[14].modprsl); + ReadOnly#(Bool) qsfp14_scl_out_en <- mkOutputSyncFor(controller.qsfp[14].scl.out_en); + ReadOnly#(Bit#(1)) qsfp14_scl_out <- mkOutputSyncFor(controller.qsfp[14].scl.out); + InputReg#(Bit#(1), 2) qsfp14_scl_in <- mkInputSyncFor(controller.qsfp[14].scl.in); + TriState#(Bit#(1)) qsfp14_scl <- mkTriState(qsfp14_scl_out_en, qsfp14_scl_out); + mkConnection(sync(qsfp14_scl_in), qsfp14_scl._read); + ReadOnly#(Bool) qsfp14_sda_out_en <- mkOutputSyncFor(controller.qsfp[14].sda.out_en); + ReadOnly#(Bit#(1)) qsfp14_sda_out <- mkOutputSyncFor(controller.qsfp[14].sda.out); + InputReg#(Bit#(1), 2) qsfp14_sda_in <- mkInputSyncFor(controller.qsfp[14].sda.in); + TriState#(Bit#(1)) qsfp14_sda <- mkTriState(qsfp14_sda_out_en, qsfp14_sda_out); + mkConnection(sync(qsfp14_sda_in), qsfp14_sda._read); + + // P15 + ReadOnly#(Bool) qsfp15_hsc_en <- mkOutputSyncFor(controller.qsfp[15].power_en); + ReadOnly#(Bit#(1)) qsfp15_lpmode <- mkOutputSyncFor(controller.qsfp[15].lpmode); + ReadOnly#(Bit#(1)) qsfp15_resetl <- mkOutputSyncFor(controller.qsfp[15].resetl); + InputReg#(Bool, 2) qsfp15_hsc_pg <- mkInputSyncFor(controller.qsfp[15].power_good); + InputReg#(Bit#(1), 2) qsfp15_intl <- mkInputSyncFor(controller.qsfp[15].intl); + InputReg#(Bit#(1), 2) qsfp15_modprsl<- mkInputSyncFor(controller.qsfp[15].modprsl); + ReadOnly#(Bool) qsfp15_scl_out_en <- mkOutputSyncFor(controller.qsfp[15].scl.out_en); + ReadOnly#(Bit#(1)) qsfp15_scl_out <- mkOutputSyncFor(controller.qsfp[15].scl.out); + InputReg#(Bit#(1), 2) qsfp15_scl_in <- mkInputSyncFor(controller.qsfp[15].scl.in); + TriState#(Bit#(1)) qsfp15_scl <- mkTriState(qsfp15_scl_out_en, qsfp15_scl_out); + mkConnection(sync(qsfp15_scl_in), qsfp15_scl._read); + ReadOnly#(Bool) qsfp15_sda_out_en <- mkOutputSyncFor(controller.qsfp[15].sda.out_en); + ReadOnly#(Bit#(1)) qsfp15_sda_out <- mkOutputSyncFor(controller.qsfp[15].sda.out); + InputReg#(Bit#(1), 2) qsfp15_sda_in <- mkInputSyncFor(controller.qsfp[15].sda.in); + TriState#(Bit#(1)) qsfp15_sda <- mkTriState(qsfp15_sda_out_en, qsfp15_sda_out); + mkConnection(sync(qsfp15_sda_in), qsfp15_sda._read); + + // + // SPI Peripheral + // + + InputReg#(Bit#(1), 2) csn <- mkInputSyncFor(controller.spi.csn); + InputReg#(Bit#(1), 2) sclk <- mkInputSyncFor(controller.spi.sclk); + InputReg#(Bit#(1), 2) copi <- mkInputSyncFor(controller.spi.copi); + ReadOnly#(Bit#(1)) cipo <- mkOutputSyncFor(controller.spi.cipo); + + // + // Power + // + + // + // PHY + // + ReadOnly#(Bool) phy_vr_en <- mkOutputSyncFor(controller.vsc8562.v1p0.en); + InputReg#(Bool, 2) phy_v1p0_pg <- mkInputSyncFor(controller.vsc8562.v1p0.pg); + InputReg#(Bool, 2) phy_v2p5_pg <- mkInputSyncFor(controller.vsc8562.v2p5.pg); + + ReadOnly#(Bit#(1)) phy_coma_mode <- mkOutputSyncFor(controller.vsc8562.coma_mode); + ReadOnly#(Bit#(1)) phy_refclk_en <- mkOutputSyncFor(controller.vsc8562.refclk_en); + ReadOnly#(Bit#(1)) phy_reset_ <- mkOutputSyncFor(controller.vsc8562.reset_); + + ReadOnly#(Bit#(1)) phy_mdc <- mkOutputSyncFor(controller.vsc8562.smi.mdc); + InputReg#(Bit#(1), 2) phy_mdint <- mkInputSyncFor(controller.vsc8562.mdint); + ReadOnly#(Bool) phy_mdio_out_en <- mkOutputSyncFor(controller.vsc8562.smi.mdio.out_en); + ReadOnly#(Bit#(1)) phy_mdio_out <- mkOutputSyncFor(controller.vsc8562.smi.mdio.out); + InputReg#(Bit#(1), 2) phy_mdio_in <- mkInputSyncFor(controller.vsc8562.smi.mdio.in); + TriState#(Bit#(1)) phy_mdio <- mkTriState(phy_mdio_out_en, phy_mdio_out); + mkConnection(sync(phy_mdio_in), phy_mdio._read); + + // + // Miscellaneous + // + ReadOnly#(Bit#(1)) fpga_led_blinky <- mkOutputSyncFor(controller.blinky.led[0]); + InputReg#(Bit#(1), 2) fpga_app_id <- mkInputSyncFor(controller.top.fpga_app_id); + ReadOnly#(Bit#(1)) led_reset <- mkOutputSyncFor(controller.top.led_controller_reset); + ReadOnly#(Bit#(1)) led_oe <- mkOutputSyncFor(controller.top.led_controller_output_en); + InputReg#(Bit#(1), 2) pmbus_v3p3_alert <- mkInputSync(); + InputReg#(Bit#(1), 2) vr_v3p3_pg <- mkInputSync(); + InputReg#(Bit#(5), 2) fpga_board_ver_in <- mkInputSyncFor(controller.top.fpga_board_ver); + + // + // Wire design out to the device pins + // + + // + // QSFP Ports + // + method fpga_to_qsfp_en_0 = qsfp0_hsc_en; + method fpga_to_qsfp_lpmode_0 = qsfp0_lpmode; + method fpga_to_qsfp_reset_l_0 = qsfp0_resetl; + method qsfp_to_fpga_pg_0 = sync(qsfp0_hsc_pg); + method qsfp_to_fpga_irq_l_0 = sync(qsfp0_intl); + method qsfp_to_fpga_present_l_0 = sync(qsfp0_modprsl); + interface i2c_fpga_to_qsfp_scl_0 = qsfp0_scl.io; + interface i2c_fpga_to_qsfp_sda_0 = qsfp0_sda.io; + + method fpga_to_qsfp_en_1 = qsfp1_hsc_en; + method fpga_to_qsfp_lpmode_1 = qsfp1_lpmode; + method fpga_to_qsfp_reset_l_1 = qsfp1_resetl; + method qsfp_to_fpga_pg_1 = sync(qsfp1_hsc_pg); + method qsfp_to_fpga_irq_l_1 = sync(qsfp1_intl); + method qsfp_to_fpga_present_l_1 = sync(qsfp1_modprsl); + interface i2c_fpga_to_qsfp_scl_1 = qsfp1_scl.io; + interface i2c_fpga_to_qsfp_sda_1 = qsfp1_sda.io; + + method fpga_to_qsfp_en_2 = qsfp2_hsc_en; + method fpga_to_qsfp_lpmode_2 = qsfp2_lpmode; + method fpga_to_qsfp_reset_l_2 = qsfp2_resetl; + method qsfp_to_fpga_pg_2 = sync(qsfp2_hsc_pg); + method qsfp_to_fpga_irq_l_2 = sync(qsfp2_intl); + method qsfp_to_fpga_present_l_2 = sync(qsfp2_modprsl); + interface i2c_fpga_to_qsfp_scl_2 = qsfp2_scl.io; + interface i2c_fpga_to_qsfp_sda_2 = qsfp2_sda.io; + + method fpga_to_qsfp_en_3 = qsfp3_hsc_en; + method fpga_to_qsfp_lpmode_3 = qsfp3_lpmode; + method fpga_to_qsfp_reset_l_3 = qsfp3_resetl; + method qsfp_to_fpga_pg_3 = sync(qsfp3_hsc_pg); + method qsfp_to_fpga_irq_l_3 = sync(qsfp3_intl); + method qsfp_to_fpga_present_l_3 = sync(qsfp3_modprsl); + interface i2c_fpga_to_qsfp_scl_3 = qsfp3_scl.io; + interface i2c_fpga_to_qsfp_sda_3 = qsfp3_sda.io; + + method fpga_to_qsfp_en_4 = qsfp4_hsc_en; + method fpga_to_qsfp_lpmode_4 = qsfp4_lpmode; + method fpga_to_qsfp_reset_l_4 = qsfp4_resetl; + method qsfp_to_fpga_pg_4 = sync(qsfp4_hsc_pg); + method qsfp_to_fpga_irq_l_4 = sync(qsfp4_intl); + method qsfp_to_fpga_present_l_4 = sync(qsfp4_modprsl); + interface i2c_fpga_to_qsfp_scl_4 = qsfp4_scl.io; + interface i2c_fpga_to_qsfp_sda_4 = qsfp4_sda.io; + + method fpga_to_qsfp_en_5 = qsfp5_hsc_en; + method fpga_to_qsfp_lpmode_5 = qsfp5_lpmode; + method fpga_to_qsfp_reset_l_5 = qsfp5_resetl; + method qsfp_to_fpga_pg_5 = sync(qsfp5_hsc_pg); + method qsfp_to_fpga_irq_l_5 = sync(qsfp5_intl); + method qsfp_to_fpga_present_l_5 = sync(qsfp5_modprsl); + interface i2c_fpga_to_qsfp_scl_5 = qsfp5_scl.io; + interface i2c_fpga_to_qsfp_sda_5 = qsfp5_sda.io; + + method fpga_to_qsfp_en_6 = qsfp6_hsc_en; + method fpga_to_qsfp_lpmode_6 = qsfp6_lpmode; + method fpga_to_qsfp_reset_l_6 = qsfp6_resetl; + method qsfp_to_fpga_pg_6 = sync(qsfp6_hsc_pg); + method qsfp_to_fpga_irq_l_6 = sync(qsfp6_intl); + method qsfp_to_fpga_present_l_6 = sync(qsfp6_modprsl); + interface i2c_fpga_to_qsfp_scl_6 = qsfp6_scl.io; + interface i2c_fpga_to_qsfp_sda_6 = qsfp6_sda.io; + + method fpga_to_qsfp_en_7 = qsfp7_hsc_en; + method fpga_to_qsfp_lpmode_7 = qsfp7_lpmode; + method fpga_to_qsfp_reset_l_7 = qsfp7_resetl; + method qsfp_to_fpga_pg_7 = sync(qsfp7_hsc_pg); + method qsfp_to_fpga_irq_l_7 = sync(qsfp7_intl); + method qsfp_to_fpga_present_l_7 = sync(qsfp7_modprsl); + interface i2c_fpga_to_qsfp_scl_7 = qsfp7_scl.io; + interface i2c_fpga_to_qsfp_sda_7 = qsfp7_sda.io; + + method fpga_to_qsfp_en_8 = qsfp8_hsc_en; + method fpga_to_qsfp_lpmode_8 = qsfp8_lpmode; + method fpga_to_qsfp_reset_l_8 = qsfp8_resetl; + method qsfp_to_fpga_pg_8 = sync(qsfp8_hsc_pg); + method qsfp_to_fpga_irq_l_8 = sync(qsfp8_intl); + method qsfp_to_fpga_present_l_8 = sync(qsfp8_modprsl); + interface i2c_fpga_to_qsfp_scl_8 = qsfp8_scl.io; + interface i2c_fpga_to_qsfp_sda_8 = qsfp8_sda.io; + + method fpga_to_qsfp_en_9 = qsfp9_hsc_en; + method fpga_to_qsfp_lpmode_9 = qsfp9_lpmode; + method fpga_to_qsfp_reset_l_9 = qsfp9_resetl; + method qsfp_to_fpga_pg_9 = sync(qsfp9_hsc_pg); + method qsfp_to_fpga_irq_l_9 = sync(qsfp9_intl); + method qsfp_to_fpga_present_l_9 = sync(qsfp9_modprsl); + interface i2c_fpga_to_qsfp_scl_9 = qsfp9_scl.io; + interface i2c_fpga_to_qsfp_sda_9 = qsfp9_sda.io; + + method fpga_to_qsfp_en_10 = qsfp10_hsc_en; + method fpga_to_qsfp_lpmode_10 = qsfp10_lpmode; + method fpga_to_qsfp_reset_l_10 = qsfp10_resetl; + method qsfp_to_fpga_pg_10 = sync(qsfp10_hsc_pg); + method qsfp_to_fpga_irq_l_10 = sync(qsfp10_intl); + method qsfp_to_fpga_present_l_10 = sync(qsfp10_modprsl); + interface i2c_fpga_to_qsfp_scl_10 = qsfp10_scl.io; + interface i2c_fpga_to_qsfp_sda_10 = qsfp10_sda.io; + + method fpga_to_qsfp_en_11 = qsfp11_hsc_en; + method fpga_to_qsfp_lpmode_11 = qsfp11_lpmode; + method fpga_to_qsfp_reset_l_11 = qsfp11_resetl; + method qsfp_to_fpga_pg_11 = sync(qsfp11_hsc_pg); + method qsfp_to_fpga_irq_l_11 = sync(qsfp11_intl); + method qsfp_to_fpga_present_l_11 = sync(qsfp11_modprsl); + interface i2c_fpga_to_qsfp_scl_11 = qsfp11_scl.io; + interface i2c_fpga_to_qsfp_sda_11 = qsfp11_sda.io; + + method fpga_to_qsfp_en_12 = qsfp12_hsc_en; + method fpga_to_qsfp_lpmode_12 = qsfp12_lpmode; + method fpga_to_qsfp_reset_l_12 = qsfp12_resetl; + method qsfp_to_fpga_pg_12 = sync(qsfp12_hsc_pg); + method qsfp_to_fpga_irq_l_12 = sync(qsfp12_intl); + method qsfp_to_fpga_present_l_12 = sync(qsfp12_modprsl); + interface i2c_fpga_to_qsfp_scl_12 = qsfp12_scl.io; + interface i2c_fpga_to_qsfp_sda_12 = qsfp12_sda.io; + + method fpga_to_qsfp_en_13 = qsfp13_hsc_en; + method fpga_to_qsfp_lpmode_13 = qsfp13_lpmode; + method fpga_to_qsfp_reset_l_13 = qsfp13_resetl; + method qsfp_to_fpga_pg_13 = sync(qsfp13_hsc_pg); + method qsfp_to_fpga_irq_l_13 = sync(qsfp13_intl); + method qsfp_to_fpga_present_l_13 = sync(qsfp13_modprsl); + interface i2c_fpga_to_qsfp_scl_13 = qsfp13_scl.io; + interface i2c_fpga_to_qsfp_sda_13 = qsfp13_sda.io; + + method fpga_to_qsfp_en_14 = qsfp14_hsc_en; + method fpga_to_qsfp_lpmode_14 = qsfp14_lpmode; + method fpga_to_qsfp_reset_l_14 = qsfp14_resetl; + method qsfp_to_fpga_pg_14 = sync(qsfp14_hsc_pg); + method qsfp_to_fpga_irq_l_14 = sync(qsfp14_intl); + method qsfp_to_fpga_present_l_14 = sync(qsfp14_modprsl); + interface i2c_fpga_to_qsfp_scl_14 = qsfp14_scl.io; + interface i2c_fpga_to_qsfp_sda_14 = qsfp14_sda.io; + + method fpga_to_qsfp_en_15 = qsfp15_hsc_en; + method fpga_to_qsfp_lpmode_15 = qsfp15_lpmode; + method fpga_to_qsfp_reset_l_15 = qsfp15_resetl; + method qsfp_to_fpga_pg_15 = sync(qsfp15_hsc_pg); + method qsfp_to_fpga_irq_l_15 = sync(qsfp15_intl); + method qsfp_to_fpga_present_l_15 = sync(qsfp15_modprsl); + interface i2c_fpga_to_qsfp_scl_15 = qsfp15_scl.io; + interface i2c_fpga_to_qsfp_sda_15 = qsfp15_sda.io; + + // + // SPI Peripheral + // + + method spi_main_to_fpga_cs1_l = sync(csn); + method spi_main_to_fpga_sck = sync(sclk); + method spi_main_to_fpga_mosi = sync(copi); + method spi_main_to_fpga_miso_r = cipo; + + // + // Power + // + + // + // PHY + // + + method fpga_to_vr_phy_en = phy_vr_en; + method vr_v1p0_phy_to_fpga_pg = sync(phy_v1p0_pg); + method vr_v2p5_phy_to_fpga_pg = sync(phy_v2p5_pg); + + method fpga_to_phy_refclk_en; + // The PHY oscillator on Rev B and C boards has an errata for its EN + // pin, causing it on occasion to misbehave when enabled (much) later + // after PoR. On these boards always enable the output irrespective of + // sequencer state. + if (fpga_board_ver_in == 'h1 || fpga_board_ver_in == 'h2) begin + return 1; + end else begin + return phy_refclk_en; + end + endmethod + method fpga_to_phy_coma_mode = phy_coma_mode; + method fpga_to_phy_reset_l = ~phy_reset_; + + method miim_fpga_to_phy_mdc = phy_mdc; + method miim_phy_to_fpga_mdint_l = sync_inverted(phy_mdint); + interface miim_fpga_to_phy_mdio = phy_mdio.io; + + // + // Miscellaneous + // + + method Bit#(1) fpga_to_vr_v3p3_qsfp_en = 1; + method vr_v3p3_qsfp_to_fpga_pg = sync(vr_v3p3_pg); + method pmbus_v3p3_qsfp_to_fpga_alert = sync(pmbus_v3p3_alert); + + method Bit#(1) fpga_to_main_irq_r_l = 1; + method Bit#(1) fpga_led = fpga_led_blinky; + method Bit#(1) fpga_to_leds0_reset_l = ~led_reset; + method Bit#(1) fpga_to_leds0_oe_l = ~led_oe; + method fpga_app_id_r = sync(fpga_app_id); + method Bit#(8) debug_fpga_io = { + qsfp3_sda._read, // Bit 7, J31 pin 10 + qsfp3_scl._read, // Bit 6, J31 pin 9 + qsfp2_sda._read, // Bit 5, J31 pin 8 + qsfp2_scl._read, // Bit 4, J31 pin 7 + qsfp1_sda._read, // Bit 3, J31 pin 4 + qsfp1_scl._read, // Bit 2, J31 pin 3 + qsfp0_sda._read, // Bit 1, J31 pin 2 + qsfp0_scl._read}; // Bit 0, J31 pin 1 + method fpga_board_ver = sync(fpga_board_ver_in); +endmodule + +endpackage: QsfpX32ControllerTop diff --git a/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerTopRegs.bsv b/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerTopRegs.bsv index fbbade08..b88efb55 100644 --- a/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerTopRegs.bsv +++ b/hdl/projects/sidecar/qsfp_x32/QsfpX32ControllerTopRegs.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/VSC8562/VSC8562.bsv b/hdl/projects/sidecar/qsfp_x32/VSC8562/VSC8562.bsv index 7841c5cc..d80feec3 100644 --- a/hdl/projects/sidecar/qsfp_x32/VSC8562/VSC8562.bsv +++ b/hdl/projects/sidecar/qsfp_x32/VSC8562/VSC8562.bsv @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/VSC8562/test/VSC8562Tests.bsv b/hdl/projects/sidecar/qsfp_x32/VSC8562/test/VSC8562Tests.bsv index 2c76f8e5..fad3492b 100644 --- a/hdl/projects/sidecar/qsfp_x32/VSC8562/test/VSC8562Tests.bsv +++ b/hdl/projects/sidecar/qsfp_x32/VSC8562/test/VSC8562Tests.bsv @@ -1,4 +1,3 @@ -// Copyright 2023 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/VSC8562/vsc8562.rdl b/hdl/projects/sidecar/qsfp_x32/VSC8562/vsc8562.rdl index 9e21ee25..8425c6f8 100644 --- a/hdl/projects/sidecar/qsfp_x32/VSC8562/vsc8562.rdl +++ b/hdl/projects/sidecar/qsfp_x32/VSC8562/vsc8562.rdl @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/sidecar/qsfp_x32/qsfp_x32_controller.rdl b/hdl/projects/sidecar/qsfp_x32/qsfp_x32_controller.rdl index 09df4a26..a90924c4 100644 --- a/hdl/projects/sidecar/qsfp_x32/qsfp_x32_controller.rdl +++ b/hdl/projects/sidecar/qsfp_x32/qsfp_x32_controller.rdl @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/hdl/projects/ulx3s/Board.bsv b/hdl/projects/ulx3s/Board.bsv index 2ae47e79..856e3ecb 100644 --- a/hdl/projects/ulx3s/Board.bsv +++ b/hdl/projects/ulx3s/Board.bsv @@ -1,4 +1,3 @@ -// Copyright 2021 Oxide Computer Company // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/toolchains/vivado_toolchain.bzl b/toolchains/vivado_toolchain.bzl index cf6a788a..a960320d 100644 --- a/toolchains/vivado_toolchain.bzl +++ b/toolchains/vivado_toolchain.bzl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company _VIVADO = select({ "DEFAULT": "vivado", diff --git a/toolchains/vsg_toolchain.bzl b/toolchains/vsg_toolchain.bzl index 55e143b3..c924667f 100644 --- a/toolchains/vsg_toolchain.bzl +++ b/toolchains/vsg_toolchain.bzl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company _VSG = select({ "DEFAULT": "vsg", diff --git a/tools/bsv-tests.bxl b/tools/bsv-tests.bxl index 2ae103a5..92348e44 100644 --- a/tools/bsv-tests.bxl +++ b/tools/bsv-tests.bxl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2026 Oxide Computer Company # BXL script to discover and list all BSV Bluesim test targets # Usage: buck2 bxl //tools/bsv-tests.bxl:bsv_test_gen diff --git a/tools/bsv.bzl b/tools/bsv.bzl index afc7d914..fac3837a 100644 --- a/tools/bsv.bzl +++ b/tools/bsv.bzl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2026 Oxide Computer Company # BSV (Bluespec SystemVerilog) build rules diff --git a/tools/bsv_bluescan/bluescan_wrapper.py b/tools/bsv_bluescan/bluescan_wrapper.py index 527a5198..56f0d406 100755 --- a/tools/bsv_bluescan/bluescan_wrapper.py +++ b/tools/bsv_bluescan/bluescan_wrapper.py @@ -1,6 +1,5 @@ #!/usr/bin/env python3 # -# Copyright 2026 Oxide Computer Company # # This Source Code Form is subject to the terms of the Mozilla Public # License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/tools/bsv_common.bzl b/tools/bsv_common.bzl index 4abe114d..cec19bcf 100644 --- a/tools/bsv_common.bzl +++ b/tools/bsv_common.bzl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2026 Oxide Computer Company # BSV (Bluespec SystemVerilog) build system providers and types # This file contains provider definitions for the BSV buck2 build system diff --git a/tools/bz2compress/bz2compress.py b/tools/bz2compress/bz2compress.py index 7ec18562..9c655c65 100644 --- a/tools/bz2compress/bz2compress.py +++ b/tools/bz2compress/bz2compress.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import argparse import bz2 diff --git a/tools/hdl.bzl b/tools/hdl.bzl index cacea534..b11c24a5 100644 --- a/tools/hdl.bzl +++ b/tools/hdl.bzl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company load( "@prelude//python:toolchain.bzl", diff --git a/tools/hdl_common.bzl b/tools/hdl_common.bzl index 69871b55..183703e3 100644 --- a/tools/hdl_common.bzl +++ b/tools/hdl_common.bzl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # This stuff is factored here because it is used potentially in multiple bzl files # and we don't want deal with possible circular dependencies diff --git a/tools/multitool/multitool_cli.py b/tools/multitool/multitool_cli.py index d41d8a01..cbb82076 100644 --- a/tools/multitool/multitool_cli.py +++ b/tools/multitool/multitool_cli.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import argparse import json diff --git a/tools/rdl.bzl b/tools/rdl.bzl index 13d086bb..6c83b973 100644 --- a/tools/rdl.bzl +++ b/tools/rdl.bzl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # RDL files can have 0 or more dependencies on other RDL files # This block provides the following providers: diff --git a/tools/site_cobble/bluescan.py b/tools/site_cobble/bluescan.py index 999628a1..218bf29d 100755 --- a/tools/site_cobble/bluescan.py +++ b/tools/site_cobble/bluescan.py @@ -1,6 +1,5 @@ #!/usr/bin/env python3 # -# Copyright 2021 Oxide Computer Company # # This Source Code Form is subject to the terms of the Mozilla Public # License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/tools/site_cobble/bluespec.py b/tools/site_cobble/bluespec.py index 4df74f93..ff6b1dda 100644 --- a/tools/site_cobble/bluespec.py +++ b/tools/site_cobble/bluespec.py @@ -1,4 +1,3 @@ -# Copyright 2021 Oxide Computer Company # # This Source Code Form is subject to the terms of the Mozilla Public # License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/tools/site_cobble/bsv_fpga_version.py b/tools/site_cobble/bsv_fpga_version.py index 23847808..a209a20c 100644 --- a/tools/site_cobble/bsv_fpga_version.py +++ b/tools/site_cobble/bsv_fpga_version.py @@ -1,4 +1,3 @@ -# Copyright 2021 Oxide Computer Company # # This Source Code Form is subject to the terms of the Mozilla Public # License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/tools/site_cobble/nextpnr.py b/tools/site_cobble/nextpnr.py index d078659d..04c0ba95 100644 --- a/tools/site_cobble/nextpnr.py +++ b/tools/site_cobble/nextpnr.py @@ -1,4 +1,3 @@ -# Copyright 2021 Oxide Computer Company # # This Source Code Form is subject to the terms of the Mozilla Public # License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/tools/site_cobble/rdl.py b/tools/site_cobble/rdl.py index fc28f9ba..ea2a9819 100644 --- a/tools/site_cobble/rdl.py +++ b/tools/site_cobble/rdl.py @@ -1,4 +1,3 @@ -# Copyright 2021 Oxide Computer Company # # This Source Code Form is subject to the terms of the Mozilla Public # License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/tools/site_cobble/rdl_pkg/demo.rdl b/tools/site_cobble/rdl_pkg/demo.rdl index a48c2672..61f3bd49 100644 --- a/tools/site_cobble/rdl_pkg/demo.rdl +++ b/tools/site_cobble/rdl_pkg/demo.rdl @@ -1,4 +1,3 @@ -// Copyright 2022 Oxide Computer Company // This is an example SystemRDL description of the sw-accesible registers regfile a_reg_block { diff --git a/tools/site_cobble/rdl_pkg/exporter.py b/tools/site_cobble/rdl_pkg/exporter.py index 4366af9b..e9a8fdcb 100644 --- a/tools/site_cobble/rdl_pkg/exporter.py +++ b/tools/site_cobble/rdl_pkg/exporter.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company from pathlib import Path from os import PathLike diff --git a/tools/site_cobble/rdl_pkg/json_dump.py b/tools/site_cobble/rdl_pkg/json_dump.py index 9b4ca212..9125c242 100644 --- a/tools/site_cobble/rdl_pkg/json_dump.py +++ b/tools/site_cobble/rdl_pkg/json_dump.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # Note: This code is a lightly modified version of the systemRDL example JSON dumper # https://systemrdl-compiler.readthedocs.io/en/latest/examples/json_exporter.html diff --git a/tools/site_cobble/rdl_pkg/listeners.py b/tools/site_cobble/rdl_pkg/listeners.py index 317906f0..41dc8cdd 100644 --- a/tools/site_cobble/rdl_pkg/listeners.py +++ b/tools/site_cobble/rdl_pkg/listeners.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company from systemrdl import RDLListener, AddrmapNode, RegfileNode, RegNode, FieldNode, MemNode diff --git a/tools/site_cobble/rdl_pkg/models.py b/tools/site_cobble/rdl_pkg/models.py index 9df555f6..71a2057e 100644 --- a/tools/site_cobble/rdl_pkg/models.py +++ b/tools/site_cobble/rdl_pkg/models.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import copy from typing import List, Tuple diff --git a/tools/site_cobble/rdl_pkg/rdl_cli.py b/tools/site_cobble/rdl_pkg/rdl_cli.py index de720b75..652f0c9a 100644 --- a/tools/site_cobble/rdl_pkg/rdl_cli.py +++ b/tools/site_cobble/rdl_pkg/rdl_cli.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import sys import argparse diff --git a/tools/site_cobble/rdl_pkg/utils.py b/tools/site_cobble/rdl_pkg/utils.py index ed51d394..3e6fd7d0 100644 --- a/tools/site_cobble/rdl_pkg/utils.py +++ b/tools/site_cobble/rdl_pkg/utils.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import inflection diff --git a/tools/site_cobble/shell.py b/tools/site_cobble/shell.py index 4c312e14..7b7950fb 100644 --- a/tools/site_cobble/shell.py +++ b/tools/site_cobble/shell.py @@ -1,4 +1,3 @@ -# Copyright 2021 Oxide Computer Company # # This Source Code Form is subject to the terms of the Mozilla Public # License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/tools/site_cobble/yosys.py b/tools/site_cobble/yosys.py index ec7bed01..6f0327df 100644 --- a/tools/site_cobble/yosys.py +++ b/tools/site_cobble/yosys.py @@ -1,4 +1,3 @@ -# Copyright 2021 Oxide Computer Company # # This Source Code Form is subject to the terms of the Mozilla Public # License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/tools/speeker/espi_mux.py b/tools/speeker/espi_mux.py index 82369355..230728a4 100644 --- a/tools/speeker/espi_mux.py +++ b/tools/speeker/espi_mux.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # Control ruby power from gfruit over sgpio diff --git a/tools/speeker/example.py b/tools/speeker/example.py index e12374b6..7c664c14 100644 --- a/tools/speeker/example.py +++ b/tools/speeker/example.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # Super simple read/write example diff --git a/tools/speeker/gfruit_mux.py b/tools/speeker/gfruit_mux.py index 2a64a971..0e5bf911 100644 --- a/tools/speeker/gfruit_mux.py +++ b/tools/speeker/gfruit_mux.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # Super simple read/write example diff --git a/tools/speeker/ruby_power.py b/tools/speeker/ruby_power.py index b249cf2e..5411ec79 100644 --- a/tools/speeker/ruby_power.py +++ b/tools/speeker/ruby_power.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # Control ruby power from gfruit over sgpio diff --git a/tools/speeker/udp_if.py b/tools/speeker/udp_if.py index 7fdeaa17..ad1158fe 100644 --- a/tools/speeker/udp_if.py +++ b/tools/speeker/udp_if.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # This implements a simple UDP peek/poke interface that conforms to the # protocol specified here: diff --git a/tools/vhdl-ls.bxl b/tools/vhdl-ls.bxl index 1e5fb369..1385a87d 100644 --- a/tools/vhdl-ls.bxl +++ b/tools/vhdl-ls.bxl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # This function queries the build graph and finds rules starting # with vhdl ie (vhdl_unit) getting the sources and libraries diff --git a/tools/vivado.bzl b/tools/vivado.bzl index 105c4bcc..1cb3a216 100644 --- a/tools/vivado.bzl +++ b/tools/vivado.bzl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2025 Oxide Computer Company load( "@prelude//python:toolchain.bzl", diff --git a/tools/vivado_gen/vivado_gen.py b/tools/vivado_gen/vivado_gen.py index fc04e4cb..a791f763 100644 --- a/tools/vivado_gen/vivado_gen.py +++ b/tools/vivado_gen/vivado_gen.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import argparse import json diff --git a/tools/vsg-format.bxl b/tools/vsg-format.bxl index 66a270bb..9b3273db 100644 --- a/tools/vsg-format.bxl +++ b/tools/vsg-format.bxl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # This function queries the build graph and finds rules starting # with vhdl ie (vhdl_unit) getting the sources for any of our diff --git a/tools/vunit-sims.bxl b/tools/vunit-sims.bxl index ea39bd1e..756678c3 100644 --- a/tools/vunit-sims.bxl +++ b/tools/vunit-sims.bxl @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company # This function queries the build graph and targets that are # simulation targets and runs them diff --git a/tools/vunit_gen/vunit_com_codec_gen.py b/tools/vunit_gen/vunit_com_codec_gen.py index 03c9ebf4..043464c0 100644 --- a/tools/vunit_gen/vunit_com_codec_gen.py +++ b/tools/vunit_gen/vunit_com_codec_gen.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import argparse from pathlib import Path diff --git a/tools/vunit_gen/vunit_gen_cli.py b/tools/vunit_gen/vunit_gen_cli.py index 2de65a5f..c9a33d8f 100644 --- a/tools/vunit_gen/vunit_gen_cli.py +++ b/tools/vunit_gen/vunit_gen_cli.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import argparse from pathlib import Path diff --git a/tools/yosys_gen/yosys_gen_cli.py b/tools/yosys_gen/yosys_gen_cli.py index 89739b2d..15027d76 100644 --- a/tools/yosys_gen/yosys_gen_cli.py +++ b/tools/yosys_gen/yosys_gen_cli.py @@ -2,7 +2,6 @@ # License, v. 2.0. If a copy of the MPL was not distributed with this # file, You can obtain one at https://mozilla.org/MPL/2.0/. # -# Copyright 2024 Oxide Computer Company import argparse import json