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Add a file for the friday lunch talk

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commit 9d27d141caa1772c7e81c6967eeb49c2381cac1e 1 parent 7bf82bd
Omar ZENATI authored

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  1. +248 0 talk/presentation.tex
248 talk/presentation.tex
... ... @@ -0,0 +1,248 @@
  1 +\documentclass{beamer}
  2 +\usetheme{Warsaw}
  3 +\useoutertheme{infolines}
  4 +\setbeamertemplate{headline}[default]
  5 +%\setbeamercovered{transparent}
  6 +%\setbeamertemplate{footline}[default]
  7 +%\setbeamertemplate{headline}[split]
  8 +\usepackage[T1]{fontenc}
  9 +\usepackage[utf8x]{inputenc}
  10 +\usepackage[english]{babel}
  11 +\usepackage{color}
  12 +%%%%%%%%%definition des variables%%%%%%%%%%%%%%%
  13 +%\usepackage[latin1]{inputenc}
  14 +%\usepackage[T1]{fontenc}
  15 +%\usepackage{textcomp}
  16 +%\usepackage{lmodern}
  17 +%\usepackage{listings}
  18 +
  19 +
  20 +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  21 +\def\sujet{}
  22 +%Oral Presentation of Parallel Architecture
  23 +\def\projet{Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture}
  24 +\def\etape{}
  25 +\def\gA{Omar \textsc{Zenati}}
  26 +\def\prof{Susan \textsc{Medina} \& Denis \textsc{Barthou}}
  27 +
  28 +
  29 +%%%%%%%%%%%%%%%% Header %%%%%%%%%%%%%%%%
  30 + \title[Oral Presentation]{
  31 + {\bfseries \projet\\}
  32 + {\bfseries \huge \sujet}
  33 +}
  34 +
  35 +\institute[3A]{
  36 + {\normalsize \bfseries \sffamily Professor:} {\large \prof}~~~\\
  37 +
  38 +}
  39 +
  40 +\author[Zenati]{
  41 + {\normalsize \bfseries \sffamily Student:} {\large \gA}~~~~~~~~~~\\
  42 +}
  43 +
  44 +\begin{document}
  45 +
  46 +\begin{frame}
  47 +\maketitle
  48 +\end{frame}
  49 +
  50 +\begin{frame}{Plan}
  51 +\tableofcontents
  52 +\end{frame}
  53 +
  54 +\AtBeginSection[]{
  55 + \begin{frame}{Summary}
  56 + \tableofcontents[currentsection,hideallsubsections]
  57 + \end{frame}
  58 +}
  59 +
  60 +\section{Introduction}
  61 +\begin{frame}
  62 +\frametitle{Introduction}
  63 +\framesubtitle{Moore's Law}
  64 +Moore states: \textit{"Computer chips double in speed every 1.5 to 2 years period"}
  65 +\pause
  66 +\begin{exampleblock}{}
  67 +\underline{Reason:}
  68 +\begin{center}
  69 +Use of smaller transistors
  70 +\end{center}
  71 +\end{exampleblock}{}
  72 +\pause
  73 +\underline{Problem:} Stopped by Heat Wall
  74 +\pause
  75 +\begin{exampleblock}{}
  76 +\underline{Solution:}
  77 +\begin{center}
  78 +Increase of number of cores
  79 +\end{center}
  80 +\end{exampleblock}{}
  81 +\pause
  82 +\underline{Problem:} Stopped by Memory Wall
  83 +\pause
  84 +\begin{exampleblock}{}
  85 +\underline{Solution:}
  86 +\begin{center}
  87 +Optimise at all levels
  88 +\end{center}
  89 +\end{exampleblock}{}
  90 +\end{frame}
  91 +
  92 +\begin{frame}
  93 +\frametitle{Introduction}
  94 +\framesubtitle{The cache}
  95 +\begin{figure}
  96 +\includegraphics[width=0.8\textwidth]{archi_multiprocessor.jpg}
  97 +\end{figure}
  98 +\begin{center}
  99 +Access to the cache is faster than access memory !
  100 +\end{center}
  101 +\end{frame}
  102 +
  103 +
  104 +
  105 +\section{XORM Address Mapping Scheme}
  106 +\begin{frame}
  107 +\frametitle{Cache}
  108 +\framesubtitle{Organisation}
  109 +\begin{exampleblock}{}
  110 +\begin{itemize}
  111 +\item \underline{Cache Line:} Data bloc corresponding to a contiguous data bloc in memory.
  112 +\item Cache lines are organized into sets of lines.
  113 +\end{itemize}
  114 +\end{exampleblock}{}
  115 +Each part of a memory address shows how to find the equivalent bloc in the cache:
  116 +\begin{exampleblock}{}
  117 +\begin{itemize}
  118 +\item Tag: Identification of the address
  119 +\item Cache set: Number of the equivalent set
  120 +\item Offset: Position in the cache line
  121 +\end{itemize}
  122 +\end{exampleblock}{}
  123 +\begin{figure}
  124 +\includegraphics[width=0.8\textwidth]{address_memory.png}
  125 +\end{figure}
  126 +\end{frame}
  127 +
  128 +\begin{frame}
  129 +\frametitle{Cache}
  130 +\framesubtitle{Problem}
  131 +The conflict miss problem :
  132 +\begin{figure}
  133 +\includegraphics[width=0.8\textwidth]{problem.png}
  134 +\end{figure}
  135 +\end{frame}
  136 +
  137 +\begin{frame}
  138 +\frametitle{Conflict Miss}
  139 +\framesubtitle{Some solution}
  140 +To reduce conflict miss in cache :
  141 +\begin{exampleblock}{}
  142 +\begin{itemize}
  143 +\item Skewed-associative cache
  144 +\item Victim cache
  145 +\item Column-associative cache
  146 +\item Prime-indexed cache
  147 +\item ...
  148 +\end{itemize}
  149 +\end{exampleblock}{}
  150 +\pause
  151 +The main shortcomings of these schemes are:
  152 +\begin{exampleblock}{}
  153 +\begin{itemize}
  154 +\item Computing complexity
  155 +\item Implementing cost
  156 +\end{itemize}
  157 +\end{exampleblock}{}
  158 +\end{frame}
  159 +
  160 +
  161 +\begin{frame}
  162 +\frametitle{XORM scheme}
  163 +\framesubtitle{Principle}
  164 +\underline{Definition :}
  165 +\begin{figure}
  166 +\includegraphics[width=0.8\textwidth]{def.png}
  167 +\end{figure}
  168 +\pause
  169 +\begin{figure}
  170 +\includegraphics[width=0.5\textwidth]{xorm_scheme.png}
  171 +\end{figure}
  172 +\pause
  173 +\begin{exampleblock}{}
  174 +\begin{center}
  175 +$ index = A_3 H_{m*m} \oplus A_2$\\
  176 +$ interleave = A_4 H_{m*m} \oplus A_1$
  177 +\end{center}
  178 +\end{exampleblock}{}
  179 +\end{frame}
  180 +
  181 +
  182 +\section{Simulation and Result}
  183 +\begin{frame}
  184 +\frametitle{Simulation}
  185 +\framesubtitle{Godson-T Simulator Architecture}
  186 +\begin{figure}
  187 +\includegraphics[width=0.8\textwidth]{godsont.png}
  188 +\end{figure}
  189 +\end{frame}
  190 +
  191 +\begin{frame}
  192 +\frametitle{Simulation}
  193 +\framesubtitle{Target algorithm}
  194 +The simulation was applied with :
  195 +\begin{exampleblock}{}
  196 +\begin{itemize}
  197 +\item Matrix multiplication
  198 +\item FFT decomposition
  199 +\item LU decomposition
  200 +\item Pfind algorithm
  201 +\end{itemize}
  202 +\end{exampleblock}{}
  203 +\end{frame}
  204 +
  205 +\begin{frame}
  206 +\frametitle{Results}
  207 +\begin{figure}
  208 +\includegraphics[width=0.8\textwidth]{result1.png}
  209 +\end{figure}
  210 +\end{frame}
  211 +
  212 +\begin{frame}
  213 +\frametitle{Results}
  214 +\begin{figure}
  215 +\includegraphics[width=0.8\textwidth]{result2.png}
  216 +\end{figure}
  217 +\end{frame}
  218 +
  219 +
  220 +\section{Conclusion}
  221 +\begin{frame}
  222 +\frametitle{Conclusion}
  223 +\underline{XORM scheme :}
  224 +\begin{exampleblock}{}
  225 +\begin{itemize}
  226 +\item Less miss conflict
  227 +\item Better performance
  228 +\end{itemize}
  229 +\end{exampleblock}{}
  230 +\underline{Questions :}
  231 +\begin{exampleblock}{}
  232 +\begin{itemize}
  233 +\item What about others architectures?
  234 +\end{itemize}
  235 +\end{exampleblock}{}
  236 +\end{frame}
  237 +
  238 +
  239 +\frame{
  240 +\frametitle{Conclusion}
  241 +\begin{exampleblock}{}
  242 +\begin{center}
  243 +\huge{Thank you for your attention}
  244 +\end{center}
  245 +\end{exampleblock}{}
  246 +}
  247 +
  248 +\end{document}

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