Starter file + drivers for the Digilent Nexys 3 / Xilinx Spartan-6 FPGA board
Verilog
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README.md
counter.v
debounce.v
nexys3_top.v
seven_segment_display.v

README.md

Nexys 3 Starter Files

  • counter.v - Simple counter circuit, outputs high one each cycle
  • debounce.v - Debounce circuit for noisy inputs (buttons)
  • seven_segment_display.v - Driver to use the 7-seg to display 4 hexadecimal numbers
  • nexys3_top.v - Top-level file that instantiates all inputs/outputs on the board

Top-level File

The top-level file is still a work-in-progress and does not instantiate all of the inputs or outputs yet. I will be expanding it as I interface with more and more of the board. Feel free to add in the missing I/O and assignments.