From 4e5d863291bf3ba3601ef325bca2d6ef4f71eebf Mon Sep 17 00:00:00 2001 From: Gautier Hattenberger Date: Thu, 23 Feb 2017 19:31:50 +0100 Subject: [PATCH] [board] support of the Chimera autopilot based on STM32F7 (#2018) * [board] support of the Chimera autopilot based on STM32F7 - based on ChibiOS only (updated to master for proper support of F7) - requires some specific ram for DMA operations - SBUS driver updated and support of internal inverted logic option of F7 * [chibios] fix some compilation errors * [chibios] fix some a few PR comments - test less MCU types - support F1 for uart driver - more autodetect for VTOR_INIT * use correct path * choose a working version of chibios * [chibios] fix some comments from PR review - add some doc - protect LED - update TRUE/FALSE for lowercase - pick a slightly older version of chibios (wrong path in makefile not fixed yet) --- conf/Makefile.chibios | 26 +- conf/airframes/ENAC/fixed-wing/chimera.xml | 227 +++ conf/boards/apogee_1.0_chibios.makefile | 5 +- conf/boards/chimera_1.0.makefile | 99 ++ conf/boards/lia_1.1_chibios.makefile | 2 +- conf/boards/lisa_mx_2.1_chibios.makefile | 5 +- conf/boards/px4fmu_2.4_chibios.makefile | 3 +- conf/boards/vms_ecu_1.0_chibios.makefile | 3 +- conf/chibios/chibios_rules.mk | 42 +- .../subsystems/shared/baro_board.makefile | 9 + conf/flash_modes.xml | 3 + conf/modules/imu_chimera.xml | 20 + sw/airborne/arch/chibios/chconf.h | 67 +- sw/airborne/arch/chibios/halconf.h | 70 +- sw/airborne/arch/chibios/led_hw.h | 1 + sw/airborne/arch/chibios/mcu_arch.c | 24 +- sw/airborne/arch/chibios/mcu_arch.h | 48 +- .../arch/chibios/mcu_periph/adc_arch.c | 9 +- .../arch/chibios/mcu_periph/gpio_arch.c | 19 +- .../arch/chibios/mcu_periph/gpio_arch.h | 9 +- .../arch/chibios/mcu_periph/i2c_arch.c | 59 + .../arch/chibios/mcu_periph/pwm_input_arch.c | 12 +- .../arch/chibios/mcu_periph/ram_arch.h | 62 + .../arch/chibios/mcu_periph/sdio_arch.c | 18 +- .../arch/chibios/mcu_periph/spi_arch.c | 114 +- .../arch/chibios/mcu_periph/uart_arch.c | 51 +- .../arch/chibios/modules/core/rtos_mon_arch.c | 10 +- .../subsystems/actuators/actuators_pwm_arch.c | 24 +- sw/airborne/arch/stm32/mcu_periph/gpio_arch.h | 5 + .../boards/apogee/chibios/v1.0/board.h | 25 + sw/airborne/boards/chimera/baro_board.h | 18 + .../boards/chimera/chibios/v1.0/board.c | 132 ++ .../boards/chimera/chibios/v1.0/board.h | 1544 +++++++++++++++++ .../boards/chimera/chibios/v1.0/board.mk | 20 + .../boards/chimera/chibios/v1.0/chimera.h | 560 ++++++ .../boards/chimera/chibios/v1.0/ffconf.h | 239 +++ .../boards/chimera/chibios/v1.0/mcuconf.h | 472 +++++ sw/airborne/mcu_periph/uart.c | 4 + sw/airborne/mcu_periph/uart.h | 5 +- sw/airborne/modules/loggers/sdlog_chibios.c | 18 +- .../modules/loggers/sdlog_chibios/printf.c | 2 +- .../modules/loggers/sdlog_chibios/printf.h | 3 + .../modules/loggers/sdlog_chibios/sdLog.c | 36 +- .../loggers/sdlog_chibios/usbStorage.c | 21 +- sw/airborne/subsystems/imu/imu_mpu9250_i2c.c | 31 +- sw/airborne/subsystems/radio_control/sbus.c | 8 +- .../subsystems/radio_control/sbus_common.c | 67 +- .../subsystems/radio_control/sbus_common.h | 4 +- .../subsystems/radio_control/sbus_dual.c | 18 +- sw/ext/chibios | 2 +- 50 files changed, 4074 insertions(+), 201 deletions(-) create mode 100644 conf/airframes/ENAC/fixed-wing/chimera.xml create mode 100644 conf/boards/chimera_1.0.makefile create mode 100644 conf/modules/imu_chimera.xml create mode 100644 sw/airborne/arch/chibios/mcu_periph/ram_arch.h create mode 100644 sw/airborne/boards/chimera/baro_board.h create mode 100644 sw/airborne/boards/chimera/chibios/v1.0/board.c create mode 100644 sw/airborne/boards/chimera/chibios/v1.0/board.h create mode 100644 sw/airborne/boards/chimera/chibios/v1.0/board.mk create mode 100644 sw/airborne/boards/chimera/chibios/v1.0/chimera.h create mode 100644 sw/airborne/boards/chimera/chibios/v1.0/ffconf.h create mode 100644 sw/airborne/boards/chimera/chibios/v1.0/mcuconf.h diff --git a/conf/Makefile.chibios b/conf/Makefile.chibios index adf754cb522..fa48b567b5b 100644 --- a/conf/Makefile.chibios +++ b/conf/Makefile.chibios @@ -50,7 +50,7 @@ ifdef CHIBIOS_BOOTLOADER_SCRIPT CHIBIOS_LINKER_DIR ?= $(PAPARAZZI_SRC)/sw/airborne/arch/chibios/ else # we use the original linker script -CHIBIOS_LINKER_DIR ?= $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld +CHIBIOS_LINKER_DIR ?= $(STARTUPLD) endif # Launch with "make Q=''" to get full command display @@ -129,6 +129,11 @@ endif # Enable this if you want link time optimizations (LTO) ifeq ($(USE_LTO),) USE_LTO = no +else +# Force LTO to 'no' if in debug mode +ifeq (,$(findstring $(RTOS_DEBUG),0 FALSE)) + USE_LTO = no +endif endif # If enabled, this option allows to compile the application in THUMB mode. @@ -171,9 +176,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU on Cortex-M4. +# Enables the use of FPU on Cortex-M4 / M7 (no, softfp, hard). ifeq ($(USE_FPU),) - USE_FPU = yes + USE_FPU = hard endif # @@ -188,7 +193,7 @@ endif # Imported source files and paths # Startup files. -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/$(CHIBIOS_BOARD_STARTUP) +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/$(CHIBIOS_BOARD_STARTUP) # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/ports/STM32/$(CHIBIOS_BOARD_PLATFORM) @@ -196,9 +201,9 @@ include $(CHIBIOS_BOARD_DIR)/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). -#include $(CHIBIOS)/test/rt/test.mk +# ifeq ($(USE_FATFS), TRUE) include $(PAPARAZZI_HOME)/conf/chibios/fatfs.mk endif @@ -246,9 +251,9 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) -INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ +INCDIR = $(CHIBIOS)/os/license $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(FATFSINC) \ $(CHIBIOS)/os/various $(CHIBIOS_BOARD_DIR) $(CHIBIOS_PROJECT_DIR) @@ -308,7 +313,7 @@ UADEFS = $($(TARGET).CFLAGS) $(USER_CFLAGS) $(BOARD_CFLAGS) # List all user directories here # remove -I before include dir because ChibiOS is adding them again -UINCDIR = $(patsubst -I%,%,$(INCLUDES)) +UINCDIR = $(CHIBIOS)/os/license $(patsubst -I%,%,$(INCLUDES)) # List the user directory to look for the libraries here ULIBDIR = @@ -334,7 +339,6 @@ endif # Settings for GDB -# default port configuration for BMP GDB = $(shell which arm-none-eabi-gdb) @@ -355,7 +359,7 @@ include $(PAPARAZZI_HOME)/conf/Makefile.stm32-upload ############################################################################### -RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC #include $(RULESPATH)/rules.mk EXTRA_RULES_INCLUDE_PATH = $(PAPARAZZI_HOME)/conf/chibios/chibios_extra_rules.mk diff --git a/conf/airframes/ENAC/fixed-wing/chimera.xml b/conf/airframes/ENAC/fixed-wing/chimera.xml new file mode 100644 index 00000000000..233e1c30446 --- /dev/null +++ b/conf/airframes/ENAC/fixed-wing/chimera.xml @@ -0,0 +1,227 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + diff --git a/conf/boards/apogee_1.0_chibios.makefile b/conf/boards/apogee_1.0_chibios.makefile index 7154251544f..6b36d6cdc6c 100644 --- a/conf/boards/apogee_1.0_chibios.makefile +++ b/conf/boards/apogee_1.0_chibios.makefile @@ -14,9 +14,8 @@ $(TARGET).ARCHDIR = $(ARCH) RTOS=chibios -# FPU on F4 -USE_FPU=yes -HARD_FLOAT=yes +## FPU on F4 +USE_FPU=softfp $(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD -DUSE_HARD_FAULT_RECOVERY diff --git a/conf/boards/chimera_1.0.makefile b/conf/boards/chimera_1.0.makefile new file mode 100644 index 00000000000..2275c2909c0 --- /dev/null +++ b/conf/boards/chimera_1.0.makefile @@ -0,0 +1,99 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# chimera_1.0.makefile +# +# based on STM32F7 +# pre-version, only compatible with ChibiOS +# + +BOARD=chimera +BOARD_VERSION=1.0 +BOARD_DIR=$(BOARD)/chibios/v$(BOARD_VERSION) +BOARD_CFG=\"boards/$(BOARD_DIR)/$(BOARD).h\" + +ARCH=chibios +$(TARGET).ARCHDIR = $(ARCH) + +RTOS=chibios +MCU=cortex-m7 + +## FPU on F7 +USE_FPU=softfp +USE_FPU_OPT= -mfpu=fpv5-d16 + +USE_LTO=yes + +$(TARGET).CFLAGS += -DSTM32F7 -DPPRZLINK_ENABLE_FD -DUSE_HARD_FAULT_RECOVERY + +############################################################################## +# Architecture or project specific options +# +# Define project name here (target) +PROJECT = $(TARGET) + +# Project specific files and paths (see Makefile.chibios for details) +CHIBIOS_BOARD_PLATFORM = STM32F7xx/platform.mk +CHIBIOS_BOARD_PORT = ARMCMx/STM32F7xx/port.mk +CHIBIOS_BOARD_LINKER = STM32F76xxI.ld +CHIBIOS_BOARD_STARTUP = startup_stm32f7xx.mk + +# ITCM flash is a special flash that allow faster operations +# At the moment it is not possible to flash the code in this mode using dfu-util +# but it should work with the BlackMagicProbe or STLINK +# By default, normal flash is used +ifeq ($(USE_ITCM),1) +$(TARGET).CFLAGS += -DUSE_ITCM=1 +DFU_ADDR = 0x00200000 +else +$(TARGET).CFLAGS += -DUSE_ITCM=0 +DFU_ADDR = 0x08000000 +endif + +############################################################################## +# Compiler settings +# + +# default flash mode is via usb dfu bootloader +# possibilities: DFU-UTIL, SWD, STLINK +FLASH_MODE ?= DFU-UTIL + +HAS_LUFTBOOT = FALSE + +# +# default LED configuration +# +RADIO_CONTROL_LED ?= 4 +BARO_LED ?= none +AHRS_ALIGNER_LED ?= 2 +GPS_LED ?= 3 +SYS_TIME_LED ?= 1 + +# +# default UART configuration (modem, gps, spektrum) +# + +MODEM_PORT ?= UART3 +MODEM_BAUD ?= B57600 + +GPS_PORT ?= UART8 +GPS_BAUD ?= B57600 + +RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART4 +RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART7 + +# single mode +SBUS_PORT ?= UART7 +# dual mode +SBUS1_PORT ?= UART7 +SBUS2_PORT ?= UART4 + +# +# default actuator configuration +# +# you can use different actuators by adding a configure option to your firmware section +# e.g. +# +ACTUATORS ?= actuators_pwm + diff --git a/conf/boards/lia_1.1_chibios.makefile b/conf/boards/lia_1.1_chibios.makefile index 805f1d36290..89bf57dd1f8 100644 --- a/conf/boards/lia_1.1_chibios.makefile +++ b/conf/boards/lia_1.1_chibios.makefile @@ -38,4 +38,4 @@ GPS_BAUD ?= B38400 # ACTUATORS ?= actuators_pwm -include $(PAPARAZZI_SRC)/conf/boards/lisa_m_common_chibios.makefile +include $(PAPARAZZI_HOME)/conf/boards/lisa_m_common_chibios.makefile diff --git a/conf/boards/lisa_mx_2.1_chibios.makefile b/conf/boards/lisa_mx_2.1_chibios.makefile index 48a697923d0..afc6ca609ff 100644 --- a/conf/boards/lisa_mx_2.1_chibios.makefile +++ b/conf/boards/lisa_mx_2.1_chibios.makefile @@ -14,9 +14,8 @@ $(TARGET).ARCHDIR = $(ARCH) RTOS=chibios -# FPU on F4 -USE_FPU=yes -HARD_FLOAT=yes +## FPU on F4 +USE_FPU=hard $(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD diff --git a/conf/boards/px4fmu_2.4_chibios.makefile b/conf/boards/px4fmu_2.4_chibios.makefile index 6f91816a8a5..67e4d26fc05 100644 --- a/conf/boards/px4fmu_2.4_chibios.makefile +++ b/conf/boards/px4fmu_2.4_chibios.makefile @@ -17,8 +17,7 @@ $(TARGET).ARCHDIR = $(ARCH) RTOS=chibios # FPU on F4 -USE_FPU=yes -HARD_FLOAT=yes +USE_FPU=hard $(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD diff --git a/conf/boards/vms_ecu_1.0_chibios.makefile b/conf/boards/vms_ecu_1.0_chibios.makefile index 9b3ec51ffaa..9bc98612fee 100644 --- a/conf/boards/vms_ecu_1.0_chibios.makefile +++ b/conf/boards/vms_ecu_1.0_chibios.makefile @@ -15,8 +15,7 @@ $(TARGET).ARCHDIR = $(ARCH) RTOS=chibios # FPU on F4 -USE_FPU=yes -HARD_FLOAT=yes +USE_FPU=hard $(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD diff --git a/conf/chibios/chibios_rules.mk b/conf/chibios/chibios_rules.mk index 62ac388f8ae..40a80aaec31 100644 --- a/conf/chibios/chibios_rules.mk +++ b/conf/chibios/chibios_rules.mk @@ -27,17 +27,21 @@ ifeq ($(USE_LTO),yes) OPT += -flto endif +# FPU options default (Cortex-M4 and Cortex-M7 single precision). +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfpu=fpv4-sp-d16 -fsingle-precision-constant +endif + # FPU-related options -ifeq ($(USE_FPU),yes) -ifeq ($(HARD_FLOAT),yes) - OPT += -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -else - OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant +ifeq ($(USE_FPU),) + USE_FPU = no endif - DDEFS += -DCORTEX_USE_FPU=TRUE +ifneq ($(USE_FPU),no) + OPT += -mfloat-abi=$(USE_FPU) $(USE_FPU_OPT) + DDEFS += -DCORTEX_USE_FPU=TRUE DADEFS += -DCORTEX_USE_FPU=TRUE else - DDEFS += -DCORTEX_USE_FPU=FALSE + DDEFS += -DCORTEX_USE_FPU=FALSE DADEFS += -DCORTEX_USE_FPU=FALSE endif @@ -80,8 +84,8 @@ else ACSRC += $(CSRC) ACPPSRC += $(CPPSRC) endif -ASRC = $(ACSRC)$(ACPPSRC) -TSRC = $(TCSRC)$(TCPPSRC) +ASRC = $(ACSRC) $(ACPPSRC) +TSRC = $(TCSRC) $(TCPPSRC) SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) # Various directories @@ -115,24 +119,27 @@ ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) -LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT) +LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH)/ld,--script=$(LDSCRIPT)$(LDOPT) # Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) +ifneq ($(strip $(TSRC)),) CFLAGS += -DTHUMB_PRESENT CPPFLAGS += -DTHUMB_PRESENT ASFLAGS += -DTHUMB_PRESENT - ifneq ($(ASRC),) + ASXFLAGS += -DTHUMB_PRESENT + ifneq ($(strip $(ASRC)),) # Mixed ARM and THUMB mode. CFLAGS += -mthumb-interwork CPPFLAGS += -mthumb-interwork ASFLAGS += -mthumb-interwork + ASXFLAGS += -mthumb-interwork LDFLAGS += -mthumb-interwork else # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb + ASXFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb LDFLAGS += -mno-thumb-interwork -mthumb endif else @@ -140,11 +147,13 @@ else CFLAGS += -mno-thumb-interwork CPPFLAGS += -mno-thumb-interwork ASFLAGS += -mno-thumb-interwork + ASXFLAGS += -mno-thumb-interwork LDFLAGS += -mno-thumb-interwork endif # Generate dependency information ASFLAGS += -MD -MP -MF $(BUILDDIR)/.dep/$(@F).d +ASXFLAGS += -MD -MP -MF $(BUILDDIR)/.dep/$(@F).d CFLAGS += -MD -MP -MF $(BUILDDIR)/.dep/$(@F).d CPPFLAGS += -MD -MP -MF $(BUILDDIR)/.dep/$(@F).d @@ -239,6 +248,7 @@ else endif %.elf: $(OBJS) $(LDSCRIPT) +#$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT) ifeq ($(USE_VERBOSE_COMPILE),yes) @echo $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ @@ -247,7 +257,7 @@ else @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ endif -%.hex: %.elf $(LDSCRIPT) +%.hex: %.elf ifeq ($(USE_VERBOSE_COMPILE),yes) $(HEX) $< $@ else @@ -255,7 +265,7 @@ else @$(HEX) $< $@ endif -%.bin: %.elf $(LDSCRIPT) +%.bin: %.elf ifeq ($(USE_VERBOSE_COMPILE),yes) $(BIN) $< $@ else @@ -263,7 +273,7 @@ else @$(BIN) $< $@ endif -%.srec: %.elf $(LDSCRIPT) +%.srec: %.elf ifeq ($(USE_VERBOSE_COMPILE),yes) $(SREC) $< $@ else @@ -271,7 +281,7 @@ else @$(SREC) $< $@ endif -%.dmp: %.elf $(LDSCRIPT) +%.dmp: %.elf ifeq ($(USE_VERBOSE_COMPILE),yes) $(OD) $(ODFLAGS) $< > $@ $(SZ) $< diff --git a/conf/firmwares/subsystems/shared/baro_board.makefile b/conf/firmwares/subsystems/shared/baro_board.makefile index 321e85a96ff..69e3167bf08 100644 --- a/conf/firmwares/subsystems/shared/baro_board.makefile +++ b/conf/firmwares/subsystems/shared/baro_board.makefile @@ -247,6 +247,15 @@ else ifeq ($(BOARD), openpilot_revo) BARO_BOARD_SRCS += peripherals/ms5611_i2c.c BARO_BOARD_SRCS += boards/baro_board_ms5611_i2c.c +else ifeq ($(BOARD), chimera) + BARO_BOARD_CFLAGS += -DBARO_BOARD=BARO_MS5611_I2C + BARO_BOARD_CFLAGS += -DUSE_I2C1 + BARO_BOARD_CFLAGS += -DBB_MS5611_I2C_DEV=i2c1 + BARO_BOARD_CFLAGS += -DBB_MS5611_SLAVE_ADDR=MS5611_I2C_SLAVE_ADDR_ALT + BARO_BOARD_SRCS += peripherals/ms5611.c + BARO_BOARD_SRCS += peripherals/ms5611_i2c.c + BARO_BOARD_SRCS += boards/baro_board_ms5611_i2c.c + endif # check board BARO_LED ?= none diff --git a/conf/flash_modes.xml b/conf/flash_modes.xml index 7d7b2899436..1b42fa1ad1a 100644 --- a/conf/flash_modes.xml +++ b/conf/flash_modes.xml @@ -59,6 +59,7 @@ + @@ -71,6 +72,7 @@ + @@ -88,6 +90,7 @@ + diff --git a/conf/modules/imu_chimera.xml b/conf/modules/imu_chimera.xml new file mode 100644 index 00000000000..22544d527dd --- /dev/null +++ b/conf/modules/imu_chimera.xml @@ -0,0 +1,20 @@ + + + + + + MPU9250 IMU via SPI. + Basically the same as imu_mpu9250_spi, only changed axes assignment for Chimera. + + + + + + + + + + + + + diff --git a/sw/airborne/arch/chibios/chconf.h b/sw/airborne/arch/chibios/chconf.h index 3448481e98c..106899d5d6e 100644 --- a/sw/airborne/arch/chibios/chconf.h +++ b/sw/airborne/arch/chibios/chconf.h @@ -25,8 +25,10 @@ * @{ */ -#ifndef _CHCONF_H_ -#define _CHCONF_H_ +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ /*===========================================================================*/ /** @@ -368,11 +370,16 @@ * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. */ -#if !defined(CH_DBG_ENABLE_TRACE) -#define CH_DBG_ENABLE_TRACE FALSE -#endif +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 /** * @brief Debug option, stack checks. @@ -460,6 +467,20 @@ /* Context switch code here.*/ \ } +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + /** * @brief Idle thread enter hook. * @note This hook is invoked within a critical zone, no OS functions @@ -467,6 +488,7 @@ * @note This macro can be used to activate a power saving mode. */ #define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ } /** @@ -476,6 +498,7 @@ * @note This macro can be used to deactivate a power saving mode. */ #define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ } /** @@ -504,12 +527,44 @@ /* System halt code here.*/ \ } +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + /** @} */ /*===========================================================================*/ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ + + +#ifndef CORTEX_VTOR_INIT // try to find the correct init address if not defined + +#if USE_ITCM // point to correct interrupt vector when using ITCM flash on F7 +#define CORTEX_VTOR_INIT 0x00200000U + +#elif LUFTBOOT // using LUFTBOOT bootloader +#if defined STM32F4 +#define CORTEX_VTOR_INIT 0x00004000U +#else +#define CORTEX_VTOR_INIT 0x00002000U +#endif + +#else // default value +#define CORTEX_VTOR_INIT 0x08000000U +#endif + +#endif // CORTEX_VTOR_INIT + +// allow float for the ChibiOS print function (used with logger) +#define CHPRINTF_USE_FLOAT 1 + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/sw/airborne/arch/chibios/halconf.h b/sw/airborne/arch/chibios/halconf.h index 705e89cd2d3..40d7d4137d4 100644 --- a/sw/airborne/arch/chibios/halconf.h +++ b/sw/airborne/arch/chibios/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio modified by: AggieAir, A Remote Sensing Unmanned Aerial System for Scientific Applications Utah State University, http://aggieair.usu.edu/ @@ -7,6 +7,8 @@ Michal Podhradsky (michal.podhradsky@aggiemail.usu.edu) Calvin Coopmans (c.r.coopmans@ieee.org) + modified by Gautier Hattenberger for STM32F7 support + Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at @@ -125,7 +127,11 @@ * ifdef RADIO_CONTROL_TYPE_PPM then TRUE, otherwise FALSE */ #if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#if RADIO_CONTROL_TYPE_PPM || USE_PWM_INPUT || defined USE_PWM_INPUT1 || defined USE_PWM_INPUT2 #define HAL_USE_ICU TRUE +#else +#define HAL_USE_ICU FALSE +#endif #endif /** @@ -214,6 +220,13 @@ #endif #endif +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + /*===========================================================================*/ /* ADC driver related settings. */ /*===========================================================================*/ @@ -345,6 +358,29 @@ #define SERIAL_BUFFERS_SIZE 1024 #endif +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -365,6 +401,38 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE #endif +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/sw/airborne/arch/chibios/led_hw.h b/sw/airborne/arch/chibios/led_hw.h index 246efadc558..cb893dcb6c3 100644 --- a/sw/airborne/arch/chibios/led_hw.h +++ b/sw/airborne/arch/chibios/led_hw.h @@ -35,6 +35,7 @@ */ #include "hal.h" #include "mcu_periph/gpio_def.h" +#include BOARD_CONFIG /* * Regular GPIO driven LEDs diff --git a/sw/airborne/arch/chibios/mcu_arch.c b/sw/airborne/arch/chibios/mcu_arch.c index dd0bd17baf2..e9ceb9b4ec3 100644 --- a/sw/airborne/arch/chibios/mcu_arch.c +++ b/sw/airborne/arch/chibios/mcu_arch.c @@ -41,7 +41,7 @@ #if USE_HARD_FAULT_RECOVERY -#ifdef STM32F4 +#if defined STM32F4 || defined STM32F7 #define BCKP_SECTION ".ram5" #define IN_BCKP_SECTION(var) var __attribute__ ((section(BCKP_SECTION), aligned(8))) #else @@ -85,6 +85,20 @@ CH_IRQ_HANDLER(UsageFault_Handler) } bool recovering_from_hard_fault; + +// select correct register +#if defined STM32F4 +#define __PWR_CSR PWR->CSR +#define __PWR_CSR_BRE PWR_CSR_BRE +#define __PWR_CSR_BRR PWR_CSR_BRR +#elif defined STM32F7 +#define __PWR_CSR PWR->CSR1 +#define __PWR_CSR_BRE PWR_CSR1_BRE +#define __PWR_CSR_BRR PWR_CSR1_BRR +#else +#error Hard fault recovery not supported +#endif + #endif @@ -111,11 +125,11 @@ void mcu_arch_init(void) #if USE_HARD_FAULT_RECOVERY /* Backup domain SRAM enable, and with it, the regulator */ -#if STM32F4 +#if defined STM32F4 || defined STM32F7 RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN; - PWR->CSR |= PWR_CSR_BRE; - while ((PWR->CSR & PWR_CSR_BRR) == 0) ; /* Waits until the regulator is stable */ -#endif /* STM32F4 */ + __PWR_CSR |= __PWR_CSR_BRE; + while ((__PWR_CSR & __PWR_CSR_BRR) == 0) ; /* Waits until the regulator is stable */ +#endif /* STM32F4 | STM32F7*/ // test if last reset was a 'real' hard fault recovering_from_hard_fault = false; diff --git a/sw/airborne/arch/chibios/mcu_arch.h b/sw/airborne/arch/chibios/mcu_arch.h index e1dded574cd..c0abc45c4f8 100644 --- a/sw/airborne/arch/chibios/mcu_arch.h +++ b/sw/airborne/arch/chibios/mcu_arch.h @@ -27,8 +27,6 @@ * @file arch/chibios/mcu_arch.h * Microcontroller initialization function for ChibiOS * - * ChibiOS initialized peripherals by itself, hence empty - * functions for Paparazzi compatibility. */ #ifndef CHIBIOS_MCU_ARCH_H #define CHIBIOS_MCU_ARCH_H @@ -44,4 +42,50 @@ extern void mcu_arch_init(void); extern bool recovering_from_hard_fault; #endif +#include + +/** Put MCU into deep sleep mode + * + * This can be used when closing the SD log files + * right after a power down to save the remaining + * energy for the SD card internal MCU + * + * Never call this during flight! + */ +static inline void mcu_deep_sleep(void) +{ +#if defined STM32F4 + /* clear PDDS and LPDS bits */ + PWR->CR &= ~(PWR_CR_PDDS | PWR_CR_LPDS); + /* set LPDS and clear */ + PWR->CR |= (PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF); +#elif defined STM32F7 + /* clear PDDS and LPDS bits */ + PWR->CR1 &= ~(PWR_CR1_PDDS | PWR_CR1_LPDS); + /* set LPDS and clear */ + PWR->CR1 |= (PWR_CR1_LPDS | PWR_CR1_CSBF); +#endif + + /* Setup the deepsleep mask */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + __disable_irq(); + + __SEV(); + __WFE(); + __WFE(); + + __enable_irq(); + + /* clear the deepsleep mask */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; +} + +/** Request a software reset of the MCU + */ +static inline void mcu_reset(void) +{ + NVIC_SystemReset(); +} + #endif /* CHIBIOS_MCU_ARCH_H */ diff --git a/sw/airborne/arch/chibios/mcu_periph/adc_arch.c b/sw/airborne/arch/chibios/mcu_periph/adc_arch.c index d6044054f00..3ead555d75a 100644 --- a/sw/airborne/arch/chibios/mcu_periph/adc_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/adc_arch.c @@ -54,6 +54,7 @@ #include "mcu_periph/gpio.h" #include "hal.h" #include "std.h" +#include "mcu_periph/ram_arch.h" // Macros to automatically enable the correct ADC @@ -70,11 +71,11 @@ // STM32F1xx #define ADC_SAMPLE_RATE ADC_SAMPLE_41P5 #define ADC_CR2_CFG ADC_CR2_TSVREFE -#elif defined(__STM32F4xx_H) -// STM32F4xx +#elif defined(__STM32F4xx_H) || defined(__STM32F7xx_H) +// STM32F4xx | STM32F7xx #define ADC_SAMPLE_RATE ADC_SAMPLE_480 #define ADC_CR2_CFG ADC_CR2_SWSTART -#endif // STM32F1xx vs STM32F4xx +#endif // Create channel map @@ -137,7 +138,7 @@ ADCDriver *adcp_err = NULL; #ifndef ADC_BUF_DEPTH #define ADC_BUF_DEPTH (MAX_AV_NB_SAMPLE/2) #endif -static adcsample_t adc_samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH]; +static IN_DMA_SECTION(adcsample_t adc_samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH]); #if USE_AD1 static struct adc_buf *adc1_buffers[ADC_NUM_CHANNELS]; diff --git a/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c b/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c index 39c5678f539..3a2969c7895 100644 --- a/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c @@ -58,7 +58,7 @@ void gpio_setup_input_pulldown(ioportid_t port, uint16_t gpios) chSysUnlock(); } -void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af) +void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af, bool is_output) { chSysLock(); // architecture dependent settings @@ -68,11 +68,18 @@ void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af) (void)port; (void)pin; (void)af; -#elif defined(__STM32F4xx_H) -// STM32F4xx - palSetPadMode(port, pin, PAL_MODE_ALTERNATE(af)); -#endif // STM32F1xx vs STM32F4xx - +#elif defined(__STM32F4xx_H) || defined(__STM32F7xx_H) +// STM32F4xx and STM32F7xx + if (af) { + palSetPadMode(port, pin, PAL_MODE_ALTERNATE(af)); + } else { + if (is_output) { + palSetPadMode(port, pin, PAL_MODE_OUTPUT_PUSHPULL); + } else { + palSetPadMode(port, pin, PAL_MODE_INPUT); + } + } +#endif chSysUnlock(); } diff --git a/sw/airborne/arch/chibios/mcu_periph/gpio_arch.h b/sw/airborne/arch/chibios/mcu_periph/gpio_arch.h index d80e10a6925..f9258468377 100644 --- a/sw/airborne/arch/chibios/mcu_periph/gpio_arch.h +++ b/sw/airborne/arch/chibios/mcu_periph/gpio_arch.h @@ -30,9 +30,14 @@ #ifndef GPIO_ARCH_H #define GPIO_ARCH_H -#include "hal.h" +#include #include "mcu_periph/gpio_def.h" +/** + * Abstract gpio port type for hardware independent part + */ +typedef ioportid_t gpio_port_t; + /** * Setup one or more pins of the given GPIO port as outputs. * @param[in] port @@ -65,7 +70,7 @@ extern void gpio_setup_input_pulldown(ioportid_t port, uint16_t gpios); * Setup a gpio for input or output with alternate function. * This is an STM32 specific helper funtion and should only be used in stm32 code. */ -extern void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af); +extern void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af, bool is_output); /** * Setup a gpio for analog use. diff --git a/sw/airborne/arch/chibios/mcu_periph/i2c_arch.c b/sw/airborne/arch/chibios/mcu_periph/i2c_arch.c index 8ce0acef6eb..2a7426c83e1 100644 --- a/sw/airborne/arch/chibios/mcu_periph/i2c_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/i2c_arch.c @@ -38,6 +38,9 @@ #include #include +#include "mcu_periph/ram_arch.h" +#include "string.h" + #if USE_I2C1 || USE_I2C2 || USE_I2C3 @@ -45,6 +48,9 @@ struct i2c_init { semaphore_t *sem; I2CConfig *cfg; +#ifdef STM32F7 + uint8_t *dma_buf; +#endif }; @@ -78,18 +84,41 @@ static void handle_i2c_thd(struct i2c_periph *p) msg_t status; // submit i2c transaction (R/W or R only depending of len_w) if (t->len_w > 0) { +#if defined STM32F7 + // we do stupid mem copy because F7 needs a special RAM for DMA operation + memcpy(i->dma_buf, (void*)t->buf, (size_t)(t->len_w)); + status = i2cMasterTransmitTimeout( + (I2CDriver*)p->reg_addr, + (i2caddr_t)((t->slave_addr)>>1), + (uint8_t*)i->dma_buf, (size_t)(t->len_w), + (uint8_t*)i->dma_buf, (size_t)(t->len_r), + tmo); + memcpy((void*)t->buf, i->dma_buf, (size_t)(t->len_r)); +#else status = i2cMasterTransmitTimeout( (I2CDriver*)p->reg_addr, (i2caddr_t)((t->slave_addr)>>1), (uint8_t*)t->buf, (size_t)(t->len_w), (uint8_t*)t->buf, (size_t)(t->len_r), tmo); +#endif } else { +#if defined STM32F7 + // we do stupid mem copy because F7 needs a special RAM for DMA operation + memcpy(i->dma_buf, (void*)t->buf, (size_t)(t->len_w)); + status = i2cMasterReceiveTimeout( + (I2CDriver*)p->reg_addr, + (i2caddr_t)((t->slave_addr)>>1), + (uint8_t*)i->dma_buf, (size_t)(t->len_r), + tmo); + memcpy((void*)t->buf, i->dma_buf, (size_t)(t->len_r)); +#else status = i2cMasterReceiveTimeout( (I2CDriver*)p->reg_addr, (i2caddr_t)((t->slave_addr)>>1), (uint8_t*)t->buf, (size_t)(t->len_r), tmo); +#endif } chSysLock(); @@ -151,10 +180,20 @@ static void handle_i2c_thd(struct i2c_periph *p) PRINT_CONFIG_VAR(I2C1_CLOCK_SPEED) static SEMAPHORE_DECL(i2c1_sem, 0); static I2CConfig i2cfg1 = I2C1_CFG_DEF; +#if defined STM32F7 +// We need a special buffer for DMA operations +static IN_DMA_SECTION(uint8_t i2c1_dma_buf[I2C_BUF_LEN]); +static struct i2c_init i2c1_init_s = { + .sem = &i2c1_sem, + .cfg = &i2cfg1, + .dma_buf = i2c1_dma_buf +}; +#else static struct i2c_init i2c1_init_s = { .sem = &i2c1_sem, .cfg = &i2cfg1 }; +#endif // Errors struct i2c_errors i2c1_errors; // Thread @@ -195,10 +234,20 @@ static void thd_i2c1(void *arg) PRINT_CONFIG_VAR(I2C2_CLOCK_SPEED) static SEMAPHORE_DECL(i2c2_sem, 0); static I2CConfig i2cfg2 = I2C2_CFG_DEF; +#if defined STM32F7 +// We need a special buffer for DMA operations +static IN_DMA_SECTION(uint8_t i2c2_dma_buf[I2C_BUF_LEN]); +static struct i2c_init i2c2_init_s = { + .sem = &i2c2_sem, + .cfg = &i2cfg2, + .dma_buf = i2c2_dma_buf +}; +#else static struct i2c_init i2c2_init_s = { .sem = &i2c2_sem, .cfg = &i2cfg2 }; +#endif // Errors struct i2c_errors i2c2_errors; // Thread @@ -240,10 +289,20 @@ static void thd_i2c2(void *arg) PRINT_CONFIG_VAR(I2C3_CLOCK_SPEED) static SEMAPHORE_DECL(i2c3_sem, 0); static I2CConfig i2cfg3 = I2C3_CFG_DEF; +#if defined STM32F7 +// We need a special buffer for DMA operations +static IN_DMA_SECTION(uint8_t i2c3_dma_buf[I2C_BUF_LEN]); +static struct i2c_init i2c3_init_s = { + .sem = &i2c3_sem, + .cfg = &i2cfg3, + .dma_buf = i2c3_dma_buf +}; +#else static struct i2c_init i2c3_init_s = { .sem = &i2c3_sem, .cfg = &i2cfg3 }; +#endif // Errors struct i2c_errors i2c3_errors; // Thread diff --git a/sw/airborne/arch/chibios/mcu_periph/pwm_input_arch.c b/sw/airborne/arch/chibios/mcu_periph/pwm_input_arch.c index 91854953cb1..cb9bbd970f7 100644 --- a/sw/airborne/arch/chibios/mcu_periph/pwm_input_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/pwm_input_arch.c @@ -34,12 +34,12 @@ #ifdef USE_PWM_INPUT1 static void input1_period_cb(ICUDriver *icup) { pwm_input_period_tics[PWM_INPUT1] = icuGetPeriodX(icup); - pwm_input_period_valid[PWM_INPUT1] = TRUE; + pwm_input_period_valid[PWM_INPUT1] = true; } static void input1_width_cb(ICUDriver *icup) { pwm_input_duty_tics[PWM_INPUT1] = icuGetWidthX(icup); - pwm_input_duty_valid[PWM_INPUT1] = TRUE; + pwm_input_duty_valid[PWM_INPUT1] = true; } static ICUConfig pwm_input1_cfg = { @@ -62,12 +62,12 @@ static ICUConfig pwm_input1_cfg = { #ifdef USE_PWM_INPUT2 static void input2_period_cb(ICUDriver *icup) { pwm_input_period_tics[PWM_INPUT2] = icuGetPeriodX(icup); - pwm_input_period_valid[PWM_INPUT2] = TRUE; + pwm_input_period_valid[PWM_INPUT2] = true; } static void input2_width_cb(ICUDriver *icup) { pwm_input_duty_tics[PWM_INPUT2] = icuGetWidthX(icup); - pwm_input_duty_valid[PWM_INPUT2] = TRUE; + pwm_input_duty_valid[PWM_INPUT2] = true; } static ICUConfig pwm_input2_cfg = { @@ -100,14 +100,14 @@ void pwm_input_init(void) #ifdef USE_PWM_INPUT1 icuStart(&PWM_INPUT1_ICU, &pwm_input1_cfg); - gpio_setup_pin_af(PWM_INPUT1_GPIO_PORT, PWM_INPUT1_GPIO_PIN, PWM_INPUT1_GPIO_AF); + gpio_setup_pin_af(PWM_INPUT1_GPIO_PORT, PWM_INPUT1_GPIO_PIN, PWM_INPUT1_GPIO_AF, false); icuStartCapture(&PWM_INPUT1_ICU); icuEnableNotifications(&PWM_INPUT1_ICU); #endif #ifdef USE_PWM_INPUT2 icuStart(&PWM_INPUT2_ICU, &pwm_input2_cfg); - gpio_setup_pin_af(PWM_INPUT2_GPIO_PORT, PWM_INPUT2_GPIO_PIN, PWM_INPUT2_GPIO_AF); + gpio_setup_pin_af(PWM_INPUT2_GPIO_PORT, PWM_INPUT2_GPIO_PIN, PWM_INPUT2_GPIO_AF, false); icuStartCapture(&PWM_INPUT2_ICU); icuEnableNotifications(&PWM_INPUT2_ICU); #endif diff --git a/sw/airborne/arch/chibios/mcu_periph/ram_arch.h b/sw/airborne/arch/chibios/mcu_periph/ram_arch.h new file mode 100644 index 00000000000..04f3d56500a --- /dev/null +++ b/sw/airborne/arch/chibios/mcu_periph/ram_arch.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2016 Gautier Hattenberger and Alexandre Bustico + * + * This file is part of paparazzi. + * + * paparazzi is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * paparazzi is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with paparazzi; see the file COPYING. If not, see + * . + */ + +/** + * @file arch/chibios/mcu_periph/ram_arch.h + * + * Specific RAM section for DMA usage on F7 + * + * F1 + * ram0: 64ko std + * + * F4 + * ram4: 64ko ccm, fast, no dma + * ram0: 128Ko std + * + * F7 + * ram0: std, fast, no dma + * ram3: dma + */ + +#ifndef RAM_ARCH_H +#define RAM_ARCH_H + +#if defined STM32F1 +#define STD_SECTION ".ram0" +#define FAST_SECTION ".ram0" +#define DMA_SECTION ".ram0" +#elif defined STM32F4 +#define STD_SECTION ".ram0" +#define FAST_SECTION ".ram4" +#define DMA_SECTION ".ram0" +#elif defined STM32F7 +#define STD_SECTION ".ram0" +#define FAST_SECTION ".ram0" +#define DMA_SECTION ".ram3" +#else +#error "section defined only for STM32F1, STM32F4 and STM32F7" +#endif + +#define IN_STD_SECTION(var) var __attribute__ ((section(STD_SECTION), aligned(8))) +#define IN_FAST_SECTION(var) var __attribute__ ((section(FAST_SECTION), aligned(8))) +#define IN_DMA_SECTION(var) var __attribute__ ((section(DMA_SECTION), aligned(8))) + +#endif + diff --git a/sw/airborne/arch/chibios/mcu_periph/sdio_arch.c b/sw/airborne/arch/chibios/mcu_periph/sdio_arch.c index 8682e4f141e..46de50207f1 100644 --- a/sw/airborne/arch/chibios/mcu_periph/sdio_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/sdio_arch.c @@ -38,6 +38,8 @@ #include #include "mcu_periph/sdio.h" #include +#include "mcu_periph/gpio.h" +#include BOARD_CONFIG static enum {STOP, CONNECT} cnxState = STOP; @@ -56,17 +58,17 @@ bool sdio_connect(void) /* * Initializes the SDIO drivers. * - * FIXME hardcoded for Apogee board ? + * FIXME This could be hardcoded in board file ? */ - const uint32_t mode = PAL_MODE_ALTERNATE(12) | PAL_STM32_OTYPE_PUSHPULL | + const uint32_t mode = PAL_MODE_ALTERNATE(SDIO_AF) | PAL_STM32_OTYPE_PUSHPULL | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING | PAL_STM32_MODE_ALTERNATE; - palSetPadMode (GPIOC, GPIOC_SDIO_D0, mode | PAL_STM32_PUPDR_PULLUP); - palSetPadMode (GPIOC, GPIOC_SDIO_D1, mode | PAL_STM32_PUPDR_PULLUP); - palSetPadMode (GPIOC, GPIOC_SDIO_D2, mode | PAL_STM32_PUPDR_PULLUP); - palSetPadMode (GPIOC, GPIOC_SDIO_D3, mode | PAL_STM32_PUPDR_PULLUP); - palSetPadMode (GPIOC, GPIOC_SDIO_CK, mode); - palSetPadMode (GPIOD, GPIOD_SDIO_CMD, mode | PAL_STM32_PUPDR_PULLUP); + palSetPadMode (SDIO_D0_PORT, SDIO_D0_PIN, mode | PAL_STM32_PUPDR_PULLUP); + palSetPadMode (SDIO_D1_PORT, SDIO_D1_PIN, mode | PAL_STM32_PUPDR_PULLUP); + palSetPadMode (SDIO_D2_PORT, SDIO_D2_PIN, mode | PAL_STM32_PUPDR_PULLUP); + palSetPadMode (SDIO_D3_PORT, SDIO_D3_PIN, mode | PAL_STM32_PUPDR_PULLUP); + palSetPadMode (SDIO_CK_PORT, SDIO_CK_PIN, mode); + palSetPadMode (SDIO_CMD_PORT, SDIO_CMD_PIN, mode | PAL_STM32_PUPDR_PULLUP); // palSetPadMode (GPIOD, GPIOD_SDIO_CMD, mode); chThdSleepMilliseconds(100); diff --git a/sw/airborne/arch/chibios/mcu_periph/spi_arch.c b/sw/airborne/arch/chibios/mcu_periph/spi_arch.c index 6e6e7b78761..94280523006 100644 --- a/sw/airborne/arch/chibios/mcu_periph/spi_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/spi_arch.c @@ -31,6 +31,9 @@ #include "mcu_periph/spi.h" #include "mcu_periph/gpio.h" +#include +#include "mcu_periph/ram_arch.h" + #if SPI_SLAVE #error "ChibiOS operates only in SPI_MASTER mode" #endif @@ -39,6 +42,16 @@ #error "ChibiOS architectures don't have SPI0" #endif +// private SPI init structure +struct spi_init { + semaphore_t *sem; +#ifdef STM32F7 + uint8_t *dma_buf_out; + uint8_t *dma_buf_in; +#endif +}; +#define SPI_DMA_BUF_LEN 512 // it has to be big enough + /** * Resolve slave port * @@ -140,15 +153,15 @@ static inline uint16_t spi_resolve_slave_pin(uint8_t slave) * SPIx_CR1 register. * * This function is currently architecture dependent (for STM32F1xx - * and STM32F4xx only) + * STM32F4xx and STM32F7xx only) * TODO: extend for other architectures too * * @param[in] t pointer to a @p spi_transaction struct */ -static inline uint16_t spi_resolve_CR1(struct spi_transaction *t) +static inline uint16_t spi_resolve_CR1(struct spi_transaction *t __attribute__((unused))) { uint16_t CR1 = 0; -#if defined(__STM32F10x_H) || defined(__STM32F105xC_H) || defined (__STM32F107xC_H) || defined(__STM32F4xx_H) +#if defined(STM32F1) || defined(STM32F4) || defined(STM32F7) if (t->dss == SPIDss16bit) { CR1 |= SPI_CR1_DFF; } @@ -189,10 +202,36 @@ static inline uint16_t spi_resolve_CR1(struct spi_transaction *t) default: break; } -#endif /* __STM32F10x_H || __STM32F105xC_H || __STM32F107xC_H || STM32F4xx_H */ +#endif /* STM32F1 || STM32F4 || STM32F7 */ return CR1; } +/** + * Resolve CR2 + * + * Given the transaction settings, returns the right configuration of + * SPIx_CR2 register. + * + * This function is currently architecture dependent (for STM32F1xx + * STM32F4xx and STM32F7xx only) + * TODO: extend for other architectures too + * + * @param[in] t pointer to a @p spi_transaction struct + */ +static inline uint16_t spi_resolve_CR2(struct spi_transaction *t __attribute__((unused))) +{ + uint16_t CR2 = 0; +#if defined(STM32F7) + if (t->dss == SPIDss16bit) { + CR2 |= SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2 | SPI_CR2_DS_3; + } + else { + CR2 |= SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2; + } +#endif /* STM32F7 */ + return CR2; +} + /** * main thread function * @@ -200,8 +239,10 @@ static inline uint16_t spi_resolve_CR1(struct spi_transaction *t) */ static void handle_spi_thd(struct spi_periph *p) { + struct spi_init *i = (struct spi_init *) p->init_struct; + // wait for a transaction to be pushed in the queue - chSemWait ((semaphore_t *) p->init_struct); + chSemWait (i->sem); if ((p->trans_insert_idx == p->trans_extract_idx) || p->suspend) { p->status = SPIIdle; @@ -218,7 +259,8 @@ static void handle_spi_thd(struct spi_periph *p) NULL, // no callback spi_resolve_slave_port(t->slave_idx), spi_resolve_slave_pin(t->slave_idx), - spi_resolve_CR1(t) + spi_resolve_CR1(t), + spi_resolve_CR2(t) }; // find max transaction length @@ -240,7 +282,14 @@ static void handle_spi_thd(struct spi_periph *p) } // Start synchronous data transfer +#if defined STM32F7 + // we do stupid mem copy because F7 needs a special RAM for DMA operation + memcpy(i->dma_buf_out, (void*)t->output_buf, (size_t)t->output_length); + spiExchange((SPIDriver *)p->reg_addr, t_length, i->dma_buf_out, i->dma_buf_in); + memcpy((void*)t->input_buf, i->dma_buf_in, (size_t)t->input_length); +#else spiExchange((SPIDriver *)p->reg_addr, t_length, (uint8_t*)t->output_buf, (uint8_t*)t->input_buf); +#endif // Unselect the slave spiUnselect((SPIDriver *)p->reg_addr); @@ -273,6 +322,21 @@ static void handle_spi_thd(struct spi_periph *p) #if USE_SPI1 static SEMAPHORE_DECL(spi1_sem, 0); +#if defined STM32F7 +// We need a special buffer for DMA operations +static IN_DMA_SECTION(uint8_t spi1_dma_buf_out[SPI_DMA_BUF_LEN]); +static IN_DMA_SECTION(uint8_t spi1_dma_buf_in[SPI_DMA_BUF_LEN]); +static struct spi_init spi1_init_s = { + .sem = &spi1_sem, + .dma_buf_out = spi1_dma_buf_out, + .dma_buf_in = spi1_dma_buf_in +}; +#else +static struct spi_init spi1_init_s = { + .sem = &spi1_sem, +}; +#endif + static __attribute__((noreturn)) void thd_spi1(void *arg) { (void) arg; @@ -288,7 +352,7 @@ static THD_WORKING_AREA(wa_thd_spi1, 1024); void spi1_arch_init(void) { spi1.reg_addr = &SPID1; - spi1.init_struct = &spi1_sem; + spi1.init_struct = &spi1_init_s; // Create thread chThdCreateStatic(wa_thd_spi1, sizeof(wa_thd_spi1), NORMALPRIO+1, thd_spi1, NULL); @@ -297,6 +361,21 @@ void spi1_arch_init(void) #if USE_SPI2 static SEMAPHORE_DECL(spi2_sem, 0); +#if defined STM32F7 +// We need a special buffer for DMA operations +static IN_DMA_SECTION(uint8_t spi2_dma_buf_out[SPI_DMA_BUF_LEN]); +static IN_DMA_SECTION(uint8_t spi2_dma_buf_in[SPI_DMA_BUF_LEN]); +static struct spi_init spi2_init_s = { + .sem = &spi2_sem, + .dma_buf_out = spi2_dma_buf_out, + .dma_buf_in = spi2_dma_buf_in +}; +#else +static struct spi_init spi2_init_s = { + .sem = &spi2_sem, +}; +#endif + static __attribute__((noreturn)) void thd_spi2(void *arg) { (void) arg; @@ -312,7 +391,7 @@ static THD_WORKING_AREA(wa_thd_spi2, 1024); void spi2_arch_init(void) { spi2.reg_addr = &SPID2; - spi2.init_struct = &spi2_sem; + spi2.init_struct = &spi2_init_s; // Create thread chThdCreateStatic(wa_thd_spi2, sizeof(wa_thd_spi2), NORMALPRIO+1, thd_spi2, NULL); @@ -321,6 +400,21 @@ void spi2_arch_init(void) #if USE_SPI3 static SEMAPHORE_DECL(spi3_sem, 0); +#if defined STM32F7 +// We need a special buffer for DMA operations +static IN_DMA_SECTION(uint8_t spi3_dma_buf_out[SPI_DMA_BUF_LEN]); +static IN_DMA_SECTION(uint8_t spi3_dma_buf_in[SPI_DMA_BUF_LEN]); +static struct spi_init spi3_init_s = { + .sem = &spi3_sem, + .dma_buf_out = spi3_dma_buf_out, + .dma_buf_in = spi3_dma_buf_in +}; +#else +static struct spi_init spi3_init_s = { + .sem = &spi3_sem, +}; +#endif + static __attribute__((noreturn)) void thd_spi3(void *arg) { (void) arg; @@ -336,7 +430,7 @@ static THD_WORKING_AREA(wa_thd_spi3, 1024); void spi3_arch_init(void) { spi3.reg_addr = &SPID3; - spi3.init_struct = &spi3_sem; + spi3.init_struct = &spi3_init_s; // Create thread chThdCreateStatic(wa_thd_spi3, sizeof(wa_thd_spi3), NORMALPRIO+1, thd_spi3, NULL); @@ -383,7 +477,7 @@ bool spi_submit(struct spi_periph *p, struct spi_transaction *t) p->trans_insert_idx = idx; chSysUnlock(); - chSemSignal ((semaphore_t *) p->init_struct); + chSemSignal (((struct spi_init *)p->init_struct)->sem); // transaction submitted return TRUE; } diff --git a/sw/airborne/arch/chibios/mcu_periph/uart_arch.c b/sw/airborne/arch/chibios/mcu_periph/uart_arch.c index 45de78daf79..fc5d52d4f2d 100644 --- a/sw/airborne/arch/chibios/mcu_periph/uart_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/uart_arch.c @@ -38,6 +38,7 @@ #include #include #include "mcu_periph/gpio.h" +#include BOARD_CONFIG struct SerialInit { SerialConfig *conf; @@ -195,11 +196,20 @@ void uart1_init(void) #define USE_UART2_RX TRUE #endif +/* by default disable HW flow control */ +#ifndef UART2_HW_FLOW_CONTROL +#define UART2_HW_FLOW_CONTROL FALSE +#endif + static SerialConfig usart2_config = { UART2_BAUD, /* BITRATE */ 0, /* USART CR1 */ USART_CR2_STOP1_BITS, /* USART CR2 */ +#if UART2_HW_FLOW_CONTROL + USART_CR3_CTSE | USART_CR3_RTSE +#else 0 /* USART CR3 */ +#endif }; static struct SerialInit uart2_init_struct = { NULL, NULL, NULL, NULL, NULL }; @@ -852,6 +862,14 @@ void uart_periph_set_baudrate(struct uart_periph *p, uint32_t baud ) void uart_periph_set_mode(struct uart_periph *p __attribute__((unused)), bool tx_enabled __attribute__((unused)), bool rx_enabled __attribute__((unused)), bool hw_flow_control __attribute__((unused))) {} +#if defined STM32F7 +#define __USART_CR1_M USART_CR1_M_0 +#elif defined STM32F1 || defined STM32F4 +#define __USART_CR1_M USART_CR1_M +#else +#error unsupported board +#endif + /** * Set parity and stop bits */ @@ -866,21 +884,21 @@ void uart_periph_set_bits_stop_parity(struct uart_periph *p, conf->cr1 |= USART_CR1_PCE; // set parity control bit conf->cr1 &= ~USART_CR1_PS; // clear parity selection bit if (bits == UBITS_7) { - conf->cr1 &= ~USART_CR1_M; // clear word length bit + conf->cr1 &= ~__USART_CR1_M; // clear word length bit } else { // 8 data bits by default - conf->cr1 |= USART_CR1_M; // set word length bit + conf->cr1 |= __USART_CR1_M; // set word length bit } } else if (parity == UPARITY_ODD) { conf->cr1 |= USART_CR1_PCE; // set parity control bit conf->cr1 |= USART_CR1_PS; // set parity selection bit if (bits == UBITS_7) { - conf->cr1 &= ~USART_CR1_M; // clear word length bit + conf->cr1 &= ~__USART_CR1_M; // clear word length bit } else { // 8 data bits by default - conf->cr1 |= USART_CR1_M; // set word length bit + conf->cr1 |= __USART_CR1_M; // set word length bit } } else { // 8 data bist, NO_PARITY by default conf->cr1 &= ~USART_CR1_PCE; // clear parity control bit - conf->cr1 &= ~USART_CR1_M; // clear word length bit + conf->cr1 &= ~__USART_CR1_M; // clear word length bit } /* Configure USART stop bits */ conf->cr2 &= ~USART_CR2_STOP; // clear stop bits @@ -894,6 +912,29 @@ void uart_periph_set_bits_stop_parity(struct uart_periph *p, sdStart((SerialDriver*)(p->reg_addr), conf); } +#ifdef STM32F7 +/** + * Invert data logic + */ +void uart_periph_invert_data_logic(struct uart_periph *p, bool invert_rx, bool invert_tx) +{ + struct SerialInit *init_struct = (struct SerialInit*)(p->init_struct); + SerialConfig *conf = init_struct->conf; + if (invert_rx) { + conf->cr2 |= USART_CR2_RXINV; // set rxinv bit + } else { + conf->cr2 &= ~USART_CR2_RXINV; // clear rxinv bit + } + if (invert_tx) { + conf->cr2 |= USART_CR2_TXINV; // set txinv bit + } else { + conf->cr2 &= ~USART_CR2_TXINV; // clear txinv bit + } + sdStop((SerialDriver*)(p->reg_addr)); + sdStart((SerialDriver*)(p->reg_addr), conf); +} +#endif + // Check free space and set a positive value for fd if valid // and lock driver with mutex bool uart_check_free_space(struct uart_periph *p, long *fd, uint16_t len) diff --git a/sw/airborne/arch/chibios/modules/core/rtos_mon_arch.c b/sw/airborne/arch/chibios/modules/core/rtos_mon_arch.c index 78894bac171..4122cd37a00 100644 --- a/sw/airborne/arch/chibios/modules/core/rtos_mon_arch.c +++ b/sw/airborne/arch/chibios/modules/core/rtos_mon_arch.c @@ -59,8 +59,8 @@ void rtos_mon_periodic_arch(void) tp = chRegFirstThread(); do { // add beginning of thread name to buffer - for (i = 0; i < RTOS_MON_NAME_LEN-1 && tp->p_name[i] != '\0'; i++) { - rtos_mon.thread_names[rtos_mon.thread_name_idx++] = tp->p_name[i]; + for (i = 0; i < RTOS_MON_NAME_LEN-1 && tp->name[i] != '\0'; i++) { + rtos_mon.thread_names[rtos_mon.thread_name_idx++] = tp->name[i]; } rtos_mon.thread_names[rtos_mon.thread_name_idx++] = ';'; @@ -68,12 +68,12 @@ void rtos_mon_periodic_arch(void) rtos_mon.thread_free_stack[i] = get_stack_free(tp); // store time spend in thread - thread_p_time[rtos_mon.thread_counter] = tp->p_time; - sum += (float)(tp->p_time); + thread_p_time[rtos_mon.thread_counter] = tp->time; + sum += (float)(tp->time); // if current thread is 'idle' thread, store its value separately if (tp == chSysGetIdleThreadX()) { - idle_counter = (uint32_t)tp->p_time; + idle_counter = (uint32_t)tp->time; } // get next thread tp = chRegNextThread(tp); diff --git a/sw/airborne/arch/chibios/subsystems/actuators/actuators_pwm_arch.c b/sw/airborne/arch/chibios/subsystems/actuators/actuators_pwm_arch.c index 743ca5ee7a5..911be31d70c 100644 --- a/sw/airborne/arch/chibios/subsystems/actuators/actuators_pwm_arch.c +++ b/sw/airborne/arch/chibios/subsystems/actuators/actuators_pwm_arch.c @@ -89,40 +89,40 @@ void actuators_pwm_arch_init(void) * Configure GPIO *----------------*/ #ifdef PWM_SERVO_0 - gpio_setup_pin_af(PWM_SERVO_0_GPIO, PWM_SERVO_0_PIN, PWM_SERVO_0_AF); + gpio_setup_pin_af(PWM_SERVO_0_GPIO, PWM_SERVO_0_PIN, PWM_SERVO_0_AF, true); #endif #ifdef PWM_SERVO_1 - gpio_setup_pin_af(PWM_SERVO_1_GPIO, PWM_SERVO_1_PIN, PWM_SERVO_1_AF); + gpio_setup_pin_af(PWM_SERVO_1_GPIO, PWM_SERVO_1_PIN, PWM_SERVO_1_AF, true); #endif #ifdef PWM_SERVO_2 - gpio_setup_pin_af(PWM_SERVO_2_GPIO, PWM_SERVO_2_PIN, PWM_SERVO_2_AF); + gpio_setup_pin_af(PWM_SERVO_2_GPIO, PWM_SERVO_2_PIN, PWM_SERVO_2_AF, true); #endif #ifdef PWM_SERVO_3 - gpio_setup_pin_af(PWM_SERVO_3_GPIO, PWM_SERVO_3_PIN, PWM_SERVO_3_AF); + gpio_setup_pin_af(PWM_SERVO_3_GPIO, PWM_SERVO_3_PIN, PWM_SERVO_3_AF, true); #endif #ifdef PWM_SERVO_4 - gpio_setup_pin_af(PWM_SERVO_4_GPIO, PWM_SERVO_4_PIN, PWM_SERVO_4_AF); + gpio_setup_pin_af(PWM_SERVO_4_GPIO, PWM_SERVO_4_PIN, PWM_SERVO_4_AF, true); #endif #ifdef PWM_SERVO_5 - gpio_setup_pin_af(PWM_SERVO_5_GPIO, PWM_SERVO_5_PIN, PWM_SERVO_5_AF); + gpio_setup_pin_af(PWM_SERVO_5_GPIO, PWM_SERVO_5_PIN, PWM_SERVO_5_AF, true); #endif #ifdef PWM_SERVO_6 - gpio_setup_pin_af(PWM_SERVO_6_GPIO, PWM_SERVO_6_PIN, PWM_SERVO_6_AF); + gpio_setup_pin_af(PWM_SERVO_6_GPIO, PWM_SERVO_6_PIN, PWM_SERVO_6_AF, true); #endif #ifdef PWM_SERVO_7 - gpio_setup_pin_af(PWM_SERVO_7_GPIO, PWM_SERVO_7_PIN, PWM_SERVO_7_AF); + gpio_setup_pin_af(PWM_SERVO_7_GPIO, PWM_SERVO_7_PIN, PWM_SERVO_7_AF, true); #endif #ifdef PWM_SERVO_8 - gpio_setup_pin_af(PWM_SERVO_8_GPIO, PWM_SERVO_8_PIN, PWM_SERVO_8_AF); + gpio_setup_pin_af(PWM_SERVO_8_GPIO, PWM_SERVO_8_PIN, PWM_SERVO_8_AF, true); #endif #ifdef PWM_SERVO_9 - gpio_setup_pin_af(PWM_SERVO_9_GPIO, PWM_SERVO_9_PIN, PWM_SERVO_9_AF); + gpio_setup_pin_af(PWM_SERVO_9_GPIO, PWM_SERVO_9_PIN, PWM_SERVO_9_AF, true); #endif #ifdef PWM_SERVO_10 - gpio_setup_pin_af(PWM_SERVO_10_GPIO, PWM_SERVO_10_PIN, PWM_SERVO_10_AF); + gpio_setup_pin_af(PWM_SERVO_10_GPIO, PWM_SERVO_10_PIN, PWM_SERVO_10_AF, true); #endif #ifdef PWM_SERVO_11 - gpio_setup_pin_af(PWM_SERVO_11_GPIO, PWM_SERVO_11_PIN, PWM_SERVO_11_AF); + gpio_setup_pin_af(PWM_SERVO_11_GPIO, PWM_SERVO_11_PIN, PWM_SERVO_11_AF, true); #endif /*--------------- diff --git a/sw/airborne/arch/stm32/mcu_periph/gpio_arch.h b/sw/airborne/arch/stm32/mcu_periph/gpio_arch.h index ee8e7b48f25..43957b87d7d 100644 --- a/sw/airborne/arch/stm32/mcu_periph/gpio_arch.h +++ b/sw/airborne/arch/stm32/mcu_periph/gpio_arch.h @@ -33,6 +33,11 @@ #include +/** + * Abstract gpio port type for hardware independent part + */ +typedef uint32_t gpio_port_t; + /** * Setup one or more pins of the given GPIO port as outputs. * @param[in] port diff --git a/sw/airborne/boards/apogee/chibios/v1.0/board.h b/sw/airborne/boards/apogee/chibios/v1.0/board.h index 15f4117e409..9585626f53b 100644 --- a/sw/airborne/boards/apogee/chibios/v1.0/board.h +++ b/sw/airborne/boards/apogee/chibios/v1.0/board.h @@ -1019,6 +1019,31 @@ #define ActuatorsDefaultInit() ActuatorsPwmInit() #define ActuatorsDefaultCommit() ActuatorsPwmCommit() + +/** + * SDIO + */ +#define SDIO_D0_PORT GPIOC +#define SDIO_D0_PIN GPIOC_SDIO_D0 +#define SDIO_D1_PORT GPIOC +#define SDIO_D1_PIN GPIOC_SDIO_D1 +#define SDIO_D2_PORT GPIOC +#define SDIO_D2_PIN GPIOC_SDIO_D2 +#define SDIO_D3_PORT GPIOC +#define SDIO_D3_PIN GPIOC_SDIO_D3 +#define SDIO_CK_PORT GPIOC +#define SDIO_CK_PIN GPIOC_SDIO_CK +#define SDIO_CMD_PORT GPIOD +#define SDIO_CMD_PIN GPIOD_SDIO_CMD +#define SDIO_AF 12 +// bat monitoring for file closing +#define SDLOG_BAT_ADC ADCD1 +#define SDLOG_BAT_CHAN AD1_4_CHANNEL +// usb led status +#define SDLOG_USB_LED 4 +#define SDLOG_USB_VBUS_PORT GPIOA +#define SDLOG_USB_VBUS_PIN GPIO9 + #if !defined(_FROM_ASM_) #ifdef __cplusplus extern "C" { diff --git a/sw/airborne/boards/chimera/baro_board.h b/sw/airborne/boards/chimera/baro_board.h new file mode 100644 index 00000000000..57d14f0c9d5 --- /dev/null +++ b/sw/airborne/boards/chimera/baro_board.h @@ -0,0 +1,18 @@ + +/* + * board specific functions for the chimera board + * + */ + +#ifndef BOARDS_CHIMERA_BARO_H +#define BOARDS_CHIMERA_BARO_H + +// only for printing the baro type during compilation +#ifndef BARO_BOARD +#define BARO_BOARD BARO_MS5611_I2C +#endif + +extern void baro_event(void); +#define BaroEvent baro_event + +#endif /* BOARDS_CHIMERA_BARO_H */ diff --git a/sw/airborne/boards/chimera/chibios/v1.0/board.c b/sw/airborne/boards/chimera/chibios/v1.0/board.c new file mode 100644 index 00000000000..b35b4271f26 --- /dev/null +++ b/sw/airborne/boards/chimera/chibios/v1.0/board.c @@ -0,0 +1,132 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + return !palReadLine (LINE_SD_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} + diff --git a/sw/airborne/boards/chimera/chibios/v1.0/board.h b/sw/airborne/boards/chimera/chibios/v1.0/board.h new file mode 100644 index 00000000000..f8839cefac7 --- /dev/null +++ b/sw/airborne/boards/chimera/chibios/v1.0/board.h @@ -0,0 +1,1544 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#pragma once + +/* + * Board identifier. + */ +#define BOARD_CHIMERA +#define BOARD_NAME "Chimera Autopilot" + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 16000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F767xx + +/* + * IO pins assignments. + */ +#define AUX3 0U +#define RC1_UART4_RX 1U +#define AUX2 2U +#define AUX1 3U +#define VBAT_MEAS 4U +#define AUX0 5U +#define SRV0_TIM3_CH1 6U +#define SRV1_TIM3_CH2 7U +#define XB_ASSO 8U +#define USB_VBUS 9U +#define SD_DETECT 10U +#define OTG_FS_DM 11U +#define OTG_FS_DP 12U +#define SWDIO 13U +#define SWCLK 14U +#define SPI1_CS 15U + +#define SRV2_TIM3_CH3 0U +#define SRV3_TIM3_CH4 1U +#define RC1 2U +#define SPI1_SCK 3U +#define SPI1_MISO 4U +#define SPI1_MOSI 5U +#define USART1_TX 6U +#define USART1_RX 7U +#define I2C1_SCL 8U +#define I2C1_SDA 9U +#define I2C2_SCL 10U +#define I2C2_SDA 11U +#define LED1 12U +#define LED2 13U +#define DIS_C 14U +#define DIS_DP 15U + +#define PC00 0U +#define PC01 1U +#define AUX5 2U +#define AUX4 3U +#define EN_COMP 4U +#define PC05 5U +#define AUX6 6U +#define AUX7 7U +#define SDMMC1_D0 8U +#define SDMMC1_D1 9U +#define SDMMC1_D2 10U +#define SDMMC1_D3 11U +#define SDMMC1_CK 12U +#define PC13 13U +#define OSC32_IN 14U +#define OSC32_OUT 15U + +#define CAN1_RX 0U +#define CAN1_TX 1U +#define SDMMC1_CMD 2U +#define USART2_CTS 3U +#define USART2_RTS 4U +#define USART2_TX 5U +#define USART2_RX 6U +#define IMU_INT 7U +#define USART3_TX 8U +#define USART3_RX 9U +#define LED3 10U +#define LED4 11U +#define SRV4_TIM4_CH1 12U +#define SRV5_TIM4_CH2 13U +#define SRV6_TIM4_CH3 14U +#define SRV7_TIM4_CH4 15U + +#define UART8_RX 0U +#define UART8_TX 1U +#define DIS_G 2U +#define DIS_F 3U +#define DIS_A 4U +#define DIS_B 5U +#define APSW 6U +#define RC2_UART7_RX 7U +#define DIS_E 8U +#define DIS_D 9U +#define PE10 10U +#define PE11 11U +#define PE12 12U +#define PE13 13U +#define PE14 14U +#define XB_RST 15U + +#define PF00 0U +#define PF01 1U +#define PF02 2U +#define PF03 3U +#define PF04 4U +#define PF05 5U +#define PF06 6U +#define PF07 7U +#define PF08 8U +#define PF09 9U +#define PF10 10U +#define PF11 11U +#define PF12 12U +#define PF13 13U +#define PF14 14U +#define PF15 15U + +#define PG00 0U +#define PG01 1U +#define PG02 2U +#define PG03 3U +#define PG04 4U +#define PG05 5U +#define PG06 6U +#define PG07 7U +#define PG08 8U +#define PG09 9U +#define PG10 10U +#define PG11 11U +#define PG12 12U +#define PG13 13U +#define PG14 14U +#define PG15 15U + +#define OSC_IN 0U +#define OSC_OUT 1U +#define PH02 2U +#define PH03 3U +#define PH04 4U +#define PH05 5U +#define PH06 6U +#define PH07 7U +#define PH08 8U +#define PH09 9U +#define PH10 10U +#define PH11 11U +#define PH12 12U +#define PH13 13U +#define PH14 14U +#define PH15 15U + +#define PI00 0U +#define PI01 1U +#define PI02 2U +#define PI03 3U +#define PI04 4U +#define PI05 5U +#define PI06 6U +#define PI07 7U +#define PI08 8U +#define PI09 9U +#define PI10 10U +#define PI11 11U +#define PI12 12U +#define PI13 13U +#define PI14 14U +#define PI15 15U + +#define PJ00 0U +#define PJ01 1U +#define PJ02 2U +#define PJ03 3U +#define PJ04 4U +#define PJ05 5U +#define PJ06 6U +#define PJ07 7U +#define PJ08 8U +#define PJ09 9U +#define PJ10 10U +#define PJ11 11U +#define PJ12 12U +#define PJ13 13U +#define PJ14 14U +#define PJ15 15U + +#define PK00 0U +#define PK01 1U +#define PK02 2U +#define PK03 3U +#define PK04 4U +#define PK05 5U +#define PK06 6U +#define PK07 7U +#define PK08 8U +#define PK09 9U +#define PK10 10U +#define PK11 11U +#define PK12 12U +#define PK13 13U +#define PK14 14U +#define PK15 15U + +/* + * IO lines assignments. + */ +#define LINE_AUX3 PAL_LINE(GPIOA, 0U) +#define LINE_RC1_UART4_RX PAL_LINE(GPIOA, 1U) +#define LINE_AUX2 PAL_LINE(GPIOA, 2U) +#define LINE_AUX1 PAL_LINE(GPIOA, 3U) +#define LINE_VBAT_MEAS PAL_LINE(GPIOA, 4U) +#define LINE_AUX0 PAL_LINE(GPIOA, 5U) +#define LINE_SRV0_TIM3_CH1 PAL_LINE(GPIOA, 6U) +#define LINE_SRV1_TIM3_CH2 PAL_LINE(GPIOA, 7U) +#define LINE_XB_ASSO PAL_LINE(GPIOA, 8U) +#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U) +#define LINE_SD_DETECT PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_SPI1_CS PAL_LINE(GPIOA, 15U) + +#define LINE_SRV2_TIM3_CH3 PAL_LINE(GPIOB, 0U) +#define LINE_SRV3_TIM3_CH4 PAL_LINE(GPIOB, 1U) +#define LINE_RC1 PAL_LINE(GPIOB, 2U) +#define LINE_SPI1_SCK PAL_LINE(GPIOB, 3U) +#define LINE_SPI1_MISO PAL_LINE(GPIOB, 4U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOB, 5U) +#define LINE_USART1_TX PAL_LINE(GPIOB, 6U) +#define LINE_USART1_RX PAL_LINE(GPIOB, 7U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) +#define LINE_I2C2_SCL PAL_LINE(GPIOB, 10U) +#define LINE_I2C2_SDA PAL_LINE(GPIOB, 11U) +#define LINE_LED1 PAL_LINE(GPIOB, 12U) +#define LINE_LED2 PAL_LINE(GPIOB, 13U) +#define LINE_DIS_C PAL_LINE(GPIOB, 14U) +#define LINE_DIS_DP PAL_LINE(GPIOB, 15U) + +#define LINE_AUX5 PAL_LINE(GPIOC, 2U) +#define LINE_AUX4 PAL_LINE(GPIOC, 3U) +#define LINE_EN_COMP PAL_LINE(GPIOC, 4U) +#define LINE_AUX6 PAL_LINE(GPIOC, 6U) +#define LINE_AUX7 PAL_LINE(GPIOC, 7U) +#define LINE_SDMMC1_D0 PAL_LINE(GPIOC, 8U) +#define LINE_SDMMC1_D1 PAL_LINE(GPIOC, 9U) +#define LINE_SDMMC1_D2 PAL_LINE(GPIOC, 10U) +#define LINE_SDMMC1_D3 PAL_LINE(GPIOC, 11U) +#define LINE_SDMMC1_CK PAL_LINE(GPIOC, 12U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) + +#define LINE_CAN1_RX PAL_LINE(GPIOD, 0U) +#define LINE_CAN1_TX PAL_LINE(GPIOD, 1U) +#define LINE_SDMMC1_CMD PAL_LINE(GPIOD, 2U) +#define LINE_USART2_CTS PAL_LINE(GPIOD, 3U) +#define LINE_USART2_RTS PAL_LINE(GPIOD, 4U) +#define LINE_USART2_TX PAL_LINE(GPIOD, 5U) +#define LINE_USART2_RX PAL_LINE(GPIOD, 6U) +#define LINE_IMU_INT PAL_LINE(GPIOD, 7U) +#define LINE_USART3_TX PAL_LINE(GPIOD, 8U) +#define LINE_USART3_RX PAL_LINE(GPIOD, 9U) +#define LINE_LED3 PAL_LINE(GPIOD, 10U) +#define LINE_LED4 PAL_LINE(GPIOD, 11U) +#define LINE_SRV4_TIM4_CH1 PAL_LINE(GPIOD, 12U) +#define LINE_SRV5_TIM4_CH2 PAL_LINE(GPIOD, 13U) +#define LINE_SRV6_TIM4_CH3 PAL_LINE(GPIOD, 14U) +#define LINE_SRV7_TIM4_CH4 PAL_LINE(GPIOD, 15U) + +#define LINE_UART8_RX PAL_LINE(GPIOE, 0U) +#define LINE_UART8_TX PAL_LINE(GPIOE, 1U) +#define LINE_DIS_G PAL_LINE(GPIOE, 2U) +#define LINE_DIS_F PAL_LINE(GPIOE, 3U) +#define LINE_DIS_A PAL_LINE(GPIOE, 4U) +#define LINE_DIS_B PAL_LINE(GPIOE, 5U) +#define LINE_APSW PAL_LINE(GPIOE, 6U) +#define LINE_RC2_UART7_RX PAL_LINE(GPIOE, 7U) +#define LINE_DIS_E PAL_LINE(GPIOE, 8U) +#define LINE_DIS_D PAL_LINE(GPIOE, 9U) +#define LINE_XB_RST PAL_LINE(GPIOE, 15U) + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LEVEL_LOW(n) (0U << (n)) +#define PIN_ODR_LEVEL_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_SPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_SPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_SPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_SPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(AUX3) | \ + PIN_MODE_INPUT(RC1_UART4_RX) | \ + PIN_MODE_INPUT(AUX2) | \ + PIN_MODE_INPUT(AUX1) | \ + PIN_MODE_ANALOG(VBAT_MEAS) | \ + PIN_MODE_INPUT(AUX0) | \ + PIN_MODE_INPUT(SRV0_TIM3_CH1) | \ + PIN_MODE_INPUT(SRV1_TIM3_CH2) | \ + PIN_MODE_INPUT(XB_ASSO) | \ + PIN_MODE_INPUT(USB_VBUS) | \ + PIN_MODE_INPUT(SD_DETECT) | \ + PIN_MODE_ALTERNATE(OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(SWDIO) | \ + PIN_MODE_ALTERNATE(SWCLK) | \ + PIN_MODE_OUTPUT(SPI1_CS)) + +#define VAL_GPIOA_OTYPER (PIN_OTYPE_OPENDRAIN(AUX3) | \ + PIN_OTYPE_OPENDRAIN(RC1_UART4_RX) | \ + PIN_OTYPE_OPENDRAIN(AUX2) | \ + PIN_OTYPE_OPENDRAIN(AUX1) | \ + PIN_OTYPE_PUSHPULL(VBAT_MEAS) | \ + PIN_OTYPE_OPENDRAIN(AUX0) | \ + PIN_OTYPE_OPENDRAIN(SRV0_TIM3_CH1) | \ + PIN_OTYPE_OPENDRAIN(SRV1_TIM3_CH2) | \ + PIN_OTYPE_OPENDRAIN(XB_ASSO) | \ + PIN_OTYPE_OPENDRAIN(USB_VBUS) | \ + PIN_OTYPE_OPENDRAIN(SD_DETECT) | \ + PIN_OTYPE_PUSHPULL(OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(SWDIO) | \ + PIN_OTYPE_PUSHPULL(SWCLK) | \ + PIN_OTYPE_PUSHPULL(SPI1_CS)) + +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(AUX3) | \ + PIN_OSPEED_SPEED_VERYLOW(RC1_UART4_RX) | \ + PIN_OSPEED_SPEED_VERYLOW(AUX2) | \ + PIN_OSPEED_SPEED_VERYLOW(AUX1) | \ + PIN_OSPEED_SPEED_VERYLOW(VBAT_MEAS) | \ + PIN_OSPEED_SPEED_VERYLOW(AUX0) | \ + PIN_OSPEED_SPEED_VERYLOW(SRV0_TIM3_CH1) | \ + PIN_OSPEED_SPEED_VERYLOW(SRV1_TIM3_CH2) | \ + PIN_OSPEED_SPEED_VERYLOW(XB_ASSO) | \ + PIN_OSPEED_SPEED_VERYLOW(USB_VBUS) | \ + PIN_OSPEED_SPEED_VERYLOW(SD_DETECT) | \ + PIN_OSPEED_SPEED_HIGH(OTG_FS_DM) | \ + PIN_OSPEED_SPEED_HIGH(OTG_FS_DP) | \ + PIN_OSPEED_SPEED_HIGH(SWDIO) | \ + PIN_OSPEED_SPEED_HIGH(SWCLK) | \ + PIN_OSPEED_SPEED_HIGH(SPI1_CS)) + +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(AUX3) | \ + PIN_PUPDR_PULLDOWN(RC1_UART4_RX) | \ + PIN_PUPDR_PULLDOWN(AUX2) | \ + PIN_PUPDR_PULLDOWN(AUX1) | \ + PIN_PUPDR_FLOATING(VBAT_MEAS) | \ + PIN_PUPDR_PULLDOWN(AUX0) | \ + PIN_PUPDR_PULLDOWN(SRV0_TIM3_CH1) | \ + PIN_PUPDR_PULLDOWN(SRV1_TIM3_CH2) | \ + PIN_PUPDR_FLOATING(XB_ASSO) | \ + PIN_PUPDR_PULLDOWN(USB_VBUS) | \ + PIN_PUPDR_PULLUP(SD_DETECT) | \ + PIN_PUPDR_FLOATING(OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(SWDIO) | \ + PIN_PUPDR_FLOATING(SWCLK) | \ + PIN_PUPDR_FLOATING(SPI1_CS)) + +#define VAL_GPIOA_ODR (PIN_ODR_LEVEL_HIGH(AUX3) | \ + PIN_ODR_LEVEL_HIGH(RC1_UART4_RX) | \ + PIN_ODR_LEVEL_HIGH(AUX2) | \ + PIN_ODR_LEVEL_HIGH(AUX1) | \ + PIN_ODR_LEVEL_LOW(VBAT_MEAS) | \ + PIN_ODR_LEVEL_HIGH(AUX0) | \ + PIN_ODR_LEVEL_HIGH(SRV0_TIM3_CH1) | \ + PIN_ODR_LEVEL_HIGH(SRV1_TIM3_CH2) | \ + PIN_ODR_LEVEL_LOW(XB_ASSO) | \ + PIN_ODR_LEVEL_LOW(USB_VBUS) | \ + PIN_ODR_LEVEL_LOW(SD_DETECT) | \ + PIN_ODR_LEVEL_HIGH(OTG_FS_DM) | \ + PIN_ODR_LEVEL_HIGH(OTG_FS_DP) | \ + PIN_ODR_LEVEL_HIGH(SWDIO) | \ + PIN_ODR_LEVEL_HIGH(SWCLK) | \ + PIN_ODR_LEVEL_HIGH(SPI1_CS)) + +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(AUX3, 0) | \ + PIN_AFIO_AF(RC1_UART4_RX, 0) | \ + PIN_AFIO_AF(AUX2, 0) | \ + PIN_AFIO_AF(AUX1, 0) | \ + PIN_AFIO_AF(VBAT_MEAS, 0) | \ + PIN_AFIO_AF(AUX0, 0) | \ + PIN_AFIO_AF(SRV0_TIM3_CH1, 0) | \ + PIN_AFIO_AF(SRV1_TIM3_CH2, 0)) + +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(XB_ASSO, 0) | \ + PIN_AFIO_AF(USB_VBUS, 0) | \ + PIN_AFIO_AF(SD_DETECT, 0) | \ + PIN_AFIO_AF(OTG_FS_DM, 10) | \ + PIN_AFIO_AF(OTG_FS_DP, 10) | \ + PIN_AFIO_AF(SWDIO, 0) | \ + PIN_AFIO_AF(SWCLK, 0) | \ + PIN_AFIO_AF(SPI1_CS, 0)) + +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(SRV2_TIM3_CH3) | \ + PIN_MODE_INPUT(SRV3_TIM3_CH4) | \ + PIN_MODE_INPUT(RC1) | \ + PIN_MODE_ALTERNATE(SPI1_SCK) | \ + PIN_MODE_ALTERNATE(SPI1_MISO) | \ + PIN_MODE_ALTERNATE(SPI1_MOSI) | \ + PIN_MODE_ALTERNATE(USART1_TX) | \ + PIN_MODE_ALTERNATE(USART1_RX) | \ + PIN_MODE_ALTERNATE(I2C1_SCL) | \ + PIN_MODE_ALTERNATE(I2C1_SDA) | \ + PIN_MODE_ALTERNATE(I2C2_SCL) | \ + PIN_MODE_ALTERNATE(I2C2_SDA) | \ + PIN_MODE_OUTPUT(LED1) | \ + PIN_MODE_OUTPUT(LED2) | \ + PIN_MODE_OUTPUT(DIS_C) | \ + PIN_MODE_OUTPUT(DIS_DP)) + +#define VAL_GPIOB_OTYPER (PIN_OTYPE_OPENDRAIN(SRV2_TIM3_CH3) | \ + PIN_OTYPE_OPENDRAIN(SRV3_TIM3_CH4) | \ + PIN_OTYPE_OPENDRAIN(RC1) | \ + PIN_OTYPE_PUSHPULL(SPI1_SCK) | \ + PIN_OTYPE_PUSHPULL(SPI1_MISO) | \ + PIN_OTYPE_PUSHPULL(SPI1_MOSI) | \ + PIN_OTYPE_PUSHPULL(USART1_TX) | \ + PIN_OTYPE_PUSHPULL(USART1_RX) | \ + PIN_OTYPE_OPENDRAIN(I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(I2C1_SDA) | \ + PIN_OTYPE_OPENDRAIN(I2C2_SCL) | \ + PIN_OTYPE_OPENDRAIN(I2C2_SDA) | \ + PIN_OTYPE_PUSHPULL(LED1) | \ + PIN_OTYPE_PUSHPULL(LED2) | \ + PIN_OTYPE_PUSHPULL(DIS_C) | \ + PIN_OTYPE_PUSHPULL(DIS_DP)) + +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(SRV2_TIM3_CH3) | \ + PIN_OSPEED_SPEED_VERYLOW(SRV3_TIM3_CH4) | \ + PIN_OSPEED_SPEED_VERYLOW(RC1) | \ + PIN_OSPEED_SPEED_HIGH(SPI1_SCK) | \ + PIN_OSPEED_SPEED_HIGH(SPI1_MISO) | \ + PIN_OSPEED_SPEED_HIGH(SPI1_MOSI) | \ + PIN_OSPEED_SPEED_HIGH(USART1_TX) | \ + PIN_OSPEED_SPEED_HIGH(USART1_RX) | \ + PIN_OSPEED_SPEED_HIGH(I2C1_SCL) | \ + PIN_OSPEED_SPEED_HIGH(I2C1_SDA) | \ + PIN_OSPEED_SPEED_HIGH(I2C2_SCL) | \ + PIN_OSPEED_SPEED_HIGH(I2C2_SDA) | \ + PIN_OSPEED_SPEED_VERYLOW(LED1) | \ + PIN_OSPEED_SPEED_VERYLOW(LED2) | \ + PIN_OSPEED_SPEED_VERYLOW(DIS_C) | \ + PIN_OSPEED_SPEED_VERYLOW(DIS_DP)) + +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLDOWN(SRV2_TIM3_CH3) | \ + PIN_PUPDR_PULLDOWN(SRV3_TIM3_CH4) | \ + PIN_PUPDR_PULLDOWN(RC1) | \ + PIN_PUPDR_FLOATING(SPI1_SCK) | \ + PIN_PUPDR_FLOATING(SPI1_MISO) | \ + PIN_PUPDR_FLOATING(SPI1_MOSI) | \ + PIN_PUPDR_FLOATING(USART1_TX) | \ + PIN_PUPDR_FLOATING(USART1_RX) | \ + PIN_PUPDR_PULLUP(I2C1_SCL) | \ + PIN_PUPDR_PULLUP(I2C1_SDA) | \ + PIN_PUPDR_PULLUP(I2C2_SCL) | \ + PIN_PUPDR_PULLUP(I2C2_SDA) | \ + PIN_PUPDR_FLOATING(LED1) | \ + PIN_PUPDR_FLOATING(LED2) | \ + PIN_PUPDR_FLOATING(DIS_C) | \ + PIN_PUPDR_FLOATING(DIS_DP)) + +#define VAL_GPIOB_ODR (PIN_ODR_LEVEL_HIGH(SRV2_TIM3_CH3) | \ + PIN_ODR_LEVEL_HIGH(SRV3_TIM3_CH4) | \ + PIN_ODR_LEVEL_HIGH(RC1) | \ + PIN_ODR_LEVEL_HIGH(SPI1_SCK) | \ + PIN_ODR_LEVEL_HIGH(SPI1_MISO) | \ + PIN_ODR_LEVEL_HIGH(SPI1_MOSI) | \ + PIN_ODR_LEVEL_HIGH(USART1_TX) | \ + PIN_ODR_LEVEL_HIGH(USART1_RX) | \ + PIN_ODR_LEVEL_HIGH(I2C1_SCL) | \ + PIN_ODR_LEVEL_HIGH(I2C1_SDA) | \ + PIN_ODR_LEVEL_HIGH(I2C2_SCL) | \ + PIN_ODR_LEVEL_HIGH(I2C2_SDA) | \ + PIN_ODR_LEVEL_LOW(LED1) | \ + PIN_ODR_LEVEL_LOW(LED2) | \ + PIN_ODR_LEVEL_LOW(DIS_C) | \ + PIN_ODR_LEVEL_LOW(DIS_DP)) + +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(SRV2_TIM3_CH3, 0) | \ + PIN_AFIO_AF(SRV3_TIM3_CH4, 0) | \ + PIN_AFIO_AF(RC1, 0) | \ + PIN_AFIO_AF(SPI1_SCK, 5) | \ + PIN_AFIO_AF(SPI1_MISO, 5) | \ + PIN_AFIO_AF(SPI1_MOSI, 5) | \ + PIN_AFIO_AF(USART1_TX, 7) | \ + PIN_AFIO_AF(USART1_RX, 7)) + +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(I2C1_SCL, 4) | \ + PIN_AFIO_AF(I2C1_SDA, 4) | \ + PIN_AFIO_AF(I2C2_SCL, 4) | \ + PIN_AFIO_AF(I2C2_SDA, 4) | \ + PIN_AFIO_AF(LED1, 0) | \ + PIN_AFIO_AF(LED2, 0) | \ + PIN_AFIO_AF(DIS_C, 0) | \ + PIN_AFIO_AF(DIS_DP, 0)) + +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(PC00) | \ + PIN_MODE_INPUT(PC01) | \ + PIN_MODE_INPUT(AUX5) | \ + PIN_MODE_INPUT(AUX4) | \ + PIN_MODE_OUTPUT(EN_COMP) | \ + PIN_MODE_INPUT(PC05) | \ + PIN_MODE_INPUT(AUX6) | \ + PIN_MODE_INPUT(AUX7) | \ + PIN_MODE_ALTERNATE(SDMMC1_D0) | \ + PIN_MODE_ALTERNATE(SDMMC1_D1) | \ + PIN_MODE_ALTERNATE(SDMMC1_D2) | \ + PIN_MODE_ALTERNATE(SDMMC1_D3) | \ + PIN_MODE_ALTERNATE(SDMMC1_CK) | \ + PIN_MODE_INPUT(PC13) | \ + PIN_MODE_ALTERNATE(OSC32_IN) | \ + PIN_MODE_ALTERNATE(OSC32_OUT)) + +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(PC00) | \ + PIN_OTYPE_PUSHPULL(PC01) | \ + PIN_OTYPE_OPENDRAIN(AUX5) | \ + PIN_OTYPE_OPENDRAIN(AUX4) | \ + PIN_OTYPE_PUSHPULL(EN_COMP) | \ + PIN_OTYPE_PUSHPULL(PC05) | \ + PIN_OTYPE_OPENDRAIN(AUX6) | \ + PIN_OTYPE_OPENDRAIN(AUX7) | \ + PIN_OTYPE_PUSHPULL(SDMMC1_D0) | \ + PIN_OTYPE_PUSHPULL(SDMMC1_D1) | \ + PIN_OTYPE_PUSHPULL(SDMMC1_D2) | \ + PIN_OTYPE_PUSHPULL(SDMMC1_D3) | \ + PIN_OTYPE_PUSHPULL(SDMMC1_CK) | \ + PIN_OTYPE_PUSHPULL(PC13) | \ + PIN_OTYPE_PUSHPULL(OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(OSC32_OUT)) + +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PC00) | \ + PIN_OSPEED_SPEED_VERYLOW(PC01) | \ + PIN_OSPEED_SPEED_VERYLOW(AUX5) | \ + PIN_OSPEED_SPEED_VERYLOW(AUX4) | \ + PIN_OSPEED_SPEED_VERYLOW(EN_COMP) | \ + PIN_OSPEED_SPEED_VERYLOW(PC05) | \ + PIN_OSPEED_SPEED_VERYLOW(AUX6) | \ + PIN_OSPEED_SPEED_VERYLOW(AUX7) | \ + PIN_OSPEED_SPEED_HIGH(SDMMC1_D0) | \ + PIN_OSPEED_SPEED_HIGH(SDMMC1_D1) | \ + PIN_OSPEED_SPEED_HIGH(SDMMC1_D2) | \ + PIN_OSPEED_SPEED_HIGH(SDMMC1_D3) | \ + PIN_OSPEED_SPEED_HIGH(SDMMC1_CK) | \ + PIN_OSPEED_SPEED_VERYLOW(PC13) | \ + PIN_OSPEED_SPEED_HIGH(OSC32_IN) | \ + PIN_OSPEED_SPEED_HIGH(OSC32_OUT)) + +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLDOWN(PC00) | \ + PIN_PUPDR_PULLDOWN(PC01) | \ + PIN_PUPDR_PULLDOWN(AUX5) | \ + PIN_PUPDR_PULLDOWN(AUX4) | \ + PIN_PUPDR_FLOATING(EN_COMP) | \ + PIN_PUPDR_PULLDOWN(PC05) | \ + PIN_PUPDR_PULLDOWN(AUX6) | \ + PIN_PUPDR_PULLDOWN(AUX7) | \ + PIN_PUPDR_PULLUP(SDMMC1_D0) | \ + PIN_PUPDR_PULLUP(SDMMC1_D1) | \ + PIN_PUPDR_PULLUP(SDMMC1_D2) | \ + PIN_PUPDR_PULLUP(SDMMC1_D3) | \ + PIN_PUPDR_PULLUP(SDMMC1_CK) | \ + PIN_PUPDR_PULLDOWN(PC13) | \ + PIN_PUPDR_FLOATING(OSC32_IN) | \ + PIN_PUPDR_FLOATING(OSC32_OUT)) + +#define VAL_GPIOC_ODR (PIN_ODR_LEVEL_LOW(PC00) | \ + PIN_ODR_LEVEL_LOW(PC01) | \ + PIN_ODR_LEVEL_HIGH(AUX5) | \ + PIN_ODR_LEVEL_HIGH(AUX4) | \ + PIN_ODR_LEVEL_HIGH(EN_COMP) | \ + PIN_ODR_LEVEL_LOW(PC05) | \ + PIN_ODR_LEVEL_HIGH(AUX6) | \ + PIN_ODR_LEVEL_HIGH(AUX7) | \ + PIN_ODR_LEVEL_HIGH(SDMMC1_D0) | \ + PIN_ODR_LEVEL_HIGH(SDMMC1_D1) | \ + PIN_ODR_LEVEL_HIGH(SDMMC1_D2) | \ + PIN_ODR_LEVEL_HIGH(SDMMC1_D3) | \ + PIN_ODR_LEVEL_HIGH(SDMMC1_CK) | \ + PIN_ODR_LEVEL_LOW(PC13) | \ + PIN_ODR_LEVEL_HIGH(OSC32_IN) | \ + PIN_ODR_LEVEL_HIGH(OSC32_OUT)) + +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(PC00, 0) | \ + PIN_AFIO_AF(PC01, 0) | \ + PIN_AFIO_AF(AUX5, 0) | \ + PIN_AFIO_AF(AUX4, 0) | \ + PIN_AFIO_AF(EN_COMP, 0) | \ + PIN_AFIO_AF(PC05, 0) | \ + PIN_AFIO_AF(AUX6, 0) | \ + PIN_AFIO_AF(AUX7, 0)) + +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(SDMMC1_D0, 12) | \ + PIN_AFIO_AF(SDMMC1_D1, 12) | \ + PIN_AFIO_AF(SDMMC1_D2, 12) | \ + PIN_AFIO_AF(SDMMC1_D3, 12) | \ + PIN_AFIO_AF(SDMMC1_CK, 12) | \ + PIN_AFIO_AF(PC13, 0) | \ + PIN_AFIO_AF(OSC32_IN, 0) | \ + PIN_AFIO_AF(OSC32_OUT, 0)) + +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(CAN1_RX) | \ + PIN_MODE_ALTERNATE(CAN1_TX) | \ + PIN_MODE_ALTERNATE(SDMMC1_CMD) | \ + PIN_MODE_INPUT(USART2_CTS) | \ + PIN_MODE_INPUT(USART2_RTS) | \ + PIN_MODE_INPUT(USART2_TX) | \ + PIN_MODE_INPUT(USART2_RX) | \ + PIN_MODE_INPUT(IMU_INT) | \ + PIN_MODE_ALTERNATE(USART3_TX) | \ + PIN_MODE_ALTERNATE(USART3_RX) | \ + PIN_MODE_OUTPUT(LED3) | \ + PIN_MODE_OUTPUT(LED4) | \ + PIN_MODE_INPUT(SRV4_TIM4_CH1) | \ + PIN_MODE_INPUT(SRV5_TIM4_CH2) | \ + PIN_MODE_INPUT(SRV6_TIM4_CH3) | \ + PIN_MODE_INPUT(SRV7_TIM4_CH4)) + +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(CAN1_RX) | \ + PIN_OTYPE_PUSHPULL(CAN1_TX) | \ + PIN_OTYPE_PUSHPULL(SDMMC1_CMD) | \ + PIN_OTYPE_OPENDRAIN(USART2_CTS) | \ + PIN_OTYPE_OPENDRAIN(USART2_RTS) | \ + PIN_OTYPE_OPENDRAIN(USART2_TX) | \ + PIN_OTYPE_OPENDRAIN(USART2_RX) | \ + PIN_OTYPE_OPENDRAIN(IMU_INT) | \ + PIN_OTYPE_PUSHPULL(USART3_TX) | \ + PIN_OTYPE_PUSHPULL(USART3_RX) | \ + PIN_OTYPE_PUSHPULL(LED3) | \ + PIN_OTYPE_PUSHPULL(LED4) | \ + PIN_OTYPE_OPENDRAIN(SRV4_TIM4_CH1) | \ + PIN_OTYPE_OPENDRAIN(SRV5_TIM4_CH2) | \ + PIN_OTYPE_OPENDRAIN(SRV6_TIM4_CH3) | \ + PIN_OTYPE_OPENDRAIN(SRV7_TIM4_CH4)) + +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_SPEED_HIGH(CAN1_RX) | \ + PIN_OSPEED_SPEED_HIGH(CAN1_TX) | \ + PIN_OSPEED_SPEED_HIGH(SDMMC1_CMD) | \ + PIN_OSPEED_SPEED_VERYLOW(USART2_CTS) | \ + PIN_OSPEED_SPEED_VERYLOW(USART2_RTS) | \ + PIN_OSPEED_SPEED_VERYLOW(USART2_TX) | \ + PIN_OSPEED_SPEED_VERYLOW(USART2_RX) | \ + PIN_OSPEED_SPEED_VERYLOW(IMU_INT) | \ + PIN_OSPEED_SPEED_HIGH(USART3_TX) | \ + PIN_OSPEED_SPEED_HIGH(USART3_RX) | \ + PIN_OSPEED_SPEED_VERYLOW(LED3) | \ + PIN_OSPEED_SPEED_VERYLOW(LED4) | \ + PIN_OSPEED_SPEED_VERYLOW(SRV4_TIM4_CH1) | \ + PIN_OSPEED_SPEED_VERYLOW(SRV5_TIM4_CH2) | \ + PIN_OSPEED_SPEED_VERYLOW(SRV6_TIM4_CH3) | \ + PIN_OSPEED_SPEED_VERYLOW(SRV7_TIM4_CH4)) + +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(CAN1_RX) | \ + PIN_PUPDR_FLOATING(CAN1_TX) | \ + PIN_PUPDR_PULLUP(SDMMC1_CMD) | \ + PIN_PUPDR_PULLDOWN(USART2_CTS) | \ + PIN_PUPDR_PULLDOWN(USART2_RTS) | \ + PIN_PUPDR_PULLDOWN(USART2_TX) | \ + PIN_PUPDR_PULLDOWN(USART2_RX) | \ + PIN_PUPDR_FLOATING(IMU_INT) | \ + PIN_PUPDR_FLOATING(USART3_TX) | \ + PIN_PUPDR_FLOATING(USART3_RX) | \ + PIN_PUPDR_FLOATING(LED3) | \ + PIN_PUPDR_FLOATING(LED4) | \ + PIN_PUPDR_PULLDOWN(SRV4_TIM4_CH1) | \ + PIN_PUPDR_PULLDOWN(SRV5_TIM4_CH2) | \ + PIN_PUPDR_PULLDOWN(SRV6_TIM4_CH3) | \ + PIN_PUPDR_PULLDOWN(SRV7_TIM4_CH4)) + +#define VAL_GPIOD_ODR (PIN_ODR_LEVEL_HIGH(CAN1_RX) | \ + PIN_ODR_LEVEL_HIGH(CAN1_TX) | \ + PIN_ODR_LEVEL_HIGH(SDMMC1_CMD) | \ + PIN_ODR_LEVEL_HIGH(USART2_CTS) | \ + PIN_ODR_LEVEL_HIGH(USART2_RTS) | \ + PIN_ODR_LEVEL_HIGH(USART2_TX) | \ + PIN_ODR_LEVEL_HIGH(USART2_RX) | \ + PIN_ODR_LEVEL_LOW(IMU_INT) | \ + PIN_ODR_LEVEL_HIGH(USART3_TX) | \ + PIN_ODR_LEVEL_HIGH(USART3_RX) | \ + PIN_ODR_LEVEL_LOW(LED3) | \ + PIN_ODR_LEVEL_LOW(LED4) | \ + PIN_ODR_LEVEL_HIGH(SRV4_TIM4_CH1) | \ + PIN_ODR_LEVEL_HIGH(SRV5_TIM4_CH2) | \ + PIN_ODR_LEVEL_HIGH(SRV6_TIM4_CH3) | \ + PIN_ODR_LEVEL_HIGH(SRV7_TIM4_CH4)) + +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(CAN1_RX, 9) | \ + PIN_AFIO_AF(CAN1_TX, 9) | \ + PIN_AFIO_AF(SDMMC1_CMD, 12) | \ + PIN_AFIO_AF(USART2_CTS, 0) | \ + PIN_AFIO_AF(USART2_RTS, 0) | \ + PIN_AFIO_AF(USART2_TX, 0) | \ + PIN_AFIO_AF(USART2_RX, 0) | \ + PIN_AFIO_AF(IMU_INT, 0)) + +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(USART3_TX, 7) | \ + PIN_AFIO_AF(USART3_RX, 7) | \ + PIN_AFIO_AF(LED3, 0) | \ + PIN_AFIO_AF(LED4, 0) | \ + PIN_AFIO_AF(SRV4_TIM4_CH1, 0) | \ + PIN_AFIO_AF(SRV5_TIM4_CH2, 0) | \ + PIN_AFIO_AF(SRV6_TIM4_CH3, 0) | \ + PIN_AFIO_AF(SRV7_TIM4_CH4, 0)) + +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(UART8_RX) | \ + PIN_MODE_ALTERNATE(UART8_TX) | \ + PIN_MODE_OUTPUT(DIS_G) | \ + PIN_MODE_OUTPUT(DIS_F) | \ + PIN_MODE_OUTPUT(DIS_A) | \ + PIN_MODE_OUTPUT(DIS_B) | \ + PIN_MODE_OUTPUT(APSW) | \ + PIN_MODE_INPUT(RC2_UART7_RX) | \ + PIN_MODE_OUTPUT(DIS_E) | \ + PIN_MODE_OUTPUT(DIS_D) | \ + PIN_MODE_INPUT(PE10) | \ + PIN_MODE_INPUT(PE11) | \ + PIN_MODE_INPUT(PE12) | \ + PIN_MODE_INPUT(PE13) | \ + PIN_MODE_INPUT(PE14) | \ + PIN_MODE_OUTPUT(XB_RST)) + +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(UART8_RX) | \ + PIN_OTYPE_PUSHPULL(UART8_TX) | \ + PIN_OTYPE_PUSHPULL(DIS_G) | \ + PIN_OTYPE_PUSHPULL(DIS_F) | \ + PIN_OTYPE_PUSHPULL(DIS_A) | \ + PIN_OTYPE_PUSHPULL(DIS_B) | \ + PIN_OTYPE_PUSHPULL(APSW) | \ + PIN_OTYPE_OPENDRAIN(RC2_UART7_RX) | \ + PIN_OTYPE_PUSHPULL(DIS_E) | \ + PIN_OTYPE_PUSHPULL(DIS_D) | \ + PIN_OTYPE_PUSHPULL(PE10) | \ + PIN_OTYPE_PUSHPULL(PE11) | \ + PIN_OTYPE_PUSHPULL(PE12) | \ + PIN_OTYPE_PUSHPULL(PE13) | \ + PIN_OTYPE_PUSHPULL(PE14) | \ + PIN_OTYPE_PUSHPULL(XB_RST)) + +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_SPEED_HIGH(UART8_RX) | \ + PIN_OSPEED_SPEED_HIGH(UART8_TX) | \ + PIN_OSPEED_SPEED_VERYLOW(DIS_G) | \ + PIN_OSPEED_SPEED_VERYLOW(DIS_F) | \ + PIN_OSPEED_SPEED_VERYLOW(DIS_A) | \ + PIN_OSPEED_SPEED_VERYLOW(DIS_B) | \ + PIN_OSPEED_SPEED_VERYLOW(APSW) | \ + PIN_OSPEED_SPEED_VERYLOW(RC2_UART7_RX) | \ + PIN_OSPEED_SPEED_VERYLOW(DIS_E) | \ + PIN_OSPEED_SPEED_VERYLOW(DIS_D) | \ + PIN_OSPEED_SPEED_VERYLOW(PE10) | \ + PIN_OSPEED_SPEED_VERYLOW(PE11) | \ + PIN_OSPEED_SPEED_VERYLOW(PE12) | \ + PIN_OSPEED_SPEED_VERYLOW(PE13) | \ + PIN_OSPEED_SPEED_VERYLOW(PE14) | \ + PIN_OSPEED_SPEED_VERYLOW(XB_RST)) + +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(UART8_RX) | \ + PIN_PUPDR_FLOATING(UART8_TX) | \ + PIN_PUPDR_FLOATING(DIS_G) | \ + PIN_PUPDR_FLOATING(DIS_F) | \ + PIN_PUPDR_FLOATING(DIS_A) | \ + PIN_PUPDR_FLOATING(DIS_B) | \ + PIN_PUPDR_FLOATING(APSW) | \ + PIN_PUPDR_PULLDOWN(RC2_UART7_RX) | \ + PIN_PUPDR_FLOATING(DIS_E) | \ + PIN_PUPDR_FLOATING(DIS_D) | \ + PIN_PUPDR_PULLDOWN(PE10) | \ + PIN_PUPDR_PULLDOWN(PE11) | \ + PIN_PUPDR_PULLDOWN(PE12) | \ + PIN_PUPDR_PULLDOWN(PE13) | \ + PIN_PUPDR_PULLDOWN(PE14) | \ + PIN_PUPDR_FLOATING(XB_RST)) + +#define VAL_GPIOE_ODR (PIN_ODR_LEVEL_HIGH(UART8_RX) | \ + PIN_ODR_LEVEL_HIGH(UART8_TX) | \ + PIN_ODR_LEVEL_LOW(DIS_G) | \ + PIN_ODR_LEVEL_LOW(DIS_F) | \ + PIN_ODR_LEVEL_LOW(DIS_A) | \ + PIN_ODR_LEVEL_LOW(DIS_B) | \ + PIN_ODR_LEVEL_HIGH(APSW) | \ + PIN_ODR_LEVEL_HIGH(RC2_UART7_RX) | \ + PIN_ODR_LEVEL_LOW(DIS_E) | \ + PIN_ODR_LEVEL_LOW(DIS_D) | \ + PIN_ODR_LEVEL_LOW(PE10) | \ + PIN_ODR_LEVEL_LOW(PE11) | \ + PIN_ODR_LEVEL_LOW(PE12) | \ + PIN_ODR_LEVEL_LOW(PE13) | \ + PIN_ODR_LEVEL_LOW(PE14) | \ + PIN_ODR_LEVEL_HIGH(XB_RST)) + +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(UART8_RX, 8) | \ + PIN_AFIO_AF(UART8_TX, 8) | \ + PIN_AFIO_AF(DIS_G, 0) | \ + PIN_AFIO_AF(DIS_F, 0) | \ + PIN_AFIO_AF(DIS_A, 0) | \ + PIN_AFIO_AF(DIS_B, 0) | \ + PIN_AFIO_AF(APSW, 0) | \ + PIN_AFIO_AF(RC2_UART7_RX, 0)) + +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(DIS_E, 0) | \ + PIN_AFIO_AF(DIS_D, 0) | \ + PIN_AFIO_AF(PE10, 0) | \ + PIN_AFIO_AF(PE11, 0) | \ + PIN_AFIO_AF(PE12, 0) | \ + PIN_AFIO_AF(PE13, 0) | \ + PIN_AFIO_AF(PE14, 0) | \ + PIN_AFIO_AF(XB_RST, 0)) + +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(PF00) | \ + PIN_MODE_INPUT(PF01) | \ + PIN_MODE_INPUT(PF02) | \ + PIN_MODE_INPUT(PF03) | \ + PIN_MODE_INPUT(PF04) | \ + PIN_MODE_INPUT(PF05) | \ + PIN_MODE_INPUT(PF06) | \ + PIN_MODE_INPUT(PF07) | \ + PIN_MODE_INPUT(PF08) | \ + PIN_MODE_INPUT(PF09) | \ + PIN_MODE_INPUT(PF10) | \ + PIN_MODE_INPUT(PF11) | \ + PIN_MODE_INPUT(PF12) | \ + PIN_MODE_INPUT(PF13) | \ + PIN_MODE_INPUT(PF14) | \ + PIN_MODE_INPUT(PF15)) + +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(PF00) | \ + PIN_OTYPE_PUSHPULL(PF01) | \ + PIN_OTYPE_PUSHPULL(PF02) | \ + PIN_OTYPE_PUSHPULL(PF03) | \ + PIN_OTYPE_PUSHPULL(PF04) | \ + PIN_OTYPE_PUSHPULL(PF05) | \ + PIN_OTYPE_PUSHPULL(PF06) | \ + PIN_OTYPE_PUSHPULL(PF07) | \ + PIN_OTYPE_PUSHPULL(PF08) | \ + PIN_OTYPE_PUSHPULL(PF09) | \ + PIN_OTYPE_PUSHPULL(PF10) | \ + PIN_OTYPE_PUSHPULL(PF11) | \ + PIN_OTYPE_PUSHPULL(PF12) | \ + PIN_OTYPE_PUSHPULL(PF13) | \ + PIN_OTYPE_PUSHPULL(PF14) | \ + PIN_OTYPE_PUSHPULL(PF15)) + +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PF00) | \ + PIN_OSPEED_SPEED_VERYLOW(PF01) | \ + PIN_OSPEED_SPEED_VERYLOW(PF02) | \ + PIN_OSPEED_SPEED_VERYLOW(PF03) | \ + PIN_OSPEED_SPEED_VERYLOW(PF04) | \ + PIN_OSPEED_SPEED_VERYLOW(PF05) | \ + PIN_OSPEED_SPEED_VERYLOW(PF06) | \ + PIN_OSPEED_SPEED_VERYLOW(PF07) | \ + PIN_OSPEED_SPEED_VERYLOW(PF08) | \ + PIN_OSPEED_SPEED_VERYLOW(PF09) | \ + PIN_OSPEED_SPEED_VERYLOW(PF10) | \ + PIN_OSPEED_SPEED_VERYLOW(PF11) | \ + PIN_OSPEED_SPEED_VERYLOW(PF12) | \ + PIN_OSPEED_SPEED_VERYLOW(PF13) | \ + PIN_OSPEED_SPEED_VERYLOW(PF14) | \ + PIN_OSPEED_SPEED_VERYLOW(PF15)) + +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLDOWN(PF00) | \ + PIN_PUPDR_PULLDOWN(PF01) | \ + PIN_PUPDR_PULLDOWN(PF02) | \ + PIN_PUPDR_PULLDOWN(PF03) | \ + PIN_PUPDR_PULLDOWN(PF04) | \ + PIN_PUPDR_PULLDOWN(PF05) | \ + PIN_PUPDR_PULLDOWN(PF06) | \ + PIN_PUPDR_PULLDOWN(PF07) | \ + PIN_PUPDR_PULLDOWN(PF08) | \ + PIN_PUPDR_PULLDOWN(PF09) | \ + PIN_PUPDR_PULLDOWN(PF10) | \ + PIN_PUPDR_PULLDOWN(PF11) | \ + PIN_PUPDR_PULLDOWN(PF12) | \ + PIN_PUPDR_PULLDOWN(PF13) | \ + PIN_PUPDR_PULLDOWN(PF14) | \ + PIN_PUPDR_PULLDOWN(PF15)) + +#define VAL_GPIOF_ODR (PIN_ODR_LEVEL_LOW(PF00) | \ + PIN_ODR_LEVEL_LOW(PF01) | \ + PIN_ODR_LEVEL_LOW(PF02) | \ + PIN_ODR_LEVEL_LOW(PF03) | \ + PIN_ODR_LEVEL_LOW(PF04) | \ + PIN_ODR_LEVEL_LOW(PF05) | \ + PIN_ODR_LEVEL_LOW(PF06) | \ + PIN_ODR_LEVEL_LOW(PF07) | \ + PIN_ODR_LEVEL_LOW(PF08) | \ + PIN_ODR_LEVEL_LOW(PF09) | \ + PIN_ODR_LEVEL_LOW(PF10) | \ + PIN_ODR_LEVEL_LOW(PF11) | \ + PIN_ODR_LEVEL_LOW(PF12) | \ + PIN_ODR_LEVEL_LOW(PF13) | \ + PIN_ODR_LEVEL_LOW(PF14) | \ + PIN_ODR_LEVEL_LOW(PF15)) + +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(PF00, 0) | \ + PIN_AFIO_AF(PF01, 0) | \ + PIN_AFIO_AF(PF02, 0) | \ + PIN_AFIO_AF(PF03, 0) | \ + PIN_AFIO_AF(PF04, 0) | \ + PIN_AFIO_AF(PF05, 0) | \ + PIN_AFIO_AF(PF06, 0) | \ + PIN_AFIO_AF(PF07, 0)) + +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(PF08, 0) | \ + PIN_AFIO_AF(PF09, 0) | \ + PIN_AFIO_AF(PF10, 0) | \ + PIN_AFIO_AF(PF11, 0) | \ + PIN_AFIO_AF(PF12, 0) | \ + PIN_AFIO_AF(PF13, 0) | \ + PIN_AFIO_AF(PF14, 0) | \ + PIN_AFIO_AF(PF15, 0)) + +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(PG00) | \ + PIN_MODE_INPUT(PG01) | \ + PIN_MODE_INPUT(PG02) | \ + PIN_MODE_INPUT(PG03) | \ + PIN_MODE_INPUT(PG04) | \ + PIN_MODE_INPUT(PG05) | \ + PIN_MODE_INPUT(PG06) | \ + PIN_MODE_INPUT(PG07) | \ + PIN_MODE_INPUT(PG08) | \ + PIN_MODE_INPUT(PG09) | \ + PIN_MODE_INPUT(PG10) | \ + PIN_MODE_INPUT(PG11) | \ + PIN_MODE_INPUT(PG12) | \ + PIN_MODE_INPUT(PG13) | \ + PIN_MODE_INPUT(PG14) | \ + PIN_MODE_INPUT(PG15)) + +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(PG00) | \ + PIN_OTYPE_PUSHPULL(PG01) | \ + PIN_OTYPE_PUSHPULL(PG02) | \ + PIN_OTYPE_PUSHPULL(PG03) | \ + PIN_OTYPE_PUSHPULL(PG04) | \ + PIN_OTYPE_PUSHPULL(PG05) | \ + PIN_OTYPE_PUSHPULL(PG06) | \ + PIN_OTYPE_PUSHPULL(PG07) | \ + PIN_OTYPE_PUSHPULL(PG08) | \ + PIN_OTYPE_PUSHPULL(PG09) | \ + PIN_OTYPE_PUSHPULL(PG10) | \ + PIN_OTYPE_PUSHPULL(PG11) | \ + PIN_OTYPE_PUSHPULL(PG12) | \ + PIN_OTYPE_PUSHPULL(PG13) | \ + PIN_OTYPE_PUSHPULL(PG14) | \ + PIN_OTYPE_PUSHPULL(PG15)) + +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PG00) | \ + PIN_OSPEED_SPEED_VERYLOW(PG01) | \ + PIN_OSPEED_SPEED_VERYLOW(PG02) | \ + PIN_OSPEED_SPEED_VERYLOW(PG03) | \ + PIN_OSPEED_SPEED_VERYLOW(PG04) | \ + PIN_OSPEED_SPEED_VERYLOW(PG05) | \ + PIN_OSPEED_SPEED_VERYLOW(PG06) | \ + PIN_OSPEED_SPEED_VERYLOW(PG07) | \ + PIN_OSPEED_SPEED_VERYLOW(PG08) | \ + PIN_OSPEED_SPEED_VERYLOW(PG09) | \ + PIN_OSPEED_SPEED_VERYLOW(PG10) | \ + PIN_OSPEED_SPEED_VERYLOW(PG11) | \ + PIN_OSPEED_SPEED_VERYLOW(PG12) | \ + PIN_OSPEED_SPEED_VERYLOW(PG13) | \ + PIN_OSPEED_SPEED_VERYLOW(PG14) | \ + PIN_OSPEED_SPEED_VERYLOW(PG15)) + +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLDOWN(PG00) | \ + PIN_PUPDR_PULLDOWN(PG01) | \ + PIN_PUPDR_PULLDOWN(PG02) | \ + PIN_PUPDR_PULLDOWN(PG03) | \ + PIN_PUPDR_PULLDOWN(PG04) | \ + PIN_PUPDR_PULLDOWN(PG05) | \ + PIN_PUPDR_PULLDOWN(PG06) | \ + PIN_PUPDR_PULLDOWN(PG07) | \ + PIN_PUPDR_PULLDOWN(PG08) | \ + PIN_PUPDR_PULLDOWN(PG09) | \ + PIN_PUPDR_PULLDOWN(PG10) | \ + PIN_PUPDR_PULLDOWN(PG11) | \ + PIN_PUPDR_PULLDOWN(PG12) | \ + PIN_PUPDR_PULLDOWN(PG13) | \ + PIN_PUPDR_PULLDOWN(PG14) | \ + PIN_PUPDR_PULLDOWN(PG15)) + +#define VAL_GPIOG_ODR (PIN_ODR_LEVEL_LOW(PG00) | \ + PIN_ODR_LEVEL_LOW(PG01) | \ + PIN_ODR_LEVEL_LOW(PG02) | \ + PIN_ODR_LEVEL_LOW(PG03) | \ + PIN_ODR_LEVEL_LOW(PG04) | \ + PIN_ODR_LEVEL_LOW(PG05) | \ + PIN_ODR_LEVEL_LOW(PG06) | \ + PIN_ODR_LEVEL_LOW(PG07) | \ + PIN_ODR_LEVEL_LOW(PG08) | \ + PIN_ODR_LEVEL_LOW(PG09) | \ + PIN_ODR_LEVEL_LOW(PG10) | \ + PIN_ODR_LEVEL_LOW(PG11) | \ + PIN_ODR_LEVEL_LOW(PG12) | \ + PIN_ODR_LEVEL_LOW(PG13) | \ + PIN_ODR_LEVEL_LOW(PG14) | \ + PIN_ODR_LEVEL_LOW(PG15)) + +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(PG00, 0) | \ + PIN_AFIO_AF(PG01, 0) | \ + PIN_AFIO_AF(PG02, 0) | \ + PIN_AFIO_AF(PG03, 0) | \ + PIN_AFIO_AF(PG04, 0) | \ + PIN_AFIO_AF(PG05, 0) | \ + PIN_AFIO_AF(PG06, 0) | \ + PIN_AFIO_AF(PG07, 0)) + +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(PG08, 0) | \ + PIN_AFIO_AF(PG09, 0) | \ + PIN_AFIO_AF(PG10, 0) | \ + PIN_AFIO_AF(PG11, 0) | \ + PIN_AFIO_AF(PG12, 0) | \ + PIN_AFIO_AF(PG13, 0) | \ + PIN_AFIO_AF(PG14, 0) | \ + PIN_AFIO_AF(PG15, 0)) + +#define VAL_GPIOH_MODER (PIN_MODE_ALTERNATE(OSC_IN) | \ + PIN_MODE_ALTERNATE(OSC_OUT) | \ + PIN_MODE_INPUT(PH02) | \ + PIN_MODE_INPUT(PH03) | \ + PIN_MODE_INPUT(PH04) | \ + PIN_MODE_INPUT(PH05) | \ + PIN_MODE_INPUT(PH06) | \ + PIN_MODE_INPUT(PH07) | \ + PIN_MODE_INPUT(PH08) | \ + PIN_MODE_INPUT(PH09) | \ + PIN_MODE_INPUT(PH10) | \ + PIN_MODE_INPUT(PH11) | \ + PIN_MODE_INPUT(PH12) | \ + PIN_MODE_INPUT(PH13) | \ + PIN_MODE_INPUT(PH14) | \ + PIN_MODE_INPUT(PH15)) + +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(OSC_IN) | \ + PIN_OTYPE_PUSHPULL(OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(PH02) | \ + PIN_OTYPE_PUSHPULL(PH03) | \ + PIN_OTYPE_PUSHPULL(PH04) | \ + PIN_OTYPE_PUSHPULL(PH05) | \ + PIN_OTYPE_PUSHPULL(PH06) | \ + PIN_OTYPE_PUSHPULL(PH07) | \ + PIN_OTYPE_PUSHPULL(PH08) | \ + PIN_OTYPE_PUSHPULL(PH09) | \ + PIN_OTYPE_PUSHPULL(PH10) | \ + PIN_OTYPE_PUSHPULL(PH11) | \ + PIN_OTYPE_PUSHPULL(PH12) | \ + PIN_OTYPE_PUSHPULL(PH13) | \ + PIN_OTYPE_PUSHPULL(PH14) | \ + PIN_OTYPE_PUSHPULL(PH15)) + +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_SPEED_HIGH(OSC_IN) | \ + PIN_OSPEED_SPEED_HIGH(OSC_OUT) | \ + PIN_OSPEED_SPEED_VERYLOW(PH02) | \ + PIN_OSPEED_SPEED_VERYLOW(PH03) | \ + PIN_OSPEED_SPEED_VERYLOW(PH04) | \ + PIN_OSPEED_SPEED_VERYLOW(PH05) | \ + PIN_OSPEED_SPEED_VERYLOW(PH06) | \ + PIN_OSPEED_SPEED_VERYLOW(PH07) | \ + PIN_OSPEED_SPEED_VERYLOW(PH08) | \ + PIN_OSPEED_SPEED_VERYLOW(PH09) | \ + PIN_OSPEED_SPEED_VERYLOW(PH10) | \ + PIN_OSPEED_SPEED_VERYLOW(PH11) | \ + PIN_OSPEED_SPEED_VERYLOW(PH12) | \ + PIN_OSPEED_SPEED_VERYLOW(PH13) | \ + PIN_OSPEED_SPEED_VERYLOW(PH14) | \ + PIN_OSPEED_SPEED_VERYLOW(PH15)) + +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(OSC_IN) | \ + PIN_PUPDR_FLOATING(OSC_OUT) | \ + PIN_PUPDR_PULLDOWN(PH02) | \ + PIN_PUPDR_PULLDOWN(PH03) | \ + PIN_PUPDR_PULLDOWN(PH04) | \ + PIN_PUPDR_PULLDOWN(PH05) | \ + PIN_PUPDR_PULLDOWN(PH06) | \ + PIN_PUPDR_PULLDOWN(PH07) | \ + PIN_PUPDR_PULLDOWN(PH08) | \ + PIN_PUPDR_PULLDOWN(PH09) | \ + PIN_PUPDR_PULLDOWN(PH10) | \ + PIN_PUPDR_PULLDOWN(PH11) | \ + PIN_PUPDR_PULLDOWN(PH12) | \ + PIN_PUPDR_PULLDOWN(PH13) | \ + PIN_PUPDR_PULLDOWN(PH14) | \ + PIN_PUPDR_PULLDOWN(PH15)) + +#define VAL_GPIOH_ODR (PIN_ODR_LEVEL_HIGH(OSC_IN) | \ + PIN_ODR_LEVEL_HIGH(OSC_OUT) | \ + PIN_ODR_LEVEL_LOW(PH02) | \ + PIN_ODR_LEVEL_LOW(PH03) | \ + PIN_ODR_LEVEL_LOW(PH04) | \ + PIN_ODR_LEVEL_LOW(PH05) | \ + PIN_ODR_LEVEL_LOW(PH06) | \ + PIN_ODR_LEVEL_LOW(PH07) | \ + PIN_ODR_LEVEL_LOW(PH08) | \ + PIN_ODR_LEVEL_LOW(PH09) | \ + PIN_ODR_LEVEL_LOW(PH10) | \ + PIN_ODR_LEVEL_LOW(PH11) | \ + PIN_ODR_LEVEL_LOW(PH12) | \ + PIN_ODR_LEVEL_LOW(PH13) | \ + PIN_ODR_LEVEL_LOW(PH14) | \ + PIN_ODR_LEVEL_LOW(PH15)) + +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(OSC_IN, 0) | \ + PIN_AFIO_AF(OSC_OUT, 0) | \ + PIN_AFIO_AF(PH02, 0) | \ + PIN_AFIO_AF(PH03, 0) | \ + PIN_AFIO_AF(PH04, 0) | \ + PIN_AFIO_AF(PH05, 0) | \ + PIN_AFIO_AF(PH06, 0) | \ + PIN_AFIO_AF(PH07, 0)) + +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(PH08, 0) | \ + PIN_AFIO_AF(PH09, 0) | \ + PIN_AFIO_AF(PH10, 0) | \ + PIN_AFIO_AF(PH11, 0) | \ + PIN_AFIO_AF(PH12, 0) | \ + PIN_AFIO_AF(PH13, 0) | \ + PIN_AFIO_AF(PH14, 0) | \ + PIN_AFIO_AF(PH15, 0)) + +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(PI00) | \ + PIN_MODE_INPUT(PI01) | \ + PIN_MODE_INPUT(PI02) | \ + PIN_MODE_INPUT(PI03) | \ + PIN_MODE_INPUT(PI04) | \ + PIN_MODE_INPUT(PI05) | \ + PIN_MODE_INPUT(PI06) | \ + PIN_MODE_INPUT(PI07) | \ + PIN_MODE_INPUT(PI08) | \ + PIN_MODE_INPUT(PI09) | \ + PIN_MODE_INPUT(PI10) | \ + PIN_MODE_INPUT(PI11) | \ + PIN_MODE_INPUT(PI12) | \ + PIN_MODE_INPUT(PI13) | \ + PIN_MODE_INPUT(PI14) | \ + PIN_MODE_INPUT(PI15)) + +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(PI00) | \ + PIN_OTYPE_PUSHPULL(PI01) | \ + PIN_OTYPE_PUSHPULL(PI02) | \ + PIN_OTYPE_PUSHPULL(PI03) | \ + PIN_OTYPE_PUSHPULL(PI04) | \ + PIN_OTYPE_PUSHPULL(PI05) | \ + PIN_OTYPE_PUSHPULL(PI06) | \ + PIN_OTYPE_PUSHPULL(PI07) | \ + PIN_OTYPE_PUSHPULL(PI08) | \ + PIN_OTYPE_PUSHPULL(PI09) | \ + PIN_OTYPE_PUSHPULL(PI10) | \ + PIN_OTYPE_PUSHPULL(PI11) | \ + PIN_OTYPE_PUSHPULL(PI12) | \ + PIN_OTYPE_PUSHPULL(PI13) | \ + PIN_OTYPE_PUSHPULL(PI14) | \ + PIN_OTYPE_PUSHPULL(PI15)) + +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PI00) | \ + PIN_OSPEED_SPEED_VERYLOW(PI01) | \ + PIN_OSPEED_SPEED_VERYLOW(PI02) | \ + PIN_OSPEED_SPEED_VERYLOW(PI03) | \ + PIN_OSPEED_SPEED_VERYLOW(PI04) | \ + PIN_OSPEED_SPEED_VERYLOW(PI05) | \ + PIN_OSPEED_SPEED_VERYLOW(PI06) | \ + PIN_OSPEED_SPEED_VERYLOW(PI07) | \ + PIN_OSPEED_SPEED_VERYLOW(PI08) | \ + PIN_OSPEED_SPEED_VERYLOW(PI09) | \ + PIN_OSPEED_SPEED_VERYLOW(PI10) | \ + PIN_OSPEED_SPEED_VERYLOW(PI11) | \ + PIN_OSPEED_SPEED_VERYLOW(PI12) | \ + PIN_OSPEED_SPEED_VERYLOW(PI13) | \ + PIN_OSPEED_SPEED_VERYLOW(PI14) | \ + PIN_OSPEED_SPEED_VERYLOW(PI15)) + +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLDOWN(PI00) | \ + PIN_PUPDR_PULLDOWN(PI01) | \ + PIN_PUPDR_PULLDOWN(PI02) | \ + PIN_PUPDR_PULLDOWN(PI03) | \ + PIN_PUPDR_PULLDOWN(PI04) | \ + PIN_PUPDR_PULLDOWN(PI05) | \ + PIN_PUPDR_PULLDOWN(PI06) | \ + PIN_PUPDR_PULLDOWN(PI07) | \ + PIN_PUPDR_PULLDOWN(PI08) | \ + PIN_PUPDR_PULLDOWN(PI09) | \ + PIN_PUPDR_PULLDOWN(PI10) | \ + PIN_PUPDR_PULLDOWN(PI11) | \ + PIN_PUPDR_PULLDOWN(PI12) | \ + PIN_PUPDR_PULLDOWN(PI13) | \ + PIN_PUPDR_PULLDOWN(PI14) | \ + PIN_PUPDR_PULLDOWN(PI15)) + +#define VAL_GPIOI_ODR (PIN_ODR_LEVEL_LOW(PI00) | \ + PIN_ODR_LEVEL_LOW(PI01) | \ + PIN_ODR_LEVEL_LOW(PI02) | \ + PIN_ODR_LEVEL_LOW(PI03) | \ + PIN_ODR_LEVEL_LOW(PI04) | \ + PIN_ODR_LEVEL_LOW(PI05) | \ + PIN_ODR_LEVEL_LOW(PI06) | \ + PIN_ODR_LEVEL_LOW(PI07) | \ + PIN_ODR_LEVEL_LOW(PI08) | \ + PIN_ODR_LEVEL_LOW(PI09) | \ + PIN_ODR_LEVEL_LOW(PI10) | \ + PIN_ODR_LEVEL_LOW(PI11) | \ + PIN_ODR_LEVEL_LOW(PI12) | \ + PIN_ODR_LEVEL_LOW(PI13) | \ + PIN_ODR_LEVEL_LOW(PI14) | \ + PIN_ODR_LEVEL_LOW(PI15)) + +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(PI00, 0) | \ + PIN_AFIO_AF(PI01, 0) | \ + PIN_AFIO_AF(PI02, 0) | \ + PIN_AFIO_AF(PI03, 0) | \ + PIN_AFIO_AF(PI04, 0) | \ + PIN_AFIO_AF(PI05, 0) | \ + PIN_AFIO_AF(PI06, 0) | \ + PIN_AFIO_AF(PI07, 0)) + +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(PI08, 0) | \ + PIN_AFIO_AF(PI09, 0) | \ + PIN_AFIO_AF(PI10, 0) | \ + PIN_AFIO_AF(PI11, 0) | \ + PIN_AFIO_AF(PI12, 0) | \ + PIN_AFIO_AF(PI13, 0) | \ + PIN_AFIO_AF(PI14, 0) | \ + PIN_AFIO_AF(PI15, 0)) + +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(PJ00) | \ + PIN_MODE_INPUT(PJ01) | \ + PIN_MODE_INPUT(PJ02) | \ + PIN_MODE_INPUT(PJ03) | \ + PIN_MODE_INPUT(PJ04) | \ + PIN_MODE_INPUT(PJ05) | \ + PIN_MODE_INPUT(PJ06) | \ + PIN_MODE_INPUT(PJ07) | \ + PIN_MODE_INPUT(PJ08) | \ + PIN_MODE_INPUT(PJ09) | \ + PIN_MODE_INPUT(PJ10) | \ + PIN_MODE_INPUT(PJ11) | \ + PIN_MODE_INPUT(PJ12) | \ + PIN_MODE_INPUT(PJ13) | \ + PIN_MODE_INPUT(PJ14) | \ + PIN_MODE_INPUT(PJ15)) + +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(PJ00) | \ + PIN_OTYPE_PUSHPULL(PJ01) | \ + PIN_OTYPE_PUSHPULL(PJ02) | \ + PIN_OTYPE_PUSHPULL(PJ03) | \ + PIN_OTYPE_PUSHPULL(PJ04) | \ + PIN_OTYPE_PUSHPULL(PJ05) | \ + PIN_OTYPE_PUSHPULL(PJ06) | \ + PIN_OTYPE_PUSHPULL(PJ07) | \ + PIN_OTYPE_PUSHPULL(PJ08) | \ + PIN_OTYPE_PUSHPULL(PJ09) | \ + PIN_OTYPE_PUSHPULL(PJ10) | \ + PIN_OTYPE_PUSHPULL(PJ11) | \ + PIN_OTYPE_PUSHPULL(PJ12) | \ + PIN_OTYPE_PUSHPULL(PJ13) | \ + PIN_OTYPE_PUSHPULL(PJ14) | \ + PIN_OTYPE_PUSHPULL(PJ15)) + +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PJ00) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ01) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ02) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ03) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ04) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ05) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ06) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ07) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ08) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ09) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ10) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ11) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ12) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ13) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ14) | \ + PIN_OSPEED_SPEED_VERYLOW(PJ15)) + +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLDOWN(PJ00) | \ + PIN_PUPDR_PULLDOWN(PJ01) | \ + PIN_PUPDR_PULLDOWN(PJ02) | \ + PIN_PUPDR_PULLDOWN(PJ03) | \ + PIN_PUPDR_PULLDOWN(PJ04) | \ + PIN_PUPDR_PULLDOWN(PJ05) | \ + PIN_PUPDR_PULLDOWN(PJ06) | \ + PIN_PUPDR_PULLDOWN(PJ07) | \ + PIN_PUPDR_PULLDOWN(PJ08) | \ + PIN_PUPDR_PULLDOWN(PJ09) | \ + PIN_PUPDR_PULLDOWN(PJ10) | \ + PIN_PUPDR_PULLDOWN(PJ11) | \ + PIN_PUPDR_PULLDOWN(PJ12) | \ + PIN_PUPDR_PULLDOWN(PJ13) | \ + PIN_PUPDR_PULLDOWN(PJ14) | \ + PIN_PUPDR_PULLDOWN(PJ15)) + +#define VAL_GPIOJ_ODR (PIN_ODR_LEVEL_LOW(PJ00) | \ + PIN_ODR_LEVEL_LOW(PJ01) | \ + PIN_ODR_LEVEL_LOW(PJ02) | \ + PIN_ODR_LEVEL_LOW(PJ03) | \ + PIN_ODR_LEVEL_LOW(PJ04) | \ + PIN_ODR_LEVEL_LOW(PJ05) | \ + PIN_ODR_LEVEL_LOW(PJ06) | \ + PIN_ODR_LEVEL_LOW(PJ07) | \ + PIN_ODR_LEVEL_LOW(PJ08) | \ + PIN_ODR_LEVEL_LOW(PJ09) | \ + PIN_ODR_LEVEL_LOW(PJ10) | \ + PIN_ODR_LEVEL_LOW(PJ11) | \ + PIN_ODR_LEVEL_LOW(PJ12) | \ + PIN_ODR_LEVEL_LOW(PJ13) | \ + PIN_ODR_LEVEL_LOW(PJ14) | \ + PIN_ODR_LEVEL_LOW(PJ15)) + +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(PJ00, 0) | \ + PIN_AFIO_AF(PJ01, 0) | \ + PIN_AFIO_AF(PJ02, 0) | \ + PIN_AFIO_AF(PJ03, 0) | \ + PIN_AFIO_AF(PJ04, 0) | \ + PIN_AFIO_AF(PJ05, 0) | \ + PIN_AFIO_AF(PJ06, 0) | \ + PIN_AFIO_AF(PJ07, 0)) + +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(PJ08, 0) | \ + PIN_AFIO_AF(PJ09, 0) | \ + PIN_AFIO_AF(PJ10, 0) | \ + PIN_AFIO_AF(PJ11, 0) | \ + PIN_AFIO_AF(PJ12, 0) | \ + PIN_AFIO_AF(PJ13, 0) | \ + PIN_AFIO_AF(PJ14, 0) | \ + PIN_AFIO_AF(PJ15, 0)) + +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(PK00) | \ + PIN_MODE_INPUT(PK01) | \ + PIN_MODE_INPUT(PK02) | \ + PIN_MODE_INPUT(PK03) | \ + PIN_MODE_INPUT(PK04) | \ + PIN_MODE_INPUT(PK05) | \ + PIN_MODE_INPUT(PK06) | \ + PIN_MODE_INPUT(PK07) | \ + PIN_MODE_INPUT(PK08) | \ + PIN_MODE_INPUT(PK09) | \ + PIN_MODE_INPUT(PK10) | \ + PIN_MODE_INPUT(PK11) | \ + PIN_MODE_INPUT(PK12) | \ + PIN_MODE_INPUT(PK13) | \ + PIN_MODE_INPUT(PK14) | \ + PIN_MODE_INPUT(PK15)) + +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(PK00) | \ + PIN_OTYPE_PUSHPULL(PK01) | \ + PIN_OTYPE_PUSHPULL(PK02) | \ + PIN_OTYPE_PUSHPULL(PK03) | \ + PIN_OTYPE_PUSHPULL(PK04) | \ + PIN_OTYPE_PUSHPULL(PK05) | \ + PIN_OTYPE_PUSHPULL(PK06) | \ + PIN_OTYPE_PUSHPULL(PK07) | \ + PIN_OTYPE_PUSHPULL(PK08) | \ + PIN_OTYPE_PUSHPULL(PK09) | \ + PIN_OTYPE_PUSHPULL(PK10) | \ + PIN_OTYPE_PUSHPULL(PK11) | \ + PIN_OTYPE_PUSHPULL(PK12) | \ + PIN_OTYPE_PUSHPULL(PK13) | \ + PIN_OTYPE_PUSHPULL(PK14) | \ + PIN_OTYPE_PUSHPULL(PK15)) + +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PK00) | \ + PIN_OSPEED_SPEED_VERYLOW(PK01) | \ + PIN_OSPEED_SPEED_VERYLOW(PK02) | \ + PIN_OSPEED_SPEED_VERYLOW(PK03) | \ + PIN_OSPEED_SPEED_VERYLOW(PK04) | \ + PIN_OSPEED_SPEED_VERYLOW(PK05) | \ + PIN_OSPEED_SPEED_VERYLOW(PK06) | \ + PIN_OSPEED_SPEED_VERYLOW(PK07) | \ + PIN_OSPEED_SPEED_VERYLOW(PK08) | \ + PIN_OSPEED_SPEED_VERYLOW(PK09) | \ + PIN_OSPEED_SPEED_VERYLOW(PK10) | \ + PIN_OSPEED_SPEED_VERYLOW(PK11) | \ + PIN_OSPEED_SPEED_VERYLOW(PK12) | \ + PIN_OSPEED_SPEED_VERYLOW(PK13) | \ + PIN_OSPEED_SPEED_VERYLOW(PK14) | \ + PIN_OSPEED_SPEED_VERYLOW(PK15)) + +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLDOWN(PK00) | \ + PIN_PUPDR_PULLDOWN(PK01) | \ + PIN_PUPDR_PULLDOWN(PK02) | \ + PIN_PUPDR_PULLDOWN(PK03) | \ + PIN_PUPDR_PULLDOWN(PK04) | \ + PIN_PUPDR_PULLDOWN(PK05) | \ + PIN_PUPDR_PULLDOWN(PK06) | \ + PIN_PUPDR_PULLDOWN(PK07) | \ + PIN_PUPDR_PULLDOWN(PK08) | \ + PIN_PUPDR_PULLDOWN(PK09) | \ + PIN_PUPDR_PULLDOWN(PK10) | \ + PIN_PUPDR_PULLDOWN(PK11) | \ + PIN_PUPDR_PULLDOWN(PK12) | \ + PIN_PUPDR_PULLDOWN(PK13) | \ + PIN_PUPDR_PULLDOWN(PK14) | \ + PIN_PUPDR_PULLDOWN(PK15)) + +#define VAL_GPIOK_ODR (PIN_ODR_LEVEL_LOW(PK00) | \ + PIN_ODR_LEVEL_LOW(PK01) | \ + PIN_ODR_LEVEL_LOW(PK02) | \ + PIN_ODR_LEVEL_LOW(PK03) | \ + PIN_ODR_LEVEL_LOW(PK04) | \ + PIN_ODR_LEVEL_LOW(PK05) | \ + PIN_ODR_LEVEL_LOW(PK06) | \ + PIN_ODR_LEVEL_LOW(PK07) | \ + PIN_ODR_LEVEL_LOW(PK08) | \ + PIN_ODR_LEVEL_LOW(PK09) | \ + PIN_ODR_LEVEL_LOW(PK10) | \ + PIN_ODR_LEVEL_LOW(PK11) | \ + PIN_ODR_LEVEL_LOW(PK12) | \ + PIN_ODR_LEVEL_LOW(PK13) | \ + PIN_ODR_LEVEL_LOW(PK14) | \ + PIN_ODR_LEVEL_LOW(PK15)) + +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(PK00, 0) | \ + PIN_AFIO_AF(PK01, 0) | \ + PIN_AFIO_AF(PK02, 0) | \ + PIN_AFIO_AF(PK03, 0) | \ + PIN_AFIO_AF(PK04, 0) | \ + PIN_AFIO_AF(PK05, 0) | \ + PIN_AFIO_AF(PK06, 0) | \ + PIN_AFIO_AF(PK07, 0)) + +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(PK08, 0) | \ + PIN_AFIO_AF(PK09, 0) | \ + PIN_AFIO_AF(PK10, 0) | \ + PIN_AFIO_AF(PK11, 0) | \ + PIN_AFIO_AF(PK12, 0) | \ + PIN_AFIO_AF(PK13, 0) | \ + PIN_AFIO_AF(PK14, 0) | \ + PIN_AFIO_AF(PK15, 0)) + +#define AF_OTG_FS_DM 10U +#define AF_LINE_OTG_FS_DM 10U +#define AF_OTG_FS_DP 10U +#define AF_LINE_OTG_FS_DP 10U +#define AF_SWDIO 0U +#define AF_LINE_SWDIO 0U +#define AF_SWCLK 0U +#define AF_LINE_SWCLK 0U +#define AF_SPI1_SCK 5U +#define AF_LINE_SPI1_SCK 5U +#define AF_SPI1_MISO 5U +#define AF_LINE_SPI1_MISO 5U +#define AF_SPI1_MOSI 5U +#define AF_LINE_SPI1_MOSI 5U +#define AF_USART1_TX 7U +#define AF_LINE_USART1_TX 7U +#define AF_USART1_RX 7U +#define AF_LINE_USART1_RX 7U +#define AF_I2C1_SCL 4U +#define AF_LINE_I2C1_SCL 4U +#define AF_I2C1_SDA 4U +#define AF_LINE_I2C1_SDA 4U +#define AF_I2C2_SCL 4U +#define AF_LINE_I2C2_SCL 4U +#define AF_I2C2_SDA 4U +#define AF_LINE_I2C2_SDA 4U +#define AF_SDMMC1_D0 12U +#define AF_LINE_SDMMC1_D0 12U +#define AF_SDMMC1_D1 12U +#define AF_LINE_SDMMC1_D1 12U +#define AF_SDMMC1_D2 12U +#define AF_LINE_SDMMC1_D2 12U +#define AF_SDMMC1_D3 12U +#define AF_LINE_SDMMC1_D3 12U +#define AF_SDMMC1_CK 12U +#define AF_LINE_SDMMC1_CK 12U +#define AF_OSC32_IN 0U +#define AF_LINE_OSC32_IN 0U +#define AF_OSC32_OUT 0U +#define AF_LINE_OSC32_OUT 0U +#define AF_CAN1_RX 9U +#define AF_LINE_CAN1_RX 9U +#define AF_CAN1_TX 9U +#define AF_LINE_CAN1_TX 9U +#define AF_SDMMC1_CMD 12U +#define AF_LINE_SDMMC1_CMD 12U +#define AF_USART3_TX 7U +#define AF_LINE_USART3_TX 7U +#define AF_USART3_RX 7U +#define AF_LINE_USART3_RX 7U +#define AF_UART8_RX 8U +#define AF_LINE_UART8_RX 8U +#define AF_UART8_TX 8U +#define AF_LINE_UART8_TX 8U +#define AF_OSC_IN 0U +#define AF_LINE_OSC_IN 0U +#define AF_OSC_OUT 0U +#define AF_LINE_OSC_OUT 0U + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + diff --git a/sw/airborne/boards/chimera/chibios/v1.0/board.mk b/sw/airborne/boards/chimera/chibios/v1.0/board.mk new file mode 100644 index 00000000000..5a109515f46 --- /dev/null +++ b/sw/airborne/boards/chimera/chibios/v1.0/board.mk @@ -0,0 +1,20 @@ +# +# ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Required include directories +BOARDINC = $(CHIBIOS_BOARD_DIR) + +# List of all the board related files. +BOARDSRC = ${BOARDINC}/board.c diff --git a/sw/airborne/boards/chimera/chibios/v1.0/chimera.h b/sw/airborne/boards/chimera/chibios/v1.0/chimera.h new file mode 100644 index 00000000000..90b14d8dd1f --- /dev/null +++ b/sw/airborne/boards/chimera/chibios/v1.0/chimera.h @@ -0,0 +1,560 @@ +#ifndef CONFIG_CHIMERA_1_00_H +#define CONFIG_CHIMERA_1_00_H + +#define BOARD_CHIMERA + +/** + * ChibiOS board file + */ +#include "boards/chimera/chibios/v1.0/board.h" + +/** + * PPRZ definitions + */ + +/* + * AHB_CLK + */ +#define AHB_CLK STM32_HCLK + + +/* + * LEDs + */ +/* red, on PB12, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_1 +#define USE_LED_1 1 +#endif +#define LED_1_GPIO GPIOB +#define LED_1_GPIO_PIN GPIO12 +#define LED_1_GPIO_ON gpio_set +#define LED_1_GPIO_OFF gpio_clear + +/* orange, on PB13, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_2 +#define USE_LED_2 1 +#endif +#define LED_2_GPIO GPIOB +#define LED_2_GPIO_PIN GPIO13 +#define LED_2_GPIO_ON gpio_set +#define LED_2_GPIO_OFF gpio_clear + +/* green, on PD10, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_3 +#define USE_LED_3 1 +#endif +#define LED_3_GPIO GPIOD +#define LED_3_GPIO_PIN GPIO10 +#define LED_3_GPIO_ON gpio_set +#define LED_3_GPIO_OFF gpio_clear + +/* yellow, on PD11, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_4 +#define USE_LED_4 1 +#endif +#define LED_4_GPIO GPIOD +#define LED_4_GPIO_PIN GPIO11 +#define LED_4_GPIO_ON gpio_set +#define LED_4_GPIO_OFF gpio_clear + +/* AUX0, on PA5, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_5 +#define USE_LED_5 0 +#endif +#define LED_5_GPIO GPIOA +#define LED_5_GPIO_PIN GPIO5 +#define LED_5_GPIO_ON gpio_set +#define LED_5_GPIO_OFF gpio_clear + +/* AUX1, on PA3, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_6 +#define USE_LED_6 0 +#endif +#define LED_6_GPIO GPIOA +#define LED_6_GPIO_PIN GPIO3 +#define LED_6_GPIO_ON gpio_set +#define LED_6_GPIO_OFF gpio_clear + +/* AUX2, on PA2, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_7 +#define USE_LED_7 0 +#endif +#define LED_7_GPIO GPIOA +#define LED_7_GPIO_PIN GPIO2 +#define LED_7_GPIO_ON gpio_set +#define LED_7_GPIO_OFF gpio_clear + +/* AUX3, on PA0, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_8 +#define USE_LED_8 0 +#endif +#define LED_8_GPIO GPIOA +#define LED_8_GPIO_PIN GPIO0 +#define LED_8_GPIO_ON gpio_set +#define LED_8_GPIO_OFF gpio_clear + +/* AUX4, on PC3, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_9 +#define USE_LED_9 0 +#endif +#define LED_9_GPIO GPIOC +#define LED_9_GPIO_PIN GPIO3 +#define LED_9_GPIO_ON gpio_set +#define LED_9_GPIO_OFF gpio_clear + +/* AUX5, on PC2, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_10 +#define USE_LED_10 0 +#endif +#define LED_10_GPIO GPIOC +#define LED_10_GPIO_PIN GPIO2 +#define LED_10_GPIO_ON gpio_set +#define LED_10_GPIO_OFF gpio_clear + +/* AUX6, on PC6, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_11 +#define USE_LED_11 0 +#endif +#define LED_11_GPIO GPIOC +#define LED_11_GPIO_PIN GPIO6 +#define LED_11_GPIO_ON gpio_set +#define LED_11_GPIO_OFF gpio_clear + +/* AUX7, on PC7, 1 on LED_ON, 0 on LED_OFF */ +#ifndef USE_LED_12 +#define USE_LED_12 0 +#endif +#define LED_12_GPIO GPIOC +#define LED_12_GPIO_PIN GPIO7 +#define LED_12_GPIO_ON gpio_set +#define LED_12_GPIO_OFF gpio_clear + +/* + * ADCs + */ +// AUX 0 +#if USE_ADC_1 +#define AD1_1_CHANNEL ADC_CHANNEL_IN5 +#define ADC_1 AD1_1 +#define ADC_1_GPIO_PORT GPIOA +#define ADC_1_GPIO_PIN GPIO5 +#endif + +// AUX 0 +#if USE_ADC_2 +#define AD1_2_CHANNEL ADC_CHANNEL_IN2 +#define ADC_2 AD1_2 +#define ADC_2_GPIO_PORT GPIOA +#define ADC_2_GPIO_PIN GPIO2 +#endif + +// AUX 2 +#if USE_ADC_3 +#define AD1_3_CHANNEL ADC_CHANNEL_IN2 +#define ADC_3 AD1_3 +#define ADC_3_GPIO_PORT GPIOA +#define ADC_3_GPIO_PIN GPIO3 +#endif + +// AUX 3 +#if USE_ADC_4 +#define AD1_4_CHANNEL ADC_CHANNEL_IN0 +#define ADC_4 AD1_4 +#define ADC_4_GPIO_PORT GPIOA +#define ADC_4_GPIO_PIN GPIO0 +#endif + +// AUX 4 +#if USE_ADC_5 +#define AD1_5_CHANNEL ADC_CHANNEL_IN13 +#define ADC_5 AD1_5 +#define ADC_5_GPIO_PORT GPIOC +#define ADC_5_GPIO_PIN GPIO3 +#endif + +// AUX 5 +#if USE_ADC_6 +#define AD1_6_CHANNEL ADC_CHANNEL_IN12 +#define ADC_6 AD1_6 +#define ADC_6_GPIO_PORT GPIOC +#define ADC_6_GPIO_PIN GPIO2 +#endif + +// Internal ADC for battery enabled by default +#ifndef USE_ADC_7 +#define USE_ADC_7 1 +#endif +#if USE_ADC_7 +#define AD1_7_CHANNEL ADC_CHANNEL_IN4 +#define ADC_7 AD1_7 +#define ADC_7_GPIO_PORT GPIOA +#define ADC_7_GPIO_PIN GPIO4 +#endif + +/* allow to define ADC_CHANNEL_VSUPPLY in the airframe file*/ +#ifndef ADC_CHANNEL_VSUPPLY +#define ADC_CHANNEL_VSUPPLY ADC_7 +#endif + +/* + * R1 = 3.3k + * R2 = 22k + * adc * (3.3 / 2^12) * ((R1 + R2) / R1) + */ +#define VBAT_R1 3300.0f +#define VBAT_R2 22000.0f +#define DefaultVoltageOfAdc(adc) ((3.3f/4096.0f)*((VBAT_R1+VBAT_R2)/VBAT_R1)*adc) + +//TODO configure DAC (ADC_1) + +/* + * PWM defines + */ +#ifndef USE_PWM0 +#define USE_PWM0 1 +#endif +#if USE_PWM0 +#define PWM_SERVO_0 0 +#define PWM_SERVO_0_GPIO GPIOA +#define PWM_SERVO_0_PIN GPIO6 +#define PWM_SERVO_0_AF GPIO_AF2 +#define PWM_SERVO_0_DRIVER PWMD3 +#define PWM_SERVO_0_CHANNEL 0 +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM1 +#define USE_PWM1 1 +#endif +#if USE_PWM1 +#define PWM_SERVO_1 1 +#define PWM_SERVO_1_GPIO GPIOA +#define PWM_SERVO_1_PIN GPIO7 +#define PWM_SERVO_1_AF GPIO_AF2 +#define PWM_SERVO_1_DRIVER PWMD3 +#define PWM_SERVO_1_CHANNEL 1 +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM2 +#define USE_PWM2 1 +#endif +#if USE_PWM2 +#define PWM_SERVO_2 2 +#define PWM_SERVO_2_GPIO GPIOB +#define PWM_SERVO_2_PIN GPIO0 +#define PWM_SERVO_2_AF GPIO_AF2 +#define PWM_SERVO_2_DRIVER PWMD3 +#define PWM_SERVO_2_CHANNEL 2 +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM3 +#define USE_PWM3 1 +#endif +#if USE_PWM3 +#define PWM_SERVO_3 3 +#define PWM_SERVO_3_GPIO GPIOB +#define PWM_SERVO_3_PIN GPIO1 +#define PWM_SERVO_3_AF GPIO_AF2 +#define PWM_SERVO_3_DRIVER PWMD3 +#define PWM_SERVO_3_CHANNEL 3 +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM4 +#define USE_PWM4 1 +#endif +#if USE_PWM4 +#define PWM_SERVO_4 4 +#define PWM_SERVO_4_GPIO GPIOD +#define PWM_SERVO_4_PIN GPIO12 +#define PWM_SERVO_4_AF GPIO_AF2 +#define PWM_SERVO_4_DRIVER PWMD4 +#define PWM_SERVO_4_CHANNEL 0 +#define PWM_SERVO_4_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_4_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM5 +#define USE_PWM5 1 +#endif +#if USE_PWM5 +#define PWM_SERVO_5 5 +#define PWM_SERVO_5_GPIO GPIOD +#define PWM_SERVO_5_PIN GPIO13 +#define PWM_SERVO_5_AF GPIO_AF2 +#define PWM_SERVO_5_DRIVER PWMD4 +#define PWM_SERVO_5_CHANNEL 1 +#define PWM_SERVO_5_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_5_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM6 +#define USE_PWM6 1 +#endif +#if USE_PWM6 +#define PWM_SERVO_6 6 +#define PWM_SERVO_6_GPIO GPIOD +#define PWM_SERVO_6_PIN GPIO14 +#define PWM_SERVO_6_AF GPIO_AF2 +#define PWM_SERVO_6_DRIVER PWMD4 +#define PWM_SERVO_6_CHANNEL 2 +#define PWM_SERVO_6_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_6_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM6 +#define USE_PWM6 1 +#endif +#if USE_PWM7 +#define PWM_SERVO_7 7 +#define PWM_SERVO_7_GPIO GPIOD +#define PWM_SERVO_7_PIN GPIO15 +#define PWM_SERVO_7_AF GPIO_AF2 +#define PWM_SERVO_7_DRIVER PWMD4 +#define PWM_SERVO_7_CHANNEL 3 +#define PWM_SERVO_7_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_7_ACTIVE PWM_OUTPUT_DISABLED +#endif + +// TODO PWM on AUX pins + +#ifdef STM32_PWM_USE_TIM3 +#define PWM_CONF_TIM3 STM32_PWM_USE_TIM3 +#else +#define PWM_CONF_TIM3 1 +#endif +#define PWM_CONF3_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM3_SERVO_HZ, \ + NULL, \ + { \ + { PWM_SERVO_0_ACTIVE, NULL }, \ + { PWM_SERVO_1_ACTIVE, NULL }, \ + { PWM_SERVO_2_ACTIVE, NULL }, \ + { PWM_SERVO_3_ACTIVE, NULL }, \ + }, \ + 0, \ + 0 \ +} + +#ifdef STM32_PWM_USE_TIM4 +#define PWM_CONF_TIM4 STM32_PWM_USE_TIM4 +#else +#define PWM_CONF_TIM4 1 +#endif +#define PWM_CONF4_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM4_SERVO_HZ, \ + NULL, \ + { \ + { PWM_SERVO_4_ACTIVE, NULL }, \ + { PWM_SERVO_5_ACTIVE, NULL }, \ + { PWM_SERVO_6_ACTIVE, NULL }, \ + { PWM_SERVO_7_ACTIVE, NULL }, \ + }, \ + 0, \ + 0 \ +} + +/** + * UART2 (with optional flow control activated by default) + */ +#define UART2_GPIO_PORT_TX GPIOD +#define UART2_GPIO_TX GPIO5 +#define UART2_GPIO_PORT_RX GPIOD +#define UART2_GPIO_RX GPIO6 +#define UART2_GPIO_AF 7 +#ifndef UART2_HW_FLOW_CONTROL +#define UART2_HW_FLOW_CONTROL TRUE +#endif + +/** + * UART3 (XBee slot), UART8 (GPS) and UART1 (Companion) + * are configured as UART from ChibiOS board file + */ + +/** + * SBUS + * + * primary SBUS port is UART7, a.k.a. RC2 on Chimera board + * secondary port (in dual driver) is UART4, a.k.a. RC1 on Chimera board + */ + +// In case, do dynamic config of UARTs +#define USE_UART7_RX TRUE +#ifndef USE_UART7_TX // may be used in half duplex mode +#define USE_UART7_TX FALSE +#endif +#define UART7_GPIO_PORT_RX GPIOE +#define UART7_GPIO_RX GPIO7 +#define UART7_GPIO_AF 8 + +#define USE_UART4_RX TRUE +#define USE_UART4_TX FALSE +#define UART4_GPIO_PORT_RX GPIOE +#define UART4_GPIO_RX GPIO7 +#define UART4_GPIO_AF 8 + +/* + * Spektrum + * + * Not supported yet in chibios arch + * Only here for future reference + * + * primary Spektrum port is UART4, a.k.a. RC1 on Chimera board + * secondary port is UART7, a.k.a. RC2 on Chimera board + */ +/* The line that is pulled low at power up to initiate the bind process */ +/* These are not common between versions of lisa/mx and thus defined in the + * version specific header files. */ +#define SPEKTRUM_UART4_BANK UART4_GPIO_PORT_RX +#define SPEKTRUM_UART4_PIN UART4_GPIO_RX +#define SPEKTRUM_UART4_AF UART4_GPIO_AF +#define SPEKTRUM_UART4_DEV SD4 + +#define SPEKTRUM_UART7_BANK UART7_GPIO_PORT_RX +#define SPEKTRUM_UART7_PIN UART7_GPIO_RX +#define SPEKTRUM_UART7_AF UART7_GPIO_AF +#define SPEKTRUM_UART7_DEV SD7 + +/** + * PPM radio defines + * + * available on RC1 + */ +#define RC_PPM_TICKS_PER_USEC 6 +#define PPM_TIMER_FREQUENCY 6000000 +#define PPM_CHANNEL ICU_CHANNEL_2 +#define PPM_TIMER ICUD5 + +/* + * PWM input + */ +// PWM_INPUT 1 on PA0 (AUX3) +#define PWM_INPUT1_ICU ICUD2 +#define PWM_INPUT1_CHANNEL ICU_CHANNEL_1 +#define PWM_INPUT1_GPIO_PORT GPIOA +#define PWM_INPUT1_GPIO_PIN GPIO0 +#define PWM_INPUT1_GPIO_AF GPIO_AF1 + +// PWM_INPUT 2 on PC7 (AUX7) +#define PWM_INPUT2_ICU ICUD8 +#define PWM_INPUT2_CHANNEL ICU_CHANNEL_2 +#define PWM_INPUT2_GPIO_PORT GPIOC +#define PWM_INPUT2_GPIO_PIN GPIO7 +#define PWM_INPUT2_GPIO_AF GPIO_AF3 + +/** + * I2C defines + */ +// Digital noise filter: 0 disabled, [0x1 - 0xF] enable up to n t_I2CCLK +#define STM32_CR1_DNF(n) ((n & 0x0f) << 8) +// Timing register +#define I2C_FAST_400KHZ_DNF0_100NS_PCLK54MHZ_TIMINGR (STM32_TIMINGR_PRESC(0U) | \ + STM32_TIMINGR_SCLDEL(10U) | STM32_TIMINGR_SDADEL(0U) | \ + STM32_TIMINGR_SCLH(34U) | STM32_TIMINGR_SCLL(86U)) + +#define I2C1_CLOCK_SPEED 400000 +#define I2C1_CFG_DEF { \ + .timingr = I2C_FAST_400KHZ_DNF0_100NS_PCLK54MHZ_TIMINGR, \ + .cr1 = STM32_CR1_DNF(0), \ + .cr2 = 0 \ +} + +#define I2C2_CLOCK_SPEED 400000 +#define I2C2_CFG_DEF { \ + .timingr = I2C_FAST_400KHZ_DNF0_100NS_PCLK54MHZ_TIMINGR, \ + .cr1 = STM32_CR1_DNF(0), \ + .cr2 = 0 \ +} + +/** + * SPI Config + */ +#define SPI1_GPIO_AF GPIO_AF5 +#define SPI1_GPIO_PORT_MISO GPIOB +#define SPI1_GPIO_MISO GPIO4 +#define SPI1_GPIO_PORT_MOSI GPIOB +#define SPI1_GPIO_MOSI GPIO5 +#define SPI1_GPIO_PORT_SCK GPIO3 +#define SPI1_GPIO_SCK GPIO3 + +// SLAVE0 on SPI connector +#define SPI_SELECT_SLAVE0_PORT GPIOA +#define SPI_SELECT_SLAVE0_PIN GPIO15 +// SLAVE1 on AUX0 +#define SPI_SELECT_SLAVE1_PORT GPIOA +#define SPI_SELECT_SLAVE1_PIN GPIO5 +// SLAVE2 on AUX1 +#define SPI_SELECT_SLAVE2_PORT GPIOA +#define SPI_SELECT_SLAVE2_PIN GPIO3 +// SLAVE3 on AUX2 +#define SPI_SELECT_SLAVE3_PORT GPIOA +#define SPI_SELECT_SLAVE3_PIN GPIO2 +// SLAVE4 on AUX3 +#define SPI_SELECT_SLAVE4_PORT GPIOA +#define SPI_SELECT_SLAVE4_PIN GPIO0 +// SLAVE5 on AUX4 +#define SPI_SELECT_SLAVE5_PORT GPIOC +#define SPI_SELECT_SLAVE5_PIN GPIO3 + +/** + * Baro + * + * Apparently needed for backwards compatibility + * with the ancient onboard baro boards + */ +#ifndef USE_BARO_BOARD +#define USE_BARO_BOARD 1 +#endif + +/** + * SDIO + */ +#define SDIO_D0_PORT GPIOC +#define SDIO_D0_PIN GPIO8 +#define SDIO_D1_PORT GPIOC +#define SDIO_D1_PIN GPIO9 +#define SDIO_D2_PORT GPIOC +#define SDIO_D2_PIN GPIO10 +#define SDIO_D3_PORT GPIOC +#define SDIO_D3_PIN GPIO11 +#define SDIO_CK_PORT GPIOC +#define SDIO_CK_PIN GPIO12 +#define SDIO_CMD_PORT GPIOD +#define SDIO_CMD_PIN GPIO2 +#define SDIO_AF 12 +// bat monitoring for file closing +#define SDLOG_BAT_ADC ADCD1 +#define SDLOG_BAT_CHAN AD1_7_CHANNEL +// usb led status +#define SDLOG_USB_LED 4 +#define SDLOG_USB_VBUS_PORT GPIOA +#define SDLOG_USB_VBUS_PIN GPIO9 + + +/* + * Actuators for fixedwing + */ + /* Default actuators driver */ +#define DEFAULT_ACTUATORS "subsystems/actuators/actuators_pwm.h" +#define ActuatorDefaultSet(_x,_y) ActuatorPwmSet(_x,_y) +#define ActuatorsDefaultInit() ActuatorsPwmInit() +#define ActuatorsDefaultCommit() ActuatorsPwmCommit() + +#endif /* CONFIG_CHIMERA_1_00_H */ + diff --git a/sw/airborne/boards/chimera/chibios/v1.0/ffconf.h b/sw/airborne/boards/chimera/chibios/v1.0/ffconf.h new file mode 100644 index 00000000000..cd1c5cca30b --- /dev/null +++ b/sw/airborne/boards/chimera/chibios/v1.0/ffconf.h @@ -0,0 +1,239 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.10b (C)ChaN, 2014 +/---------------------------------------------------------------------------*/ + +#ifndef _FFCONF +#define _FFCONF 8051 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/---------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, it reduces memory consumption _MAX_SS bytes each +/ file object. For file data transfer, FatFs uses the common sector buffer in +/ the file system object (FATFS) instead of private sector buffer eliminated +/ from the file object (FIL). */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write(), f_sync(), f_unlink(), f_mkdir(), f_chmod(), +/ f_rename(), f_truncate() and useless f_getfree(). */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove API functions. +/ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(), +/ f_truncate() and f_rename() function are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define _USE_STRFUNC 2 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs() function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + +#define _USE_LABEL 0 /* 0:Disable or 1:Enable */ +/* To enable volume label functions, set _USE_LAVEL to 1 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward() function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift_JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII (Valid for only non-LFN configuration) */ + + +#define _USE_LFN 2 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN feature. +/ +/ 0: Disable LFN feature. _MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ When enable LFN feature, Unicode handling functions ff_convert() and ff_wtoupper() +/ function must be added to the project. +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. When use stack for the +/ working buffer, take care on stack overflow. When use heap memory for the working +/ buffer, memory management functions, ff_memalloc() and ff_memfree(), must be added +/ to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character encoding on the FatFs API (TCHAR) to Unicode, enable LFN +/ feature and set _LFN_UNICODE to 1. This option affects behavior of string I/O +/ functions. This option must be 0 when LFN feature is not enabled. */ + + +#define _STRF_ENCODE 3 /* 0:ANSI/OEM, 1:UTF-16LE, 2:UTF-16BE, 3:UTF-8 */ +/* When Unicode API is enabled by _LFN_UNICODE option, this option selects the character +/ encoding on the file to be read/written via string I/O functions, f_gets(), f_putc(), +/ f_puts and f_printf(). This option has no effect when Unicode API is not enabled. */ + + +#define _FS_RPATH 2 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() function are available. +/ 2: f_getcwd() function is available in addition to 1. +/ +/ Note that output of the f_readdir() fnction is affected by this option. */ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _STR_VOLUME_ID 0 /* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */ +#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3" +/* When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. _VOLUME_STRS defines the drive ID strings for each logical +/ drives. Number of items must be equal to _VOLUMES. Valid characters for the drive ID +/ strings are: 0-9 and A-Z. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Enable multiple partition */ +/* By default(0), each logical drive number is bound to the same physical drive number +/ and only a FAT volume found on the physical drive is mounted. When it is set to 1, +/ each logical drive number is bound to arbitrary drive/partition listed in VolToPart[]. +*/ + + +#define _MIN_SS 512 +#define _MAX_SS 512 +/* These options configure the range of sector size to be supported. (512, 1024, 2048 or +/ 4096) Always set both 512 for most systems, all memory card and harddisk. But a larger +/ value may be required for on-board flash memory and some type of optical media. +/ When _MAX_SS is larger than _MIN_SS, FatFs is configured to variable sector size and +/ GET_SECTOR_SIZE command must be implemented to the disk_ioctl() function. */ + + +#define _USE_ERASE 1 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. Also CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl() function. */ + + +#define _FS_NOFSINFO 0 /* 0 to 3 */ +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this option +/ and f_getfree() function at first time after volume mount will force a full FAT scan. +/ Bit 1 controls the last allocated cluster number as bit 0. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT MS2ST(1000) /* Timeout period in unit of time tick */ +#define _SYNC_t semaphore_t* /* O/S dependent sync object type. e.g. HANDLE, OS_EVENT*, ID, SemaphoreHandle_t and etc.. */ +/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs module. +/ +/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function must be added to the project. +*/ + + +#define _WORD_ACCESS 1 /* 0 or 1 */ +/* The _WORD_ACCESS option is an only platform dependent option. It defines +/ which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. Always compatible with all platforms. +/ 1: Word access. Do not choose this unless under both the following conditions. +/ +/ * Address misaligned memory access is always allowed for ALL instructions. +/ * Byte order on the memory is little-endian. +/ +/ If it is the case, _WORD_ACCESS can also be set to 1 to improve performance and +/ reduce code size. Following table shows an example of some processor types. +/ +/ ARM7TDMI 0 ColdFire 0 V850E2 0 +/ Cortex-M3 0 Z80 0/1 V850ES 0/1 +/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1 +/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1 +/ AVR32 0 RL78 0 R32C 0 +/ PIC18 0/1 SH-2 0 M16C 0/1 +/ PIC24 0 H8S 0 MSP430 0 +/ PIC32 0 H8/300H 0 x86 0/1 +*/ + + + + +#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */ +/* To enable file lock control feature, set _FS_LOCK to non-zero value. +/ The value defines how many files/sub-directories can be opened simultaneously +/ with file lock control. This feature uses bss _FS_LOCK * 12 bytes. +/ +/ IMPORTANT NOTE: +/ For Paparazzi, we don't need file locking since all file are written sequentially +/ from one thread (thdSdLog) +/ +*/ + + + +#endif /* _FFCONF */ diff --git a/sw/airborne/boards/chimera/chibios/v1.0/mcuconf.h b/sw/airborne/boards/chimera/chibios/v1.0/mcuconf.h new file mode 100644 index 00000000000..d19af0de4f6 --- /dev/null +++ b/sw/airborne/boards/chimera/chibios/v1.0/mcuconf.h @@ -0,0 +1,472 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 16 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 // STM32_I2C1SEL_SYSCLK +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#if USE_CAN1 +#define STM32_CAN_USE_CAN1 TRUE +#else +#define STM32_CAN_USE_CAN1 FALSE +#endif +#if USE_CAN2 +#define STM32_CAN_USE_CAN2 TRUE +#else +#define STM32_CAN_USE_CAN2 FALSE +#endif +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#if USE_DAC1 +#define STM32_DAC_USE_DAC1_CH2 TRUE +#else +#define STM32_DAC_USE_DAC1_CH2 FALSE +#endif +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +//#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE // keep free if in tickless mode +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#if USE_I2C1 +#define STM32_I2C_USE_I2C1 TRUE +#else +#define STM32_I2C_USE_I2C1 FALSE +#endif +#if USE_I2C2 // CAN or I2C2 because of dma conflict +#define STM32_I2C_USE_I2C2 TRUE +#else +#define STM32_I2C_USE_I2C2 FALSE +#endif +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +//#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#ifdef USE_PWM_INPUT1 +#define STM32_ICU_USE_TIM2 TRUE +#else +#define STM32_ICU_USE_TIM2 FALSE // keep free if in tickless mode +#endif +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#if RADIO_CONTROL_TYPE_PPM +#define STM32_ICU_USE_TIM5 TRUE +#else +#define STM32_ICU_USE_TIM5 FALSE +#endif +#ifdef USE_PWM_INPUT2 +#define STM32_ICU_USE_TIM8 TRUE +#else +#define STM32_ICU_USE_TIM8 FALSE +#endif +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#ifndef STM32_PWM_USE_TIM2 +#define STM32_PWM_USE_TIM2 FALSE // keep free if in tickless mode, can be used in systick mode +#endif +#ifndef STM32_PWM_USE_TIM3 +#define STM32_PWM_USE_TIM3 TRUE +#endif +#ifndef STM32_PWM_USE_TIM4 +#define STM32_PWM_USE_TIM4 TRUE +#endif +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#if USE_UART1 +#define STM32_SERIAL_USE_USART1 TRUE +#else +#define STM32_SERIAL_USE_USART1 FALSE +#endif +#if USE_UART2 +#define STM32_SERIAL_USE_USART2 TRUE +#else +#define STM32_SERIAL_USE_USART2 FALSE +#endif +#if USE_UART3 +#define STM32_SERIAL_USE_USART3 TRUE +#else +#define STM32_SERIAL_USE_USART3 FALSE +#endif +#if USE_UART4 +#define STM32_SERIAL_USE_UART4 TRUE +#else +#define STM32_SERIAL_USE_UART4 FALSE +#endif +#if USE_UART5 +#define STM32_SERIAL_USE_UART5 TRUE +#else +#define STM32_SERIAL_USE_UART5 FALSE +#endif +#if USE_UART6 +#define STM32_SERIAL_USE_USART6 TRUE +#else +#define STM32_SERIAL_USE_USART6 FALSE +#endif +#if USE_UART7 +#define STM32_SERIAL_USE_UART7 TRUE +#else +#define STM32_SERIAL_USE_UART7 FALSE +#endif +#if USE_UART8 +#define STM32_SERIAL_USE_UART8 TRUE +#else +#define STM32_SERIAL_USE_UART8 FALSE +#endif +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#if USE_SPI1 +#define STM32_SPI_USE_SPI1 TRUE +#else +#define STM32_SPI_USE_SPI1 FALSE +#endif +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +//#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE /* DMA OK */ +#define STM32_UART_USE_USART2 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_USART3 FALSE /* DMA OK */ +#define STM32_UART_USE_UART4 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_UART5 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_USART6 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_UART7 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USE_UART8 FALSE /* NO DMA AVAIL */ +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +/* #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) */ +/* #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */ +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +/* #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) */ +/* #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) */ +/* #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */ +/* #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) */ +/* #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) */ +/* #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) */ +/* #define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) */ +/* #define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) */ +/* #define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */ +/* #define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */ +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 TRUE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* sdlog message buffer and queue configuration + */ +#define SDLOG_QUEUE_BUCKETS 512 +#define SDLOG_ALL_BUFFERS_SIZE 8192 +#define SDLOG_MAX_MESSAGE_LEN 252 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + + +//#define CH_HEAP_SIZE (32*1024) +//#define CH_HEAP_USE_TLSF 1 // if 0 or undef, chAlloc will be used + + + +#endif /* _MCUCONF_H_ */ diff --git a/sw/airborne/mcu_periph/uart.c b/sw/airborne/mcu_periph/uart.c index 3e3ffefaeba..c5d34c32611 100644 --- a/sw/airborne/mcu_periph/uart.c +++ b/sw/airborne/mcu_periph/uart.c @@ -296,3 +296,7 @@ void WEAK uart_arch_init(void) { } +void WEAK uart_periph_invert_data_logic(struct uart_periph *p __attribute__((unused)), bool invert_rx __attribute__((unused)), bool invert_tx __attribute__((unused))) +{ +} + diff --git a/sw/airborne/mcu_periph/uart.h b/sw/airborne/mcu_periph/uart.h index aa52b1ab495..dca304f3a9d 100644 --- a/sw/airborne/mcu_periph/uart.h +++ b/sw/airborne/mcu_periph/uart.h @@ -33,7 +33,7 @@ #include "std.h" #ifndef UART_RX_BUFFER_SIZE -#ifdef STM32F4 //the F4 has enough memory +#if defined STM32F4 || defined STM32F7 //the F4 and F7 have enough memory #define UART_RX_BUFFER_SIZE 256 #else #define UART_RX_BUFFER_SIZE 128 @@ -41,7 +41,7 @@ #endif #ifndef UART_TX_BUFFER_SIZE -#ifdef STM32F4 //the F4 has enough memory, and the PX4 bootloader needs more then 128 +#if defined STM32F4 || defined STM32F7 //the F4 and F7 have enough memory, and the PX4 bootloader needs more then 128 #define UART_TX_BUFFER_SIZE 256 #else #define UART_TX_BUFFER_SIZE 128 @@ -97,6 +97,7 @@ extern void uart_periph_init(struct uart_periph *p); extern void uart_periph_set_baudrate(struct uart_periph *p, uint32_t baud); extern void uart_periph_set_bits_stop_parity(struct uart_periph *p, uint8_t bits, uint8_t stop, uint8_t parity); extern void uart_periph_set_mode(struct uart_periph *p, bool tx_enabled, bool rx_enabled, bool hw_flow_control); +extern void uart_periph_invert_data_logic(struct uart_periph *p, bool invert_rx, bool invert_tx); extern void uart_put_byte(struct uart_periph *p, long fd, uint8_t data); extern void uart_put_buffer(struct uart_periph *p, long fd, const uint8_t *data, uint16_t len); extern bool uart_check_free_space(struct uart_periph *p, long *fd, uint16_t len); diff --git a/sw/airborne/modules/loggers/sdlog_chibios.c b/sw/airborne/modules/loggers/sdlog_chibios.c index 0d4a1c2b3cc..c61323e6d3b 100644 --- a/sw/airborne/modules/loggers/sdlog_chibios.c +++ b/sw/airborne/modules/loggers/sdlog_chibios.c @@ -32,10 +32,11 @@ #include "modules/loggers/sdlog_chibios.h" #include "modules/tlsf/tlsf_malloc.h" #include "mcu_periph/adc.h" +#include "mcu.h" #include "led.h" #if HAL_USE_RTC -#include +#include #include #include "subsystems/gps.h" #endif @@ -67,7 +68,6 @@ static __attribute__((noreturn)) void thd_startlog(void *arg); static THD_WORKING_AREA(wa_thd_bat_survey, 1024); static __attribute__((noreturn)) void thd_bat_survey(void *arg); static void powerOutageIsr (void); -static void systemDeepSleep (void); event_source_t powerOutageSource; event_listener_t powerOutageListener; @@ -235,13 +235,12 @@ static void thd_bat_survey(void *arg) chEvtRegister(&powerOutageSource, &powerOutageListener, 1); chThdSleepMilliseconds (2000); - // FIXME: &ADCD1 and channel AD1_4 should not be hardcoded like this - register_adc_watchdog(&ADCD1, AD1_4_CHANNEL, V_ALERT, &powerOutageIsr); + register_adc_watchdog(&SDLOG_BAT_ADC, SDLOG_BAT_CHAN, V_ALERT, &powerOutageIsr); chEvtWaitOne(EVENT_MASK(1)); sdlog_chibios_finish (true); chThdExit(0); - systemDeepSleep(); + mcu_deep_sleep(); chThdSleepMilliseconds (TIME_INFINITE); while (1); // never goes here, only to avoid compiler warning: 'noreturn' function does return } @@ -255,12 +254,3 @@ static void powerOutageIsr (void) chEvtBroadcastI(&powerOutageSource); } - -static void systemDeepSleep (void) -{ - chSysLock(); - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - PWR->CR |= (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF); - __WFE(); - chSysUnlock(); -} diff --git a/sw/airborne/modules/loggers/sdlog_chibios/printf.c b/sw/airborne/modules/loggers/sdlog_chibios/printf.c index 335c850a00f..fde4cffe661 100644 --- a/sw/airborne/modules/loggers/sdlog_chibios/printf.c +++ b/sw/airborne/modules/loggers/sdlog_chibios/printf.c @@ -191,7 +191,7 @@ static void _chvsnprintf(char *buffer, BaseSequentialStream *chp, size_t size, c return true; } } else if (chp != NULL) { - chSequentialStreamPut(chp, _c); + streamPut(chp, _c); return false; } return false; diff --git a/sw/airborne/modules/loggers/sdlog_chibios/printf.h b/sw/airborne/modules/loggers/sdlog_chibios/printf.h index 0abd8891fea..44cc577b233 100644 --- a/sw/airborne/modules/loggers/sdlog_chibios/printf.h +++ b/sw/airborne/modules/loggers/sdlog_chibios/printf.h @@ -30,6 +30,9 @@ #define _PRINTF_H_ #include +#include +#include + /** * @brief Float type support. */ diff --git a/sw/airborne/modules/loggers/sdlog_chibios/sdLog.c b/sw/airborne/modules/loggers/sdlog_chibios/sdLog.c index 961d21a8540..f21a7e30218 100644 --- a/sw/airborne/modules/loggers/sdlog_chibios/sdLog.c +++ b/sw/airborne/modules/loggers/sdlog_chibios/sdLog.c @@ -78,17 +78,25 @@ #ifdef SDLOG_NEED_QUEUE #include "modules/loggers/sdlog_chibios/msg_queue.h" -#if defined STM32F4XX -#define NODMA_SECTION ".ram4" -#define DMA_SECTION ".ram0" -#elif defined STM32F7XX -#define NODMA_SECTION ".ram0" -#define DMA_SECTION ".ram3" -#else -#error "section defined only for STM32F4 and STM32F7" -#endif +#include "mcu_periph/ram_arch.h" + +/* + The buffers that do DMA are the caches (named buf) in the FIL and FATFS struct of fatfs library + It's the only buffers that have to reside in DMA capable memory. + + The buffer associated with message queue, and the cache buffer for caching file write + could reside in non DMA capable memory. + + stm32f4 : regular sram : 128ko, dma, slow + ccm sram : 64ko, no_dma, fast -static msg_t queMbBuffer[SDLOG_QUEUE_BUCKETS] __attribute__((section(NODMA_SECTION), aligned(8))) ; + stm32f7 : regular sram : 256ko, dma only possible if data cache are explicitely flushed, fast + dtcm sram : 64ko, dma, slow (no cache) + */ + + + +static msg_t IN_STD_SECTION (queMbBuffer[SDLOG_QUEUE_BUCKETS]); static MsgQueue messagesQueue; #define WRITE_BYTE_CACHE_SIZE 15 // limit overhead : @@ -113,7 +121,7 @@ struct FilePoolUnit { uint8_t writeByteSeek; }; -static struct FilePoolUnit fileDes[SDLOG_NUM_BUFFER] = { +static struct FilePoolUnit IN_DMA_SECTION (fileDes[SDLOG_NUM_BUFFER]) = { [0 ... SDLOG_NUM_BUFFER - 1] = { .fil = {0}, .inUse = false, .tagAtClose = false, .writeByteCache = NULL, .writeByteSeek = 0 @@ -138,8 +146,8 @@ struct _SdLogBuffer { #define LOG_MESSAGE_PREBUF_LEN (SDLOG_MAX_MESSAGE_LEN+sizeof(LogMessage)) #endif // SDLOG_NEED_QUEUE - -static FATFS fatfs; /* File system object */ +/* File system object */ +static IN_DMA_SECTION (FATFS fatfs); #ifdef SDLOG_NEED_QUEUE static size_t logMessageLen(const LogMessage *lm); @@ -801,7 +809,7 @@ static msg_t thdSdLog(void *arg) } ; UINT bw; - static struct PerfBuffer perfBuffers[SDLOG_NUM_BUFFER] __attribute__((section(DMA_SECTION), aligned(8))) = { + static IN_STD_SECTION(struct PerfBuffer perfBuffers[SDLOG_NUM_BUFFER]) = { [0 ... SDLOG_NUM_BUFFER - 1] = {.buffer = {0}, .size = 0} }; diff --git a/sw/airborne/modules/loggers/sdlog_chibios/usbStorage.c b/sw/airborne/modules/loggers/sdlog_chibios/usbStorage.c index 370efb6355e..a843423f4d8 100644 --- a/sw/airborne/modules/loggers/sdlog_chibios/usbStorage.c +++ b/sw/airborne/modules/loggers/sdlog_chibios/usbStorage.c @@ -32,7 +32,9 @@ #include #include #include "main_chibios.h" +#include "mcu.h" #include "mcu_periph/sdio.h" +#include "led.h" static uint8_t nibbleToHex(uint8_t nibble); static void populateSerialNumberDescriptorData(void); @@ -44,8 +46,6 @@ static bool isRunning = false; /* endpoint index */ #define USB_MS_DATA_EP 1 -// cortex_m4 specific -#define MCU_RESTART() {*((unsigned long *)0x0E000ED0C) = 0x05FA0004;} /* USB device descriptor */ static const uint8_t deviceDescriptorData[] = { @@ -221,12 +221,13 @@ const USBConfig usbConfig = { }; /* Turns on a LED when there is I/O activity on the USB port */ -static void usbActivity(bool active) +static void usbActivity(bool active __attribute__((unused))) { -#ifdef GPIOC_LED4 - palWritePad(GPIOC, GPIOC_LED4, active); -#else - (void)active; +#ifdef SDLOG_USB_LED + if (active) + LED_ON(SDLOG_USB_LED); + else + LED_OFF(SDLOG_USB_LED); #endif } @@ -285,7 +286,7 @@ static void thdUsbStorage(void *arg) // Should be fixed when using chibios-rt branch // FIXME: Is the comment still relevant? while (!chThdShouldTerminateX() && antiBounce) { - const bool usbConnected = palReadPad(GPIOA, GPIOA_OTG_FS_VBUS); + const bool usbConnected = palReadPad(SDLOG_USB_VBUS_PORT, SDLOG_USB_VBUS_PIN); if (usbConnected) { antiBounce--; } else { @@ -326,7 +327,7 @@ static void thdUsbStorage(void *arg) pprz_terminate_autopilot_threads(); /* wait until usb-storage is unmount and usb cable is unplugged*/ - while (!chThdShouldTerminateX() && palReadPad(GPIOA, GPIOA_OTG_FS_VBUS)) { + while (!chThdShouldTerminateX() && palReadPad(SDLOG_USB_VBUS_PORT, SDLOG_USB_VBUS_PIN)) { chThdSleepMilliseconds(10); } @@ -337,7 +338,7 @@ static void thdUsbStorage(void *arg) msdStop(&UMSD1); sdio_disconnect(); - MCU_RESTART(); + mcu_reset(); return; } diff --git a/sw/airborne/subsystems/imu/imu_mpu9250_i2c.c b/sw/airborne/subsystems/imu/imu_mpu9250_i2c.c index 1fd4f52c217..b9cabc84f7f 100644 --- a/sw/airborne/subsystems/imu/imu_mpu9250_i2c.c +++ b/sw/airborne/subsystems/imu/imu_mpu9250_i2c.c @@ -83,6 +83,19 @@ PRINT_CONFIG_VAR(IMU_MPU9250_CHAN_Y) #endif PRINT_CONFIG_VAR(IMU_MPU9250_CHAN_Z) +#ifndef IMU_MPU9250_X_SIGN +#define IMU_MPU9250_X_SIGN 1 +#endif +PRINT_CONFIG_VAR(IMU_MPU9250_X_SIGN) +#ifndef IMU_MPU9250_Y_SIGN +#define IMU_MPU9250_Y_SIGN 1 +#endif +PRINT_CONFIG_VAR(IMU_MPU9250_Y_SIGN) +#ifndef IMU_MPU9250_Z_SIGN +#define IMU_MPU9250_Z_SIGN 1 +#endif +PRINT_CONFIG_VAR(IMU_MPU9250_Z_SIGN) + struct ImuMpu9250 imu_mpu9250; @@ -113,14 +126,14 @@ void imu_mpu9250_event(void) if (imu_mpu9250.mpu.data_available) { // set channel order struct Int32Vect3 accel = { - (int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_X]), - (int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_Y]), - (int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_Z]) + IMU_MPU9250_X_SIGN * (int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_X]), + IMU_MPU9250_Y_SIGN * (int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_Y]), + IMU_MPU9250_Z_SIGN * (int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_Z]) }; struct Int32Rates rates = { - (int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_X]), - (int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_Y]), - (int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_Z]) + IMU_MPU9250_X_SIGN * (int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_X]), + IMU_MPU9250_Y_SIGN * (int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_Y]), + IMU_MPU9250_Z_SIGN * (int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_Z]) }; // unscaled vector VECT3_COPY(imu.accel_unscaled, accel); @@ -137,9 +150,9 @@ void imu_mpu9250_event(void) // Test if mag data are updated if (imu_mpu9250.mpu.akm.data_available) { struct Int32Vect3 mag = { - (int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_Y]), - (int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_X]), - -(int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_Z]) + IMU_MPU9250_X_SIGN * (int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_Y]), + IMU_MPU9250_Y_SIGN * (int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_X]), + -IMU_MPU9250_Z_SIGN * (int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_Z]) }; VECT3_COPY(imu.mag_unscaled, mag); imu_mpu9250.mpu.akm.data_available = false; diff --git a/sw/airborne/subsystems/radio_control/sbus.c b/sw/airborne/subsystems/radio_control/sbus.c index a9dbb2663db..6fee69ee17a 100644 --- a/sw/airborne/subsystems/radio_control/sbus.c +++ b/sw/airborne/subsystems/radio_control/sbus.c @@ -28,6 +28,12 @@ #include "subsystems/radio_control/sbus.h" #include BOARD_CONFIG +#ifndef RC_POLARITY_GPIO_PORT +#define RC_POLARITY_GPIO_PORT 0 +#endif +#ifndef RC_POLARITY_GPIO_PIN +#define RC_POLARITY_GPIO_PIN 0 +#endif /** SBUS struct */ struct Sbus sbus; @@ -47,7 +53,7 @@ static void send_sbus(struct transport_tx *trans, struct link_device *dev) // Init function void radio_control_impl_init(void) { - sbus_common_init(&sbus, &SBUS_UART_DEV); + sbus_common_init(&sbus, &SBUS_UART_DEV, RC_POLARITY_GPIO_PORT, RC_POLARITY_GPIO_PIN); // Register telemetry message #if PERIODIC_TELEMETRY diff --git a/sw/airborne/subsystems/radio_control/sbus_common.c b/sw/airborne/subsystems/radio_control/sbus_common.c index 4f567017437..c6d6c64016d 100644 --- a/sw/airborne/subsystems/radio_control/sbus_common.c +++ b/sw/airborne/subsystems/radio_control/sbus_common.c @@ -26,7 +26,6 @@ #include "subsystems/radio_control.h" #include "subsystems/radio_control/sbus_common.h" #include BOARD_CONFIG -#include "mcu_periph/gpio.h" #include /* @@ -54,7 +53,8 @@ #endif -void sbus_common_init(struct Sbus *sbus_p, struct uart_periph *dev) +void sbus_common_init(struct Sbus *sbus_p, struct uart_periph *dev, + gpio_port_t gpio_polarity_port, uint16_t gpio_polarity_pin) { sbus_p->frame_available = false; sbus_p->status = SBUS_STATUS_UNINIT; @@ -62,12 +62,14 @@ void sbus_common_init(struct Sbus *sbus_p, struct uart_periph *dev) // Set UART parameters (100K, 8 bits, 2 stops, even parity) uart_periph_set_baudrate(dev, B100000); uart_periph_set_bits_stop_parity(dev, UBITS_8, USTOP_2, UPARITY_EVEN); + // Try to invert RX data logic when available in hardware periph + uart_periph_invert_data_logic(dev, true, false); - // Set polarity -#ifdef RC_POLARITY_GPIO_PORT - gpio_setup_output(RC_POLARITY_GPIO_PORT, RC_POLARITY_GPIO_PIN); - RC_SET_POLARITY(RC_POLARITY_GPIO_PORT, RC_POLARITY_GPIO_PIN); -#endif + // Set polarity (when not done in hardware, don't use both!) + if (gpio_polarity_port != 0) { + gpio_setup_output(gpio_polarity_port, gpio_polarity_pin); + RC_SET_POLARITY(gpio_polarity_port, gpio_polarity_pin); + } } @@ -76,36 +78,31 @@ void sbus_common_init(struct Sbus *sbus_p, struct uart_periph *dev) static void decode_sbus_buffer(const uint8_t *src, uint16_t *dst, bool *available, uint16_t *dstppm __attribute__((unused))) { - // reset counters - uint8_t byteInRawBuf = 0; - uint8_t bitInRawBuf = 0; - uint8_t channel = 0; - uint8_t bitInChannel = 0; - - // clear bits - memset(dst, 0, SBUS_NB_CHANNEL * sizeof(uint16_t)); - - // decode sbus data - for (uint8_t i = 0; i < (SBUS_NB_CHANNEL * SBUS_BIT_PER_CHANNEL); i++) { - if (src[byteInRawBuf] & (1 << bitInRawBuf)) { - dst[channel] |= (1 << bitInChannel); - } - - bitInRawBuf++; - bitInChannel++; - - if (bitInRawBuf == SBUS_BIT_PER_BYTE) { - bitInRawBuf = 0; - byteInRawBuf++; - } - if (bitInChannel == SBUS_BIT_PER_CHANNEL) { - bitInChannel = 0; + // decode sbus data, unrolling the loop for efficiency + dst[0] = ((src[0] ) | (src[1]<<8)) & 0x07FF; + dst[1] = ((src[1]>>3 ) | (src[2]<<5)) & 0x07FF; + dst[2] = ((src[2]>>6 ) | (src[3]<<2) | (src[4]<<10)) & 0x07FF; + dst[3] = ((src[4]>>1 ) | (src[5]<<7)) & 0x07FF; + dst[4] = ((src[5]>>4 ) | (src[6]<<4)) & 0x07FF; + dst[5] = ((src[6]>>7 ) | (src[7]<<1 ) | (src[8]<<9)) & 0x07FF; + dst[6] = ((src[8]>>2 ) | (src[9]<<6)) & 0x07FF; + dst[7] = ((src[9]>>5) | (src[10]<<3)) & 0x07FF; + dst[8] = ((src[11] ) | (src[12]<<8)) & 0x07FF; + dst[9] = ((src[12]>>3) | (src[13]<<5)) & 0x07FF; + dst[10] = ((src[13]>>6) | (src[14]<<2) | (src[15]<<10)) & 0x07FF; + dst[11] = ((src[15]>>1) | (src[16]<<7)) & 0x07FF; + dst[12] = ((src[16]>>4) | (src[17]<<4)) & 0x07FF; + dst[13] = ((src[17]>>7) | (src[18]<<1) | (src[19]<<9)) & 0x07FF; + dst[14] = ((src[19]>>2) | (src[20]<<6)) & 0x07FF; + dst[15] = ((src[20]>>5) | (src[21]<<3)) & 0x07FF; + + // convert sbus to ppm #if PERIODIC_TELEMETRY - dstppm[channel] = USEC_OF_RC_PPM_TICKS(dst[channel]); -#endif - channel++; - } + for (int channel=0; channel < SBUS_NB_CHANNEL; channel++) { + dstppm[channel] = USEC_OF_RC_PPM_TICKS(dst[channel]); } +#endif + // test frame lost flag *available = !bit_is_set(src[SBUS_FLAGS_BYTE], SBUS_FRAME_LOST_BIT); } diff --git a/sw/airborne/subsystems/radio_control/sbus_common.h b/sw/airborne/subsystems/radio_control/sbus_common.h index b47c5537b4c..cc0d042dea7 100644 --- a/sw/airborne/subsystems/radio_control/sbus_common.h +++ b/sw/airborne/subsystems/radio_control/sbus_common.h @@ -29,6 +29,7 @@ #include "std.h" #include "mcu_periph/uart.h" +#include "mcu_periph/gpio.h" /* in case you want to override RADIO_CONTROL_NB_CHANNEL */ #include "generated/airframe.h" @@ -87,7 +88,8 @@ struct Sbus { /** * Init function */ -void sbus_common_init(struct Sbus *sbus, struct uart_periph *dev); +void sbus_common_init(struct Sbus *sbus, struct uart_periph *dev, + gpio_port_t gpio_polarity_port, uint16_t gpio_polarity_pin); /** * Decoding event function diff --git a/sw/airborne/subsystems/radio_control/sbus_dual.c b/sw/airborne/subsystems/radio_control/sbus_dual.c index 84320c06439..c7e4c43334d 100644 --- a/sw/airborne/subsystems/radio_control/sbus_dual.c +++ b/sw/airborne/subsystems/radio_control/sbus_dual.c @@ -28,9 +28,21 @@ #include "subsystems/radio_control/sbus_dual.h" #include BOARD_CONFIG #include "mcu_periph/uart.h" -#include "mcu_periph/gpio.h" #include +#ifndef RC_POLARITY_GPIO_PORT +#define RC_POLARITY_GPIO_PORT 0 +#endif +#ifndef RC_POLARITY_GPIO_PIN +#define RC_POLARITY_GPIO_PIN 0 +#endif + +#ifndef RC2_POLARITY_GPIO_PORT +#define RC2_POLARITY_GPIO_PORT RC_POLARITY_GPIO_PORT +#endif +#ifndef RC2_POLARITY_GPIO_PIN +#define RC2_POLARITY_GPIO_PIN RC_POLARITY_GPIO_PIN +#endif /** SBUS struct */ struct Sbus sbus1, sbus2; @@ -50,8 +62,8 @@ static void send_sbus(struct transport_tx *trans, struct link_device *dev) // Init function void radio_control_impl_init(void) { - sbus_common_init(&sbus1, &SBUS1_UART_DEV); - sbus_common_init(&sbus2, &SBUS2_UART_DEV); + sbus_common_init(&sbus1, &SBUS1_UART_DEV, RC_POLARITY_GPIO_PORT, RC_POLARITY_GPIO_PIN); + sbus_common_init(&sbus2, &SBUS2_UART_DEV, RC2_POLARITY_GPIO_PORT, RC2_POLARITY_GPIO_PIN); // Register telemetry message #if PERIODIC_TELEMETRY diff --git a/sw/ext/chibios b/sw/ext/chibios index 024738d265b..0db56fc105f 160000 --- a/sw/ext/chibios +++ b/sw/ext/chibios @@ -1 +1 @@ -Subproject commit 024738d265bd3ef20dff3bb2809feabe3e24fb32 +Subproject commit 0db56fc105f39b7652254199e754fba58bb3b1f6