Flash scripts / instructions for Parallella board
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olajep env.txt: Set bootdelay to 0
If a serial cable is not attached, the missing pull-up resistor on the
RX pin can cause jitter. This can be interpreted as a key press by

Setting bootdelay to 0 prevents the board getting stuck at the uboot
prompt at boot, but it will also be impossible to stop the boot with a
key press.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Latest commit b24d65d Dec 19, 2016


Instructions for creating Parallella board flash images

WARNING: This is work in progress. Don't try this at home unless you have a Xilinx JTAG cable / Porcupine board at hand.


  • Use SPL in uboot
  • Create empty Parallella project with working I2C.
  • Export ps7_init* from that project to Parallella U-boot.
  • Generate bitstreams for z7010 and z7020.
  • Embed both bitstreams in boot image (there is room)
  • Load bitstream early in u-boot before calling power_init()
  • == one flash image for all boards.


File                      | Description
mkbootflash.sh            | Script that creates boot flash image.  
boot.bif                  | Boot image description  
version.bin               | Boot image version. Written into last 64 kb of  
                          | flash by flash.sh  
                          | See VERSION FORMAT for more info.  
BOOT.bin                  | Generated by bootgen, called from flash.sh.  
FSBL.elf                  | Generated by Xilinx SDK.  
elink2_top_wrapper.bit    | Bitstream generated by Xilinx Vivado.  
uboot.elf                 | U-boot image.  
env.txt                   | Default uboot environment
env.bin                   | Default uboot environment (generated)
uEnv.txt                  | Example 2nd stage boot script.  


TODO: Not sure if we need this. We can put it in the default uboot environment instead.

Little endian:

struct {
    u32 version; /* Running number starting with 1 */
    u32 magic;   /* 0x13371338 */
} __attribute__((packed));


  1. Download flash git repository
  2. Build U-BOOT
  3. Build bitstream in Xilinx Vivado and export hardware
  4. Generate FSBL in Xilinx SDK
  5. Increment version number in version.bin with your favorite hex editor
  6. Run mkbootflash.sh
  7. Run mkenvimage


Boot from SD-card if inserted, otherwise boot from TFTP.

SD-boot: If uEnv.txt is present on SD-card add its content to the environment and "run sdboot". Otherwise, use old boot method (hardcoded paths).

TFTP: Load uEnv.txt from server and "run tftpboot_stage2".

See uEnv.txt for an example script that probes the board model and loads the correct bitstream / devicetree / uImage and boots linux.

###1. Download flash git repository

$ git clone https://github.com/parallella/parallella-flash

###2. Build U-BOOT

$ git clone https://github.com/parallella/parallella-uboot --branch parallella-next
$ cd parallella-uboot
$ make adapteva_parallella_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabihf-
$ cp u-boot path/to/parallella-flash/u-boot.elf

###3. Build bitstream in Xilinx Vivado and export hardware

  1. Start Vivado
  2. Load elink project
  3. Build the bitstream for the FPGA on the board you want to flash
  4. Copy the bitstream to path.to/parallella-flash/elink2_top_wrapper.bit

File->Export->Export hardware
File->Launch SDK
Point it to the directory where you exported the hardware
Xilinx SDK starts.

###4. Generate FSBL in Xilinx SDK

  • File->New->Application Project
  • Set name to FSBL
  • Press next
  • Select the Zynq FSBL template
  • Press finish
  • Copy FSBL/Debug/FSBL.elf to path/to/parallella-flash

###5. Increment version number in version.bin with your favorite hex editor

TODO: Not sure if we need this. Could put it in environment instead.

###6. Run mkbootflash.sh

Run mkbootflash.sh to create boot flash image

###7. Run mkenvimage to generate environment (from uboot/tools)

mkenvimage -s 131072 -o env.bin env.txt

###8. Further You now have all files and are ready to flash your board.
for further instructions.