Senior in Computer Engineering at UIUC, with interests in Network Applications, System Software and Digital Design.
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rv32im_ooo_cpu
rv32im_ooo_cpu PublicA RISC-V Out of Order CPU with explicit register renaming, branch prediction, split load-store queues and return address stack.
Verilog
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HTTP_lwip_FPGA
HTTP_lwip_FPGA PublicThe first network stack implementation for the Urbana Board FPGA, from physical to application layer.
VHDL
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