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[Core] Fixes I2C slave mode #1309
Core crashes when I2C is configured in slave mode.
Steps to Test
So I pulled and tested this, I no longer can get valid I2C communication with these changes. Where as with my PR #1305 (which I updated as I did not perform unit testing), I am able to properly send and receive data. I will take a look into this with my logic analyzer tomorrow just wanted to chime in before bed.
So I think this block is not needed, and removing it fixes the problem.
The comment claims that with clock stretching enabled it will pull SCL low if DR is empty. However this is only partially true.
The stm will only stretch the clock if it believes it has more data to send. It decides if there is more data to send based on the Master's ACK/NACK of the last transfered byte. If it recieves an ACK it will stretch the clock until the next byte is ready to be shifted out. How-ever if it recieves a nack it will not hold the clock as according to the I2C specification that is how the master signals to the slave that the current transfer is over.
I believe this also applies to the photon/electron as well. According to the reference manual for those devices the same logic as above is applied.