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ppc64: final cleanup and complete

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1 parent 0ce4325 commit f5c6116c17b6cba9c72aaa3d192abfbab4507762 @vsukharev vsukharev committed Mar 27, 2014
Showing with 96 additions and 35 deletions.
  1. +3 −1 include/libunwind-ppc64.h
  2. +1 −1 include/tdep-ppc64/dwarf-config.h
  3. +49 −14 src/ppc64/Gglobal.c
  4. +1 −1 src/ppc64/Ginit.c
  5. +25 −3 src/ppc64/Gstep.c
  6. +16 −7 src/ppc64/init.h
  7. +1 −8 src/ppc64/regname.c
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4 include/libunwind-ppc64.h
@@ -228,7 +228,9 @@ typedef enum
UNW_PPC64_VSR30 = 210,
UNW_PPC64_VSR31 = 212,
-#define UNW_PPC64_REGS_AMOUNT 214
+ UNW_PPC64_SPE_ACC = 214,
+ UNW_PPC64_SPEFSCR = 216,
+#define UNW_PPC64_REGS_AMOUNT 218
UNW_TDEP_LAST_REG = UNW_PPC64_NIP, // maybe it should be some some more registers to restore
View
2 include/tdep-ppc64/dwarf-config.h
@@ -33,7 +33,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#define dwarf_config_h
/* For PPC64, see register numbers in include/libunwind-ppc64.h, that is equal to /usr/include/asm/ptrace.h */
-#define DWARF_NUM_PRESERVED_REGS 214
+#define DWARF_NUM_PRESERVED_REGS 218
#define DWARF_REGNUM_MAP_LENGTH (DWARF_NUM_PRESERVED_REGS)
View
63 src/ppc64/Gglobal.c
@@ -68,6 +68,21 @@ uint8_t dwarf_to_unw_regnum_map[DWARF_REGNUM_MAP_LENGTH] =
[UNW_PPC64_R30]=UNW_PPC64_R30,
[UNW_PPC64_R31]=UNW_PPC64_R31,
+ [UNW_PPC64_NIP]=UNW_PPC64_NIP,
+ [UNW_PPC64_MSR]=UNW_PPC64_MSR,
+ [UNW_PPC64_ORIG_R3]=UNW_PPC64_ORIG_R3,
+ [UNW_PPC64_CTR]=UNW_PPC64_CTR,
+ [UNW_PPC64_LR]=UNW_PPC64_LR,
+ [UNW_PPC64_XER]=UNW_PPC64_XER,
+ [UNW_PPC64_CCR]=UNW_PPC64_CCR,
+ [UNW_PPC64_SOFTE]=UNW_PPC64_SOFTE,
+ [UNW_PPC64_TRAP]=UNW_PPC64_TRAP,
+ [UNW_PPC64_DAR]=UNW_PPC64_DAR,
+ [UNW_PPC64_DSISR]=UNW_PPC64_DSISR,
+ [UNW_PPC64_RESULT]=UNW_PPC64_RESULT,
+ [UNW_PPC64_REGS_COUNT]=UNW_PPC64_REGS_COUNT,
+ [UNW_PPC64_ARG_POINTER]=UNW_PPC64_ARG_POINTER,
+
[UNW_PPC64_F0]=UNW_PPC64_F0,
[UNW_PPC64_F1]=UNW_PPC64_F1,
[UNW_PPC64_F2]=UNW_PPC64_F2,
@@ -101,20 +116,7 @@ uint8_t dwarf_to_unw_regnum_map[DWARF_REGNUM_MAP_LENGTH] =
[UNW_PPC64_F30]=UNW_PPC64_F30,
[UNW_PPC64_F31]=UNW_PPC64_F31,
- [UNW_PPC64_LR]=UNW_PPC64_LR,
- [UNW_PPC64_CTR]=UNW_PPC64_CTR,
- [UNW_PPC64_ARG_POINTER]=UNW_PPC64_ARG_POINTER,
-
- [UNW_PPC64_CR0]=UNW_PPC64_CR0,
- [UNW_PPC64_CR1]=UNW_PPC64_CR1,
- [UNW_PPC64_CR2]=UNW_PPC64_CR2,
- [UNW_PPC64_CR3]=UNW_PPC64_CR3,
- [UNW_PPC64_CR4]=UNW_PPC64_CR4,
- [UNW_PPC64_CR5]=UNW_PPC64_CR5,
- [UNW_PPC64_CR6]=UNW_PPC64_CR6,
- [UNW_PPC64_CR7]=UNW_PPC64_CR7,
-
- [UNW_PPC64_XER]=UNW_PPC64_XER,
+ [UNW_PPC64_FPSCR]=UNW_PPC64_FPSCR,
[UNW_PPC64_V0]=UNW_PPC64_V0,
[UNW_PPC64_V1]=UNW_PPC64_V1,
@@ -153,6 +155,39 @@ uint8_t dwarf_to_unw_regnum_map[DWARF_REGNUM_MAP_LENGTH] =
[UNW_PPC64_VSCR]=UNW_PPC64_VSCR,
[UNW_PPC64_SPE_ACC]=UNW_PPC64_SPE_ACC,
[UNW_PPC64_SPEFSCR]=UNW_PPC64_SPEFSCR,
+
+ [UNW_PPC64_VSR0]=UNW_PPC64_VSR0,
+ [UNW_PPC64_VSR1]=UNW_PPC64_VSR1,
+ [UNW_PPC64_VSR2]=UNW_PPC64_VSR2,
+ [UNW_PPC64_VSR3]=UNW_PPC64_VSR3,
+ [UNW_PPC64_VSR4]=UNW_PPC64_VSR4,
+ [UNW_PPC64_VSR5]=UNW_PPC64_VSR5,
+ [UNW_PPC64_VSR6]=UNW_PPC64_VSR6,
+ [UNW_PPC64_VSR7]=UNW_PPC64_VSR7,
+ [UNW_PPC64_VSR8]=UNW_PPC64_VSR8,
+ [UNW_PPC64_VSR9]=UNW_PPC64_VSR9,
+ [UNW_PPC64_VSR10]=UNW_PPC64_VSR10,
+ [UNW_PPC64_VSR11]=UNW_PPC64_VSR11,
+ [UNW_PPC64_VSR12]=UNW_PPC64_VSR12,
+ [UNW_PPC64_VSR13]=UNW_PPC64_VSR13,
+ [UNW_PPC64_VSR14]=UNW_PPC64_VSR14,
+ [UNW_PPC64_VSR15]=UNW_PPC64_VSR15,
+ [UNW_PPC64_VSR16]=UNW_PPC64_VSR16,
+ [UNW_PPC64_VSR17]=UNW_PPC64_VSR17,
+ [UNW_PPC64_VSR18]=UNW_PPC64_VSR18,
+ [UNW_PPC64_VSR19]=UNW_PPC64_VSR19,
+ [UNW_PPC64_VSR20]=UNW_PPC64_VSR20,
+ [UNW_PPC64_VSR21]=UNW_PPC64_VSR21,
+ [UNW_PPC64_VSR22]=UNW_PPC64_VSR22,
+ [UNW_PPC64_VSR23]=UNW_PPC64_VSR23,
+ [UNW_PPC64_VSR24]=UNW_PPC64_VSR24,
+ [UNW_PPC64_VSR25]=UNW_PPC64_VSR25,
+ [UNW_PPC64_VSR26]=UNW_PPC64_VSR26,
+ [UNW_PPC64_VSR27]=UNW_PPC64_VSR27,
+ [UNW_PPC64_VSR28]=UNW_PPC64_VSR28,
+ [UNW_PPC64_VSR29]=UNW_PPC64_VSR29,
+ [UNW_PPC64_VSR30]=UNW_PPC64_VSR30,
+ [UNW_PPC64_VSR31]=UNW_PPC64_VSR31,
};
HIDDEN void
View
2 src/ppc64/Ginit.c
@@ -79,7 +79,7 @@ uc_addr (ucontext_t *uc, int reg)
case UNW_PPC64_XER:
gregs_idx = XER_IDX;
break;
- case UNW_PPC64_CR0:
+ case UNW_PPC64_CCR:
gregs_idx = CCR_IDX;
break;
default:
View
28 src/ppc64/Gstep.c
@@ -232,7 +232,10 @@ unw_step (unw_cursor_t * cursor)
/* This CR0 assignment is probably wrong. There are 8 dwarf columns
assigned to the CR registers, but only one CR register in the
mcontext structure */
- c->dwarf.loc[UNW_PPC64_CR0] =
+ // Thats all right, accordingly to A2 Processor manual, "2.4.2.3 Condition Register"
+ // The Condition Register (CR) is a 32-bit register of its own unique type
+ // and is divided up into eight, independent 4-bit fields (CR0-CR7).
+ c->dwarf.loc[UNW_PPC64_CCR] =
DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_CCR, 0);
c->dwarf.loc[UNW_PPC64_XER] =
DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_XER, 0);
@@ -243,8 +246,27 @@ unw_step (unw_cursor_t * cursor)
pseudo frame pointer (which is sp + some fixed offset, I
assume), based on the contents of the ucontext record
structure? For now, set this loc to null. */
- c->dwarf.loc[UNW_PPC64_FRAME_POINTER] = DWARF_NULL_LOC;
-
+ /*
+ wtf is physical FRAME_POINTER? ABI declares it logically as R1
+ c->dwarf.loc[UNW_PPC64_FRAME_POINTER] = DWARF_NULL_LOC;
+ */
+
+ /* It seems the following registers doesnt need to be restored
+ * UNW_PPC64_MSR,
+ * UNW_PPC64_ORIG_R3,
+ * UNW_PPC64_SOFTE,
+ * UNW_PPC64_TRAP,
+ * UNW_PPC64_DAR,
+ * UNW_PPC64_DSISR,
+ * UNW_PPC64_RESULT,
+ * UNW_PPC64_REGS_COUNT,
+ * UNW_PPC64_ARG_POINTER,
+ * UNW_PPC64_FPSCR
+ * UNW_PPC64_VSCR
+ * UNW_PPC64_VRSAVE
+ * UNW_PPC64_SPE_ACC
+ * UNW_PPC64_SPEFSCR
+ */
c->dwarf.loc[UNW_PPC64_F0] =
DWARF_LOC (ucontext + UC_MCONTEXT_FREGS_R0, 0);
c->dwarf.loc[UNW_PPC64_F1] =
View
23 src/ppc64/init.h
@@ -42,16 +42,25 @@ common_init_ppc64 (struct cursor *c, unsigned use_prev_instr)
for (i = UNW_PPC64_V0; i <= UNW_PPC64_V31; i++) {
c->dwarf.loc[i] = DWARF_VREG_LOC (&c->dwarf, i);
}
-
- for (i = UNW_PPC64_CR0; i <= UNW_PPC64_CR7; i++) {
- c->dwarf.loc[i] = DWARF_REG_LOC (&c->dwarf, i);
+ for (i = UNW_PPC64_VSR0; i <= UNW_PPC64_VSR31; i++) {
+ c->dwarf.loc[i] = DWARF_VREG_LOC (&c->dwarf, i);
}
- c->dwarf.loc[UNW_PPC64_ARG_POINTER] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_ARG_POINTER);
- c->dwarf.loc[UNW_PPC64_CTR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_CTR);
- c->dwarf.loc[UNW_PPC64_VSCR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_VSCR);
- c->dwarf.loc[UNW_PPC64_XER] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_XER);
+ c->dwarf.loc[UNW_PPC64_MSR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_MSR);
+ c->dwarf.loc[UNW_PPC64_ORIG_R3] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_ORIG_R3);
+ c->dwarf.loc[UNW_PPC64_CTR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_CTR);
c->dwarf.loc[UNW_PPC64_LR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_LR);
+ c->dwarf.loc[UNW_PPC64_XER] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_XER);
+ c->dwarf.loc[UNW_PPC64_CCR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_CCR);
+ c->dwarf.loc[UNW_PPC64_SOFTE] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_SOFTE);
+ c->dwarf.loc[UNW_PPC64_TRAP] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_TRAP);
+ c->dwarf.loc[UNW_PPC64_DAR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_DAR);
+ c->dwarf.loc[UNW_PPC64_DSISR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_DSISR);
+ c->dwarf.loc[UNW_PPC64_RESULT] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_RESULT);
+ c->dwarf.loc[UNW_PPC64_REGS_COUNT] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_REGS_COUNT);
+ c->dwarf.loc[UNW_PPC64_ARG_POINTER] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_ARG_POINTER);
+ c->dwarf.loc[UNW_PPC64_FPSCR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_FPSCR);
+ c->dwarf.loc[UNW_PPC64_VSCR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_VSCR);
c->dwarf.loc[UNW_PPC64_VRSAVE] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_VRSAVE);
c->dwarf.loc[UNW_PPC64_SPEFSCR] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_SPEFSCR);
c->dwarf.loc[UNW_PPC64_SPE_ACC] = DWARF_REG_LOC (&c->dwarf, UNW_PPC64_SPE_ACC);
View
9 src/ppc64/regname.c
@@ -110,14 +110,7 @@ static const char *regname[] =
[UNW_PPC64_F30]="FPR30",
[UNW_PPC64_F31]="FPR31",
- [UNW_PPC64_CR0]="CR0",
- [UNW_PPC64_CR1]="CR1",
- [UNW_PPC64_CR2]="CR2",
- [UNW_PPC64_CR3]="CR3",
- [UNW_PPC64_CR4]="CR4",
- [UNW_PPC64_CR5]="CR5",
- [UNW_PPC64_CR6]="CR6",
- [UNW_PPC64_CR7]="CR7",
+ [UNW_PPC64_FPSCR]="UNW_PPC64_FPSCR",
[UNW_PPC64_V0]="VR0",
[UNW_PPC64_V1]="VR1",

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