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420c14a @koriakin Merge upstream commit 5a4ff9f48f638d0cddeb6788743f32d8cdc89423
koriakin authored
1 /*
2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "drm.h"
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34
420c14a @koriakin Merge upstream commit 5a4ff9f48f638d0cddeb6788743f32d8cdc89423
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35 #include "nouveau_drv.h"
36
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37 static int
38 nv40_mem_timing_calc(struct drm_device *dev, u32 freq,
39 struct nouveau_pm_tbl_entry *e, u8 len,
40 struct nouveau_pm_memtiming *boot,
41 struct nouveau_pm_memtiming *t)
42 {
43 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
44
45 /* XXX: I don't trust the -1's and +1's... they must come
46 * from somewhere! */
47 t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
48 1 << 16 |
49 (e->tWTR + 2 + (t->tCWL - 1)) << 8 |
50 (e->tCL + 2 - (t->tCWL - 1));
51
52 t->reg[2] = 0x20200000 |
53 ((t->tCWL - 1) << 24 |
54 e->tRRD << 16 |
55 e->tRCDWR << 8 |
56 e->tRCDRD);
57
58 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", t->id,
59 t->reg[0], t->reg[1], t->reg[2]);
60 return 0;
61 }
62
63 static int
64 nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
65 struct nouveau_pm_tbl_entry *e, u8 len,
66 struct nouveau_pm_memtiming *boot,
67 struct nouveau_pm_memtiming *t)
420c14a @koriakin Merge upstream commit 5a4ff9f48f638d0cddeb6788743f32d8cdc89423
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68 {
69 struct drm_nouveau_private *dev_priv = dev->dev_private;
70 struct bit_entry P;
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71 uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3;
72
73 if (bit_table(dev, 'P', &P))
74 return -EINVAL;
75
76 switch (min(len, (u8) 22)) {
77 case 22:
78 unk21 = e->tUNK_21;
79 case 21:
80 unk20 = e->tUNK_20;
81 case 20:
82 if (e->tCWL > 0)
83 t->tCWL = e->tCWL;
84 case 19:
85 unk18 = e->tUNK_18;
86 break;
87 }
88
89 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
90
91 t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
92 max(unk18, (u8) 1) << 16 |
93 (e->tWTR + 2 + (t->tCWL - 1)) << 8;
94
95 t->reg[2] = ((t->tCWL - 1) << 24 |
96 e->tRRD << 16 |
97 e->tRCDWR << 8 |
98 e->tRCDRD);
99
100 t->reg[4] = e->tUNK_13 << 8 | e->tUNK_13;
101
102 t->reg[5] = (e->tRFC << 24 | max(e->tRCDRD, e->tRCDWR) << 16 | e->tRP);
103
104 t->reg[8] = boot->reg[8] & 0xffffff00;
105
106 if (P.version == 1) {
107 t->reg[1] |= (e->tCL + 2 - (t->tCWL - 1));
108
109 t->reg[3] = (0x14 + e->tCL) << 24 |
110 0x16 << 16 |
111 (e->tCL - 1) << 8 |
112 (e->tCL - 1);
113
114 t->reg[4] |= boot->reg[4] & 0xffff0000;
115
116 t->reg[6] = (0x33 - t->tCWL) << 16 |
117 t->tCWL << 8 |
118 (0x2e + e->tCL - t->tCWL);
119
120 t->reg[7] = 0x4000202 | (e->tCL - 1) << 16;
121
122 /* XXX: P.version == 1 only has DDR2 and GDDR3? */
123 if (dev_priv->vram_type == NV_MEM_TYPE_DDR2) {
124 t->reg[5] |= (e->tCL + 3) << 8;
125 t->reg[6] |= (t->tCWL - 2) << 8;
126 t->reg[8] |= (e->tCL - 4);
127 } else {
128 t->reg[5] |= (e->tCL + 2) << 8;
129 t->reg[6] |= t->tCWL << 8;
130 t->reg[8] |= (e->tCL - 2);
420c14a @koriakin Merge upstream commit 5a4ff9f48f638d0cddeb6788743f32d8cdc89423
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131 }
132 } else {
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133 t->reg[1] |= (5 + e->tCL - (t->tCWL));
134
135 /* XXX: 0xb? 0x30? */
136 t->reg[3] = (0x30 + e->tCL) << 24 |
137 (boot->reg[3] & 0x00ff0000)|
138 (0xb + e->tCL) << 8 |
139 (e->tCL - 1);
140
141 t->reg[4] |= (unk20 << 24 | unk21 << 16);
142
143 /* XXX: +6? */
144 t->reg[5] |= (t->tCWL + 6) << 8;
145
146 t->reg[6] = (0x5a + e->tCL) << 16 |
147 (6 - e->tCL + t->tCWL) << 8 |
148 (0x50 + e->tCL - t->tCWL);
149
150 tmp7_3 = (boot->reg[7] & 0xff000000) >> 24;
151 t->reg[7] = (tmp7_3 << 24) |
152 ((tmp7_3 - 6 + e->tCL) << 16) |
153 0x202;
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154 }
155
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156 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", t->id,
157 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
158 NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
159 t->reg[4], t->reg[5], t->reg[6], t->reg[7]);
160 NV_DEBUG(dev, " 240: %08x\n", t->reg[8]);
161 return 0;
162 }
163
164 static int
165 nvc0_mem_timing_calc(struct drm_device *dev, u32 freq,
166 struct nouveau_pm_tbl_entry *e, u8 len,
167 struct nouveau_pm_memtiming *boot,
168 struct nouveau_pm_memtiming *t)
169 {
170 if (e->tCWL > 0)
171 t->tCWL = e->tCWL;
172
173 t->reg[0] = (e->tRP << 24 | (e->tRAS & 0x7f) << 17 |
174 e->tRFC << 8 | e->tRC);
175
176 t->reg[1] = (boot->reg[1] & 0xff000000) |
177 (e->tRCDWR & 0x0f) << 20 |
178 (e->tRCDRD & 0x0f) << 14 |
179 (t->tCWL << 7) |
180 (e->tCL & 0x0f);
181
182 t->reg[2] = (boot->reg[2] & 0xff0000ff) |
183 e->tWR << 16 | e->tWTR << 8;
184
185 t->reg[3] = (e->tUNK_20 & 0x1f) << 9 |
186 (e->tUNK_21 & 0xf) << 5 |
187 (e->tUNK_13 & 0x1f);
188
189 t->reg[4] = (boot->reg[4] & 0xfff00fff) |
190 (e->tRRD&0x1f) << 15;
191
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192 NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", t->id,
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193 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
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194 NV_DEBUG(dev, " 2a0: %08x\n", t->reg[4]);
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195 return 0;
196 }
197
198 /**
199 * MR generation methods
200 */
201
202 static int
203 nouveau_mem_ddr2_mr(struct drm_device *dev, u32 freq,
204 struct nouveau_pm_tbl_entry *e, u8 len,
205 struct nouveau_pm_memtiming *boot,
206 struct nouveau_pm_memtiming *t)
207 {
208 t->drive_strength = 0;
209 if (len < 15) {
210 t->odt = boot->odt;
211 } else {
212 t->odt = e->RAM_FT1 & 0x07;
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213 }
214
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215 if (e->tCL >= NV_MEM_CL_DDR2_MAX) {
216 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
217 return -ERANGE;
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218 }
219
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220 if (e->tWR >= NV_MEM_WR_DDR2_MAX) {
221 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
222 return -ERANGE;
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223 }
224
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225 if (t->odt > 3) {
226 NV_WARN(dev, "(%u) Invalid odt value, assuming disabled: %x",
227 t->id, t->odt);
228 t->odt = 0;
229 }
230
231 t->mr[0] = (boot->mr[0] & 0x100f) |
232 (e->tCL) << 4 |
233 (e->tWR - 1) << 9;
234 t->mr[1] = (boot->mr[1] & 0x101fbb) |
235 (t->odt & 0x1) << 2 |
236 (t->odt & 0x2) << 5;
237
238 NV_WARN(dev, "(%u) MR: %08x", t->id, t->mr[0]);
239 return 0;
240 }
241
242 uint8_t nv_mem_wr_lut_ddr3[NV_MEM_WR_DDR3_MAX] = {
243 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
244
245 static int
246 nouveau_mem_ddr3_mr(struct drm_device *dev, u32 freq,
247 struct nouveau_pm_tbl_entry *e, u8 len,
248 struct nouveau_pm_memtiming *boot,
249 struct nouveau_pm_memtiming *t)
250 {
251 u8 cl = e->tCL - 4;
252
253 t->drive_strength = 0;
254 if (len < 15) {
255 t->odt = boot->odt;
256 } else {
257 t->odt = e->RAM_FT1 & 0x07;
258 }
259
260 if (e->tCL >= NV_MEM_CL_DDR3_MAX || e->tCL < 4) {
261 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
262 return -ERANGE;
263 }
264
265 if (e->tWR >= NV_MEM_WR_DDR3_MAX || e->tWR < 4) {
266 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
267 return -ERANGE;
268 }
269
270 if (e->tCWL < 5) {
271 NV_WARN(dev, "(%u) Invalid tCWL: %u", t->id, e->tCWL);
272 return -ERANGE;
273 }
274
275 t->mr[0] = (boot->mr[0] & 0x180b) |
276 /* CAS */
277 (cl & 0x7) << 4 |
278 (cl & 0x8) >> 1 |
279 (nv_mem_wr_lut_ddr3[e->tWR]) << 9;
280 t->mr[1] = (boot->mr[1] & 0x101dbb) |
281 (t->odt & 0x1) << 2 |
282 (t->odt & 0x2) << 5 |
283 (t->odt & 0x4) << 7;
284 t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3;
285
286 NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]);
287 return 0;
288 }
289
290 uint8_t nv_mem_cl_lut_gddr3[NV_MEM_CL_GDDR3_MAX] = {
291 0, 0, 0, 0, 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11};
292 uint8_t nv_mem_wr_lut_gddr3[NV_MEM_WR_GDDR3_MAX] = {
293 0, 0, 0, 0, 0, 2, 3, 8, 9, 10, 11, 0, 0, 1, 1, 0, 3};
294
295 static int
296 nouveau_mem_gddr3_mr(struct drm_device *dev, u32 freq,
297 struct nouveau_pm_tbl_entry *e, u8 len,
298 struct nouveau_pm_memtiming *boot,
299 struct nouveau_pm_memtiming *t)
300 {
301 if (len < 15) {
302 t->drive_strength = boot->drive_strength;
303 t->odt = boot->odt;
304 } else {
305 t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
306 t->odt = e->RAM_FT1 & 0x07;
307 }
308
309 if (e->tCL >= NV_MEM_CL_GDDR3_MAX) {
310 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
311 return -ERANGE;
312 }
313
314 if (e->tWR >= NV_MEM_WR_GDDR3_MAX) {
315 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
316 return -ERANGE;
317 }
318
319 if (t->odt > 3) {
320 NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
321 t->id, t->odt);
322 t->odt = 0;
323 }
324
325 t->mr[0] = (boot->mr[0] & 0xe0b) |
326 /* CAS */
327 ((nv_mem_cl_lut_gddr3[e->tCL] & 0x7) << 4) |
328 ((nv_mem_cl_lut_gddr3[e->tCL] & 0x8) >> 2);
329 t->mr[1] = (boot->mr[1] & 0x100f40) | t->drive_strength |
330 (t->odt << 2) |
331 (nv_mem_wr_lut_gddr3[e->tWR] & 0xf) << 4;
332 t->mr[2] = boot->mr[2];
333
334 NV_DEBUG(dev, "(%u) MR: %08x %08x %08x", t->id,
335 t->mr[0], t->mr[1], t->mr[2]);
336 return 0;
337 }
338
339 static int
340 nouveau_mem_gddr5_mr(struct drm_device *dev, u32 freq,
341 struct nouveau_pm_tbl_entry *e, u8 len,
342 struct nouveau_pm_memtiming *boot,
343 struct nouveau_pm_memtiming *t)
344 {
345 u8 add_term; /* CMD/ADD termination */
346 if (len < 15) {
347 t->drive_strength = boot->drive_strength;
348 t->odt = boot->odt;
349 } else {
350 t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
351 t->odt = e->RAM_FT1 & 0x03;
352 }
353
354 if (e->tCL >= NV_MEM_CL_GDDR5_MAX) {
355 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
356 return -ERANGE;
357 }
358
359 if (e->tWR >= NV_MEM_WR_GDDR5_MAX) {
360 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
361 return -ERANGE;
362 }
363
364 if (t->odt > 2) {
365 NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
366 t->id, t->odt);
367 t->odt = 0;
368 }
369
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370 if (len >= 23)
371 add_term = (e->RAM_FT2 >> 2) & 3;
372 else if(t->odt)
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373 add_term = t->odt;
374 else
375 add_term = 3;
376
377 t->mr[0] = (boot->mr[0] & 0x007) |
378 ((e->tCL - 5) << 3) |
379 ((e->tWR - 4) << 8);
380 t->mr[1] = (boot->mr[1] & 0x1007c0) |
381 t->drive_strength |
382 (t->odt << 2) |
383 (add_term << 4);
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384 t->mr[2] = boot->mr[2];
385 if (len >= 23)
386 t->mr[3] = (boot->mr[3] & ~0x20) | (e->RAM_FT2 & 2 ? 0x20 : 0);
387 else
388 t->mr[3] = boot->mr[3];
389
390 /* I suspect the remainder is in ramcfg rather than memtiming */
391 t->mr[4] = boot->mr[4]; /* Error detection, probably never touched */
392 t->mr[5] = boot->mr[5] & ~6; /* Figure out when LP3/LP2 is set */
393 t->mr[6] = boot->mr[6]; /* Figure out when changed? WCK PIN */
394 t->mr[7] = boot->mr[7]; /* Half VREFD and LF mode are important here */
395 t->mr[8] = boot->mr[8]; /* seems to always be untouched */
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396
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397 NV_DEBUG(dev, "(%u) MR: %08x %08x %08x", t->id, t->mr[0], t->mr[1], t->mr[3]);
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398 return 0;
399 }
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400
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401 int
402 nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
403 struct nouveau_pm_memtiming *t)
404 {
405 struct drm_nouveau_private *dev_priv = dev->dev_private;
406 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
407 struct nouveau_pm_memtiming *boot = &pm->boot.timing;
408 struct nouveau_pm_tbl_entry *e;
409 u8 ver, len, *ptr, *ramcfg;
410 int ret;
411
412 ptr = nouveau_perf_timing(dev, freq, &ver, &len);
413 if (!ptr || ptr[0] == 0x00) {
414 *t = *boot;
415 return 0;
416 }
417 e = (struct nouveau_pm_tbl_entry *)ptr;
418
419 t->tCWL = boot->tCWL;
420
421 switch (dev_priv->card_type) {
422 case NV_40:
423 ret = nv40_mem_timing_calc(dev, freq, e, len, boot, t);
424 break;
425 case NV_50:
426 ret = nv50_mem_timing_calc(dev, freq, e, len, boot, t);
427 break;
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428 case NV_D0:
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429 case NV_C0:
430 ret = nvc0_mem_timing_calc(dev, freq, e, len, boot, t);
431 break;
432 default:
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433 ret = -ENODEV;
434 break;
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435 }
436
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437 if (ret)
438 return ret;
439
440 switch (dev_priv->vram_type) {
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441 case NV_MEM_TYPE_GDDR3:
442 ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t);
443 break;
444 case NV_MEM_TYPE_GDDR5:
445 ret = nouveau_mem_gddr5_mr(dev, freq, e, len, boot, t);
446 break;
447 case NV_MEM_TYPE_DDR2:
448 ret = nouveau_mem_ddr2_mr(dev, freq, e, len, boot, t);
449 break;
450 case NV_MEM_TYPE_DDR3:
451 ret = nouveau_mem_ddr3_mr(dev, freq, e, len, boot, t);
452 break;
453 default:
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454 NV_WARN(dev, "Unknown memory type %u\n", dev_priv->vram_type);
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455 ret = -EINVAL;
456 break;
457 }
458
459 ramcfg = nouveau_perf_ramcfg(dev, freq, &ver, &len);
460 if (ramcfg) {
461 int dll_off;
462
463 if (ver == 0x00)
464 dll_off = !!(ramcfg[3] & 0x04);
465 else
466 dll_off = !!(ramcfg[2] & 0x40);
467
468 switch (dev_priv->vram_type) {
469 case NV_MEM_TYPE_GDDR3:
470 t->mr[1] &= ~0x00000040;
471 t->mr[1] |= 0x00000040 * dll_off;
472 break;
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473 default:
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474 t->mr[1] &= ~0x00000001;
475 t->mr[1] |= 0x00000001 * dll_off;
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476 break;
477 }
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478 }
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479
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480 return ret;
481 }
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482
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483 void
484 nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
485 {
486 struct drm_nouveau_private *dev_priv = dev->dev_private;
487 u32 timing_base, timing_regs, mr_base;
488 int i;
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489
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490 if (dev_priv->card_type >= 0xC0) {
491 timing_base = 0x10f290;
492 mr_base = 0x10f300;
493 } else {
494 timing_base = 0x100220;
495 mr_base = 0x1002c0;
496 }
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497
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498 t->id = -1;
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499
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500 switch (dev_priv->card_type) {
501 case NV_50:
502 timing_regs = 9;
503 break;
504 case NV_C0:
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505 case NV_D0:
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506 timing_regs = 5;
507 break;
508 case NV_30:
509 case NV_40:
510 timing_regs = 3;
511 break;
512 default:
513 timing_regs = 0;
514 return;
515 }
516 for(i = 0; i < timing_regs; i++)
517 t->reg[i] = nv_rd32(dev, timing_base + (0x04 * i));
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518
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519 t->tCWL = 0;
520 if (dev_priv->card_type < NV_C0) {
521 t->tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1;
522 } else {
523 t->tCWL = ((nv_rd32(dev, 0x10f294) & 0x00000f80) >> 7);
524 }
525
526 t->mr[0] = nv_rd32(dev, mr_base);
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527 if (dev_priv->vram_type != NV_MEM_TYPE_GDDR5) {
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528 t->mr[1] = nv_rd32(dev, mr_base + 0x04);
529 t->mr[2] = nv_rd32(dev, mr_base + 0x20);
530 t->mr[3] = nv_rd32(dev, mr_base + 0x24);
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531 } else {
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532 int i;
533 for (i = 1; i < 9; ++i)
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534 t->mr[i] = nv_rd32(dev, mr_base + 0x2c + i * 4);
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535 }
536
537 t->odt = 0;
538 t->drive_strength = 0;
539
540 switch (dev_priv->vram_type) {
541 case NV_MEM_TYPE_DDR3:
542 t->odt |= (t->mr[1] & 0x200) >> 7;
543 case NV_MEM_TYPE_DDR2:
544 t->odt |= (t->mr[1] & 0x04) >> 2 |
545 (t->mr[1] & 0x40) >> 5;
546 break;
547 case NV_MEM_TYPE_GDDR3:
548 case NV_MEM_TYPE_GDDR5:
549 t->drive_strength = t->mr[1] & 0x03;
550 t->odt = (t->mr[1] & 0x0c) >> 2;
551 break;
552 default:
553 break;
554 }
555 }
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556
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557 int
558 nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
559 struct nouveau_pm_level *perflvl)
560 {
561 struct drm_nouveau_private *dev_priv = exec->dev->dev_private;
562 struct nouveau_pm_memtiming *info = &perflvl->timing;
563 u32 tMRD = 1000, tCKSRE = 0, tCKSRX = 0, tXS = 0, tDLLK = 0;
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564 u32 mr[9] = { info->mr[0], info->mr[1], info->mr[2] };
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565 u32 mr1_dlloff;
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566 int i;
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567
568 switch (dev_priv->vram_type) {
569 case NV_MEM_TYPE_DDR2:
570 tDLLK = 2000;
571 mr1_dlloff = 0x00000001;
572 break;
573 case NV_MEM_TYPE_DDR3:
574 tDLLK = 12000;
575 mr1_dlloff = 0x00000001;
576 break;
577 case NV_MEM_TYPE_GDDR3:
578 tDLLK = 40000;
579 mr1_dlloff = 0x00000040;
580 break;
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581 case NV_MEM_TYPE_GDDR5:
582 mr1_dlloff = 0;
583 tCKSRE = 1000;
584 break;
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585 default:
586 NV_ERROR(exec->dev, "cannot reclock unsupported memtype\n");
587 return -ENODEV;
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588 }
589
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590 /* fetch current MRs */
591 switch (dev_priv->vram_type) {
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592 case NV_MEM_TYPE_GDDR5:
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593 mr[8] = exec->mrg(exec, 15);
594 for (i = 7; i >= 3; --i)
595 mr[i] = exec->mrg(exec, i);
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596 case NV_MEM_TYPE_GDDR3:
597 case NV_MEM_TYPE_DDR3:
598 mr[2] = exec->mrg(exec, 2);
599 default:
600 mr[1] = exec->mrg(exec, 1);
601 mr[0] = exec->mrg(exec, 0);
602 break;
603 }
604
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605 if (dev_priv->vram_type < NV_MEM_TYPE_GDDR5) {
606 /* DLL 'on' -> DLL 'off' mode, disable before entering self-refresh */
607 if (!(mr[1] & mr1_dlloff) && (info->mr[1] & mr1_dlloff)) {
608 exec->precharge(exec);
609 exec->mrs (exec, 1, mr[1] | mr1_dlloff);
610 exec->wait(exec, tMRD);
611 }
612 /* enter self-refresh mode */
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613 exec->precharge(exec);
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614 exec->refresh(exec);
615 exec->refresh(exec);
616 } else if (dev_priv->vram_type == NV_MEM_TYPE_GDDR5) {
617 u32 dtold = mr[1] & 0xc, dtnew = info->mr[1] & 0xc;
618 if (dtold < dtnew) {
619 exec->mrs(exec, 1, info->mr[1]);
620 mr[1] = info->mr[1];
621 }
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622 }
623 exec->refresh_auto(exec, false);
624 exec->refresh_self(exec, true);
625 exec->wait(exec, tCKSRE);
626
627 /* modify input clock frequency */
628 exec->clock_set(exec);
629
630 /* exit self-refresh mode */
631 exec->wait(exec, tCKSRX);
632 exec->precharge(exec);
633 exec->refresh_self(exec, false);
634 exec->refresh_auto(exec, true);
635 exec->wait(exec, tXS);
636
637 /* update MRs */
638 if (mr[2] != info->mr[2]) {
639 exec->mrs (exec, 2, info->mr[2]);
640 exec->wait(exec, tMRD);
641 }
642
643 if (mr[1] != info->mr[1]) {
644 /* need to keep DLL off until later, at least on GDDR3 */
645 exec->mrs (exec, 1, info->mr[1] | (mr[1] & mr1_dlloff));
646 exec->wait(exec, tMRD);
647 }
648
649 if (mr[0] != info->mr[0]) {
650 exec->mrs (exec, 0, info->mr[0]);
651 exec->wait(exec, tMRD);
652 }
653
654 /* update PFB timing registers */
655 exec->timing_set(exec);
656
657 /* DLL (enable + ) reset */
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658 if (dev_priv->vram_type == NV_MEM_TYPE_GDDR5) {
659 for (i = 3; i < 8; ++i)
660 if (mr[i] != info->mr[i])
661 exec->mrs(exec, i, info->mr[i]);
662 if (mr[8] != info->mr[8])
663 exec->mrs(exec, 15, info->mr[8]);
664 } else if (!(info->mr[1] & mr1_dlloff)) {
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665 if (mr[1] & mr1_dlloff) {
666 exec->mrs (exec, 1, info->mr[1]);
667 exec->wait(exec, tMRD);
668 }
669 exec->mrs (exec, 0, info->mr[0] | 0x00000100);
670 exec->wait(exec, tMRD);
671 exec->mrs (exec, 0, info->mr[0] | 0x00000000);
672 exec->wait(exec, tMRD);
673 exec->wait(exec, tDLLK);
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674 if (dev_priv->vram_type == NV_MEM_TYPE_GDDR3)
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675 exec->precharge(exec);
676 }
677
678 return 0;
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679 }
680
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681 int
682 nouveau_mem_vbios_type(struct drm_device *dev)
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683 {
684 struct drm_nouveau_private *dev_priv = dev->dev_private;
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685 struct bit_entry M;
686 u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
687 if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
688 u8 *table = ROMPTR(&dev_priv->vbios, M.data[3]);
689 if (table && table[0] == 0x10 && ramcfg < table[3]) {
690 u8 *entry = table + table[1] + (ramcfg * table[2]);
691 switch (entry[0] & 0x0f) {
692 case 0: return NV_MEM_TYPE_DDR2;
693 case 1: return NV_MEM_TYPE_DDR3;
694 case 2: return NV_MEM_TYPE_GDDR3;
695 case 3: return NV_MEM_TYPE_GDDR5;
696 default:
697 break;
698 }
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699
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700 }
701 }
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702 WARN(dev, "Could not determine vbios type!\n");
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703 return NV_MEM_TYPE_UNKNOWN;
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704 }
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