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nvc0: Only enable PLL mode on clocks that can use it

Based on darktamas commit after I reported the issue
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mlankhorst committed Feb 10, 2012
1 parent 2f00026 commit 180624c462bcb39b5bad8c08f1c3d11576a0ed72
Showing with 1 addition and 1 deletion.
  1. +1 −1 pscnv/nvc0_pm.c
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@@ -269,7 +269,7 @@ calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
clk0 = calc_div(dev, clk, clk0, freq, &div1D);
/* see if we can get any closer using PLLs */
- if (clk0 != freq) {
+ if (clk0 != freq && (0x00004387 & (1 << clk))) {
if (clk < 7)
clk1 = calc_pll(dev, clk, freq, &info->coef);
else

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