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# Create clk_wiz
cell xilinx.com:ip:clk_wiz:6.0 pll_0 {
PRIMITIVE PLL
PRIM_IN_FREQ.VALUE_SRC USER
PRIM_IN_FREQ 125.0
PRIM_SOURCE Differential_clock_capable_pin
CLKOUT1_USED true
CLKOUT1_REQUESTED_OUT_FREQ 125.0
CLKOUT2_USED true
CLKOUT2_REQUESTED_OUT_FREQ 250.0
CLKOUT2_REQUESTED_PHASE -90.0
USE_RESET false
} {
clk_in1_p adc_clk_p_i
clk_in1_n adc_clk_n_i
}
# Create processing_system7
cell xilinx.com:ip:processing_system7:5.5 ps_0 {
PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
} {
M_AXI_GP0_ACLK pll_0/clk_out1
}
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
make_external {FIXED_IO, DDR}
Master Disable
Slave Disable
} [get_bd_cells ps_0]
# Create xlconstant
cell xilinx.com:ip:xlconstant:1.1 const_0
# Create proc_sys_reset
cell xilinx.com:ip:proc_sys_reset:5.0 rst_0 {} {
ext_reset_in const_0/dout
}
# ADC
# Create axis_red_pitaya_adc
cell pavel-demin:user:axis_red_pitaya_adc:2.0 adc_0 {} {
aclk pll_0/clk_out1
adc_dat_a adc_dat_a_i
adc_dat_b adc_dat_b_i
adc_csn adc_csn_o
}
# Create axis_broadcaster
cell xilinx.com:ip:axis_broadcaster:1.1 bcast_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 4
M_TDATA_NUM_BYTES 2
M00_TDATA_REMAP {tdata[15:0]}
M01_TDATA_REMAP {tdata[31:16]}
} {
S_AXIS adc_0/M_AXIS
aclk pll_0/clk_out1
aresetn rst_0/peripheral_aresetn
}
# DAC
# Create axis_combiner
cell xilinx.com:ip:axis_combiner:1.1 comb_0 {
TDATA_NUM_BYTES.VALUE_SRC USER
TDATA_NUM_BYTES 2
} {
aclk pll_0/clk_out1
aresetn rst_0/peripheral_aresetn
}
# Create axis_red_pitaya_dac
cell pavel-demin:user:axis_red_pitaya_dac:1.0 dac_0 {} {
aclk pll_0/clk_out1
ddr_clk pll_0/clk_out2
locked pll_0/locked
S_AXIS comb_0/M_AXIS
dac_clk dac_clk_o
dac_rst dac_rst_o
dac_sel dac_sel_o
dac_wrt dac_wrt_o
dac_dat dac_dat_o
}
# DNA
# Create dna_reader
cell pavel-demin:user:dna_reader:1.0 dna_0 {} {
aclk pll_0/clk_out1
aresetn rst_0/peripheral_aresetn
}
# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_0 {
NUM_PORTS 2
IN0_WIDTH 32
IN1_WIDTH 64
} {
In0 const_0/dout
In1 dna_0/dna_data
}
# Create axi_sts_register
cell pavel-demin:user:axi_sts_register:1.0 sts_0 {
STS_DATA_WIDTH 96
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
} {
sts_data concat_0/dout
}
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins sts_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg0]
set_property OFFSET 0x40000000 [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg0]
# GPIO
# Delete input/output port
delete_bd_objs [get_bd_ports exp_p_tri_io]
# Create output port
create_bd_port -dir O -from 1 -to 0 exp_p_tri_io
# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_1 {
NUM_PORTS 2
IN0_WIDTH 1
IN1_WIDTH 1
} {
dout exp_p_tri_io
}
# TRX
module trx_0 {
source projects/sdr_transceiver/trx.tcl
} {
out_slice_0/dout concat_1/In0
rx_0/mult_0/S_AXIS_A bcast_0/M00_AXIS
tx_0/mult_0/M_AXIS_DOUT comb_0/S00_AXIS
}
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins trx_0/cfg_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
set_property OFFSET 0x40001000 [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins trx_0/sts_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg01]
set_property OFFSET 0x40002000 [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg01]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins trx_0/rx_0/reader_0/S_AXI]
set_property RANGE 32K [get_bd_addr_segs ps_0/Data/SEG_reader_0_reg0]
set_property OFFSET 0x40010000 [get_bd_addr_segs ps_0/Data/SEG_reader_0_reg0]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins trx_0/tx_0/writer_0/S_AXI]
set_property RANGE 32K [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg0]
set_property OFFSET 0x40018000 [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg0]
module trx_1 {
source projects/sdr_transceiver/trx.tcl
} {
out_slice_0/dout concat_1/In1
rx_0/mult_0/S_AXIS_A bcast_0/M01_AXIS
tx_0/mult_0/M_AXIS_DOUT comb_0/S01_AXIS
}
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins trx_1/cfg_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg01]
set_property OFFSET 0x40003000 [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg01]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins trx_1/sts_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg02]
set_property OFFSET 0x40004000 [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg02]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins trx_1/rx_0/reader_0/S_AXI]
set_property RANGE 32K [get_bd_addr_segs ps_0/Data/SEG_reader_0_reg01]
set_property OFFSET 0x40020000 [get_bd_addr_segs ps_0/Data/SEG_reader_0_reg01]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins trx_1/tx_0/writer_0/S_AXI]
set_property RANGE 32K [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg01]
set_property OFFSET 0x40028000 [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg01]