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# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_0 {
DIN_WIDTH 8 DIN_FROM 0 DIN_TO 0
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_1 {
DIN_WIDTH 64 DIN_FROM 39 DIN_TO 0
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_2 {
DIN_WIDTH 64 DIN_FROM 63 DIN_TO 48
}
# Create axi_axis_writer
cell pavel-demin:user:axi_axis_writer:1.0 writer_0 {
AXI_DATA_WIDTH 32
} {
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create fifo_generator
cell xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 {
PERFORMANCE_OPTIONS First_Word_Fall_Through
INPUT_DATA_WIDTH 32
INPUT_DEPTH 8192
OUTPUT_DATA_WIDTH 64
OUTPUT_DEPTH 4096
WRITE_DATA_COUNT true
WRITE_DATA_COUNT_WIDTH 14
} {
clk /pll_0/clk_out1
srst slice_0/dout
}
# Create axis_fifo
cell pavel-demin:user:axis_fifo:1.0 fifo_0 {
S_AXIS_TDATA_WIDTH 32
M_AXIS_TDATA_WIDTH 64
} {
S_AXIS writer_0/M_AXIS
FIFO_READ fifo_generator_0/FIFO_READ
FIFO_WRITE fifo_generator_0/FIFO_WRITE
aclk /pll_0/clk_out1
}
# Create axis_dwidth_converter
cell xilinx.com:ip:axis_dwidth_converter:1.1 conv_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 8
M_TDATA_NUM_BYTES 4
} {
S_AXIS fifo_0/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create floating_point
cell xilinx.com:ip:floating_point:7.1 fp_0 {
OPERATION_TYPE Float_to_fixed
RESULT_PRECISION_TYPE Custom
C_RESULT_EXPONENT_WIDTH 2
C_RESULT_FRACTION_WIDTH 22
HAS_ARESETN true
} {
S_AXIS_A conv_0/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create fir_compiler
cell xilinx.com:ip:fir_compiler:7.2 fir_0 {
DATA_WIDTH.VALUE_SRC USER
DATA_WIDTH 24
COEFFICIENTVECTOR {-1.6475184244e-08, -4.7308459920e-08, -7.8893863768e-10, 3.0925190275e-08, 1.8615341511e-08, 3.2738579373e-08, -6.2882142522e-09, -1.5223428301e-07, -8.3034994960e-08, 3.1444110150e-07, 3.0555633077e-07, -4.7402882816e-07, -7.1331302147e-07, 5.4715344924e-07, 1.3342677196e-06, -4.1400006225e-07, -2.1499283239e-06, -6.7755353871e-08, 3.0746238214e-06, 1.0367750504e-06, -3.9432782180e-06, -2.5912407060e-06, 4.5141272867e-06, 4.7465613040e-06, -4.4915978325e-06, -7.3962527433e-06, 3.5711724673e-06, 1.0286744705e-05, -1.5034036873e-06, -1.3017335591e-05, -1.8315675010e-06, 1.5074076008e-05, 6.3528832905e-06, -1.5901411781e-05, -1.1729229997e-05, 1.5007022746e-05, 1.7367181073e-05, -1.2091222024e-05, -2.2460702942e-05, 7.1680394432e-06, 2.6096139036e-05, -6.6373904925e-07, -2.7421872543e-05, -6.5484048093e-06, 2.5857507600e-05, 1.3200217535e-05, -2.1311612230e-05, -1.7784646942e-05, 1.4363093885e-05, 1.8814046432e-05, -6.3568169131e-06, -1.5157992340e-05, -6.3327895214e-07, 6.4138787166e-06, 4.0053990895e-06, 6.7555658428e-06, -1.0036803910e-06, -2.2396337110e-05, -1.0761141791e-05, 3.7222234775e-05, 3.2693237716e-05, -4.6846333362e-05, -6.4636124159e-05, 4.6245620990e-05, 1.0437412713e-04, -3.0530082323e-05, -1.4741728946e-04, -4.1210749155e-06, 1.8713470943e-04, 5.9458033775e-05, -2.1531563984e-04, -1.3426716370e-04, 2.2316248954e-04, 2.2377561767e-04, -2.0264454791e-04, -3.1953754503e-04, 1.4805522141e-04, 4.0993927751e-04, -5.7543954433e-05, -4.8138440104e-04, -6.5657893369e-05, 5.2011019916e-04, 2.1260496857e-04, -5.1448028020e-04, -3.6890345513e-04, 4.5734587073e-04, 5.1583100637e-04, -3.4838793223e-04, -6.3270718567e-04, 1.9560355266e-04, 6.9999757638e-04, -1.5804201652e-05, -7.0301566465e-04, -1.6632027612e-04, 6.3567586190e-04, 3.2073263476e-04, -5.0368325235e-04, -4.1612973349e-04, 3.2649535977e-04, 4.2526537587e-04, -1.3744895834e-04, -3.3094790041e-04, -1.8403035937e-05, 1.3191487573e-04, 8.8939272976e-05, 1.5236012215e-04, -2.1970158766e-05, -4.7896593587e-04, -2.2612676235e-04, 7.8136180792e-04, 6.8017738605e-04, -9.7354686570e-04, -1.3370873498e-03, 9.5720862307e-04, 2.1576630162e-03, -6.3284598753e-04, -3.0615654156e-03, -8.6294827575e-05, 3.9264170707e-03, 1.2585962514e-03, -4.5919370873e-03, -2.8983074182e-03, 4.8694647415e-03, 4.9613893461e-03, -4.5566231615e-03, -7.3346907409e-03, 3.4562125456e-03, 9.8298700832e-03, -1.3978170954e-03, -1.2182859488e-02, -1.7398445415e-03, 1.4058482882e-02, 6.0068525240e-03, -1.5061536108e-02, -1.1366976828e-02, 1.4744464043e-02, 1.7682334350e-02, -1.2615303762e-02, -2.4706379782e-02, 8.1290343123e-03, 3.2077753537e-02, -6.4549692520e-04, -3.9306541246e-02, -1.0688751054e-02, 4.5724758263e-02, 2.7241749176e-02, -5.0309093724e-02, -5.1700554121e-02, 5.1008645773e-02, 9.0545335380e-02, -4.1604239425e-02, -1.6370632654e-01, -1.0777594153e-02, 3.5634204123e-01, 5.5473098802e-01, 3.5634204123e-01, -1.0777594153e-02, -1.6370632654e-01, -4.1604239425e-02, 9.0545335380e-02, 5.1008645773e-02, -5.1700554121e-02, -5.0309093724e-02, 2.7241749176e-02, 4.5724758263e-02, -1.0688751054e-02, -3.9306541246e-02, -6.4549692520e-04, 3.2077753537e-02, 8.1290343123e-03, -2.4706379782e-02, -1.2615303762e-02, 1.7682334350e-02, 1.4744464043e-02, -1.1366976828e-02, -1.5061536108e-02, 6.0068525240e-03, 1.4058482882e-02, -1.7398445415e-03, -1.2182859488e-02, -1.3978170954e-03, 9.8298700832e-03, 3.4562125456e-03, -7.3346907409e-03, -4.5566231615e-03, 4.9613893461e-03, 4.8694647415e-03, -2.8983074182e-03, -4.5919370873e-03, 1.2585962514e-03, 3.9264170707e-03, -8.6294827575e-05, -3.0615654156e-03, -6.3284598753e-04, 2.1576630162e-03, 9.5720862307e-04, -1.3370873498e-03, -9.7354686570e-04, 6.8017738605e-04, 7.8136180792e-04, -2.2612676235e-04, -4.7896593587e-04, -2.1970158766e-05, 1.5236012215e-04, 8.8939272976e-05, 1.3191487573e-04, -1.8403035937e-05, -3.3094790041e-04, -1.3744895834e-04, 4.2526537587e-04, 3.2649535977e-04, -4.1612973349e-04, -5.0368325235e-04, 3.2073263476e-04, 6.3567586190e-04, -1.6632027612e-04, -7.0301566465e-04, -1.5804201652e-05, 6.9999757638e-04, 1.9560355266e-04, -6.3270718567e-04, -3.4838793223e-04, 5.1583100637e-04, 4.5734587073e-04, -3.6890345513e-04, -5.1448028020e-04, 2.1260496857e-04, 5.2011019916e-04, -6.5657893369e-05, -4.8138440104e-04, -5.7543954433e-05, 4.0993927751e-04, 1.4805522141e-04, -3.1953754503e-04, -2.0264454791e-04, 2.2377561767e-04, 2.2316248954e-04, -1.3426716370e-04, -2.1531563984e-04, 5.9458033775e-05, 1.8713470943e-04, -4.1210749155e-06, -1.4741728946e-04, -3.0530082323e-05, 1.0437412713e-04, 4.6245620990e-05, -6.4636124159e-05, -4.6846333362e-05, 3.2693237716e-05, 3.7222234775e-05, -1.0761141791e-05, -2.2396337110e-05, -1.0036803910e-06, 6.7555658428e-06, 4.0053990895e-06, 6.4138787166e-06, -6.3327895214e-07, -1.5157992340e-05, -6.3568169131e-06, 1.8814046432e-05, 1.4363093885e-05, -1.7784646942e-05, -2.1311612230e-05, 1.3200217535e-05, 2.5857507600e-05, -6.5484048093e-06, -2.7421872543e-05, -6.6373904925e-07, 2.6096139036e-05, 7.1680394432e-06, -2.2460702942e-05, -1.2091222024e-05, 1.7367181073e-05, 1.5007022746e-05, -1.1729229997e-05, -1.5901411781e-05, 6.3528832905e-06, 1.5074076008e-05, -1.8315675010e-06, -1.3017335591e-05, -1.5034036873e-06, 1.0286744705e-05, 3.5711724673e-06, -7.3962527433e-06, -4.4915978325e-06, 4.7465613040e-06, 4.5141272867e-06, -2.5912407060e-06, -3.9432782180e-06, 1.0367750504e-06, 3.0746238214e-06, -6.7755353871e-08, -2.1499283239e-06, -4.1400006225e-07, 1.3342677196e-06, 5.4715344924e-07, -7.1331302147e-07, -4.7402882816e-07, 3.0555633077e-07, 3.1444110150e-07, -8.3034994960e-08, -1.5223428301e-07, -6.2882142522e-09, 3.2738579373e-08, 1.8615341511e-08, 3.0925190275e-08, -7.8893863768e-10, -4.7308459920e-08, -1.6475184244e-08}
COEFFICIENT_WIDTH 24
QUANTIZATION Quantize_Only
BESTPRECISION true
FILTER_TYPE Interpolation
INTERPOLATION_RATE 2
NUMBER_CHANNELS 2
NUMBER_PATHS 1
SAMPLE_FREQUENCY 1.25
CLOCK_FREQUENCY 125
OUTPUT_ROUNDING_MODE Convergent_Rounding_to_Even
OUTPUT_WIDTH 25
M_DATA_HAS_TREADY true
HAS_ARESETN true
} {
S_AXIS_DATA fp_0/M_AXIS_RESULT
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_dwidth_converter
cell xilinx.com:ip:axis_dwidth_converter:1.1 conv_1 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 4
M_TDATA_NUM_BYTES 8
} {
S_AXIS fir_0/M_AXIS_DATA
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_broadcaster
cell xilinx.com:ip:axis_broadcaster:1.1 bcast_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 8
M_TDATA_NUM_BYTES 3
M00_TDATA_REMAP {tdata[55:32]}
M01_TDATA_REMAP {tdata[23:0]}
} {
S_AXIS conv_1/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_variable
cell pavel-demin:user:axis_variable:1.0 rate_0 {
AXIS_TDATA_WIDTH 16
} {
cfg_data slice_2/dout
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_variable
cell pavel-demin:user:axis_variable:1.0 rate_1 {
AXIS_TDATA_WIDTH 16
} {
cfg_data slice_2/dout
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create cic_compiler
cell xilinx.com:ip:cic_compiler:4.0 cic_0 {
INPUT_DATA_WIDTH.VALUE_SRC USER
FILTER_TYPE Interpolation
NUMBER_OF_STAGES 6
SAMPLE_RATE_CHANGES Programmable
MINIMUM_RATE 50
MAXIMUM_RATE 8192
FIXED_OR_INITIAL_RATE 625
INPUT_SAMPLE_FREQUENCY 2.5
CLOCK_FREQUENCY 125
INPUT_DATA_WIDTH 24
QUANTIZATION Truncation
OUTPUT_DATA_WIDTH 24
USE_XTREME_DSP_SLICE false
HAS_ARESETN true
} {
S_AXIS_DATA bcast_0/M00_AXIS
S_AXIS_CONFIG rate_0/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create cic_compiler
cell xilinx.com:ip:cic_compiler:4.0 cic_1 {
INPUT_DATA_WIDTH.VALUE_SRC USER
FILTER_TYPE Interpolation
NUMBER_OF_STAGES 6
SAMPLE_RATE_CHANGES Programmable
MINIMUM_RATE 50
MAXIMUM_RATE 8192
FIXED_OR_INITIAL_RATE 625
INPUT_SAMPLE_FREQUENCY 2.5
CLOCK_FREQUENCY 125
INPUT_DATA_WIDTH 24
QUANTIZATION Truncation
OUTPUT_DATA_WIDTH 24
USE_XTREME_DSP_SLICE false
HAS_ARESETN true
} {
S_AXIS_DATA bcast_0/M01_AXIS
S_AXIS_CONFIG rate_1/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_combiner
cell xilinx.com:ip:axis_combiner:1.1 comb_0 {
TDATA_NUM_BYTES.VALUE_SRC USER
TDATA_NUM_BYTES 3
} {
S00_AXIS cic_0/M_AXIS_DATA
S01_AXIS cic_1/M_AXIS_DATA
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_constant
cell pavel-demin:user:axis_constant:1.0 phase_0 {
AXIS_TDATA_WIDTH 40
} {
cfg_data slice_1/dout
aclk /pll_0/clk_out1
}
# Create dds_compiler
cell xilinx.com:ip:dds_compiler:6.0 dds_0 {
DDS_CLOCK_RATE 125
SPURIOUS_FREE_DYNAMIC_RANGE 138
FREQUENCY_RESOLUTION 0.2
PHASE_INCREMENT Streaming
HAS_PHASE_OUT false
PHASE_WIDTH 30
OUTPUT_WIDTH 24
DSP48_USE Minimal
RESYNC true
} {
S_AXIS_PHASE phase_0/M_AXIS
aclk /pll_0/clk_out1
}
# Create axis_lfsr
cell pavel-demin:user:axis_lfsr:1.0 lfsr_0 {} {
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create cmpy
cell xilinx.com:ip:cmpy:6.0 mult_0 {
APORTWIDTH.VALUE_SRC USER
BPORTWIDTH.VALUE_SRC USER
APORTWIDTH 24
BPORTWIDTH 24
ROUNDMODE Random_Rounding
OUTPUTWIDTH 17
} {
S_AXIS_A comb_0/M_AXIS
S_AXIS_B dds_0/M_AXIS_DATA
S_AXIS_CTRL lfsr_0/M_AXIS
aclk /pll_0/clk_out1
}