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# Create clk_wiz
cell xilinx.com:ip:clk_wiz:6.0 pll_0 {
PRIMITIVE PLL
PRIM_IN_FREQ.VALUE_SRC USER
PRIM_IN_FREQ 125.0
PRIM_SOURCE Differential_clock_capable_pin
CLKOUT1_USED true
CLKOUT1_REQUESTED_OUT_FREQ 125.0
CLKOUT2_USED true
CLKOUT2_REQUESTED_OUT_FREQ 250.0
CLKOUT2_REQUESTED_PHASE -90.0
USE_RESET false
} {
clk_in1_p adc_clk_p_i
clk_in1_n adc_clk_n_i
}
# Create processing_system7
cell xilinx.com:ip:processing_system7:5.5 ps_0 {
PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
} {
M_AXI_GP0_ACLK pll_0/clk_out1
}
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
make_external {FIXED_IO, DDR}
Master Disable
Slave Disable
} [get_bd_cells ps_0]
# Create xlconstant
cell xilinx.com:ip:xlconstant:1.1 const_0
# Create proc_sys_reset
cell xilinx.com:ip:proc_sys_reset:5.0 rst_0 {} {
ext_reset_in const_0/dout
}
# XADC
# Create xadc_wiz
cell xilinx.com:ip:xadc_wiz:3.3 xadc_0 {
DCLK_FREQUENCY 125
ADC_CONVERSION_RATE 200
XADC_STARUP_SELECTION independent_adc
CHANNEL_ENABLE_VAUXP0_VAUXN0 true
CHANNEL_ENABLE_VAUXP1_VAUXN1 true
CHANNEL_ENABLE_VAUXP8_VAUXN8 true
CHANNEL_ENABLE_VAUXP9_VAUXN9 true
CHANNEL_ENABLE_VP_VN true
} {
Vp_Vn Vp_Vn
Vaux0 Vaux0
Vaux1 Vaux1
Vaux8 Vaux8
Vaux9 Vaux9
}
# ADC
# Create axis_red_pitaya_adc
cell pavel-demin:user:axis_red_pitaya_adc:2.0 adc_0 {} {
aclk pll_0/clk_out1
adc_dat_a adc_dat_a_i
adc_dat_b adc_dat_b_i
adc_csn adc_csn_o
}
# DAC
# Create axis_red_pitaya_dac
cell pavel-demin:user:axis_red_pitaya_dac:1.0 dac_0 {} {
aclk pll_0/clk_out1
ddr_clk pll_0/clk_out2
locked pll_0/locked
dac_clk dac_clk_o
dac_rst dac_rst_o
dac_sel dac_sel_o
dac_wrt dac_wrt_o
dac_dat dac_dat_o
s_axis_tvalid const_0/dout
}
# CFG
# Create axi_cfg_register
cell pavel-demin:user:axi_cfg_register:1.0 cfg_0 {
CFG_DATA_WIDTH 288
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
}
# GPIO
# Delete input/output port
delete_bd_objs [get_bd_ports exp_n_tri_io]
# Create input/output port
create_bd_port -dir IO -from 3 -to 0 exp_n_tri_io
# Create gpio_debouncer
cell pavel-demin:user:gpio_debouncer:1.0 gpio_0 {
DATA_WIDTH 4
CNTR_WIDTH 16
} {
gpio_data exp_n_tri_io
aclk pll_0/clk_out1
}
# Create util_vector_logic
cell xilinx.com:ip:util_vector_logic:2.0 not_0 {
C_SIZE 4
C_OPERATION not
} {
Op1 gpio_0/deb_data
}
# Delete input/output port
delete_bd_objs [get_bd_ports exp_p_tri_io]
# Create output port
create_bd_port -dir O -from 7 -to 0 exp_p_tri_io
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 out_slice_0 {
DIN_WIDTH 288 DIN_FROM 31 DIN_TO 24
} {
din cfg_0/cfg_data
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 ptt_slice_0 {
DIN_WIDTH 288 DIN_FROM 20 DIN_TO 20
} {
din cfg_0/cfg_data
}
# Create util_vector_logic
cell xilinx.com:ip:util_vector_logic:2.0 or_0 {
C_SIZE 1
C_OPERATION or
} {
Op1 ptt_slice_0/dout
Op2 not_0/Res
}
# Create util_vector_logic
cell xilinx.com:ip:util_vector_logic:2.0 or_1 {
C_SIZE 8
C_OPERATION or
} {
Op1 out_slice_0/dout
Op2 or_0/Res
Res exp_p_tri_io
}
# ALEX
# Create output port
create_bd_port -dir IO -from 3 -to 0 exp_n_alex
# Create axi_axis_writer
cell pavel-demin:user:axi_axis_writer:1.0 writer_0 {
AXI_DATA_WIDTH 32
} {
aclk pll_0/clk_out1
aresetn rst_0/peripheral_aresetn
}
# Create axis_data_fifo
cell xilinx.com:ip:axis_data_fifo:1.1 fifo_0 {
TDATA_NUM_BYTES.VALUE_SRC USER
TDATA_NUM_BYTES 4
FIFO_DEPTH 1024
} {
S_AXIS writer_0/M_AXIS
s_axis_aclk pll_0/clk_out1
s_axis_aresetn rst_0/peripheral_aresetn
}
# Create axis_alex
cell pavel-demin:user:axis_alex:1.0 alex_0 {} {
S_AXIS fifo_0/M_AXIS
aclk pll_0/clk_out1
aresetn rst_0/peripheral_aresetn
}
# RX 0
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 rst_slice_0 {
DIN_WIDTH 288 DIN_FROM 7 DIN_TO 0
} {
din cfg_0/cfg_data
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 rst_slice_1 {
DIN_WIDTH 288 DIN_FROM 15 DIN_TO 8
} {
din cfg_0/cfg_data
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 cfg_slice_0 {
DIN_WIDTH 288 DIN_FROM 127 DIN_TO 32
} {
din cfg_0/cfg_data
}
module rx_0 {
source projects/sdr_transceiver_hpsdr/rx.tcl
} {
slice_0/din rst_slice_0/dout
slice_1/din rst_slice_1/dout
slice_2/din rst_slice_1/dout
slice_3/din cfg_slice_0/dout
slice_4/din cfg_slice_0/dout
slice_5/din cfg_slice_0/dout
slice_6/din cfg_slice_0/dout
slice_7/din cfg_slice_0/dout
slice_8/din cfg_slice_0/dout
}
# TX 0
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 rst_slice_2 {
DIN_WIDTH 288 DIN_FROM 16 DIN_TO 16
} {
din cfg_0/cfg_data
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 rst_slice_3 {
DIN_WIDTH 288 DIN_FROM 17 DIN_TO 17
} {
din cfg_0/cfg_data
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 key_slice_0 {
DIN_WIDTH 288 DIN_FROM 18 DIN_TO 18
} {
din cfg_0/cfg_data
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 key_slice_1 {
DIN_WIDTH 288 DIN_FROM 19 DIN_TO 19
} {
din cfg_0/cfg_data
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 cfg_slice_1 {
DIN_WIDTH 288 DIN_FROM 223 DIN_TO 128
} {
din cfg_0/cfg_data
}
module tx_0 {
source projects/sdr_transceiver_hpsdr/tx.tcl
} {
fifo_generator_0/srst rst_slice_2/dout
keyer_0/key_flag key_slice_0/dout
slice_0/din rst_slice_1/dout
slice_1/din cfg_slice_1/dout
slice_2/din cfg_slice_1/dout
slice_3/din cfg_slice_1/dout
slice_4/din cfg_slice_1/dout
slice_5/din cfg_slice_1/dout
slice_6/din cfg_slice_1/dout
dds_0/m_axis_data_tdata rx_0/dds_slice_4/din
dds_0/m_axis_data_tdata rx_0/dds_slice_5/din
dds_0/m_axis_data_tdata rx_0/dds_slice_6/din
dds_0/m_axis_data_tdata rx_0/dds_slice_7/din
concat_1/dout dac_0/s_axis_tdata
mult_2/P rx_0/adc_slice_6/din
mult_2/P rx_0/adc_slice_7/din
}
# CODEC
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 cfg_slice_2 {
DIN_WIDTH 288 DIN_FROM 287 DIN_TO 224
} {
din cfg_0/cfg_data
}
module codec {
source projects/sdr_transceiver_hpsdr/codec.tcl
} {
fifo_generator_0/srst rst_slice_3/dout
keyer_0/key_flag key_slice_1/dout
slice_0/din rst_slice_0/dout
slice_1/din rst_slice_0/dout
slice_2/din cfg_slice_2/dout
slice_3/din cfg_slice_2/dout
slice_4/din cfg_slice_2/dout
i2s_0/gpio_data exp_n_alex
i2s_0/alex_data alex_0/alex_data
}
# STS
# Create dna_reader
cell pavel-demin:user:dna_reader:1.0 dna_0 {} {
aclk pll_0/clk_out1
aresetn rst_0/peripheral_aresetn
}
# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_0 {
NUM_PORTS 7
IN0_WIDTH 32
IN1_WIDTH 64
IN2_WIDTH 16
IN3_WIDTH 16
IN4_WIDTH 16
IN5_WIDTH 16
IN6_WIDTH 4
} {
In0 const_0/dout
In1 dna_0/dna_data
In2 rx_0/fifo_generator_0/rd_data_count
In3 tx_0/fifo_generator_0/wr_data_count
In4 codec/fifo_generator_0/data_count
In5 codec/fifo_generator_1/data_count
In6 not_0/Res
}
# Create axi_sts_register
cell pavel-demin:user:axi_sts_register:1.0 sts_0 {
STS_DATA_WIDTH 192
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
} {
sts_data concat_0/dout
}
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins sts_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg0]
set_property OFFSET 0x40000000 [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg0]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins cfg_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
set_property OFFSET 0x40001000 [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins writer_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg0]
set_property OFFSET 0x40002000 [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg0]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins rx_0/reader_0/S_AXI]
set_property RANGE 32K [get_bd_addr_segs ps_0/Data/SEG_reader_0_reg0]
set_property OFFSET 0x40010000 [get_bd_addr_segs ps_0/Data/SEG_reader_0_reg0]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins tx_0/writer_0/S_AXI]
set_property RANGE 16K [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg01]
set_property OFFSET 0x4000C000 [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg01]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins tx_0/switch_0/S_AXI_CTRL]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_switch_0_Reg]
set_property OFFSET 0x40003000 [get_bd_addr_segs ps_0/Data/SEG_switch_0_Reg]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins tx_0/writer_1/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_writer_1_reg0]
set_property OFFSET 0x40004000 [get_bd_addr_segs ps_0/Data/SEG_writer_1_reg0]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins codec/writer_1/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_writer_1_reg01]
set_property OFFSET 0x40005000 [get_bd_addr_segs ps_0/Data/SEG_writer_1_reg01]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins codec/writer_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg02]
set_property OFFSET 0x40006000 [get_bd_addr_segs ps_0/Data/SEG_writer_0_reg02]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins codec/reader_0/S_AXI]
set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_reader_0_reg01]
set_property OFFSET 0x40007000 [get_bd_addr_segs ps_0/Data/SEG_reader_0_reg01]
# Create all required interconnections
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
Master /ps_0/M_AXI_GP0
Clk Auto
} [get_bd_intf_pins xadc_0/s_axi_lite]
set_property RANGE 64K [get_bd_addr_segs ps_0/Data/SEG_xadc_0_Reg]
set_property OFFSET 0x40020000 [get_bd_addr_segs ps_0/Data/SEG_xadc_0_Reg]