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# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_0 {
DIN_WIDTH 8 DIN_FROM 2 DIN_TO 2
}
cell pavel-demin:user:port_slicer:1.0 slice_1 {
DIN_WIDTH 96 DIN_FROM 31 DIN_TO 0
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_2 {
DIN_WIDTH 96 DIN_FROM 47 DIN_TO 32
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_3 {
DIN_WIDTH 96 DIN_FROM 63 DIN_TO 48
}
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_4 {
DIN_WIDTH 96 DIN_FROM 79 DIN_TO 64
}
# Create axi_axis_writer
cell pavel-demin:user:axi_axis_writer:1.0 writer_0 {
AXI_DATA_WIDTH 32
} {
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create fifo_generator
cell xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 {
PERFORMANCE_OPTIONS First_Word_Fall_Through
INPUT_DATA_WIDTH 32
INPUT_DEPTH 4096
OUTPUT_DATA_WIDTH 64
OUTPUT_DEPTH 2048
WRITE_DATA_COUNT true
WRITE_DATA_COUNT_WIDTH 13
} {
clk /pll_0/clk_out1
}
# Create axis_fifo
cell pavel-demin:user:axis_fifo:1.0 fifo_0 {
S_AXIS_TDATA_WIDTH 32
M_AXIS_TDATA_WIDTH 64
} {
S_AXIS writer_0/M_AXIS
FIFO_READ fifo_generator_0/FIFO_READ
FIFO_WRITE fifo_generator_0/FIFO_WRITE
aclk /pll_0/clk_out1
}
# Create axis_subset_converter
cell xilinx.com:ip:axis_subset_converter:1.1 subset_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 8
M_TDATA_NUM_BYTES 8
TDATA_REMAP {tdata[39:32],tdata[47:40],tdata[55:48],tdata[63:56],tdata[7:0],tdata[15:8],tdata[23:16],tdata[31:24]}
} {
S_AXIS fifo_0/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_dwidth_converter
cell xilinx.com:ip:axis_dwidth_converter:1.1 conv_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 8
M_TDATA_NUM_BYTES 2
} {
S_AXIS subset_0/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create fir_compiler
cell xilinx.com:ip:fir_compiler:7.2 fir_0 {
DATA_WIDTH.VALUE_SRC USER
DATA_WIDTH 16
COEFFICIENTVECTOR {-1.6278583749e-08, -4.5104335216e-08, 1.8643238703e-10, 2.9518100256e-08, 1.6311668874e-08, 3.1133681432e-08, -3.8485539239e-09, -1.4496770037e-07, -8.2348991437e-08, 2.9937360243e-07, 2.9598773091e-07, -4.5094100085e-07, -6.8677196871e-07, 5.1944305851e-07, 1.2813799827e-06, -3.9025624673e-07, -2.0620561572e-06, -7.2763738594e-08, 2.9467958813e-06, 1.0022594115e-06, -3.7776536280e-06, -2.4921695179e-06, 4.3233346157e-06, 4.5572931869e-06, -4.3010589667e-06, -7.0958807987e-06, 3.4194451300e-06, 9.8655347899e-06, -1.4397018132e-06, -1.2483145541e-05, -1.7531304190e-06, 1.4457261586e-05, 6.0821714072e-06, -1.5256563422e-05, -1.1231147383e-05, 1.4410068309e-05, 1.6633274615e-05, -1.1630690946e-05, -2.1518372186e-05, 6.9311743997e-06, 2.5013333856e-05, -7.1818040873e-07, -2.6304243924e-05, -6.1744598820e-06, 2.4836281635e-05, 1.2535520867e-05, -2.0521832409e-05, -1.6925480024e-05, 1.3913857425e-05, 1.7923375998e-05, -6.2972919510e-06, -1.4449694558e-05, -3.4620041308e-07, 6.1206012671e-06, 3.5305735921e-06, 6.4294495935e-06, -6.2270472593e-07, -2.1331802745e-05, -1.0659990885e-05, 3.5444490810e-05, 3.1658636026e-05, -4.4572750908e-05, -6.2221593684e-05, 4.3914342607e-05, 1.0022883041e-04, -2.8794119985e-05, -1.4138599782e-04, -4.4410295010e-06, 1.7935164513e-04, 5.7464786503e-05, -2.0627343640e-04, -1.2911737100e-04, 2.1373727566e-04, 2.1483614434e-04, -1.9406127810e-04, -3.0654650750e-04, 1.4178437355e-04, 3.9314444115e-04, -5.5130787833e-05, -4.6162887546e-04, -6.2817909035e-05, 4.9883735128e-04, 2.0351771369e-04, -4.9363723808e-04, -3.5321408521e-04, 4.3918593995e-04, 4.9401653821e-04, -3.3516452954e-04, -6.0615931268e-04, 1.8920172903e-04, 6.7096892179e-04, -1.7350955410e-05, -6.7440278901e-04, -1.5680392675e-04, 6.1063649055e-04, 3.0456712827e-04, -4.8511288738e-04, -3.9603152123e-04, 3.1641789232e-04, 4.0516601081e-04, -1.3640259101e-04, -3.1554823891e-04, -1.1883132473e-05, 1.2598053968e-04, 7.8631635673e-05, 1.4491298202e-04, -1.3969570155e-05, -4.5610222421e-04, -2.2378320086e-04, 7.4397749846e-04, 6.5835462984e-04, -9.2630980215e-04, -1.2867792077e-03, 9.0909156314e-04, 2.0715811175e-03, -5.9716488691e-04, -2.9359477263e-03, -9.2463414834e-05, 3.7628678529e-03, 1.2156917746e-03, -4.3990734542e-03, -2.7862612849e-03, 4.6641282868e-03, 4.7622285630e-03, -4.3644247141e-03, -7.0356212669e-03, 3.3112164722e-03, 9.4266299861e-03, -1.3412354458e-03, -1.1683103269e-02, -1.6620127318e-03, 1.3484958927e-02, 5.7472746753e-03, -1.4454699130e-02, -1.0881151329e-02, 1.4164854778e-02, 1.6933807785e-02, -1.2145465112e-02, -2.3672753626e-02, 7.8756806946e-03, 3.0757968251e-02, -7.4318033188e-04, -3.7730976788e-02, -1.0069903021e-02, 4.3972783795e-02, 2.5878915097e-02, -4.8548541342e-02, -4.9281216309e-02, 4.9608677905e-02, 8.6599384013e-02, -4.1546560705e-02, -1.5767521732e-01, -5.9696600342e-03, 3.5273682025e-01, 5.4609132429e-01, 3.5273682025e-01, -5.9696600342e-03, -1.5767521732e-01, -4.1546560705e-02, 8.6599384013e-02, 4.9608677905e-02, -4.9281216309e-02, -4.8548541342e-02, 2.5878915097e-02, 4.3972783795e-02, -1.0069903021e-02, -3.7730976788e-02, -7.4318033188e-04, 3.0757968251e-02, 7.8756806946e-03, -2.3672753626e-02, -1.2145465112e-02, 1.6933807785e-02, 1.4164854778e-02, -1.0881151329e-02, -1.4454699130e-02, 5.7472746753e-03, 1.3484958927e-02, -1.6620127318e-03, -1.1683103269e-02, -1.3412354458e-03, 9.4266299861e-03, 3.3112164722e-03, -7.0356212669e-03, -4.3644247141e-03, 4.7622285630e-03, 4.6641282868e-03, -2.7862612849e-03, -4.3990734542e-03, 1.2156917746e-03, 3.7628678529e-03, -9.2463414834e-05, -2.9359477263e-03, -5.9716488691e-04, 2.0715811175e-03, 9.0909156314e-04, -1.2867792077e-03, -9.2630980215e-04, 6.5835462984e-04, 7.4397749846e-04, -2.2378320086e-04, -4.5610222421e-04, -1.3969570155e-05, 1.4491298202e-04, 7.8631635673e-05, 1.2598053968e-04, -1.1883132473e-05, -3.1554823891e-04, -1.3640259101e-04, 4.0516601081e-04, 3.1641789232e-04, -3.9603152123e-04, -4.8511288738e-04, 3.0456712827e-04, 6.1063649055e-04, -1.5680392675e-04, -6.7440278901e-04, -1.7350955411e-05, 6.7096892179e-04, 1.8920172903e-04, -6.0615931268e-04, -3.3516452954e-04, 4.9401653821e-04, 4.3918593995e-04, -3.5321408521e-04, -4.9363723808e-04, 2.0351771369e-04, 4.9883735128e-04, -6.2817909035e-05, -4.6162887546e-04, -5.5130787833e-05, 3.9314444115e-04, 1.4178437355e-04, -3.0654650750e-04, -1.9406127810e-04, 2.1483614434e-04, 2.1373727566e-04, -1.2911737100e-04, -2.0627343640e-04, 5.7464786503e-05, 1.7935164513e-04, -4.4410295010e-06, -1.4138599782e-04, -2.8794119985e-05, 1.0022883041e-04, 4.3914342607e-05, -6.2221593684e-05, -4.4572750908e-05, 3.1658636026e-05, 3.5444490810e-05, -1.0659990885e-05, -2.1331802745e-05, -6.2270472593e-07, 6.4294495935e-06, 3.5305735921e-06, 6.1206012671e-06, -3.4620041308e-07, -1.4449694558e-05, -6.2972919510e-06, 1.7923375998e-05, 1.3913857425e-05, -1.6925480024e-05, -2.0521832409e-05, 1.2535520867e-05, 2.4836281635e-05, -6.1744598820e-06, -2.6304243924e-05, -7.1818040873e-07, 2.5013333856e-05, 6.9311743997e-06, -2.1518372186e-05, -1.1630690946e-05, 1.6633274615e-05, 1.4410068309e-05, -1.1231147383e-05, -1.5256563422e-05, 6.0821714072e-06, 1.4457261586e-05, -1.7531304190e-06, -1.2483145541e-05, -1.4397018132e-06, 9.8655347899e-06, 3.4194451300e-06, -7.0958807987e-06, -4.3010589667e-06, 4.5572931869e-06, 4.3233346157e-06, -2.4921695179e-06, -3.7776536280e-06, 1.0022594115e-06, 2.9467958813e-06, -7.2763738594e-08, -2.0620561572e-06, -3.9025624673e-07, 1.2813799827e-06, 5.1944305851e-07, -6.8677196871e-07, -4.5094100085e-07, 2.9598773091e-07, 2.9937360243e-07, -8.2348991437e-08, -1.4496770037e-07, -3.8485539239e-09, 3.1133681432e-08, 1.6311668874e-08, 2.9518100256e-08, 1.8643238703e-10, -4.5104335216e-08, -1.6278583749e-08}
COEFFICIENT_WIDTH 24
QUANTIZATION Quantize_Only
BESTPRECISION true
FILTER_TYPE Interpolation
INTERPOLATION_RATE 2
NUMBER_CHANNELS 4
NUMBER_PATHS 1
SAMPLE_FREQUENCY 0.048
CLOCK_FREQUENCY 125
OUTPUT_ROUNDING_MODE Convergent_Rounding_to_Even
OUTPUT_WIDTH 25
M_DATA_HAS_TREADY true
HAS_ARESETN true
} {
S_AXIS_DATA conv_0/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_subset_converter
cell xilinx.com:ip:axis_subset_converter:1.1 subset_1 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 4
M_TDATA_NUM_BYTES 3
TDATA_REMAP {tdata[23:0]}
} {
S_AXIS fir_0/M_AXIS_DATA
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create fir_compiler
cell xilinx.com:ip:fir_compiler:7.2 fir_1 {
DATA_WIDTH.VALUE_SRC USER
DATA_WIDTH 24
COEFFICIENTVECTOR {-1.5956605232e-08, -1.4027210574e-08, -1.1469474085e-08, -8.2836180146e-09, -4.4848080991e-09, -1.0407677321e-10, 4.8110008357e-09, 1.0195908361e-08, 1.5969094293e-08, 2.2032206221e-08, 2.8270672406e-08, 3.4554644949e-08, 4.0740313387e-08, 4.6671591588e-08, 5.2182174508e-08, 5.7097954686e-08, 6.1239781454e-08, 6.4426538826e-08, 6.6478510946e-08, 6.7220997028e-08, 6.6488130959e-08, 6.4126854274e-08, 6.0000985295e-08, 5.3995321744e-08, 4.6019709490e-08, 3.6013006137e-08, 2.3946865196e-08, 9.8292645898e-09, -6.2922976469e-09, -2.4328017293e-08, -4.4143482806e-08, -6.5557931595e-08, -8.8343132082e-08, -1.1222295444e-07, -1.3687368619e-07, -1.6192514079e-07, -1.8696259810e-07, -2.1152960516e-07, -2.3513165443e-07, -2.5724074395e-07, -2.7730081109e-07, -2.9473401721e-07, -3.0894784686e-07, -3.1934296990e-07, -3.2532180081e-07, -3.2629767448e-07, -3.2170454392e-07, -3.1100709153e-07, -2.9371113275e-07, -2.6937417944e-07, -2.3761601956e-07, -1.9812916099e-07, -1.5068897995e-07, -9.5163409297e-08, -3.1521998405e-08, 4.0155824245e-08, 1.1967345374e-07, 2.0671094052e-07, 3.0082010894e-07, 4.0142111114e-07, 5.0780055343e-07, 6.1911131812e-07, 7.3437418709e-07, 8.5248135465e-07, 9.7220189568e-07, 1.0921892320e-06, 1.2109906146e-06, 1.3270586133e-06, 1.4387645756e-06, 1.5444139913e-06, 1.6422636642e-06, 1.7305405697e-06, 1.8074622400e-06, 1.8712584962e-06, 1.9201943142e-06, 1.9525935870e-06, 1.9668635208e-06, 1.9615193811e-06, 1.9352092825e-06, 1.8867387042e-06, 1.8150943962e-06, 1.7194673338e-06, 1.5992743742e-06, 1.4541782669e-06, 1.2841056739e-06, 1.0892628669e-06, 8.7014877882e-07, 6.2756510963e-07, 3.6262320741e-07, 7.6747475520e-08, -2.2832491072e-07, -5.5054815637e-07, -8.8757600555e-07, -1.2367739979e-06, -1.5952358658e-06, -1.9598040633e-06, -2.3270943647e-06, -2.6935244141e-06, -3.0553460519e-06, -3.4086811865e-06, -3.7495609242e-06, -4.0739676135e-06, -4.3778794099e-06, -4.6573169136e-06, -4.9083913879e-06, -5.1273540235e-06, -5.3106456767e-06, -5.4549464756e-06, -5.5572246687e-06, -5.6147840662e-06, -5.6253094176e-06, -5.5869090670e-06, -5.4981542305e-06, -5.3581142599e-06, -5.1663872742e-06, -4.9231255797e-06, -4.6290553358e-06, -4.2854899774e-06, -3.8943369612e-06, -3.4580974711e-06, -2.9798587931e-06, -2.4632791492e-06, -1.9125648688e-06, -1.3324398685e-06, -7.2810750670e-07, -1.0520498256e-07, 5.3024945391e-07, 1.1719161057e-06, 1.8131997731e-06, 2.4473214626e-06, 3.0673951871e-06, 3.6665090930e-06, 4.2378100594e-06, 4.7745908391e-06, 5.2703787377e-06, 5.7190247651e-06, 6.1147921466e-06, 6.4524430401e-06, 6.7273222820e-06, 6.9354369744e-06, 7.0735307280e-06, 7.1391513965e-06, 7.1307111696e-06, 7.0475379464e-06, 6.8899169725e-06, 6.6591218089e-06, 6.3574337970e-06, 5.9881492925e-06, 5.5555740719e-06, 5.0650044462e-06, 4.5226947708e-06, 3.9358111968e-06, 3.3123716776e-06, 2.6611724198e-06, 1.9917011434e-06, 1.3140377019e-06, 6.3874279225e-07, -2.3264333924e-08, -6.6083807074e-07, -1.2627473117e-06, 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5.3995321744e-08, 6.0000985295e-08, 6.4126854274e-08, 6.6488130959e-08, 6.7220997028e-08, 6.6478510946e-08, 6.4426538826e-08, 6.1239781454e-08, 5.7097954686e-08, 5.2182174508e-08, 4.6671591588e-08, 4.0740313387e-08, 3.4554644949e-08, 2.8270672406e-08, 2.2032206221e-08, 1.5969094293e-08, 1.0195908361e-08, 4.8110008357e-09, -1.0407677321e-10, -4.4848080991e-09, -8.2836180146e-09, -1.1469474085e-08, -1.4027210574e-08, -1.5956605232e-08}
COEFFICIENT_WIDTH 24
QUANTIZATION Maximize_Dynamic_Range
BESTPRECISION true
FILTER_TYPE Interpolation
RATE_CHANGE_TYPE Fixed_Fractional
INTERPOLATION_RATE 25
DECIMATION_RATE 24
NUMBER_CHANNELS 4
NUMBER_PATHS 1
SAMPLE_FREQUENCY 0.096
CLOCK_FREQUENCY 125
OUTPUT_ROUNDING_MODE Convergent_Rounding_to_Even
OUTPUT_WIDTH 26
M_DATA_HAS_TREADY true
HAS_ARESETN true
} {
S_AXIS_DATA subset_1/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_subset_converter
cell xilinx.com:ip:axis_subset_converter:1.1 subset_2 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 4
M_TDATA_NUM_BYTES 3
TDATA_REMAP {tdata[23:0]}
} {
S_AXIS fir_1/M_AXIS_DATA
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_dwidth_converter
cell xilinx.com:ip:axis_dwidth_converter:1.1 conv_1 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 3
M_TDATA_NUM_BYTES 12
} {
S_AXIS subset_2/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_broadcaster
cell xilinx.com:ip:axis_broadcaster:1.1 bcast_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 12
M_TDATA_NUM_BYTES 6
M00_TDATA_REMAP {tdata[47:0]}
M01_TDATA_REMAP {tdata[95:48]}
} {
S_AXIS conv_1/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create blk_mem_gen
cell xilinx.com:ip:blk_mem_gen:8.4 bram_0 {
MEMORY_TYPE True_Dual_Port_RAM
USE_BRAM_BLOCK Stand_Alone
WRITE_WIDTH_A 32
WRITE_DEPTH_A 1024
WRITE_WIDTH_B 32
ENABLE_A Always_Enabled
ENABLE_B Always_Enabled
REGISTER_PORTB_OUTPUT_OF_MEMORY_PRIMITIVES false
}
# Create axi_bram_writer
cell pavel-demin:user:axi_bram_writer:1.0 writer_1 {
AXI_DATA_WIDTH 32
AXI_ADDR_WIDTH 32
BRAM_DATA_WIDTH 32
BRAM_ADDR_WIDTH 10
} {
BRAM_PORTA bram_0/BRAM_PORTA
}
# Create axis_keyer
cell pavel-demin:user:axis_keyer:1.0 keyer_0 {
AXIS_TDATA_WIDTH 32
BRAM_DATA_WIDTH 32
BRAM_ADDR_WIDTH 10
} {
BRAM_PORTA bram_0/BRAM_PORTB
cfg_data slice_2/dout
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_subset_converter
cell xilinx.com:ip:axis_subset_converter:1.1 subset_3 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 4
M_TDATA_NUM_BYTES 6
TDATA_REMAP {24'b000000000000000000000000,tdata[23:0]}
} {
S_AXIS keyer_0/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_switch
cell xilinx.com:ip:axis_switch:1.1 switch_0 {
TDATA_NUM_BYTES.VALUE_SRC USER
TDATA_NUM_BYTES 6
ROUTING_MODE 1
NUM_SI 2
NUM_MI 1
} {
S00_AXIS bcast_0/M00_AXIS
S01_AXIS subset_3/M_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_broadcaster
cell xilinx.com:ip:axis_broadcaster:1.1 bcast_1 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 6
M_TDATA_NUM_BYTES 3
M00_TDATA_REMAP {tdata[23:0]}
M01_TDATA_REMAP {tdata[47:24]}
} {
S_AXIS switch_0/M00_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_broadcaster
cell xilinx.com:ip:axis_broadcaster:1.1 bcast_2 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 6
M_TDATA_NUM_BYTES 3
M00_TDATA_REMAP {tdata[23:0]}
M01_TDATA_REMAP {tdata[47:24]}
} {
S_AXIS bcast_0/M01_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
for {set i 0} {$i <= 3} {incr i} {
# Create cic_compiler
cell xilinx.com:ip:cic_compiler:4.0 cic_$i {
INPUT_DATA_WIDTH.VALUE_SRC USER
FILTER_TYPE Interpolation
NUMBER_OF_STAGES 6
FIXED_OR_INITIAL_RATE 1250
INPUT_SAMPLE_FREQUENCY 0.1
CLOCK_FREQUENCY 125
INPUT_DATA_WIDTH 24
QUANTIZATION Truncation
OUTPUT_DATA_WIDTH 24
USE_XTREME_DSP_SLICE false
HAS_ARESETN true
} {
S_AXIS_DATA bcast_[expr $i / 2 + 1]/M0[expr $i % 2]_AXIS
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
}
# Create axis_combiner
cell xilinx.com:ip:axis_combiner:1.1 comb_0 {
TDATA_NUM_BYTES.VALUE_SRC USER
TDATA_NUM_BYTES 3
} {
S00_AXIS cic_0/M_AXIS_DATA
S01_AXIS cic_1/M_AXIS_DATA
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create axis_constant
cell pavel-demin:user:axis_constant:1.0 phase_0 {
AXIS_TDATA_WIDTH 32
} {
cfg_data slice_1/dout
aclk /pll_0/clk_out1
}
# Create dds_compiler
cell xilinx.com:ip:dds_compiler:6.0 dds_0 {
DDS_CLOCK_RATE 125
SPURIOUS_FREE_DYNAMIC_RANGE 138
FREQUENCY_RESOLUTION 0.2
PHASE_INCREMENT Streaming
HAS_ARESETN true
HAS_PHASE_OUT false
PHASE_WIDTH 30
OUTPUT_WIDTH 24
DSP48_USE Minimal
} {
S_AXIS_PHASE phase_0/M_AXIS
aclk /pll_0/clk_out1
aresetn slice_0/dout
}
# Create axis_lfsr
cell pavel-demin:user:axis_lfsr:1.0 lfsr_0 {} {
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create cmpy
cell xilinx.com:ip:cmpy:6.0 mult_0 {
APORTWIDTH.VALUE_SRC USER
BPORTWIDTH.VALUE_SRC USER
APORTWIDTH 24
BPORTWIDTH 24
ROUNDMODE Random_Rounding
OUTPUTWIDTH 26
} {
S_AXIS_A comb_0/M_AXIS
s_axis_b_tdata dds_0/m_axis_data_tdata
s_axis_b_tvalid dds_0/m_axis_data_tvalid
S_AXIS_CTRL lfsr_0/M_AXIS
aclk /pll_0/clk_out1
}
# Create axis_lfsr
cell pavel-demin:user:axis_lfsr:1.0 lfsr_1 {} {
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create xbip_dsp48_macro
cell xilinx.com:ip:xbip_dsp48_macro:3.0 mult_1 {
INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
A_WIDTH.VALUE_SRC USER
B_WIDTH.VALUE_SRC USER
OUTPUT_PROPERTIES User_Defined
A_WIDTH 24
B_WIDTH 16
P_WIDTH 16
} {
A mult_0/m_axis_dout_tdata
B slice_3/dout
CARRYIN lfsr_1/m_axis_tdata
CLK /pll_0/clk_out1
}
# Create xbip_dsp48_macro
cell xilinx.com:ip:xbip_dsp48_macro:3.0 mult_2 {
INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
A_WIDTH.VALUE_SRC USER
B_WIDTH.VALUE_SRC USER
OUTPUT_PROPERTIES User_Defined
A_WIDTH 24
B_WIDTH 16
P_WIDTH 16
} {
A mult_0/m_axis_dout_tdata
B slice_4/dout
CARRYIN lfsr_1/m_axis_tdata
CLK /pll_0/clk_out1
}
# Create axis_combiner
cell xilinx.com:ip:axis_combiner:1.1 comb_1 {
TDATA_NUM_BYTES.VALUE_SRC USER
TDATA_NUM_BYTES 3
} {
S00_AXIS cic_2/M_AXIS_DATA
S01_AXIS cic_3/M_AXIS_DATA
aclk /pll_0/clk_out1
aresetn /rst_0/peripheral_aresetn
}
# Create cordic
cell xilinx.com:ip:cordic:6.0 cordic_0 {
INPUT_WIDTH.VALUE_SRC USER
FUNCTIONAL_SELECTION Translate
PIPELINING_MODE Optimal
INPUT_WIDTH 24
OUTPUT_WIDTH 15
ROUND_MODE Round_Pos_Neg_Inf
COMPENSATION_SCALING Embedded_Multiplier
} {
S_AXIS_CARTESIAN comb_1/M_AXIS
aclk /pll_0/clk_out1
}
# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_0 {
NUM_PORTS 2
IN0_WIDTH 16
IN1_WIDTH 16
} {
In0 mult_1/P
In1 cordic_0/m_axis_dout_tdata
}
for {set i 0} {$i <= 1} {incr i} {
# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_[expr $i + 5] {
DIN_WIDTH 96 DIN_FROM [expr $i + 80] DIN_TO [expr $i + 80]
}
# Create port_selector
cell pavel-demin:user:port_selector:1.0 selector_$i {
DOUT_WIDTH 16
} {
cfg slice_[expr $i + 5]/dout
din concat_0/dout
}
}
# Create xlconcat
cell xilinx.com:ip:xlconcat:2.1 concat_1 {
NUM_PORTS 2
IN0_WIDTH 16
IN1_WIDTH 16
} {
In0 selector_0/dout
In1 selector_1/dout
}