{"payload":{"header_redesign_enabled":false,"results":[{"id":"446579305","archived":false,"color":"#adb2cb","followers":0,"has_funding_file":false,"hl_name":"paxtonproctor/3023_Logic_Design","hl_trunc_description":"Study of topics related to the design of modern microprocessors, including Boolean algebra, logic gates, design simplification techniques…","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":446579305,"name":"3023_Logic_Design","owner_id":61135201,"owner_login":"paxtonproctor","updated_at":"2022-04-28T14:13:02.617Z","has_issues":true}},"sponsorable":false,"topics":["vhdl","verilog","logic-gates","microprocessors"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":64,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Apaxtonproctor%252F3023_Logic_Design%2B%2Blanguage%253AVHDL","metadata":null,"csrf_tokens":{"/paxtonproctor/3023_Logic_Design/star":{"post":"t3ErH_wssU0QGTHLLyp_ZFajNvrWLhTaR9VRiVJWftoZO4UMB1I9rWsp5fmvSNXpY06OAttbpjzFfu1Eydh2wQ"},"/paxtonproctor/3023_Logic_Design/unstar":{"post":"nPaCLwo7RAJ4i7gSGHu2jXceewB1McWuA90dXHQ0B0tdozFdXMIV2rZ7gHUmZdWTK3-OW0ADIyFjXE7yR68KoA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"crrhCq_FPrdUmpMZiTJeLehmLaXhBwASGfwK9a4EWqHXeo6ZLwAKTBdNv_eKTWQSzhPsrchWthei4eAYF7F_Hg"}}},"title":"Repository search results"}