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MFC r256935

MFP4:
Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30

	Add kernel side support for large TLB on BERI/CHERI.
	Modelled similar to NLM

Sponsored by:	DAPRA/AFRL
Approved by:	re (delphij)
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commit 45a606d1102ff82798f3f84d55b9a225a951edff 1 parent 9f85db3
@brooksdavis brooksdavis authored
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5 sys/conf/options.mips
@@ -81,6 +81,11 @@ OCTEON_VENDOR_GEFES opt_cvmx.h
OCTEON_BOARD_CAPK_0100ND opt_cvmx.h
#
+# Options specific to the BERI platform.
+#
+BERI_LARGE_TLB opt_global.h
+
+#
# Options that control the Atheros SoC peripherals
#
ARGE_DEBUG opt_arge.h
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2  sys/mips/beri/std.beri
@@ -2,3 +2,5 @@
files "../beri/files.beri"
cpu CPU_MIPS4KC
+
+options BERI_LARGE_TLB
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7 sys/mips/include/cpufunc.h
@@ -242,8 +242,13 @@ MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
#ifdef CPU_CNMIPS
MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
#endif
-#ifdef CPU_NLM
+#ifdef BERI_LARGE_TLB
+MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
+#endif
+#if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
+#endif
+#ifdef CPU_NLM
MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
#endif
MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
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26 sys/mips/mips/cpu.c
@@ -99,17 +99,29 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo)
/* Learn TLB size and L1 cache geometry. */
cfg1 = mips_rd_config1();
-#ifndef CPU_NLM
- cpuinfo->tlb_nentries =
- ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
-#else
+
+#if defined(CPU_NLM)
/* Account for Extended TLB entries in XLP */
tmp = mips_rd_config6();
cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1;
+#elif defined(BERI_LARGE_TLB)
+ /* Check if we support extended TLB entries and if so activate. */
+ tmp = mips_rd_config5();
+#define BERI_CP5_LTLB_SUPPORTED 0x1
+ if (tmp & BERI_CP5_LTLB_SUPPORTED) {
+ /* See how many extra TLB entries we have. */
+ tmp = mips_rd_config6();
+ cpuinfo->tlb_nentries = (tmp >> 16) + 1;
+ /* Activate the extended entries. */
+ mips_wr_config6(tmp|0x4);
+ } else
+#endif
+#if !defined(CPU_NLM)
+ cpuinfo->tlb_nentries =
+ ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
#endif
-
- /* Add extended TLB size information from config4. */
#if defined(CPU_CNMIPS)
+ /* Add extended TLB size information from config4. */
cfg4 = mips_rd_config4();
if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT)
cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40;
@@ -124,8 +136,8 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo)
1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6);
}
-#ifndef CPU_CNMIPS
/* L1 data cache. */
+#ifndef CPU_CNMIPS
tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT;
if (tmp != 0) {
cpuinfo->l1.dc_linesize = 1 << (tmp + 1);
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