1. Enable dptf feature and remove fan control part from overridetree.cb
2. Update tcc offset to 5
3. Follow thermal validation and update PL2 max_power to 51

BUG=b:167931578, b:170357248

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

The LCM ID is not really used on Jacuzzi followers and the reference
design expects ADC to return 0. However, there were hardware design
issues so the returned value became unexpected numbers.

 - Juniper and Kappa returns 1.
 - Burnet and Esche returns 1 on normal boot, and 0 on recovery boot.
 - Cerise and Stern usually returns 0, and sometimes 1.

To fix that, we are changing LCM ID to fixed value for Jacuzzi followers.

BUG=b:170916885,b:171365301
BRANCH=kukui
TEST=1. emerge-jacuzzi coreboot
     2. check burnet/esche skuid correctly

Change-Id: I3b43b9153315ec65e9168c4e84ea844dff14d446
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

Integer handling issues:
Potentially overflowing expression "1 << size_msb" with type "int"
(32 bits, signed) is evaluated using 32-bit arithmetic, and then
used in a context that expects an expression of type "uint64_t"
(64 bits, unsigned).

Fixes: CID 1435825 and 1435826

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46711
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Configure the I2C bus high and low time for all enabled I2C buses.

BUG=b:168783630
TEST=Measured the I2C bus frequency reduce to 387 KHz.

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46613
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

util/broadcom/secimage was removed in commit aea00f4, so don't
try to test it anymore.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibcc018a6b8ed4ecd407f2dc374cec62900920a92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Tested with BUILD_TIMELESS=1, all variants remain identical.

Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

- cscope: Run cscope targets
- ctags: Run ctags targets
- pbzip2: Allow compression on all cpu cores

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I31ca45fcc5880f2b0346ca3f7d36a71ae18da979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Even though both python2 and python3 are now installed to the SDK, the
default python program is not.  This sets the default to python2.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4220c316df86cb2481143a79fadb70fc734e6879
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Because docker saves a container for every run command, by breaking
the coreboot build into 3 commands, it greatly increased the size of
the docker containers needed.  When combined as one run command, the
coreboot repo that is downloaded, along with the coreboot test build
are deleted before the container is created.  Since those directories
are deleted in a later run command, they don't even make it into the
final container, and just force coreboot-sdk users to download extra
data for no reason.

While splitting the build may help with debugging failures when
creating the docker container, that debugging can be done locally by
splitting up a working copy.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia28ee4e22c0a76dc45343755c45678795308adca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

This tests some of the basic targets that coreboot-sdk needs to be
able to run.

I was running most of these tests manually after creating the sdk
image, but adding it into the Dockerfile makes sure they get run.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d4a2ad82042733a7966edb8ccf927676618977c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Jenkins has changed the name of the build directory, so it's not
currently building out of memory, it's writing to the SSD. This
changes the build back to tmpfs.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iefcf53757862feb2025aa5696f9f5dbce9dd70dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

- The ccache files don't need atime.
- Enable strict atime for the git repos.  This will help find unused
files.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I94bcc55ea5c5a74f3ad0292ca50b74874a0d920d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

This matches the what-jenkins-does target.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I20b455e0161dcebf2eb9022bd142bbec99937a19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

The linters touch every file under src and probably util.  This makes
it difficult to see what files have been accessed by the builder.

The JENKINS_SKIP_LINT_TESTS variable will only be set on the jenkins
build that looks for unused files.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I12fa31641c2a72c5e07be1c4958467f7165f21bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I902915133035fb2adff7edd9c931d4b1d3e7dc40
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

invoke LTE power off function to meet LTE power sequence while DUT is
in reboot state.

BUG=b:167565015
BRANCH=octopus
TEST=build and verify on the DUT with LTE

Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46022
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46701
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This CL fixes the policy digest that restricts deleting the nvmem spaces
to specific PCR0 states.

BRANCH=none
BUG=b:140958855
TEST=verified that nvmem spaces created with this digest can be deleted
     in the intended states, and cannot be deleted in other states
     (test details for ChromeOS - in BUG comments).

Change-Id: I3cb7d644fdebda71cec3ae36de1dc76387e61ea7
Signed-off-by: Andrey Pronin <apronin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46772
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The pins for SD and MMC must be configured properly
so we can access them in payloads.

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: Ie6bdffb987d5acf286645550f1c53f294f71c38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I2ae7684a61af76693605cc0bcf8d20c8992c7bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46388
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Rename motherboard_fill_fadt() to the common override
mainboard_fill_fadt() function to override FADT.

Tested=On OCP Delta Lake, verify FADT PM Profile is set to
Enterprise Server.

Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: Ie9ea7cc6e712d0aca57bbeac1a4154921d123be4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button
is present on Cooperlake platform.

Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

TEST=Execute "dmidecode -t 7" to check if cache error correction type
and cache sram type is correct for each cache level

Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

The corresponding devices and objects are already included in the
System Bus ACPI scope inside uncore.asl. There is no need to do this
again in the DSDT of the motherboard.

Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Add internal pull-down for GPP_D19 to improve DMIC noise issue on
nightfury.

BUG=b:171669255
BRANCH=firmware-hatch-12672.B
TEST=Built and checked GPP_D19 voltage after booting

Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

`mrc_cache_needs_update` is comparing the "new size" of the MRC data
(minus metadata size) to the size including the metadata, which causes
the driver to think the data has changed, and so it will rewrite the
MRC cache on every boot. This patch removes the metadata size from
the comparison.

BUG=b:171513942
BRANCH=volteer
TEST=1) Memory training data gets written the on a boot where the data
was wiped out.
2) Memory training data does not get written back on every subsequent
boot.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7280276f71fdaa492c327b2b7ade8e53e7c59f51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

The Kconfig variables are used in the C code for cbfs file names but
not in the Makefiles adding them.

Change-Id: Ie35508d54ae91292f06de9827f0fb543ad81734d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

This is consistent with how other binaries (e.g. FSP) are added via
Kconfig. This also makes it more visible that things need to be
configured.

Change-Id: I399de6270cc4c0ab3b8c8a9543aec0d68d3cfc03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Define device _WAK, _PTS, and _INI acpi methods with callbacks into
mainboard methods if provided.

BUG=b:158087989
BRANCH=Zork
TEST=tested backlight during reboot and suspend

Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I8020173a15db1d310459d5c1de3600949b173b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46669
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Include platform.asl to link acpi methods for _INI, _WAK, and _PTS to
correctly enable backlight in OS for zork.

BUG=b:158087989
BRANCH=Zork
TEST=check backlight during reboot and suspend

Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I702f807a5907d85d083295cf339ba9d31b246627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

Generate acpi methods which enable and disable backlight during _INI,
_WAK, and _PTS.

BUG=b:158087989
BRANCH=Zork
TEST=check backlight during reboot and suspend

Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I2f3434dc92de1f697693ff69ca15bd76647b89a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46671
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Remove code to turn on backlight during ACPI mode because backlight has
been properly enabled in ACPI.

BUG=b:158087989
BRANCH=Zork
TEST=tested backlight during reboot and suspend

Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I3bf06042aa19e4559127d611d401f0ba0516b3a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

This will let you at least dump / add these regions.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I195ba5e93823603e712cd16cecbb48141302bed6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

Change-Id: I6a16e2f829219f2eba8acd3ae7f371238c0d8de1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

The code for enabling ACPI timer emulation is the same for the SoCs
SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to
common code.

APL differs in not having the delay settings. However, the bits are
marked as "spare" and BWG mentions there are no "reserved bit checks
done". Thus, we can write them unconditionally without any effect.

Note: The ACPI timer emulation can only be used by SoCs with microcode
supporting CTC (Common Timer Copy) / ACPI timer emulation.

Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Also rename the prompt to "tested" to make it more obvious that there
is no really stable version.

Change-Id: Ib719fe5c30783a53ddad2a2dc2d9ecda37a05ac2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>

It is enabled by the vendor firmware.

Also drop spurious `io 0x60 = 0x00` setting. It's the default anyway
and the resource is kept disabled (it's controlled by the virtual
LDN 2e.008).

This fixes the hang in `PCI: 00:14.3 init` when doing
`outb(0, DMA1_RESET_REG)`.

Fixes: 2f8192b ("asus/f2a85m_pro: Fix superio type in devicetree")
Change-Id: I351c93033bf2afd824eb6baa8d7625e7a33a295a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Change-Id: I8f5a87d006f8bf20af40f7a4f09b1e4b597ba79f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46019
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Drop useless writes to read-only registers and don't re-write
default 0x00 values. In detail:

* Don't write read-only status registers.
* Don't try to write input bits in data registers
  (iow. mask data values: `data &= ~io`).
* Don't write data registers if all GPIOs are set as
  inputs (`io == 0xff`).
* Don't write default 0x00 for inversion and multiplex
  registers.

Note: Both GPIO0 and WDT1 values look spurious. Maybe they
were dumped with the virtual devices disabled?

Change-Id: I7d948d6b697285e61e4352b7354b924dbf511e9a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46020
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The LDNs don't have a 0x30 register to enable them. However,
with the devices set to `off`, coreboot won't configure them.

Change-Id: Iaea37c88524904a1dae8a6d3b5f07c6ea25bc3b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46021
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

If no correct params were found in flash, do dram full calibration.
Full calibration will load blob, dram.elf.
  Blob version: v3, size: 320KB.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

List of changes:
1. Split mem_cfg for DDR4 and LPDDR4 as per board_id
2. Move dq_pins_interleaved into board-specific memory configuration
information

TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs.

Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add general debug macros that print resource information.
These are available to select if DEFAULT_CONSOLE_LOGLEVEL_8.
The macros are helpful in debugging complex resource allocation
with multiple buses. The macros are moved from soc/intel/xeon_sp,
where they were originally developed.

Change-Id: I2bdab7770ca5ee5901f17a8af3a9a1001b6702e4
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Move the macros for printing debug information to debug.h in the
common console include directory and device include file.
These are available if the platform selects DEFAULT_CONSOLE_LOGLEVEL_8.

The macros could be used by any platform.

Change-Id: Ie237bdf8cdc42c76f38a0c820fdc92e81095f47c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Create the ambassador variant of the puff reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

BUG=b:171561514
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_AMBASSADOR

Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org>
Change-Id: Ib0e3a813a120a4a8e984f3a89dc3ba100d94da95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

BUG=b:170604353
BRANCH=volteer
TEST=emerge-volteer coreboot, and boot into kernel.

Change-Id: If354aa158f3ad60193268f38278a44f9c99bf3db
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46770
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Tested with BUILD_TIMELESS=1, all variants remain identical.

Change-Id: I0fa486b8a0fc8be974f37d0bb4eb77a254e8cd86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46703
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Tested with BUILD_TIMELESS=1, coreboot.rom remains identical.

Change-Id: I75d6594f9576c96a585526c652a070cb9616dbe9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46704
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Tested with BUILD_TIMELESS=1, all variants remain identical.

Change-Id: I0fe6de35f7471ce173df40db1444153623544f00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

`chip` entries are only hooked up via device nodes to the tree. A `chip`
without a `device` below it does nothing. To allow variants to override
SATA tuning parameters, ensure a device exists under the PCH chip scope.

Without this change, some variants would not properly override the SATA
tuning parameters after extracting the PCH parts into a different chip.

TEST=Sanity-check static.c and verify overridetrees override properly.

Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46769
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>