Commits on Oct 5, 2021

  1. Documentation: Fix spelling errors

    These issues were found and fixed by codespell, a useful tool for
    finding spelling errors.
    
    Signed-off-by: Martin Roth <martin@coreboot.org>
    Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Martin Roth authored and Martin Roth committed Oct 5, 2021
    Copy the full SHA
    6c3ece9 View commit details
    Browse the repository at this point in the history
  2. src/acpi to src/lib: Fix spelling errors

    These issues were found and fixed by codespell, a useful tool for
    finding spelling errors.
    
    Signed-off-by: Martin Roth <martin@coreboot.org>
    Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Martin Roth authored and Martin Roth committed Oct 5, 2021
    Copy the full SHA
    0949e73 View commit details
    Browse the repository at this point in the history
  3. src/mainboard to src/security: Fix spelling errors

    These issues were found and fixed by codespell, a useful tool for
    finding spelling errors.
    
    Signed-off-by: Martin Roth <martin@coreboot.org>
    Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    Martin Roth authored and Martin Roth committed Oct 5, 2021
    Copy the full SHA
    50863da View commit details
    Browse the repository at this point in the history
  4. src/soc to src/superio: Fix spelling errors

    These issues were found and fixed by codespell, a useful tool for
    finding spelling errors.
    
    Signed-off-by: Martin Roth <martin@coreboot.org>
    Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Martin Roth authored and Martin Roth committed Oct 5, 2021
    Copy the full SHA
    26f97f9 View commit details
    Browse the repository at this point in the history
  5. drivers/intel/fsp2_0: don't force-use python2

    Some distributions (e.g. NixOS, Debian) are actively working on getting
    rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and
    Python 3 as of upstream commit 0bc2b07, use whatever version is present
    by utilizing `python`.
    
    Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d
    Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    Reviewed-by:  Felix Singer <felixsinger@posteo.net>
    c0d3z3r0 authored and felixsinger committed Oct 5, 2021
    Copy the full SHA
    9990866 View commit details
    Browse the repository at this point in the history
  6. arch/x86,cpu/x86: Introduce new method for accessing cpu_info

    There is currently a fundamental flaw in the current cpu_info()
    implementation. It assumes that current stack is CONFIG_STACK_SIZE
    aligned. This assumption breaks down when performing SMM relocation.
    
    The first step in performing SMM relocation is changing the SMBASE. This
    is accomplished by installing the smmstub at 0x00038000, which is the
    default SMM entry point. The stub is configured to set up a new stack
    with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point
    of smm_do_relocation located in RAMSTAGE RAM.
    
    This means that when smm_do_relocation is executed, it is running in SMM
    with a different sized stack. When cpu_info() gets called it will be
    using CONFIG_STACK_SIZE to calculate the location of the cpu_info
    struct. This results in reading random memory. Since cpu_info() has to
    run in multiple environments, we can't use a compile time constant to
    locate the cpu_info struct.
    
    This CL introduces a new way of locating cpu_info. It uses a per-cpu
    segment descriptor that points to a per-cpu segment that is allocated on
    the stack. By using a segment descriptor to point to the per-cpu data,
    we no longer need to calculate the location of the cpu_info struct. This
    has the following advantages:
    * Stacks no longer need to be CONFIG_STACK_SIZE aligned.
    * Accessing an unconfigured segment will result in an exception. This
      ensures no one can call cpu_info() from an unsupported environment.
    * Segment selectors are cleared when entering SMM and restored when
      leaving SMM.
    * There is a 1:1 mapping between cpu and cpu_info. When using
      COOP_MULTITASKING, a new cpu_info is currently allocated at the top of
      each thread's stack. This no longer needs to happen.
    
    This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so
    reviewers can feel more comfortable knowing most of the CL is a no-op. I
    would eventually like to remove most of the guards though.
    
    This CL does not touch the LEGACY_SMP_INIT code path. I don't have any
    way of testing it.
    
    The %gs segment was chosen over the %fs segment because it's what the
    linux kernel uses for per-cpu data in x86_64 mode.
    
    BUG=b:194391185, b:179699789
    TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct
    %gs segment. Verify cpu_info looks sane. Verify booting to the OS
    works correctly with COOP_MULTITASKING enabled.
    
    Signed-off-by: Raul E Rangel <rrangel@chromium.org>
    Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Eric Peers <epeers@google.com>
    Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
    Raul E Rangel committed Oct 5, 2021
    Copy the full SHA
    b2346a5 View commit details
    Browse the repository at this point in the history
  7. lib/thread: Switch to using CPU_INFO_V2

    CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1
    cpu_info struct per cpu. This means that we no longer need to allocate
    it at the top of each threads stack.
    
    We can now in theory remove the CONFIG_STACK_SIZE alignment on the
    thread stack sizes. We can also in theory use threads in SMM if you are
    feeling venturesome.
    
    BUG=b:194391185, b:179699789
    TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING
    enabled.
    
    Signed-off-by: Raul E Rangel <rrangel@chromium.org>
    Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Eric Peers <epeers@google.com>
    Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
    Raul E Rangel committed Oct 5, 2021
    Copy the full SHA
    c842c59 View commit details
    Browse the repository at this point in the history
  8. Revert "soc/amd/cezanne: Disable Co-op multitasking"

    This reverts commit 5f80e7c.
    
    The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2
    into this patch to satisfy the dependency.
    
    BUG=b:194391185, b:179699789
    TEST=reboot stress test guybrush for 50 iterations.
    
    Signed-off-by: Raul E Rangel <rrangel@chromium.org>
    Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Eric Peers <epeers@google.com>
    Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
    Raul E Rangel committed Oct 5, 2021
    Copy the full SHA
    968f140 View commit details
    Browse the repository at this point in the history
  9. lib/thread: Remove thread stack alignment requirement

    CPU_INFO_V2 now encapsulates the cpu_info requirements. They no longer
    need to leak through to thread.c. This allows us to remove the alignment
    requirement.
    
    BUG=b:179699789
    TEST=Reboot stress test guybrush 50 times.
    
    Signed-off-by: Raul E Rangel <rrangel@chromium.org>
    Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57928
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Eric Peers <epeers@google.com>
    Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
    Raul E Rangel committed Oct 5, 2021
    Copy the full SHA
    db16ac9 View commit details
    Browse the repository at this point in the history

Commits on Oct 6, 2021

  1. soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices

    This patch ensures to pass cse device function number as argument for
    `set_cse_device_state()` to allow coreboot to perform enable/disable of
    D0i3 bit for all CSE devices to put the CSE device to Idle state or
    Active state.
    
    BUG=b:200644229
    TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is
    able to put the CSE device toidle state or active state based on `devfn`
    as argument.
    
    Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5
    Signed-off-by: Subrata Banik <subrata.banik@intel.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58039
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    subrata-b committed Oct 6, 2021
    Copy the full SHA
    c6e2552 View commit details
    Browse the repository at this point in the history
  2. soc/intel/common: Helper function to check CSE device devfn status

    This patch creates a helper function in cse common code block to check
    the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and
    CSE_4.
    
    Currently cse common code is only able to read the device state of
    `PCH_DEVFN_CSE` CSE device alone.
    
    Additionally, print `slot` and 'func' number of CSE devices in case
    the device is either disable or hidden.
    
    BUG=b:200644229
    TEST=Able to build and boot ADLRVP-P with this patch where the serial
    message listed the CSE devices that are disabled in the device tree
    as below:
    
    HECI: CSE device 16.01 is disabled
    HECI: CSE device 16.04 is disabled
    HECI: CSE device 16.05 is disabled
    
    Signed-off-by: Subrata Banik <subrata.banik@intel.com>
    Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    subrata-b committed Oct 6, 2021
    Copy the full SHA
    3710e99 View commit details
    Browse the repository at this point in the history
  3. soc/intel/alderlake: Perform heci_finalize prior to booting to OS

    `heci_finalize` ensures to put all heci devices to D3 by setting the
    D0i3 bit prior to booting to the OS.
    
    BUG=b:200644229
    TEST=Verified D0i3 bit is set for all HECI devices prior to booting
    to OS.
    
    Signed-off-by: Subrata Banik <subrata.banik@intel.com>
    Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58040
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    subrata-b committed Oct 6, 2021
    Copy the full SHA
    78e66ad View commit details
    Browse the repository at this point in the history
  4. soc/intel/alderlake: Skip setting D0I3 bit for HECI devices

    This patch skips setting D0I3 bit for all HECI devices by FSP.
    
    BUG=b:200644229
    TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is
    set to `1`.
    
    Change-Id: I86d61c49b8f187611efd495712ad901184665f31
    Signed-off-by: Subrata Banik <subrata.banik@intel.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    subrata-b committed Oct 6, 2021
    Copy the full SHA
    d6da4ef View commit details
    Browse the repository at this point in the history
  5. include/device: Generic interface for USB-C mux operations

    Create a generic interface to allow any of the EC or other drivers
    to provide set of USB-C mux operations.
    
    Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
    Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58002
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Derek Huang authored and Tim Wawrzynczak committed Oct 6, 2021
    Copy the full SHA
    89d8260 View commit details
    Browse the repository at this point in the history
  6. ec/google/chromeec: Update google_chromeec_usb_pd_control()

    Add parameter `active_cable` to obtain the cable type
    (active or passive) which is needed for USB-C configuration for
    some SoCs (at least Intel TGL and ADL), change the function name to
    google_chromeec_usb_pd_get_info() for better understanding.
    
    BUG=b:192947843
    
    Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
    Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58057
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Derek Huang authored and Tim Wawrzynczak committed Oct 6, 2021
    Copy the full SHA
    f1f9b3d View commit details
    Browse the repository at this point in the history
  7. ec/google/chromeec: Update some PD and DisplayPort APIs

    1. Update google_chromeec_pd_get_amode() to return bitmask.
    2. Update google_chromeec_wait_for_displayport() to handle the
       updated return value of google_chromeec_pd_get_amode().
    3. Drop google_chromeec_pd_get_amode() from ec.h and make it static
       because it's not used outside of ec.c.
    
    BUG=b:192947843
    
    Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
    Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58058
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Derek Huang authored and Tim Wawrzynczak committed Oct 6, 2021
    Copy the full SHA
    c0f005a View commit details
    Browse the repository at this point in the history
  8. ec/google/chromeec: Add APIs for USB-C DP ALT mode

    Add API to allow AP to send the command to EC to enter DP ALT mode
    and API to wait for DP HPD event.
    
    BUG=b:192947843
    TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build
    coreboot and update your system. Boot the system you will find below
    message in the coreboot log with or without USB-C display connected:
    'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'.
    
    Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
    Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Derek Huang authored and Tim Wawrzynczak committed Oct 6, 2021
    Copy the full SHA
    c0bd123 View commit details
    Browse the repository at this point in the history
  9. ec/google/chromeec: Add new API for USB-C mux handling

    Add google_chromeec_get_usbc_mux_info() to obtain USB-C mux
    related information.
    
    BUG=b:192947843
    
    Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
    Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58059
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Derek Huang authored and Tim Wawrzynczak committed Oct 6, 2021
    Copy the full SHA
    63ffc1a View commit details
    Browse the repository at this point in the history
  10. ec/google/chromeec: Update google_chromeec_usb_pd_get_info()

    google_chromeec_usb_pd_get_info() is used in ec.c only. Make it
    static and drop from ec.h.
    
    BUG=b:192947843
    
    Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
    Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58060
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Derek Huang authored and Tim Wawrzynczak committed Oct 6, 2021
    Copy the full SHA
    796ea82 View commit details
    Browse the repository at this point in the history
  11. ec/google/chromeec: Register USB-C mux operations

    Register USB-C mux operations to the generic interface.
    
    BUG=b:192947843
    
    Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
    Change-Id: I576c9e4c6c82d6b4055b0a0a9a75c677d4b05220
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58061
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Derek Huang authored and Tim Wawrzynczak committed Oct 6, 2021
    Copy the full SHA
    1a36876 View commit details
    Browse the repository at this point in the history
  12. sc7280: Enable bootblock compression

    This patch enables bootblock compression on SC7280. In my tests, that
    makes it boot roughly 10ms faster (which isn't much, but... might as
    well take it).
    
    Ref link: https://review.coreboot.org/c/coreboot/+/45855
    
    BUG=b:182963902
    TEST=Validated on qualcomm sc7180 and sc7280 development board.
    
    Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0
    Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Shelley Chen <shchen@google.com>
    Ravi Kumar Bokka authored and Shelley Chen committed Oct 6, 2021
    Copy the full SHA
    86b0609 View commit details
    Browse the repository at this point in the history
  13. libpayload: Enable UART driver for sc7280

    Add Qualcomm's QUPV3 serial driver for herobrine board
    
    BUG=b:182963902
    TEST=Validated on qualcomm sc7280 development board.
    
    Change-Id: I3a745afd7bbabdd29f1f369612c990526e5a2335
    Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/47527
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Shelley Chen <shchen@google.com>
    Roja Rani Yarubandi authored and Shelley Chen committed Oct 6, 2021
    Copy the full SHA
    acd2218 View commit details
    Browse the repository at this point in the history
  14. sc7280: Enable UART driver

    Enable common Uart driver on sc7280
    
    BUG=b:182963902
    TEST=Validated on qualcomm sc7280 development board
    
    Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
    Change-Id: I015e21081391bfe85edf667685bf117401a9ec00
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Reviewed-by: Shelley Chen <shchen@google.com>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Rajesh Patil authored and Shelley Chen committed Oct 6, 2021
    Copy the full SHA
    c003ea6 View commit details
    Browse the repository at this point in the history

Commits on Oct 7, 2021

  1. soc/intel/denverton_ns: Always enable SpeedStep

    When "SpeedStep" is disabled on an Intel Atom C3538,
    the maximum CPU clock speed is always 800 MHz(min CPU clock).
    Оperating system cannot change the frequency.
    Avoid this issue allow "Intel Speed step" technology
    for processors that do not have "Intel Turbo Boost".
    
    Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com>
    Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57669
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    Reviewed-by: King Sumo <kingsumos@gmail.com>
    dponamorev1976 authored and wzeh committed Oct 7, 2021
    Copy the full SHA
    fba1475 View commit details
    Browse the repository at this point in the history
  2. soc/intel/dnv_ns: correct size of GPE0 registers in FADT

    There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC
    code sets a GPE0 block size of 4 byte length instead of 32 byte.
    The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit
    instead of 256 bit).
    
    Drop the overrides and let common ACPI code set the correct values based
    on `GPE0_REG_MAX`.
    
    Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633
    Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    c0d3z3r0 authored and wzeh committed Oct 7, 2021
    Copy the full SHA
    a78ab4b View commit details
    Browse the repository at this point in the history
  3. security/vboot: Remove vb2ex_hwcrypto stubs

    Now that the vb2ex_hwcrypto_* stub functions are included in vboot fwlib
    (CL:2353775), we can remove the same stubs from coreboot.
    
    BUG=none
    TEST=emerge-brya coreboot
    TEST=emerge-cherry coreboot
    BRANCH=none
    
    Change-Id: I62bdc647eb3e34c581cc1b8d15e7f271211e6156
    Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58095
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
    Yu-Ping Wu authored and wzeh committed Oct 7, 2021
    Copy the full SHA
    2a634ab View commit details
    Browse the repository at this point in the history
  4. soc/intel/cannonlake: Enable x86_64 support

    Select HAVE_EXP_X86_64_SUPPORT.
    
    Tested on prodrive/hermes: Boots into Linux.
    
    Change-Id: I033ccd5dc793b637a2ac4271b450335464564885
    Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58089
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
    Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
    PatrickRudolph authored and wzeh committed Oct 7, 2021
    Copy the full SHA
    4dc9e5b View commit details
    Browse the repository at this point in the history
  5. sc7280: Add SHRM firmware support

    SHRM is a system hardware resource manager. It is used to manage run time
    DDRSS activities. DDRSS stands for DDR subsystem.
    
    BUG=b:182963902
    TEST=Validated on qualcomm sc7280 development board
    by trying DDR clocks which through SHRM RSI command.
    
    Change-Id: I44484573a829eaefbd34907c6fe78d427506a762
    Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Shelley Chen <shchen@google.com>
    Ravi Kumar Bokka authored and Shelley Chen committed Oct 7, 2021
    Copy the full SHA
    5afeba3 View commit details
    Browse the repository at this point in the history
  6. soc/intel/tigerlake: Hook up GMA ACPI brightness controls

    Add function needed to generate ACPI backlight control SSDT, along with
    Kconfig values for accessing the registers.
    
    Tested by adding gfx register on system76/gaze16 and booting Windows.
    Display settings has a brightness setting, and can change the brightness
    level.
    
    Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373
    Signed-off-by: Tim Crawford <tcrawford@system76.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57823
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    crawfxrd authored and i-c-o-n committed Oct 7, 2021
    Copy the full SHA
    1724b57 View commit details
    Browse the repository at this point in the history
  7. libpayload: cbgfx: Clear screen by memcpy

    Instead of setting each pixel in the framebuffer, use memcpy() to clear
    screen faster. As this method should be fast enough, remove the fast
    path using memset().
    
    The speed of clear_screen() on brya (x_resolution = 1920,
    bytes_per_line = 7680):
    
    - Using memset(): 15ms
    - Setting each pixel: 25ms
    - Using memcpy(): 14ms
    
    Also remove set_pixel_raw() since it's now used in only one place.
    
    BUG=none
    TEST=emerge-brya libpayload
    TEST=Saw developer screen on brya
    BRANCH=none
    
    Change-Id: I5f08fb50faab48d3db6b61ae022af3226914f72b
    Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58128
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Yu-Ping Wu authored and hungte committed Oct 7, 2021
    Copy the full SHA
    e5824ff View commit details
    Browse the repository at this point in the history
  8. mb/google/brya: Add PsysPmax setting to 145W

    This patch adds the setting of PsysPmax to 145W according to
    the brya board design.
    
    BUG=b:195615830
    TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
    passed to FSP by enabling FSP log & Boot into the OS
    
    Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd
    Signed-off-by: Ryan Lin <ryan.lin@intel.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    ryanlin0317 authored and Tim Wawrzynczak committed Oct 7, 2021
    Copy the full SHA
    a45377e View commit details
    Browse the repository at this point in the history
  9. mb/google/dedede/var/bugzzy: Update GPP_D5 configuration

    As we checked the panel doesn't display firmware screen if we hold
    GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy
    uses the built-in touch screen on the panel, the panel seems like
    under reset state by the TOUCHSCREEN_RESET signal.
    This change sets default GPP_D5 level to high for bugzzy.
    
    BUG=b:None
    BRANCH=dedede
    TEST=built and verified bugzzy showed firmware screen
    
    Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
    Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Edward Doan <edoan@google.com>
    Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
    Seunghwan Kim authored and karthikr-google committed Oct 7, 2021
    Copy the full SHA
    bd4487c View commit details
    Browse the repository at this point in the history
  10. mb/google/brya: Disable unused i2s pins for BT offload

    BT offload hardware design is using only i2s0 pins. Need to disable
    i2s2 pins which are not used. As per the hardware spec there is an OR
    operation between vgpio and physical gpio pins related to i2s2. During
    BT offload configuring the i2s2 pins to its native function is causing
    offload issue on proto 2 boards.
    
    BUG=b:201736222
    TEST=Verified BT offload on brya on proto 1 and proto 2.
    
    Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d
    Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
    sugnanprabhu authored and Tim Wawrzynczak committed Oct 7, 2021
    Copy the full SHA
    1de9086 View commit details
    Browse the repository at this point in the history

Commits on Oct 8, 2021

  1. payloads: Allow selecting UefiPayload on ARM64 platforms

    Some ARM64 platforms (e.g., MT8195) are now able to compile
    and run EDK2 (UefiPayload). As a result, we should allow selecting
    PAYLOAD_TIANOCORE for ARM64 platforms.
    
    TEST=show strings correctly.
    1. make menuconfig
    2. select Mainboard -> Vendor=Google, model=Cherry
    3. select Payload -> Add a payload -> Tianocorepayload
    4. make -j
    5. build/cbfstool  build/coreboot.rom extract
       --name fallback/payload --file out.elf -m arm64
    6. file out.elf # ELF 64-bit LSB executable, ARM aarch64
    7. strings out.elf | grep tianocore # lots of tianocore stuff
    
    Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
    Change-Id: I10777a341d46240b91ceeeb1be26c33a0c5db839
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58054
    Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
    Reviewed-by: Yu-Ping Wu <yupingso@google.com>
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Rex-BC Chen authored and hungte committed Oct 8, 2021
    Copy the full SHA
    dc9abea View commit details
    Browse the repository at this point in the history
  2. vc/mediatek/mt8195: fix misleading-indentation error

    Fix misleading-indentation error in dramc_pi_calibration_api.c.
    
    Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
    Change-Id: I680e9e6fffaebb23bf1f156a7f614345e952ed95
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58136
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
    Reviewed-by: Yu-Ping Wu <yupingso@google.com>
    Rex-BC Chen authored and hungte committed Oct 8, 2021
    Copy the full SHA
    1259da1 View commit details
    Browse the repository at this point in the history
  3. mb/prodrive/hermes: Enable SATA power optimizer

    Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD
    is still detected correctly by SeaBIOS (version 1.14.1).
    
    Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b
    Signed-off-by: Angel Pons <th3fanbus@gmail.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
    Th3Fanbus authored and wzeh committed Oct 8, 2021
    Copy the full SHA
    f6a54d2 View commit details
    Browse the repository at this point in the history
  4. mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-M RVP

    This patch enables eNEM flow for ADL-M
    
    TEST=Able to build and boot ADL-M RVP using eNEM mode.
    
    Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
    Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
    Reviewed-by: Subrata Banik <subrata.banik@intel.com>
    bguvendi authored and wzeh committed Oct 8, 2021
    Copy the full SHA
    953a876 View commit details
    Browse the repository at this point in the history
  5. acpi: add macros for MSR and unsupported register resource types

    These will be used in the follow-up change.
    
    Change-Id: I4723ffaf0adff8cb5b1717600ed4d1634768e2b7
    Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57887
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    c0d3z3r0 authored and wzeh committed Oct 8, 2021
    Copy the full SHA
    ab088c9 View commit details
    Browse the repository at this point in the history
  6. Documentation: Explain how to join Slack

    Change-Id: I6a4d5011ea47576c9a459f20e0b368cff8a326c2
    Signed-off-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58150
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
    pgeorgi committed Oct 8, 2021
    Copy the full SHA
    3394f4a View commit details
    Browse the repository at this point in the history
  7. mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables

    Before attempting another commit 6260bf7 ("vboot_logic: Set
    VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants
    all program EC_IN_RW as an input GPIO in bootblock so that it can be read
    from in verstage.
    
    Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0
    Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
    Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
    Tim Wawrzynczak committed Oct 8, 2021
    Copy the full SHA
    36721a4 View commit details
    Browse the repository at this point in the history

Commits on Oct 9, 2021

  1. soc/intel/dnv_ns: add the Kconfig value for CPU_XTAL_HZ

    Reference: Intel doc#558579 rev2.2
    
    Change-Id: Iab5dca6eb42abc00bc7da33f640350e994f0bd02
    Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57945
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    c0d3z3r0 committed Oct 9, 2021
    Copy the full SHA
    ef353e0 View commit details
    Browse the repository at this point in the history
  2. mb/system76: tgl-u: Add gfx register for GMA ACPI

    Add gfx register to System76 TGL-U boards so GMA ACPI data is generated.
    
    Change-Id: If944a90921b518efdcd5f0e0998bddb4f56e5764
    Signed-off-by: Tim Crawford <tcrawford@system76.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57835
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    crawfxrd authored and i-c-o-n committed Oct 9, 2021
    Copy the full SHA
    ca1851d View commit details
    Browse the repository at this point in the history
  3. payloads/tianocore/Kconfig: Extend help for bootsplash file

    Add more detail as to why a smaller-than-screen-size image is to be
    preferred, in contrast to other payloads' bootsplash images.
    
    Signed-off-by: Felix Friedlander <felix@ffetc.net>
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Change-Id: Ib4c6666bb0e49369fe8fe2ae3dc12c023f668da0
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/49233
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Angel Pons <th3fanbus@gmail.com>
    felixphew authored and Martin Roth committed Oct 9, 2021
    Copy the full SHA
    45ce841 View commit details
    Browse the repository at this point in the history

Commits on Oct 11, 2021

  1. soc/intel/dnv_ns: drop redundancies from soc_fill_fadt

    Drop overrides from `soc_fill_fadt` that do not differ from what common
    ACPI code already sets.
    
    Change-Id: I7a5f43f844b12ff0e9bc5c7426170383209c8e0a
    Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58087
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    c0d3z3r0 committed Oct 11, 2021
    Copy the full SHA
    607a266 View commit details
    Browse the repository at this point in the history
  2. mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe

    nipperkin has different H/W topology to guybrush that the eMMC device
    is on a different GPP:
    guybrush: GPP3
    nipperkin: GPP2
    
    Hence we need to enable RTD3 for nipperkin additionally which refers
    to this one:
    https://review.coreboot.org/c/coreboot/+/54967
    
    BUG=b:200246826
    BRANCH=guybrush
    TEST=emerge-guybrush coreboot chromeos-bootimage
         run suspend test on eMMC sku
    
    Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
    Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Raul Rangel <rrangel@chromium.org>
    Kevin Chiu authored and felixheld committed Oct 11, 2021
    Copy the full SHA
    7cbeaff View commit details
    Browse the repository at this point in the history
  3. mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support

    Add ALC5682-VS codec support in corori.
    
    ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
    Update hid name depending on the AUDIO field of ssfc.
    
    ALC5682-VD: _HID = "10EC5682"
    ALC5682I-VS: _HID = "RTL5682"
    
    BUG=b:201372531, b:194436265
    TEST=ALC5682-VD/ALC5682-VS audio codec can work.
    
    Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
    Change-Id: I2f3edb0b594066714b42050a411103a215e68b12
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Aseda Aboagye <aaboagye@google.com>
    Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
    Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
    Ian Feng authored and felixheld committed Oct 11, 2021
    Copy the full SHA
    16fc622 View commit details
    Browse the repository at this point in the history
  4. mb/google/brya/var/redrix: select CHROMEOS_DSM_PARAM_FILE_NAME

    Enable CHROMEOS_DSM_PARAM_FILE_NAME to report dsm parameter file name.
    
    BUG=b:197076844
    TEST=build and check SSDT.
    
    Change-Id: I726e5854bc6a8fb125cb3b7572ddedff49c3c403
    Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58175
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    Wisley Chen authored and felixheld committed Oct 11, 2021
    Copy the full SHA
    14886ae View commit details
    Browse the repository at this point in the history
  5. drivers/intel/dptf: Add support for PCH methods

    Add various methods support for pch device under dptf driver.
    This provides support of different control knobs for FIVR.
    
    BUG=b:198582766
    BRANCH=None
    TEST=Build FW and test on brya0 board
    
    Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558
    Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    sumeetpawnikar authored and felixheld committed Oct 11, 2021
    Copy the full SHA
    e0bff81 View commit details
    Browse the repository at this point in the history
  6. soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization

    The PCI-SIG engineering change requirement provides the ACPI additions
    for firmware latency optimization. This change adds additional ACPI DSM
    function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the
    USB4/TBT topology. The OS is informed to reduce latency for upstream
    ports while connecting USB4/TBT devices.
    
    BUG=b:199757442
    TEST=It was validated that the first connected device waits only 50ms
    instead of 100ms and all functions work on Voxel board.
    
    Signed-off-by: John Zhao <john.zhao@intel.com>
    Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    jzhao80 authored and felixheld committed Oct 11, 2021
    Copy the full SHA
    7227cef View commit details
    Browse the repository at this point in the history
  7. drivers/intel/dptf: return package with value

    Return the package with a value for the dptf user space service.
    This is required in write tpch method for pch device under dptf
    driver.
    
    BUG=b:198582766
    BRANCH=None
    TEST=Build FW and test on brya0 board
    
    Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba
    Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
    Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174
    Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
    Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
    sumeetpawnikar authored and felixheld committed Oct 11, 2021
    Copy the full SHA
    7c1ce19 View commit details
    Browse the repository at this point in the history