Commits on Jan 25, 2022
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soc/intel/elkhartlake: Introduce Intel PSE
The Intel® Programmable Services Engine (Intel® PSE) is a dedicated offload engine for IoT functions powered by an ARM Cortex-M7 microcontroller. It provides independent, low-DMIPS computing and low-speed I/Os for IoT applications, plus dedicated services for real-time computing and time-sensitive synchronization. The PSE hosts new functions, including remote out-of-band device management, network proxy, embedded controller lite and sensor hub. This CL enables the user to provide the base address of the PSE FW blob which will then be loaded by the FSP-S onto the ARM controller. PSE FW will do the initialization work of PSE controller and its peripherals. The loading of PSE FW should have negligible impact on boot time unless PSE controller could not locate the PSE FW and FSP will attempt to redo PSE FW loading and wait for PSE handshake until it times out. Once PSE controller locate the PSE FW, it will do initialization concurrently by itself with coreboot booting. It also adds PSE related FSP-S UPD settings which enable the setup of peripheral ownership (assigned to the PSE or x86 subsystem) and interrupts. These assignments need to take place at a given point in the boot process and cannot be changed later. To verify if PSE FW is loaded properly, the user could enable PchPseShellEnabled flag and the log will be printed at PSE UART 2. For further info please refer to doc #611825 (for HW overview) and #614110 (for PSE EDS). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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soc/intel/elkhartlake: Add PSE TSN support
Enable PSE GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Add PSE GBE ACPI devices 3. Refactor PCH GBE FSP-S code and merge it together with PSE GBE code Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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soc/intel/common: Include Alder Lake-N device IDs
Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
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mb/google/brya/variants/volmar: Configure GPIOs according to schematics
Update initial gpio configuration for volmar BUG=b:211891086 TEST=FW_NAME=volmar emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1bd3f1b3807b546d5a827ac89f0dc9bc8aaec40a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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mb/google/brya/var/volmar: Enable EC keyboard backlight
Enable EC keyboard backlight for volmar. BUG=b:211891086 TEST=FW_NAME=volmar emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I24ec7c8ca770cb438aabcf16b252032eef6d734d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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soc/intel/adl: Replace dt
HeciEnabledbyHECI1 disableconfigSince Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional
The FSP API is used to notify the FSP about different phases in the boot process. The current FSP specification supports three notify phases: - Post PCI enumeration - Ready to Boot - End of Firmware This patch attempts to make calling into the FSP Notify Phase APIs optional by using native coreboot implementations to perform the required lock down and chipset register configuration prior boot to payload. BUG=b:211954778 TEST=Able to build brya without any compilation issue and coreboot log with this code changes when SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT and SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config enabled. coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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lib/cbmem_console,console: Resurrect CONSOLE_CBMEM_DUMP_TO_UART
Chromebooks normally run with non-serial enabled firmware because writing to the UART console is very slow. This unfortunately makes debugging boot errors more difficult. We tend to rely on port 80s and/or the vboot recovery code. When CONSOLE_CBMEM_DUMP_TO_UART is selected it will dump the entire cbmem console to the UART whenever `vboot_reboot()` is called. We don't incur any boot time penalty in the happy path, but still retain the ability to access the logs when an error occurs. The previous implementation was using a hard coded UART index and `get_uart_baudrate` was always returning 0 since `CONFIG_TTYS0_BAUD` wasn't defined. This change makes it so the UART console properties are available when CONSOLE_CBMEM_DUMP_TO_UART is set. This results in the following .config diff: +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_TTYS0_LCS=3 +CONFIG_CONSOLE_SERIAL_115200=y +CONFIG_TTYS0_BAUD=115200 This functionality is especially helpful on Guybrush. PSP Verstage is run on S0i3 resume. Today, if there is an error, the cbmem console is lost since it lives in the PSP SRAM. BUG=b:213828947, b:215599230 TEST=Build non-serial guybrush FW and verify no serial output happens in happy path. Inject a vboot error and perform an S0i3 suspend/resume. Verify CBMEM console gets dumped to the correct UART. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I997942204603362e51876a9ae25e493fe527437b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> -
northbridge/intel/i945: Change types to uintptr_t where appropriate
Prepares compilation for x86_64 by avoiding casts to different sizes. Current patch fixes: 1. src/northbridge/intel/i945/raminit.c: In function 'ram_read32': src/northbridge/intel/i945/raminit.c:77:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 77 | read32((void *)offset); | ^ 2. src/northbridge/intel/i945/rcven.c: In function 'sample_strobes': src/northbridge/intel/i945/rcven.c:29:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 29 | read32((void *)addr); | ^ src/northbridge/intel/i945/rcven.c:30:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 30 | read32((void *)(addr + 0x80)); | ^ 3. src/northbridge/intel/i945/gma.c: In function 'intel_gma_init_lvds': src/northbridge/intel/i945/gma.c:98:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 98 | (void *)pgfx, mmiobase, piobase, pphysbase); | ^ src/northbridge/intel/i945/gma.c:359:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 359 | (void *)pgfx, hactive * vactive * 4); | ^ src/northbridge/intel/i945/gma.c:360:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 360 | memset((void *)pgfx, 0x00, hactive * vactive * 4); | ^ src/northbridge/intel/i945/gma.c: In function 'intel_gma_init_vga': src/northbridge/intel/i945/gma.c:384:17: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 384 | (u32)mmiobase, piobase, pphysbase); | 4. src/northbridge/intel/i945/northbridge.c: In function 'mch_domain_read_resources': src/northbridge/intel/i945/northbridge.c:64:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 64 | cbmem_topk = ((uint32_t)cbmem_top() / KiB); | ^ Change-Id: I5ac7a1cb5d85a346114f909047d5a7c21ddb43e9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> -
soc/intel/ehl: Add Kconfig option to disable reset on TCO expiration
The TCO timer is the default watchdog of an x86 host and can reset the system once it has expired for the second time. There are applications where this reset is not acceptable while the TCO is used. In these applications the TCO expire event generates an interrupt and software takes care. There is a bit in the TCO1_CNT register on Elkhart Lake to prevent this reset on expiration (called NO_REBOOT, see doc #636722 ). This bit can either be strapped on hardware or set in this register to avoid the reset on expiration. While the hardware strap cannot be overridden in software, the pure software solution is more flexible. Unfortunately, the location for this bit differs among the different platforms. This is why it has to be handled on soc level rather than on TCO common code level. This commit adds a Kconfig option where NO_REBOOT can be enabled. This makes it easy to reach this feature over to the mainboard where it can be selected if needed. Change-Id: Iaa81bfbe688edd717aa02db86f0a93fecdfcd16b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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mb/siemens/mc_ehl: Prevent reset when TCO expires
In order to guarantee data integrity an expired TCO must not hard reset the board. Select the Kconfig switch to prevent this reset. Change-Id: I04080c6bcd486e3a406438cc7a703165bb6945a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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mb/google/brya/var/taniks: Run time probe for NVMe SSD and MMC
Taniks will use two PCIE port signals with one slot, one CLK and one CLKREQ at next build. In order to accommodate this, probe statements are added to the devicetree. This only affects NVME SSD and EMMC. BUG=b:215040000 TEST=Build FSP with debug output enabled, and observe the correct root ports being initialized depending on the FW_CONFIG values for BOOT_EMMC and BOOT_NVME. Cq-Depend:chromium:3397561 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2ead505088f19fd3bf9768b541838395c82ef051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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mb/google/brya/var/taniks: swap TPM i2c with TS i2c for next build
Taniks is going to exchange i2c port for touchscreen and cr50. BUG=b:215039999 TEST=emerge-brya coreboot Cq-Depend:chromium:3397562 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I179949887f6d8f4bbdff7d806319e2ac368ebc2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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mb/google/brya/var/taniks: Modify DPTF settings for taniks
Update DPTF settings provided by thermal team BUG=b:215033682 TEST=build and tested on taniks board Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic6860980b06e876dd4c21af26752ab6c1a3f7fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/61337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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mb/system76: Enable SrcClk pin for CPU PCIe RPs
This reverts commit bd9b044 ("mb/system76: rtd3: Remove SrcClk pin on CPU RP"). Previously, RTD3 expected a PCH index for the root port and did not work with the CPU PCIe RP present on TGL, so SrcClk pin was disabled. Set them now that RTD3 supports mapping the index for the CPU RP. Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
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soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
The FSP gets these values from the UPD and sets the internal values. The document about eDP tuning is attached in issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Cq-Depend: chrome-internal:4303901 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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mb/google/guybrush/var/nipperkin: Add Board values for eDP tuning
Reference test document, update tuning registers from pass experiment setting of phy_settings. The document about eDP tuning can be gotten from the issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
