Currently the LPIT Get Constraints _DSM subfunction returns a package containing the path to a nonexistent device (\NULL). This is used to work around an issue with Windows, where returning an empty package will cause a BSOD. However, using this non-existent device can also cause confusion, as on Linux, it shows an error in dmesg, e.g. ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \NULL (20200925/dspkginit-438) Therefore, this patch modifies this returned package slightly to include the path to ACPI_CPU_STRING for CPU 0, which should always be emitted on Intel platforms that use the PEP driver. Tested on google/brya0 on ChromeOS 5.10 kernel Tested with current Windows 11 ISO Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If74a1620ff0de33bcdba06e1225c5e28c64253e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>

Change-Id: I14084f95af122c160f287f0133017a769c249d00 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

Include chausie EC and EFS only in the RO region when building with vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B regions. Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

We currently delete intermediate files. This can make it difficult to debug and is also unexpected. Setting .SECONDARY will prevent make from deleting the files. BUG=b:221231786 TEST=Build guybrush with CL stack and see .map files are preserved Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I657a696acc71d42ba94442d4754ee63efd3e6a74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>

We don't currently have a build target defined for .map files. This means they can't be used as a dependency. This change splits the .map creation into its own rule. BUG=b:221231786 TEST=Build guybrush and verify .map still exists Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1ce21902e97390aa9520670299ef08debf4458db Reviewed-on: https://review.coreboot.org/c/coreboot/+/62399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>

This will allow linker flag customization for rmodules. BUG=b:221231786 TEST=Build guybrush with patch train and verify ldflags are passed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib65476759e79c49d90856dcd7ee76d7d6e8a679a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>

Updating from commit id 10eae55: 2021-08-24 21:11:18 +0800 - (Elkhart Lake MR1 FSP) to commit id f4bbf5a: 2022-01-29 00:32:47 +0800 - (Apollo Lake MR10 FSP) This brings in 20 new commits: f4bbf5a Apollo Lake MR10 FSP aab8be0 Apollo Lake MR10 FSP 45b935f Apollo Lake MR10 FSP 755e782 Signed-off-by: Wong <swee.heng.wong@intel.com> da956c1 Whitley FSP 2.2.0.3A 7e3d894 Whitley FSP 2.2.0.3A 04ad3cd Tiger Lake - UP3 IoT FSP MR4 ccf7f35 Elkhart Lake MR2 FSP 4aa1275 Elkhart Lake MR2 FSP 8aa6a9a Cedar Island FSP 2.2.0.3A 2e2e740 Whitley FSP 2.2.0.3A 91a6117 Tiger Lake - UP3 IoT FSP MR3 2863499 Delete FspUpd.h df41c58 Delete FsptUpd.h 0d420eb Delete FspsUpd.h 53cc56a Delete FspmUpd.h ad51318 Tiger Lake - UP3 IoT FSP MR3 63273a4 Delete Fsp.fd ce61eb3 Tiger Lake - UP3 IoT FSP MR3 f7f77a2 Delete Fsp.bsf Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6128b9703498dd36be73c19cbbfe349c206c6cf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>

Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder Lake N RVP from devicetree. Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>

Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0e965513d5888398834cab8c8445e97372f2b115 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ife0f5b8b6102b543a7ace6739fa44d32ca80dcde Reviewed-on: https://review.coreboot.org/c/coreboot/+/62333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iddbf2022d03735d6a0e6d098c21643f5fdc875f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Move the instructions for flashing coreboot with fwupd to common directory as the process is identical across all models and variants. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I293acf962b32c81fdf482e0df15363e1cffa39bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>

coreboot should skip sending EOP during S3 resume since CSE doesn't require EOP in resume path. Currently EOP is being sent during PAYLOAD_BOOT or PAYLOAD_LOAD stage which doesn't get called during S3 resume. In case EOP is moved in earlier stage, coreboot might send EOP in S3 resume as well. This patch adds check before calling cse_send_eop. BUG=b:211085685 BRANCH=None TEST=Check by moving EOP to earlier stage. EOP sending is skipped during S3 resume. Change-Id: I8f22446974bc1e7b2d57468633c36bb99ffe1436 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>

Enable STT and decrease sustained_power_limit_mW to 12W BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I5b7b0156fb4a1e2be8528a5787ed82acff93f06c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>

Instead of using raw integers to indicate success/failure, enum cb_err can be used to makes things clearer, so this patch converts most functions to return that instead of int. TEST=boot to OS on google/dratini, no TPM errors seen Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifb749c931fe008b16d42fcf157af820ec8fbf5ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

In order to abstract bus-specific logic from TPM logic, the prototype for two vendor-specific tis functions are added in this patch. tis_vendor_read() can be used to read directly from TPM registers, and tis_vendor_write() can be used to write directly to TPM registers. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I939cf5b6620b6f5f6d454c53fcaf37c153702acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>

Chausie doesn't have recovery mode buttons so it's impossible to manually enter recovery mode to enable developer mode. This means we need to force developer mode. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

If an AMD FSP binary has no valid image revision information, print a warning instead of an error. Change-Id: Ie9c5a387b81205fe93382778090260e41e261776 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after warm reboot. Config GPP_B3 unlocked to make reboot works on primus. Also set GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power on sequence. BUG=b:221488504 TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage test reboot 30 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>

This patch removes Rcomp settings. In MRC design, it checks if the Rcomp settings from the board is 0 or null, if so, it uses the recommended Rcomp values. Otherwise, it uses the Rcomp settings passed from the UPD. From the change history of MRC, we're chasing a moving target. This RCOMP setting in coreboot is an old setting while the Rcomp settins in MRC are optimized settings. Moving forward, if there is a new stepping, it might be changed again which increases the maintenance effort in coreboot. IMHO, we should let MRC to set the optimized RCOMP values for the design. BUG=b:219378758 TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are filled properly by MRC. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

The linkchecker tool is now being used to find broken links in our websites. Since it's not needed for building anything, just add it to the jenkins-node Dockerfile instead. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iac2246b5378e556b5cd9f2107fc5a7e51d583b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62445 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

It's easier to read and to add new packages when each package is on its own line and they're sorted alphabetically. Indenting them also makes it easier to see what's getting installed and what's a command. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibfe297bd408ed0783fcff09c1ecb5672fe785c48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62446 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Align the setting with the adlrvp BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and works correctly in the brask Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

google/brask is using SODIMMs for DRAM. Reading spd data is surprisingly slow (~170 ms), therefore enable the SPD cache. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=run on the device and measure the boot time decrease. Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

RTC_GPIO_USER_MASK is not used in any drivers, so we remove them. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>

The XTAL 26MHz test failed on krabby, so we adjust RTC capid from default value 0x88 to 0xC0 for MT8186. We also add a new log message to show the capid value which is read from MT6366. This implementation is according to chapter 5.13 in MT8186 Functional Specification. BUG=b:218439447 TEST=set capid to 0xc0. TEST=XTAL 26MHz test passed. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>

Both the secondary and subordinate bus numbers are configured in this function but it's not easy to search for in the tree as the PCI writes are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate variables and PCI config writes to improve the readability. Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>

Fix the spelling and use the one from their website supermicro.com Change-Id: Id630d9d130082fb38f9151e0dfb6f6fbb5a2789d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

The Supermicro X9SAE target is supported since coreboot version 4.15. Documentation is available in the tree, but it's not referenced from the mainboard index page. Fix that. Change-Id: I5d3d0b5b935f1a3ea353a3d9e39208db7c7895ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Fix spelling and use the one from their website qemu.org. Change-Id: I36a88985ce3a7c59b732c1ca3198d86a591de6bd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>

The QEMU POWER9 target is supported since coreboot version 4.15. Documentation is available in the tree, but it's not referenced from the mainboard index page. Fix that. Change-Id: Ic3b98735840c146cb0bfb122df0e6f762c2beeca Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>

In order to achieve a stable eMMC interface disable the HS400 capability of the host controller. This will result in an operating mode of maximum HS200 (200 MHz single data rate) which leads to a more relaxed timing. Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

All SoCs/chipsets that select ARCH_X86 will end up using the implementation in cpu/x86/lapic/lapic.c, so to avoid confusion, drop the unused weak implementation that returns a different value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iffcd8c80260f9a7d81dda41a0ad08bffc7620c33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>

We need to save the transfer buffer so we can transfer the cbmem console and timestamps into x86 DRAM. BUG=b:221231786 TEST=Boot guybrush and verify S0i3 resume works. Also dumped the transfer buffer from the OS and verified the console contents got transferred. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

I want to reuse the transfer buffer methods in SMM, so I need to add them into their own file. I renamed `setup_cbmem_console` to `replay_transfer_buffer_cbmemc` so it has a more descriptive name. I also fixed the comment on `verify_psp_transfer_buf`. BUG=b:221231786 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

We don't need to force the caller to look up and cast the transfer region. We can do it in the function. BUG=b:221231786 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

Configure GPIOs according to schematics BUG=b:218786363 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I939bc5f8963e9cba762adeb4828729fd14e29520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

Since we want to read the non-x86 CBMEMC from SMM we need to be stricter on where we read from. This change forces the verstage binary and x86 code to agree on the CBMEMC transfer buffer location and size. BUG=b:221231786 TEST=Boot guybrush and verify verstage transfer buffer still ends up in cbmem Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

Disabled G2touch driver and add ELAN touchpanel driver for vell. Due to incorrect BIOS setting, touch screen IC FW can't update and work. According to ELAN's recommendations, we coreect the ELAN2513 driver's setting and change I2C address to 0x10 BUG=b:221340736 TEST=emerge-brya coreboot and can flash touch screen FW Change-Id: I22f04fa21b542e21e88c46547779cfb55beb5c12 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com>

…n capacity If B1FC (Battery Full Capacity) is higher than B1DC (Battery Design Capacity), only report the design capacity. This handles cases where the battery calibration is incorrect, and the battery runs out before the OS thinks it's empty. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Picasso with Cezanne and Sabrina. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=Mandolin still boots successfully to Linux desktop and dmesg doesn't show any any possibly related problems. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>

After the patch that moved the generation of the PPKG object to Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>

Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Stoneyridge with the other AMD SoCs. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=None, but equivalent change on Picasso was verified to not break anything on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>

After the patch that moved the generation of the PPKG object to Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>

In order to align with established standards for establishing DMA boundaries[1] from ACPI, the UntrustedDevice property has been renamed to DmaProperty, which follows Microsoft's implementation. After discussions with Microsoft, they have agreed to make the `UID` property optional, so it is left out here, and instead it can be applied to: 1) Internal PCI devices 2) PCIe root ports 3) Downstream PCI(e) devices [1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports BUG=b:215424986 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id70e916532e3d3d70305fc61473da28c702fc397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>

TPM1_MODE and TPM2_MODE defines have to be added to vboot and payload cflags to make them build correctly without requiring payloads to provide defines. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I567a9f04d7089699840dc7e0a063cf3030fb934b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>

In the northbridge's and root complex' read_resources function, the mmconf resource used the number of the MMIO_CONF_BASE MSR as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed) After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>

In the northbridge's and root complex' read_resources function, the GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed) After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8061364879d772469882fc060f92676de6f600a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>

Add a comment to point out that the read_resources functions aren't missing a pci_dev_read_resources call that would add the resources for the BARs of the PC device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>

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