BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that the XHCI controllers
are enumerated successfully and ACPI device objects are added in SSDT.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ad4555212ed38ea0f9029275345e4945855a8c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

Treat dimm addr_map 0 non-existent. addr_map default is 0, we don't set
it if Hw is not present. Also change the test case default to avoid 0.
SODIMM SMbus address 0x50 to 0x53 is commonly used.

BUG=b:213964936
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The MRC training does not be performed again after rebooting.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

After assessing the signal integrity, 100 MHz SPI fast speed can be
enabled for SPI ROM.

BUG=b:213403891
TEST=Build and boot to OS in Dewatt board version 2.

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Configure the power saving pin for Smart Card.

BUG=b:229356121
TEST=emerge-brya coreboot chromeos-bootimage

Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Disable SATA config from devicetree for ADL-N RVP, since we are not
planning to use it in chrome config.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ic9dce3a0b06e1a0d0d9fa495aa406eb12557d842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>

This alias name is required for the mainboard.c code to generate the
appropriate power-off seqeuence for use during orderly S5 shutdown
from the OS. It had been accidentally removed, but is required, so
this patch adds it.

BUG=b:227788351
TEST=compile

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

This patch migrates GPMR driver over DMI to accommodate future SOCs
with different interface (other than PCR/DMI).

TEST=Able to build and boot google/redrix.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

1. Remove dmi.h as it's migrated as gpmr.header
2. Remove unused gpmr definitions
3. For old platforms, define DMI defintions in c code
   for less code changes.

TEST=Build
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

This patch adds a section to the coding style that explicitly clarifies
the use of GCC extensions in coreboot (which has been long-standing
practice anyway), and expressly allows their use.

See the mailing list discussion for more details:
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/3C2QWAZ5RJ6ME5KXMEOGB5GW62UTXCLS/

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0d0eb90d6729fefeb131cdd573ad51f1884afe11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

Add PROP method under \_SB.DPTF.TPWR scope which will return static
worst case rest of platform power in miliWatts.

This value is static, which has to configured from devicetree of
overridetree for each platform

BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check PROP method

Scope (\_SB)
{
    Device (DPTF)
    {
        Device (TPWR)
        {
            Method (PROP, 0, Serialized)
            {
                Return (XXXX)
            }
        }
    }
}

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
The no-op `_DIS` methods can also be removed for the same reason.

Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.

Change-Id: I71275f2581b999d606f36773578b36dbdccf6452
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the only
mainboard using the SCH5545 code, `dell/snb_ivb_workstations`.

Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the two
mainboards using the MEC1308 code, `samsung/{lumpy, stumpy}`.

Change-Id: I5d5cdc28c2cfaa5dfcffd656060b931208977386
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

This should no longer be needed because the ASL has been fixed.

Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.

Change-Id: Ic37608ac9622b37cae6d81045740a033e9aa9d4f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
The no-op `_DIS` methods can also be removed for the same reason.

Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.

Change-Id: I7e702e9318fbf68dbd883a145111e6beb6815b8b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.

Change-Id: If56267e8a68897236d5ff73322317cbef7ab2243
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

…tion

There is no easy way to add dependencies to cbfs-structs objects and
fmap_config.h is a generated file. Follow-up commits depend on it being
available so add it in the cbfs-struct makefile function.

Change-Id: I7067ff144d38c1ff058825819419b2a2e7801e17
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Change-Id: Ie874fe2c023157fad0adc021faa45e70822208da
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

Packing structs will result in unaligned sizes, possible causing
problems for other entries.

Change-Id: Ifb756ab4e3562512e1160224678a6de23f3b84ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63714
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This reverts commit d80d88c.

Reason for revert: 100Mhz should only be enabled on DeWatt
on board version >=3. Enabling it on board version 2 will
cause failures.

BUG=b:213403891
BRANCH=guybrush
TEST=Build dewatt

Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63746
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Based on the latest schematic, exchange I2C port for TPM/touchscreen.
TPM: I2C3 -> I2C1
Touchscreen: I2C1 -> I2C3

BUG=b:202671753
TEST=emerge-brya coreboot

Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

Configure GPP_R0, GPP_R1, GPP_R2 and GPP_R3 for headset function
enable with ALC5682I+MAX98360.

BUG=b:202671753
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>

In order to enable the UFS controller (PCI device 12.7), the PCI
specification says that the device at function 0 in the same slot must
also be enabled, which is the ISH. Therefore, this CL enables both
the UFS controller and ISH.

TEST=Boot to kernel and check lspci output
     00:12.0 Serial controller: Intel Corporation Device 54fc
     00:12.7 Mass storage controller [0109]: Intel Corporation
     Device 54ff

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62662
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I3f438a7b1dff1a44a81edc8adc983d08708fdd57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

The PCI Local Bus Specification Revision 3.0 requires that
multi-function devices always implement function 0. Because of
this, enabling UFS (PCI device 12.7) requires ISH (PCI device 12.0)
to be enabled as well.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia8b9561973640edc5f7d0f579dd640e805c0af17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Enable SPI dTPM using eSPI bus.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I18ca41c143ade024ee2840b619ba777b22a2a86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Increase RFI Spread Spectrum to 6% for Vell as RF team request. The
default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard
as default.

BUG=b:228929196
TEST=emerge-brya coreboot and pass RF test as before

Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

Update SPI setting as below:

Normal speed:33mhz
Fast speed:66mhz
Alt speed:66mz
TPM speed:33mhz

BUG=b:225213679
TEST=boot skyrim and verify spi settings.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icbe4b9f4794f7e883c3819258ede809c3c8922b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

Change-Id: I530bb217bb9a944990232dcf4e08f160b5267512
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55008
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Create the osiris variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:229352299
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_OSIRIS

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I41e088a3415add86cba87c919af23494f816bb24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63650
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

MT53E512M32D1NP-046 WT:B (Micron)
MT53E1G32D2NP-046 WT:B (Micron)
H54G46CYRBX267 (Hynix)
H54G56CYRBX247 (Hynix)
K4U6E3S4AB-MGCL (Samsung)
K4UBE3D4AB-MGCL (Samsung)

BUG=None
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63706
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Taeko/Tarlo uses the WIFI_SAR_ID field in FW_CONFIG to pick which
SAR table to load.

BUG=b:226684990
TEST=emerge-brya coreboot

Cq-Depend: chrome-internal:4676926, chrome-internal:4686953
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I9852553f5c91494db845d45a94e2566248538bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

Looks like the `notify_data` struct array idea comes from the FSP 2.0
notify driver, which has a similar struct but with several additional
fields. However, there's no need for this mechanism in the CSE driver
because the struct only contains a condition (boolean) and a function
to execute, which can be expressed as a regular if-block.

Change-Id: I65fcb2fc02ea16b37c764f1fd69bdff3382fad18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63708
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Alder Lake-N has single memory controller with 64-bit bus width. Alder
Lake common meminit block driver considers bus width to be 128-bit and
populates the meminit data accordingly. By setting half_populated to
true, only the bottom half is populated.

Ideally, half_populated is used in platforms with multiple channels to
enable only one half of the channel. Alder Lake N has single channel,
and it would require for new structures to be defined in meminit block
driver for LPx memory configurations. In order to avoid adding new
structures, set half_populated to true. This has the same effect as
having single channel with 64-bit width.

BRANCH=NONE
TEST=Build and boot ADL-N RVP.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62913
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This patch drops unused LPC BIOS control macros.

BUG=b:211954778
TEST=Able to build and boot google/hatch.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib309c6bd0f27115357f8e62200808764748f51a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

This patch performs additional SPI lock configuration as per Intel
Flash Security Specification.

BUG=b:211954778
TEST=Able to build google/brya and verified all flash security
recommendations are being met.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

This patch implements two APIs to perform LPC/eSPI write protect enable/
disable operation using PCI configuration space register 0xDC
(BIOS Controller).

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8ce831218025a1d682ea2ad6be76901b0345b362
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

Add FW_CONFIG STORAGE and probe for UNKNOWN, NVME and eMMC.

BUG=b:220039297
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: If83031edcd90ea746704590765102b9b0dee03c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>

Fix WLAN PCIE speed to GEN2. Dynamic switching between speeds is causing
the PSP to hang when resuming from S0ix suspend. The root cause is still
under investigation. Just disabling PSPP fixes the hang but causes poor
PLT performance.

BUG=b:228830362
BRANCH=guybrush
TEST=suspend_stress_test on AC and DC

Change-Id: I988365e51aca0d6515c5605b3032521cf59d8d30
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63722
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on lantis.

BUG=b:223687184
TEST=emerge-dedede coreboot

Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on drawcia.

BUG=b:223687184
TEST=emerge-dedede coreboot

Change-Id: I683049e9d2b10fc9455ef782ce798f1c453073bc
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on kracko.

BUG=b:223687184
TEST=emerge-dedede coreboot

Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: Ib12265591e679e6b9ed34299f1256db05147eaef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

After assessing the signal integrity, 100 MHz SPI fast speed can be
enabled for SPI ROM.

BUG=b:213403891
BRANCH=guybrush
TEST=Build and boot to OS in Dewatt board version 3.

Change-Id: If0318abf1fed9b1f4ba876f736fdbf92c1ea6933
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Break TPM related Kconfig into the following dimensions:

TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)

TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)

What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2

What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2

The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE

Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

commit c6b041a refactor the TPM Kconfig. MAINBOARD_HAS_LPC_TPM
has changed to MEMORY_MAPPED_TPM.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63773
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add WiFi SAR table for taniks.

BUG=b:226690925
TEST=build FW and checked SAR table can load by WiFi driver.

Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I7b52f71b1fe49c02beaa48410495b81661b58fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1

BUG=b:227165770
TEST=build FW and system power on.

Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I262ef14032e0e412c63403dbb8c8fbc6a8b03dd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>