Make sure S0Ix is supported before trying to set up the EC's
lazy wake mask.

Change-Id: I78896ffe6312409c9f241b3b3224169c188bb265
Signed-off-by: Paul Moy <pmoy@chromium.org>
Reviewed-on: https://review.coreboot.org/28610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

Add definition for PCH_GPIO_PIRQ_INVERT, which is needed
for google/buddy, a to-be-merged variant of google/auron.

Taken from Chromium commit 70ee99b [buddy: change trigger type of gpio53]

Change-Id: I21448160cee791710df51d06efa32cdfecf38c0f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

Use an empty weak function for variant_romstage_entry(), rather than
having separate empty functions for boards which don't utilize it.

Change-Id: I7a278ed716484bea377a5dd98d4a534502c8bab6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

Add google/buddy (Acer Chromeboase 24) as a variant of google/auron,
with the following changes:

- add buddy-specific variant code
- add handling to auron for buddy's lan init, which no other variants have
- add handling to auron's mainboard ACPI due buddy having different PCIe
  port assigments than all other variants

Ported from Chromium branch firmware-buddy-6301.202.B, commit
ebb82ce [Buddy: Lock management engine + SPI descriptor]

Test: build/boot Linux on google/buddy using SeaBIOS and Tianocore payloads

Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

Default STAPM percentage causes a lot of thermal throttling on grunt.
AMD experimented with 80%, it works for grunt. This is initial code to
provide easy change path for other grunt based platforms.

BUG=b:111608748
TEST=build and boot grunt.

Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I49526b6aafb516a668b7b5e983a0372e3d26a8fc
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Use of device_t has been abandoned in ramstage

Change-Id: Ifc32b0f6964a8c3e3a100c787ac2a889b39322a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of device_t has been abandoned in ramstage.

Change-Id: Ifa54624664c06c606fb4e083bae98b4accc61be0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Use of device_t has been abandoned in ramstage.

Change-Id: Ib4dbb607cfd1e02d45efe141b498d6505574d6e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Use of device_t has been abandoned in ramstage.

Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28631
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

PC Engines boards are interfaced mainly via serial console.
Enable SeaBIOS serial console for these boards by default
when SeaBIOS selected as payload.

Change-Id: I9e65dd1e28859028c8c46f28a5442de8c59d4893
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27824
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

They allow reducing the visible set of options to remove clutter.

Change-Id: I18c953c7feae23c0752392a2bf8f49783c17310e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

These values override the default subsystem IDs, and aren't needed.

BUG=b:113253260
TEST=Boot grunt

Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/28652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

While the pin was set to a pull-down, with the external pull-up, this
wasn't enough to keep the pin low.  Set to output low to drive to 0V.

TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V.
BUG=b:115661061

Change-Id: Ife014b8a879274df5d892c1de386976808de1df0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

AMD has tested careena, and for the time being is recommending a scalar
of 68%, power limit of 7.8 W and time constant of 2500. Using new STAPM
configuration code, set the desired values.

BUG=b:111561217
TEST=none, code was tested with grunt.

Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

With the addition of new boards using macros to set per board settings in the
same gpio.c file is getting too complicated so link separate files.

Change-Id: I3ab05f1af6ba0a04dd827816b3bcaa506a3f6aff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Use of device_t has been abandoned in ramstage.

Change-Id: I3d1bdefd00c91a98116ede5dc03c3ce253d1f0ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: Id3199d130825a5f796108ae45ce965325511ce8b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

According to AMD, there exists an undocumented MSR which must be
written with the PSP's base address.  Read the value from the PSP's
config space and sync each core's copy of the MSR to match.

BUG=b:76167350
TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg

Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28608
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I400de0a622c2b45ea5ef1f1446f4f489ac397c32
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28673
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I4fcdb7467f1911af722f4c24ce64807079a91340
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>

…vice

The DMAR table generation depends on the VT-d feature which is
implemented in its own PCI device located in PCI:00:05.0 for
Broadwell-DE. Add a new PCI driver for this device and move
DMAR table generation to this device driver.

Change-Id: I103257c73f5e745e996a441a2535b885270bc204
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

FSP initializes the VT-d feature on Broadwell-DE and assigns an address
space to the MMIO range. coreboot's resource allocator needs to be aware
of this fixed resource as otherwise the address can be assigned to a
different PCI device. In this case addresses are overlapped and the VT-d
range is not accessible any more.

To deal with it the right way add a fixed MMIO resource to the resources
list if VT-d BAR is enabled.

TEST=Booted into Linux and checked coreboot log for resource assignment.

Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

This patch contain minimal set of changes to initial IVRS implementation
to make it work reliably. Code in this patch was tested with Xen 4.8 and
Debian 4.14.y - this software stack survived 100x reboots without any
hang on PC Engines apu2c4. Previously using IVRS provided by AGESA lead
to 29/100 hangs.

MMIO base shall not be hard coded since this value depends on platform
design.

Performance counters were selected experimentally, since lack of
them cause 4.14.y panic:
[    1.064229] AMD-Vi: IOMMU performance counters supported
[    1.069579] BUG: unable to handle kernel paging request at ffffaffc4065c000
[    1.073554] IP: iommu_go_to_state+0xf8a/0x1260
[    1.073554] PGD 12a11f067 P4D 12a11f067 PUD 12a120067 PMD 129b69067 PTE 0
[    1.073554] Oops: 0000 [#1] SMP NOPTI
[    1.073554] Modules linked in:
[    1.073554] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.14.50 #13
[    1.073554] Hardware name: PC Engines apu2/apu2, BIOS 4.8-1174-gf12b3046f0-d2
[    1.073554] task: ffff8d5d69b9f040 task.stack: ffffaffc40648000
[    1.073554] RIP: 0010:iommu_go_to_state+0xf8a/0x1260
[    1.073554] RSP: 0018:ffffaffc4064be28 EFLAGS: 00010282
[    1.073554] RAX: ffffaffc40658000 RBX: ffff8d5d69bae000 RCX: ffffffff99e57b88
[    1.073554] RDX: 0000000000000000 RSI: 0000000000000092 RDI: 0000000000000246
[    1.073554] RBP: 0000000000000040 R08: 0000000000000001 R09: 0000000000000170
[    1.073554] R10: 0000000000000000 R11: ffffffff9a435e2d R12: 0000000000000000
[    1.073554] R13: ffffffff9a29a830 R14: 0000000000000000 R15: 0000000000000000
[    1.073554] FS:  0000000000000000(0000) GS:ffff8d5d6ec80000(0000) knlGS:00000
[    1.073554] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[    1.073554] CR2: ffffaffc4065c000 CR3: 000000010fa0a000 CR4: 00000000000406e0
[    1.073554] Call Trace:
[    1.073554]  ? set_debug_rodata+0x11/0x11
[    1.073554]  amd_iommu_init+0x11/0x89
[    1.073554]  pci_iommu_init+0x16/0x3f
[    1.073554]  ? e820__memblock_setup+0x60/0x60
[    1.073554]  do_one_initcall+0x51/0x190
[    1.073554]  ? set_debug_rodata+0x11/0x11
[    1.073554]  kernel_init_freeable+0x16b/0x1ec
[    1.073554]  ? rest_init+0xb0/0xb0
[    1.073554]  kernel_init+0xa/0xf7
[    1.073554]  ret_from_fork+0x22/0x40
[    1.073554] Code: d2 31 f6 48 89 df e8 d8 15 02 ff 85 c0 75 d1 48 8b 44 24 2
[    1.073554] RIP: iommu_go_to_state+0xf8a/0x1260 RSP: ffffaffc4064be28
[    1.073554] CR2: ffffaffc4065c000
[    1.073554] ---[ end trace 44588f98aa7c7c0b ]---
[    1.255973] Kernel panic - not syncing: Attempted to kill init! exitcode=0x09
[    1.255973]
[    1.259934] ---[ end Kernel panic - not syncing: Attempted to kill init! exi9

Possible future improvements:
- compare device entries with values returned by AGESA
- enable EFRSup (this is enabled in AGESA)
- try various IVHD flags (there is difference between initial
implementation and AGESA)

Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT.

BUG=b:115965629
TEST=verified it in meep proto board which rework ram id.

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363
Reviewed-on: https://review.coreboot.org/28658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>

Update DPTF settings based on recommendation from thermal team.

BUG=b:112550414
BRANCH=None
TEST=Manually tested by thermal team.

Change-Id: I26f09392a3293ce4b3481f2be341a667d606bc10
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/28666
Reviewed-by: Todd Broch <tbroch@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The helper function to get the board version from EC returns 0 on
failure. But 0 is also a valid board version. Update the helper function
to return -1 on failure and update the use-cases.

BUG=b:114001972,b:114677884,b:114677887

Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>

The board_id() definition is the duplicate of chrome EC board_id
definition. Remove the duplicate definition and select
EC_GOOGLE_CHROMEEC_BOARDID Kconfig item.

BUG=b:114001972,b:114677884,b:114677887

Change-Id: Id8b7027d653649e8e5791e455652c4e893a746c2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Tested-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Reviewed-on: https://review.coreboot.org/28609
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

…011-09-13

This microcode update for CPU ID 0x300F10 should improve the system stability.
It is a part of microcode_amd.bin officially released by AMD at linux-firmware:
it starts at 0x217C offset, and size is 0x03C0 as specified priorly at 0x2178.

    Old version:    0x300000F [2010-04-10]
            replaced by
    New version:    0x3000027 [2011-09-13]

Change-Id: I9650fab377d957904318ebb393323c2509cfea26
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/28378
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

…ocodes

It is much more convenient to view these files if there are 8 values per line,
not 1 value which results in a very long file. The contents remain the same:
these microcodes are still the latest publicly available at the time of writing.

Change-Id: I3e5296a5b5e895702a60aca1ded7418bb345263d
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/28391
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

When preparing transition of AGESA calls to romstage, I placed a comment
indicating the place to move a particular call. Now that the AGESA call
has been moved to romstage, the comment became obsolete.

BUG=b:116095766
TEST=none.

Change-Id: I2811657385ab088747e32d4c66b99fdd01e7315e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

Remove const define for spd_smbus_address, the value can be updated
depends on platform configuration.

TEST=Build and Run on Whiskey Lake rvp platform.
Found-by: Converity Scan #1395725

Change-Id: Ib933ed872e9f85087bb3cd76a1f1e29cca75cd54
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28664
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

A negative side-effect is that those boards disappear from the board-status
output, but this is an issue on all variants.

Change-Id: Ic80804dc1f7d9c6f83ceee3db667019532c31d4c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

According to cannon lake PCH BIOS specification document #570374
target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2.

BUG=None
TEST=None

Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kin Wai Ng <nelsonaquik@gmail.com>

Update Power Limit1 and Power Limit2 values along with stepsize.
Correct the charger effect for Temperature sensor2.

BUG=b:112448519
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Grunt variants need a way to customize the mainboard vendor based on the
platform.  For future boards, this can probably be done via CBI, but
grunt doesn't support that method.

BUG=b:79874904
TEST=Build, boot, see updated mainboard vendor

Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/28651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@google.com>

Change GPP_D17 and GPP_D18 to no connects as DMIC was moved
to DMIC0.

BUG=b:113744731,b:111106010
TEST=none

Change-Id: I8ef42627e542182707c81389af9da33a114bc184
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28689
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Set up EC_IN_RW GPIO to boot depthcharge. Without this patch,
depthcharge will fail to tell if the EC firmware is RW.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
     EC_IN_RW GPIO.

Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This included the microcode for some CPUID's found in
soc/intel/skylake/bootblock/report_platform.c (others are likely pre-release
SKU's)

The amount of FIT entries needed is currently 7 so setting
CPU_INTEL_NUM_FIT_ENTRIES is set to a safe 10 will be able to fit them all.

Change-Id: I3ba504a07b2697fe55ff8f28a934f761ae05a4ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Use of device_t is deprecated.

Change-Id: If52de0d87b02419090b29a7cf1952905d3f975f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28691
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Use of device_t is deprecated.

Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

Use of device_t is deprecated.

Change-Id: Ifd1471a9cd76d2cea72262ed81b7071f31f7b375
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

Use of device_t is deprecated.

Change-Id: I70dcefd5bc9864931f66bece1f044f806f5d7ae0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Fix warning from list in table cells for nri_registers.md

Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/28354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Use of device_t is deprecated.

Change-Id: I9364c9681dd89f09480368a997f6d1f04cde1488
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

Use of device_t is deprecated.

Change-Id: I8790bc333caa367ef46bf80b5fecc3e90ef89ca0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Use of device_t is deprecated.

Change-Id: Ia50aa96901b979b947fd4d269b077814c06f60c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28677
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Use of device_t is deprecated.

Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

No support for SoC D-1 stepping is available.

According to Intel doc #332095-015 stepping C-0 has revision
id 0x21 and D-1 revision ID 0x35.

Also correct the RID_C_STEPPING_START value for C-0.

BUG=none
TEST=Built, Intel Cherry Hill Rev F.

Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27471
Reviewed-by: Wim Vervoorn
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Use of device_t is deprecated.

Change-Id: I9dde92314af8ef87a5acb550f0fb25b8ce875174
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>