Make sure that the Pre-Op register is cleared when an atomic cycle has
been finished without errors.

Change-Id: Ied88337125b125474b411e2f39f668171d15bfac
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

Add ability to define a reset gpio in acpi for a USB device.

BUG=b:119275094

Change-Id: Ife3ea43a1eadf2548aa52b8fbd792e691d7cc7f2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajat Jain <rajatja@google.com>

Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.

This change produces the following nodes in the SSDT :
    Scope (\_SB.PCI0.XHCI.RHUB.HS01)
    {
        Name (_DDN, "USB Type C Port 1")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0x09,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x1,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "OVAL",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
    }

    Scope (\_SB.PCI0.XHCI.RHUB.HS03)
    {
        Name (_DDN, "Bluetooth")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0xFF,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x0,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "UNKNOWN",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
        {
            GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
                "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
                )
                {   // Pin list
                    0x0062
                }
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
            Package (0x01)
            {
                Package (0x02)
                {
                    "reset-gpio",
                    Package (0x04)
                    {
                        \_SB.PCI0.XHCI.RHUB.HS03,
                        Zero,
                        Zero,
                        One
                    }
                }
            }
        })
    }

    Scope (\_SB.PCI0.XHCI.RHUB.HS05)
    {
        Name (_DDN, "USB Type C Port 2")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0x09,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x1,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "OVAL",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
    }

    Scope (\_SB.PCI0.XHCI.RHUB.HS07)
    {
        Name (_DDN, "POGO")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0xFF,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x0,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "UNKNOWN",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
    }

BUG=b:119275094
TEST=build and flash to nocturne, log into nocturne and
'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy
that ssdt.dsml to /tmp/ssdt.dml on host machine,
'iasl -d /tmp/ssdt.dml', then verify that "reset gpio"
shows up in the HS03 node's _DSD package in the table.

Change-Id: I65d9b580fd69fd0a2c84f14b78a8e8b5e9217b16
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajat Jain <rajatja@google.com>

The GPT version must be "00 00 01 00" and the little endian should be
represented as 0x10000.

Please refer to: https://en.wikipedia.org/wiki/GUID_Partition_Table

Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/29767
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

SeaBIOS 1.12.0 has been tagged. News are

* Initial support for "TPM CRB" hardware
* Improved cdrom media reporting in the boot menu on QEMU
* Improved floppy support on real floppy hardware
* SeaVGABIOS support for QEMU "bochs-display" and QEMU "ramfb" displays
* Several bug fixes and code cleanups

among others, see http://seabios.org/Releases

Tested by running it on a Thinkpad X230.

Change-Id: I5f8364977ce957d3e8d84d7b046d1cec36b8da6a
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/29724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

…Init()

Returned status code FspTempRamInit() is not displayed when error occurs.
Move the printk() call before the check for status.

BUG=NA
TEST=Portwell PQ7-M107

Change-Id: Id87e5c765d09f4ab199db9eba07a949b031a709a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29695
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

CONFIG_FSP_USES_UPD is not used by FSP 1.1.
Remove this config from this file.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: If922b6cb2d39b10f6657b4d80e54b226d1386c76
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>

Header contains ':' in copyright line. rmdoule is a typo
Remove the ';' and correct typo to rmodule.

BUG=N/A
TEST=N/A

Change-Id: I05b1fb80a81682646c9fba3d234de235b6bc9e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

soc/car_setup.S is included when SKIP_FSP_CAR is enabled,
but no chipset/SoC have car_setup.S available.
Remove include and post_code() call always solving build errors.

BUG=NA
TEST=NA

Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>

We need to default this to low so the speakers don't activate in S3.

BUG=b:118248953
TEST=Used a scope to look at the line and made sure depthcharge still
beeps.

Change-Id: I70d2f4a3261d212b62e784fa7414e45b1d575612
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29783
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

There is already a function with the name buffer_size(). Adding a local
variable with the same name will lead to the following error on older
GCC versions (e.g. version 4.4.7):

declaration of 'buffer_size' shadows a global declaration

To fix this rename the local variable to buffer_len.

Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

This implementation adds eSPI IO decode range for EC.
1. 0x800-0x8FF / 0x200-020F: EC host command range.
2. 0x900-0x9ff: EC memory map range.

Change-Id: I69e6b3a83c072036c5b3ae801f8d80dfda82478e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>

List of ICL board variants

1. ICL-U
    DDR4 - All possible DDR4 memory type
    LPDDR4 - Memory down fixed DIMM configuration

2. ICL-Y
    All LPDDR4 DIMM on platform

This patch ensures to have all proper SPD configuration.

Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>

BUG:none
TEST:Verify cursor response and button clicks

Change-Id: I4085b70560e2840c71b989348f56ca907e7cea4b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29777
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.

To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.

If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.

Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Gather x86 specific debug options and deflate their code a little. We
keep their hiding rules and help texts, although they don't seem much
useful.

Change-Id: I3bb8e759fc6a4871d30fccff47babfb7a291b45c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29751
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

No need to hide prompts, it's a user choice anyway, they should know.
The help texts were just rephrasing the prompts or stating the obvious.

Change-Id: I5694a88f2da57af2a20357c4e22c7c648053cc26
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29802
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Iae87a2e6f223f1d6e39034be4c8b511187eca6f5
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/29782
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: If8f662d088bf57fd27c5a01a47bc094dcb53a4de
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29806
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".

Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian

Provide a library function to set the CPU frequency to minimum
value. This will result in the lowest possible CPU clock with
the lowest possible power consumption. This can be useful in mobile
devices where the power dissipation is limited.

This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to it's need.

Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

Add a Kconfig switch to be able to set the CPU clock to the lowest
possible ratio. If enabled the CPU will consume as little power as
possible while providing the lowest performance.

This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to its need.

Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

The power budget for this mainboard is very limited while the
performance demand is low. Set the CPU clock to the lowest value to
enable maximum efficiency and thus lowest power dissipation.

Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

The mentioned bits 14:8 are wrong as the functions always write
bits 15:8. What happens is visible in the written code. There is no need
for an extra comment.

Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

According to newest TCG ACPI Specification for Family 1.2 and 2.0
Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA.

Update the table structure definition, create the log area for TPM2 in
coreboot tables and fill the missing fields in TPM2 table. TPM2 should be
now probed well in SeaBIOS rel-1.12.0 or master.

Tested on apu2 with Infineon SLB9665 TT2.0.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/29800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

It's not implemented for Skylake, all combinations that try to enable it
either result in Kconfig or linker errors.

Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's
effective.

TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default
     configs with and without this patch: binaries stay the same.

Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

The GPIO and ACPI base sizes have defines, but they are not used.
Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.

BUG=N/A
TEST=Intel BayTrail CRB

Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Huang Jin <huang.jin@intel.com>

The GPIO and ACPI base sizes have defines, but they are not used.
Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I348eda57ab9dc0bd45f8dc9ab0e7c47c462102fe
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29788
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Iad60a5c8863283b7d373e1f6aaff48c40b7bb274
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

CBFS used to have a special region for the x86 bootblock, which also
contained a pointer to a CBFS master header, which describes the
layout of the CBFS.

Since we adopted other architectures, we got rid of the bootblock region
as a separate entity and add the x86 bootblock as a CBFS file now.

The master header still exists for compatibility with old cbfstool
versions, but it's neatly wrapped in either the bootblock file or in a
file carefully crafted at the right location (on all other architectures).

All the layout information we need is now available from FMAP, a core
part of a contemporary coreboot image, even on x86, so we can just use
the generic master header locator in src/lib/cbfs.c and get rid of the
special version.

Among the advantages: the x86 header locator reduced the size of the
CBFS by 64 bytes assuming that there's the bootblock region of at least
that size - this breaks assumptions elsewhere (eg. when walking CBFS in
cbfs_boot_locate() because the last file, the bootblock, will exceed the
CBFS region as seen by coreboot (since it's CBFS - 64bytes).

TEST=emulation/qemu-q35 still boots

Change-Id: I6fa78073ee4015d7769ed588dc67f9b019d42d07
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

Change the board id detection to support rev5, since the 2T mode still
needed in DVT build.

BUG=b:116082728
TEST=verify by ODM.

Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

Remove whitespace between the function name and open
parenthesis, and fix 81+ characters lines.
Unnecessary comment about 'include sandybridge.h'removed.

Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29428
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The semantics in util/scripts/maintainers.go have changed in that a
file can be part of multiple components. This means that all files
are part of "the rest" now, which doesn't make much sense.

Change-Id: I220afe27e78aa5358fca61851242812f2d763992
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29657
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

It's not useful anymore.

Change-Id: Iba7f10dc87301911ff5f73c182b41c268fba310a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29658
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Ic12a8c145d6348086f9931af93ce6d3b3dcb9039
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

This bug/typo was spoted by Felix Held.
As documented in the datasheet, to enable PMEGPE, HPGPE, GENGPE, we need
to write 0x7 into DEV(0:01.0) register "PCI Express-G Legacy Control"
located at 0xec.
Used address at 0x114 to enable GPEs is likely a typo.

Patch not tested.

Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/27307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

Some registers are not documented in "Mobile Intel 945 Express
Chipset Family" datasheet but they are in "Intel 945G/945GZ/
945GC/945P/945PL Express Chipset Family" datasheet.

Change-Id: I81f68a5b16e195626d4d271f8c7036032611bea3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I0559b8a546f7a67759377c7f51b2faa2280aa797
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29793
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

An additional read of PTN configuration data at the end of the
ptn3460_init function is not necessary.

Change-Id: I5f7f647242e94b1af13757d00e80ed9813d435d0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

One common issue with the toolchain is that it takes a very long time
to build while it's somewhat volatile inside the coreboot tree.

Installing the toolchain elsewhere helps keep it safe but since there
is no reliable default location outside the tree, keep the default
as is.

Change-Id: Ic414cddfd3c7097412f3f2c3c7ec7b7191fa32de
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

Missing hob 7.3 FSP_NON_VOLATILE_STORAGE_HOB is reported always.
This hob is only generated by FSP during non-S3 and MRC data is changed.
Now display missing FSP_NON_VOLATILE_STORAGE_HOB only when this hob is
required.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>

Change-Id: I36de9ba6c5967dddd08a71a522cf680d6e146fae
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/c/28347
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I4e5fe3ff083f2d0db1cfde16550b57537d5f7262
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/c/28349
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Ife8f7f164b26bea65a0dcde0cab339a1bb599e38
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan T <stefan.tauner@gmx.at>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

This patch add new HDA controller pci id in common hda driver.

BUG:None
TEST:Boot to Yocto linux on kabylake rvp11 and verified audio
     playback functionality.

Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I820115c31bf6b8e1f1afe900b68690d84b51c259
Reviewed-on: https://review.coreboot.org/c/29807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

PL4 is a preemptive CPU package peak power limit,it will never be exceeded.
Power is preemptively lowered before limit is reached.

This change provides option in devicetree and feeds FSP PowerLimit4 UPD for
power limit purpose.

Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8
Reviewed-on: https://review.coreboot.org/c/29808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

This mainboard has four connected PCIe devices. The required root ports
are switched on and configured.

Change-Id: I82b13e1d245a172762ebd689ae136a762027033f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29810
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Correct typo of 'compilation'

BUG=N/A
TEST=N/A

Change-Id: Iee6b8a8afc4d885d2d4ab9ee5d596e32e5e6d3f1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

This implementation adds USB port capablity map for ICL-U and ICL-Y
RVP.

Change-Id: I20bb43c47439df0a25ff148eae2b3e0546e4bc63
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

This change configures all the pads going to debug header as not
connected.

BUG=b:111569213
BRANCH=None
TEST=None

Change-Id: Ie3ffdbf6ad9b1682deaada91b5c225b4c8dd035b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>