Disable xHCI by default if USE_BLOBS option has not been selected.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I1c3f0ff49fbe3db3ef095d99055f75d65cd6f661
Reviewed-on: https://review.coreboot.org/c/31216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1) In the EC _REG method set the flag indicating S0ix support in the OS.

2) Add a function that can be called by the LPI _DSM method to indicate
to the EC that the OS is entering or exiting S0ix.

BUG=b:73137291

Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31094
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add a separate ACPI device for the Wilco EC event interface so that the
OS drivers can bind to it separately.  Since the event handling is all
done with ACPI and not mailbox calls this will be implemented as a
standard acpi_driver in the kernel.

BUG=b:119046283
TEST=veriy device exists in DSDT

Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

AGESA doesn't detect invalid NV data during AmdInitResume(). In
cases where the data has been erased, or cannot be found, reboot
the system.  Otherwise the user will experience a hang when cbmem
isn't recovered and the postcar frame cannot be initialized.

BUG=b:122725586
TEST=Write S3 NV save data with 0xff and force reboot

Change-Id: Ib3cf2515f300decd3de198f7741660d95ee4c744
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

This implementation adds support to create ACPI package for USB port
capability (_UPC) and physical location of device (_PLD) for USB2 port 10.

BUG🅱️123375275
TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10
     in SSDT and BT is functional in discrete and integrated mode.

Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

GLK has a dedicated USB2 port that is used specifically for CNVi
BT. This requires that the ACPI tables define an additional USB 2 port
which results in _ADR for USB 3 ports being different for GLK than
APL.

This change splits the ports in xhci.asl into APL and GLK specific
ports.asl and selects the appropriate file based on
CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK
if ACPI name is requested for that port.

BUG=b:123670712
BRANCH=octopus
TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and
for reef (APL) does not include HS09 definition.

Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31172
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This change enables exporting the reset GPIO for CNVi Bluetooth module to
the kernel for use in an rf-kill operation.

BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.

Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

The FSP has a parameter to enable or disable the VTD feature
(Intel's Virtualization Technology for Directed I/O). In current header
files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to
disabled per default. Therefore, if the FSP was not modified via BCT,
this feature is most likely disabled on all mainboards.

Add a chip parameter so that VTD can be enabled on mainboard level in
devicetree and therefore this feature can be activated if needed.

Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31194
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

These boards need a working VTD therefore enable this feature.

Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

Remove memory mapped copy of the file list to use it also in romstage.
fw_cfg_find_file searches directly for the file on data port.

Change-Id: Ie97ed3f0c98a5bb18a35ab0eaf8c4777a53e5779
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Qemu provides e820 table at fw_cfg interface. Add functions to access it.

Change-Id: I547bc7fef09999baa28149a6325cbca91e31e99b
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Change-Id: I98f1c97e3ca33a12620cdd073c76fd4e271f1fcc
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Use memory map from fw_cfg e820 map to find cbmem_top in romstage to
avoid conflicts with CMOS option table. Keep qemu_gwt_memory_size() as
fallback.

Change-Id: I6465085020125fc790257f09eb157030c6ceabcb
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Use unsigned long to prevent sign overflow.
Fixes wrong MTRRs settings on x86_64 romstage.

Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1
Reviewed-on: https://review.coreboot.org/c/30502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

The default value for Chrome OS HWID should be different.
Calculated as HWID v1.

BUG=b:123336677
BRANCH=kukui
TEST=build and boots properly.

Change-Id: I39c640562c1c3b117292b8abacd36a4a9c2fa6c6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>

This reverts commit 7696290.

We're seeing trackpad problems on some units with the I2C bus running
at 1MHz but not at 400KHz.  So, revert back to 400KHz until we
understand how to make 1MHz operation more robust.

BUG=b:123650686

Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

This reconfigures the GPP_D1 GPIO pin as a no-connect.  It really
doesn't go anywhere today or on previous revs of the board.

BUG=b:110614620
BRANCH=none
TEST=atlas still boots

Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: Idfe93e454cc0ce0d8e06e23beaddee2f11f5eedd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31199
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

By APL BIOS Spec, we must not do this on warm boots.

The TODO comment seems stale and copied over. So the actual
requirements for SGX are unknown and we add a guard for that
case.

Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31200
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The default state of the HOSTSW_OWN register in the PCH is zero, which
configures GPIO pins for ACPI ownership.  The board variabt GPIO tables
can request specific pins to be configured for GPIO driver ownership.
This change sets the HOSTSW_OWN ownership bit when requested and
explicitly clears the ownership bit if not requested.

BUG=b:120884290
BRANCH=none
TEST=Build coreboot on sarien.  Verified UEFI to coreboot transition
boots successfully.

Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

The allocation is not required before romstage,
so it can be just another CAR_GLOBAL instead of
polluting the linker script.

Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31191
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This change adds keyboard backlight feature for Hatch platform.

BUG=b:122799544
BRANCH=none
TEST=keyboard backlight works when EC reports correct info.

Change-Id: I29273122f061e0e442f6629351ef3670535c0507
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31175
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

If an acpi_dp table has children but no properties then acpi_dp_write()
will write out a properties UUID and package that contains no properties.
The existing function will avoid writing out a UUID and empty package
when no children exist, but it seems to assume that properties will
always be used.  With this change properties are handled in a manner
akin to children so that a UUID and package are only written if
properties exist.

BUG=none
BRANCH=none
TEST=Confirmed that prior to this change a UUID and empty package was
present for a device that had children but no properties.  Verified that
after this change the UUID and empty package are no longer present but
the child UUID and package are still present.

Change-Id: I6f5597713a1e91ca26b409f36b3ff9eb90a010af
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

The ACPI spec has an asl example for _PLD in the form:

Name (_PLD, Package (0x01) { ToPLD (PLD_Revision = 0x2) })

When I ported this to acpigen and diffed the results I noticed that
the binary blob was no longer provided within a package.  The ACPI
spec (section 6.1.8 in version 6.2) defines _PLD as "a variable-length
Package containing a list of Buffers".  This commit changes
acpigen_write_pld to use a package (the one existing caller I found
isn't wrapping the result in a package so it doesn't look like
it was intended for the callers of acpigen_write_pld to be responsible
for using a package.

BUG=none
BRANCH=none
TEST=Verified that after this change a package is use and the result
of acpigen matches what was used in the original asl.

Change-Id: Ie2db63c976100109bfe976553e52565fb2d2d9df
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

After CL:31122, we can finally define a memory type specific for BL31,
to make sure BL31 is not loaded on other reserved area.

Change-Id: Idbd9a7fe4b12af23de1519892936d8d88a000e2c
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://review.coreboot.org/c/31123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

These are more common system types and in some cases it is important
to know when a device is a convertible or a tablet or detachable
instead of just a laptop.

This change will select the appropriate SMBIOS enclosure type based
on the selected system type.

This is important for the Intel Virtual Button driver as it does a
check on the SMBIOS enclosure type and only enables the tablet mode
events if it is set to convertible:
https://patchwork.kernel.org/patch/10236253/

Change-Id: I148ec2329a1dd38ad55c60ba277a514c66376fcc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Add an ACPI device that is compatible with the Intel Virtual
Button kernel driver for reporting tablet mode state and various
virtual button events that may come from the EC.

This driver is used in Windows and in the Linux kernel at
drivers/platform/x86/intel-vbtn.c

Because of a check in the kernel driver it expects the board to
define the SMBIOS enclosure type as convertible for the check at
driver load time for tablet/laptop and dock/undock to work.

The virtual tablet mode button will proxy the tablet mode state
sent from the Sensor Hub to a SW_TABLET_MODE event in the kernel.

The virtual power button is used during S0ix for the EC to wake
the system with an SCI.  There are separate press and release
events which are sent for completeness, although the kernel driver
will ignore the release event.

BUG=b:73137291
TEST=Test that the power button can wake the system from S0ix.
Also verify that the device is reported as laptop mode at boot.

Change-Id: I0d5dc985a3cfb1d01ff164c4e67f17e6b1cdd619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31208
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Select the appropriate system type for the different variants of
the Sarien board.

This will allow the Arcada variant to use the tablet mode feature
of the Intel Virtual Button driver.

Change-Id: I8a829aab012256ec196c8ec0fa298fd2bc77f2e1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>

It's what the doc.coreboot.org docker container is running and when
using its livehtml feature, it listens at localhost, which isn't always
desirable.

With `docker run -e SPHINXOPTS="-H $localip" ...` it now listens at
localip, which is more flexible.

Change-Id: Ia0614e57458c32169f6d614783366025e9c814b3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31128
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Neither payloads nor distributors are an integral part of the coreboot
source tree, but they're very important parts of the coreboot
ecosystems, so add some descriptions.

Change-Id: Id64744c252b6b78c4811fbded48c441ef486ad94
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Get some content on the documentation site's front page.

Change-Id: I7f36234ef783e041a44590858bb75a69b96ee668
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

This patch ensures to select chromeos kconfig only for required
CFL-U and WHL-U RVPs supported by Intel client team.

TEST=Ensure CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY is only selected
for CFL-U and WHL-U boards.

Change-Id: Ib61409402a948f8d5f91130e200c45320ea13d3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31214
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

We already had such a page on the wiki, but it's outdated and the wiki
is supposed to go the way of the dodo anyway.

This is a fresh start to make sure that all ideas we're coming up with
are still current and that there are mentors willing to support them.

Change-Id: Idd68f845930bd37a2293969b9a153cf584d6d15f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30972
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

his either sets unwanted or unnecessary settings.

Also this RCBA replay did not even originate from the T400 as this
code was copied from the Thinkpad x200 code on which this replay was
already removed in 7bcd062 'mb/lenovo/x200: Remove RCBA replay'

Change-Id: Iac6846d43395e342897e03c1ad31387638bcac64
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Change-Id: I1e9a165b722006557557058a14e9f5dac78d4538
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Change-Id: I2057bf66435fd9113cdb1eef4c273f66b07a5a79
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Some settings don't make sense like specifying input/output on native
ports or high/low on input ports.

Change-Id: Ib37837b9cdb8bb05e2523e0c43cc71fe4fbf243b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31187
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This moves a lot of the common romstage boilerplate code to a common
location, while adding a few mainboard specific hooks.

Another difference is that the settings for enable_igd and enable_peg
are now based on the static devicetree settings.

Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

- improve descriptions of Purism and ChromeOS hardware
- add entry for Libretrend Librebox
- improve description of Mr Chromebox and John Lewis'
  3rd party ChromeOS firmware offerings

Change-Id: I66bd1a3701091e499d88738a7c06126de66e58ff
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

We generate a $(obj)/cb-config.ads once and copy it per stage that uses
it to $(obj)/<stage>/cb-config.ads (to simplify the gnat-bind step). The
Ada package is called `CB.Config`. As there was no `CB` package yet, add
that too.

Change-Id: I963a6517ef4bcf84f2c8e9ae8d24a0d6b971d2b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Add maximum width and height options and set the default to 2560x1600
(WQXGA). The framebuffer will be scaled up to the displays' native
resolutions. So this should help with tiny fonts on high-DPI displays.

For laptops, reasonable defaults can be set at the mainboard level.

Change-Id: I47fba063629260c3a2854caf7a73f1a1e933d063
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Current coreboot size is not adequate for adding new features.

Note for cros: This change is for merge to ToT only and should not be
cherry-picked into reef's firmware branch.

BUG=chromium:903833
TEST=emerge-reef coreboot

Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

This change enables I2C bus 2, 3 and 4 in devicetree and configures
GPIO pads for the same. It also configures pads for I2C5 as
no-connect.

BUG=b:123711244
TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS.

Change-Id: Ib4714a670d73228332115415e4393f82802c6475
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31237
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Put the FMAP FMAP region right above the coreboot CBFS region.
The other regions like RW_MRC_CACHE and CONSOLE often have alignment
requirements so it makes sense to put those on top. This also
simplifies the code the generate the default fmap a little.

Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30419
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

If a non aligned CONFIG_CBFS_SIZE is used the region RW_MRC_CACHE and
CONSOLE could end up non aligned. Currently this is only possible if
the user messes with CONFIG_CBFS_SIZE in menuconfig, but better be
safe than sorry.

Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30420
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

This patch performs below tasks

1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.

2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.

3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.

* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC

4. Add correct FSP blobs path for WHL SoC based designs.

Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

FSP-S is currently configuring GPIOs that it should not. This results
in issues where mainboard devices don't behave as expected e.g. host
unable to receive TPM interrupts as the pad for the interrupt is
re-configured as something else.

Until FSP-S is fixed, this change adds a workaround by reconfiguring
GPIOs after FSP-S is run.

All mainboards need to call cnl_configure_pads instead of
gpio_configure_pads so that SoC code can maintain a reference to the
GPIO table and use that to re-configure GPIOs after FSP-S is run.

BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.

Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.

BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.

Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>