Some of the values used for GPIO_CFG and MISCCFG were not correct,
causing GPEs to not work correctly. This adjusts them according to the
values found in the original ACPI tables for the System76 Gazelle.

Unfortunately, the Intel documentation[1] mentioned below is
also incorrect. I have mentioned this to Intel already. The source
for the Intel CoffeeLake FSP also confirms these new numbers.

This was tested on a System76 Gazelle (gaze14). The EC uses GPP_K3 for
its GPE and GPP_K6 is used for the lid switch GPE. Both function
correctly after applying this change.

[1] Intel Document #572235:
    Intel ® 300 Series Chipset Families
    Platform Controller Hub
    External Design Specification (EDS) - Volume 2 of 2

Change-Id: I4ecc9552468037598ef5d4e10122d660dcbfe71d
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

…idth

As per EDS Sata port implemented register is byte width (bits[3:0]) hence
converting required DWORD based read/write to BYTE width read/write.

TEST=Able to boot from SATA device on CML hatch.

Change-Id: I545b823318bae461137d41a4490117eba7c87330
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34070
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix
*** Pre-CBMEM romstage console overflowed, log truncated! ***
issue.

TEST=Verified on Hatch CML platform.

Change-Id: I2de4ca2f2001b304850c27df1b3c3b2c827fe25a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Spoorthi K
Reviewed-by: Nico Huber <nico.h@gmx.de>

outb accepts a value followed by a port

Change-Id: I6fe3961b4f8cb2454e3b2564c3eae6af06c9e69d
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33940
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

When system shuts down, RTC enable eosc calibration feature to save
power. Then coreboot RTC driver needs to call rtc_enable_dcxo function
at every boot to switch RTC clock source to dcxo.

BUG=b:128467245
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

Family 17h will not use the Arch2008 (a.k.a. v5) wrapper.  Remove
all source, support functions, and comments related to AGESA.

Family 17h requires v9 which has no similarities to v5 for
integration into a host firmware.  AGESA v9 support will be added
via subsequent patches into the appropriate locations.

Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>

Similar to CB:33940, fix outb orders.

Change-Id: I1d35235abc7e02e6058f07809b738635861cc9e4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jackpot51@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

We have 3 similar Lenovo mainboards - x60 (oldest), t60, and z61t (most
recent addition). The only one with two consequent 2s as the C-types
is t60:

static acpi_cstate_t cst_entries[] = {
       { 1,  1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
       { 2,  1,  500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
       { 2, 17,  250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
};

It seems that 3 could be a better choice for the last line here.

UNTESTED on a real hardware.

Change-Id: I090e82d5f4ae25c768ff45a01a8dd76ff8a96a90
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

fms() and fls() returns an 'unsigned int'.

Change-Id: Ia328e1e5a79c2e7606961bb1b68c01db6b77da21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33817
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets
removed from the root bus as leftover unused device. With change
903b40a ("soc/intel: Replace uses of dev_find_slot()"), all uses
of dev_find_slot() were replaced by pcidev_path_on_root() which relies
on scanning of root bus to find the requested device. Since PMC device
is removed from the root bus, pcidev_path_on_root() returns NULL for
it thus resulting in configuration being skipped for the PMC
ultimately resulting in S3 failures.

Since the PCH_DEV_PMC was just used to get to chip config, this change
replaces the use of PCH_DEV_PMC with SA_DEV_ROOT.

BUG=b:136861224
TEST=Verified that S3 works fine on hatch.

Change-Id: Ie5ade00ac2aca697608f1bdea9764b71c26e2112
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

This change gets rid of unused dev param to pmc_set_afterg3.

BUG=b:136861224

Change-Id: Ic197d6fb8618db15601096f5815e82efc2b539c1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets
removed from the root bus as leftover unused device. With change
903b40a ("soc/intel: Replace uses of dev_find_slot()"), all uses
of dev_find_slot() were replaced by pcidev_path_on_root() which relies
on scanning of root bus to find the requested device. Since PMC device
is removed from the root bus, pcidev_path_on_root() returns NULL for
it thus resulting in configuration being skipped for the PMC
ultimately resulting in S3 failures.

Since the PCH_DEV_PMC was just used to get to chip config, this
change replaces the use of PCH_DEV_PMC with SA_DEV_ROOT.

BUG=b:136861224

Change-Id: Id68db8382b7b98e8e2e4a65ded1a6fb3bd057051
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

This change gets rid of unused dev param to pmc_set_afterg3.

BUG=b:136861224

Change-Id: I861bb132acf113c9d306175b670bf4a1ff742c28
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

This change intentionally removes the definition of PCH_DEV_PMC from
ramstage to avoid silent errors. This device gets hidden from PCI bus
in FSP-S and hence dropped from the root bus by the resource
allocator. In order to avoid incorrect references to the device, avoid
defining it in ramstage where it known to return NULL.

BUG=b:136861224

Change-Id: I4f69470ec80c7127a2b604ed2b1f794f5a63e126
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34120
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

While common to many Intel CPUs, this is not an architectural
MSR that should be globally defined for all x86.

Change-Id: Ibeed022dc2ba2e90f71511f9bd2640a7cafa5292
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian

G505S doesn't have any SAS or NVMe controllers and couldn't have a TPM,
so it makes sense to disable the related SeaBIOS options for this board.
This reduces the size of compiled SeaBIOS by 129344-110048=19296 bytes.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ib0183b7786ecd77bb0df923bc84908275f2fe14c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33870
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Ibddc2363e9bfea9ae41e4807435acb2e788dcb93
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Enable eMMC support for kindred.

Cq-Depend: chromium:1666982
BUG=b:135464155
BRANCH=none
TEST=Boot kindred onboard eMMC.

Change-Id: I040af6da30313f8dd59e3ef910b290922e090cdc
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33618
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

…ouchpad

Update ELAN GPIO and IRQ setting and add Synaptics Touchpad

BUG=b:132708463
BRANCH=None
TEST=Verify ELAN/Synaptics touchpad is working fine.

Change-Id: I883ce2e50ca5c6bd2b1ca76cbe24177055cc5d60
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

Add Raydium controller

BUG=b:135728282
BRANCH=master
TEST=
1. FW_NAME="kindred" emerge-hatch coreboot chromeos-bootimage
2. boot up on kindred DUT to check touchscreen device by evtest
   /dev/input/event3:	Raydium Touchscreen
3. Raydium TS is working

Change-Id: Id963300ab0dadcb78786c5a1328c2a4098a48a05
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33857
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This code is currently only used by via/epia-m850,
it is also somewhat buggy.

Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This is used a lot, cache the result so search
of domain from devicetree is only done once.

Improvement only applies when MAYBE_STATIC evaluates
to static.

Change-Id: If675abb632fe68acd59ba0bdfef854da3e0839a9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

This config option, when set, will allow the platform to skip display
initialization in normal (non-developer, non-recovery) mode. This allows
platforms that do not implement firmware UI in normal mode to skip the
display init in firmware.

TEST=Set option CONFIG_VBOOT and clear CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT
     and the display should initialize in ramstage when platform boots. Set
     CONFIG_VBOOT and set CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display
     initialization should be skipped in coreboot.

Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar@intel.com>
Change-Id: Icadad6da34dcb817af02868e89a94ea62dbfa7b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

This function executes the cpuid instruction, which takes a 32 bit input
value (idx), and then stores output in eax, ebx, ecx, and edx, which are
all 32 bit registers. Update the prototype to use fixed-width integers,
and update all usage calls appropriately.

Change-Id: I15876fa35628d3a505864fb49be4fdab1fd19f4a
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

Make sure that the type of the loop index matches the type of the upper
bound. This fixes several -Wsign-compare warnings.

Change-Id: I73a88355d86288609e03f7a6fcaec14dfedac203
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

This enables extra useful warnings.

Change-Id: I3d54988935c7df9ac0dc2f7aceb56fb720c9c4d1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

These functions are only used in the files they are defined in, so they
can be made static.

Change-Id: Ic7f78912803cbdd1cb3a75f7f69f526739dab6e7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

Change-Id: I7ee9436ba71ceea35a35272291ea245c0b7c37c5
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

None of these functions are used outside of the files they are defined
in, so they can all be static.

Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

Change-Id: I6bf041d089498780ea2b7c52402d7452d44d3f87
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33946
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The removed call was there to support case LATE_CBMEM_INIT=y,
HAVE_ACPI_RESUME=y. Same stack space is already allocated
with postcar_frame_init() call.

Change-Id: I03a44bc3252f553b1769d362b2f442d3e6ab73f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

size_t is the wrong type to store the return value of
acpi_device_path_fill(), since any negative error values will be
converted to a very large unsigned integer and potentially cause
buffer overflow.

Change-Id: Ia8ed62ecfac8eaa18a61545bd203b3c7a7cd9ca5
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

The prototype for is_ident() is in this header, so include it.

Change-Id: I45e0d58d1b891b18b3eb7741897ab691188a2bd9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

This function is only used in this file, so it can be made static.

Change-Id: I90e673da91eb926424d1730c268860da7fa1627b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

Change-Id: Id751250b07a495dc25293ff703602bfefa9011bd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

This silences several false positives from scan-build.

Change-Id: I327a967c75d6aeec0b3aba16ee696dbae8cf997d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>

Considering the following integer multiplication:

    u64 = u16 * u16

What on earth, one might wonder, is the problem with this? Well, due to
C's unfortunately abstruse integer semantics, both u16's are implicitly
converted to int before the multiplication, which cannot hold
all possible values of a u16 * u16. Even worse, after overflow the
intermediate result will be a negative number, which during the
conversion to a u64 will be sign-extended to a huge integer. Not good.

The solution is to manually cast one of the u16 to a u32 or u64, which
are large enough to not have any overflow and will prevent the implicit
conversion. The type of the u64 is preferred, though a u32 is used
instead of size_t, since that can change depending on the platform.

Change-Id: I5391221d46d620d0e5bd629e2f9680be7a53342e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 12297{03,04,05,06,07,08,09,10}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Also don't define the default as this result in spurious lines in the
.config.

TEST: The generated config.h remain exactly the same for all boards.

Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>

DCXO consists of core that generates clock and output buffers that
provide clock to other peripheral components.
This patch mainly eliminates the extra power consumption of output buffers.
We only enable the buffer for SOC and disable unused buffers for power-saving.
Also disable useless buffer power mode to guarantee the lowest power state.

BRANCH=none
TEST=Boots correctly on Kukui.

Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32323
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

After platforms have moved to POSTCAR_STAGE=y the only
remaining user is binaryPI now. Make it simpler.

Change-Id: Ia70c5c85e06c42f965fb7204b633db9b619e2e84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

This patch updates the following GPIO settings.
1. Set Native termination for GPP_G0 - G4 SD card pins.
2. Set GPP_B19 to NF1.

BUG=b:123907904
TEST=Verified SD card functionality on hatch. Checked for SD detection,
transferred files to and from SD card.

Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

increase reset off delay time

Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX
dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power
sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement.

BUG=b:135287161
BRANCH=None
TEST=local build and measure sequence with Goodix touch screen

Change-Id: I33140869990aa4715c780b0fa322921e450530ef
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The memtest86plus project has been tagged as stable. Update the coreboot
build accordingly.

Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>

No longer fallback to UDELAY_IO as default.
Since these are not cpu properties or features,
move the Kconfig location.

Change-Id: I9809cdc285c7bf741aa391ddb5755390bbfc2909
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Ib61ea29724401146eb6f008374cdf599f418e81f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

Change-Id: I240e9e767c9b38b3b06d3978fd20ddb37a96e470
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

Change-Id: Ib7f2f7773d0eef5ac4e277b44ee9114aa6729527
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: I3ca2b7752905209e8db6b1dc74b930445676792e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

The QEMU machine "PC" doesn't support MCFG.
Die after console init if the user selected the wrong qemu machine
and print a message to use the correct machine type.

Without this patch ramstage dies with non-helpful message:
"get_pbus: dev is NULL!"

Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Spotted out using -Wconversion gcc warning option.

Change-Id: Ib882cfa6d429fbfcab2b8132280182b427d510aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>