CHANGELOG.md

@@ -8,6 +8,14 @@ Releases 4.5.x are based on mainline support submitted in
 
 ## [Unreleased]
 
+## [v4.0.11] - 2017-07-21
+### Added
+- Allow to force GPP3 PCIe CLK attached to mPCIe2 slot based on
+  [sortbootorder option](https://github.com/pcengines/sortbootorder/blob/master/README.md#settings-description)
+
+### Changed
+- updated sortbootorder to v4.5.7
+
 ## [v4.0.10] - 2017-06-30
 ### Added
 - added sortbootorder to option menu
@@ -102,7 +110,8 @@ Releases 4.5.x are based on mainline support submitted in
 - forced to use SD in 2.0 mode
 - git repository in `Makefile`
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.10...coreboot-4.0.x
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.11...coreboot-4.0.x
+[v4.0.11]: https://github.com/pcengines/coreboot/compare/v4.0.10...v4.0.11
 [v4.0.10]: https://github.com/pcengines/coreboot/compare/v4.0.9...v4.0.10
 [v4.0.9]: https://github.com/pcengines/coreboot/compare/v4.0.8...v4.0.9
 [v4.0.8]: https://github.com/pcengines/coreboot/compare/v4.0.7.2...v4.0.8

src/mainboard/pcengines/apu2/bios_knobs.c

@@ -168,3 +168,27 @@ bool check_ehci0(void)
 
 	return true;
 }
+
+bool check_mpcie2_clk(void)
+{
+	u8 mpcie2_clk;
+
+	//
+	// Find the serial console item
+	//
+	mpcie2_clk = check_knob_value("mpcie2_clk");
+
+	switch (mpcie2_clk) {
+	case 0:
+		return false;
+		break;
+	case 1:
+		return true;
+		break;
+	default:
+		printk(BIOS_EMERG, "Missing or invalid mpcie2_clk knob, forcing CLK of mPCIe2 slot is not enabled .\n");
+		break;
+	}
+
+	return false;
+}

src/mainboard/pcengines/apu2/bios_knobs.h

@@ -25,6 +25,7 @@ bool check_console(void);
 bool check_uartc(void);
 bool check_uartd(void);
 bool check_ehci0(void);
+bool check_mpcie2_clk(void);
 
 #endif
 

src/mainboard/pcengines/apu2/romstage.c

@@ -41,6 +41,7 @@
 #include <northbridge/amd/pi/00730F01/eltannorthbridge.h>
 #include <eltanhudson.h>
 #include <build.h>
+#include "bios_knobs.h"
 
 //
 // GPIO Init Table
@@ -89,6 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if (!cpu_init_detectedx && boot_cpu()) {
 
 		u32 data, *memptr;
+		bool mpcie2_clk;
 
 		hudson_lpc_port80();
 		//
@@ -129,7 +131,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04));
 
 		data &= 0xFFFFFF0F;
-		data |= 0xA << (1 * 4);	// CLKREQ GFX to GFXCLK
+
+		mpcie2_clk = check_mpcie2_clk();
+		if (mpcie2_clk) {
+			// make GFXCLK to ignore CLKREQ# input
+			// force it to be always on
+			data |= 0xF << (1 * 4); // CLKREQ GFX to GFXCLK
+		}
+		else {
+			data |= 0xA << (1 * 4);	// CLKREQ GFX to GFXCLK
+		}
 
 		*((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04)) = data;
 

src/mainboard/pcengines/apu3/bios_knobs.c

@@ -168,3 +168,27 @@ bool check_ehci0(void)
 
 	return true;
 }
+
+bool check_mpcie2_clk(void)
+{
+       u8 mpcie2_clk;
+
+       //
+       // Find the serial console item
+       //
+       mpcie2_clk = check_knob_value("mpcie2_clk");
+
+       switch (mpcie2_clk) {
+       case 0:
+               return false;
+               break;
+       case 1:
+               return true;
+               break;
+       default:
+               printk(BIOS_EMERG, "Missing or invalid mpcie2_clk knob, forcing CLK of mPCIe2 slot is not enabled .\n");
+               break;
+       }
+
+       return false;
+}

src/mainboard/pcengines/apu3/bios_knobs.h

@@ -25,6 +25,7 @@ bool check_console(void);
 bool check_uartc(void);
 bool check_uartd(void);
 bool check_ehci0(void);
+bool check_mpcie2_clk(void);
 
 #endif
 

src/mainboard/pcengines/apu3/romstage.c

@@ -41,6 +41,7 @@
 #include <northbridge/amd/pi/00730F01/eltannorthbridge.h>
 #include <eltanhudson.h>
 #include <build.h>
+#include "bios_knobs.h"
 
 //
 // GPIO Init Table
@@ -90,6 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if (!cpu_init_detectedx && boot_cpu()) {
 
 		u32 data, *memptr;
+		bool mpcie2_clk;
 
 		hudson_lpc_port80();
 		//
@@ -130,7 +132,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04));
 
 		data &= 0xFFFFFF0F;
-		data |= 0xA << (1 * 4);	// CLKREQ GFX to GFXCLK
+
+		mpcie2_clk = check_mpcie2_clk();
+		if (mpcie2_clk) {
+			// make GFXCLK to ignore CLKREQ# input
+			// force it to be always on
+			data |= 0xF << (1 * 4); // CLKREQ GFX to GFXCLK
+		}
+		else {
+			data |= 0xA << (1 * 4); // CLKREQ GFX to GFXCLK
+		}
 
 		*((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04)) = data;