18 changes: 17 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -8,6 +8,21 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in

## [Unreleased]

## [v4.0.15] - 2018-03-01
## Fixed
- SeaBIOS default repository URL
- coreboot default console loglevel
- SMBIOS part number format

## Changed
- upgraded SeaBIOS to rel-1.11.0.3
- upgraded sortbootorder to v4.6.5
- iPXE is built from master branch

## Added
- network card PCI ID is set properly according to target board
- apu features can be now restored to deafults by pressing `R` in sortbootorder

## [v4.0.14] - 2017-12-22
### Changed
- upgraded SeaBIOS to 1.11.0.2
Expand Down Expand Up @@ -131,7 +146,8 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
- forced to use SD in 2.0 mode
- git repository in `Makefile`

[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.14...coreboot-4.0.x
[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.15...coreboot-4.0.x
[v4.0.15]: https://github.com/pcengines/coreboot/compare/v4.0.14...v4.0.15
[v4.0.14]: https://github.com/pcengines/coreboot/compare/v4.0.13...v4.0.14
[v4.0.13]: https://github.com/pcengines/coreboot/compare/v4.0.12...v4.0.13
[v4.0.12]: https://github.com/pcengines/coreboot/compare/v4.0.11...v4.0.12
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6 changes: 3 additions & 3 deletions payloads/external/SeaBIOS/Kconfig
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Expand Up @@ -2,7 +2,7 @@ if PAYLOAD_SEABIOS

choice
prompt "SeaBIOS repo"
default SEABIOS_GENERIC
default SEABIOS_ELTAN
depends on PAYLOAD_SEABIOS

config SEABIOS_GENERIC
Expand All @@ -23,7 +23,7 @@ choice
depends on PAYLOAD_SEABIOS

config SEABIOS_STABLE
bool "Stable version (1.11.0.2 for std)"
bool "Stable version (1.11.0.3 for std)"
help
Stable SeaBIOS version

Expand All @@ -39,7 +39,7 @@ config ELTAN_SEABIOS_TAG
depends on SEABIOS_ELTAN
depends on SEABIOS_STABLE
string "SeaBIOS TAG"
default "rel-1.11.0.2"
default "rel-1.11.0.3"
help
Specify the SeaBIOS tag to check out

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5 changes: 5 additions & 0 deletions payloads/external/SeaBIOS/Makefile.inc
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Expand Up @@ -82,6 +82,11 @@ endif
echo "# CONFIG_USB_UHCI is not set" >> seabios/.config
echo "# CONFIG_USB_OHCI is not set" >> seabios/.config
echo "# CONFIG_LPT is not set" >> seabios/.config
#
# Enable UDMA to speed up booting
#
echo "CONFIG_ATA_DMA=y" >> seabios/.config
echo "CONFIG_ATA_PIO32=y" >> seabios/.config

# This shows how to force a previously set .config option *off*
#echo "# CONFIG_SMBIOS is not set" >> seabios/.config
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6 changes: 4 additions & 2 deletions payloads/external/iPXE/Kconfig
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Expand Up @@ -38,7 +38,7 @@ endchoice

choice
prompt "iPXE version"
default IPXE_STABLE
default IPXE_MASTER
depends on BUILD_IPXE

config IPXE_STABLE
Expand Down Expand Up @@ -72,7 +72,9 @@ config PXE_SERIAL_CONSOLE

config PXE_ROM_ID
string "network card PCI IDs"
default "8086,157b"
default "8086,157b" if BOARD_PCENGINES_APU2
default "8086,1539" if BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
BOARD_PCENGINES_APU5
help
The comma-separated PCI vendor and device ID that would associate
your PXE ROM to your network card.
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2 changes: 1 addition & 1 deletion payloads/external/sortbootorder/Makefile.inc
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@@ -1,4 +1,4 @@
version=4.5.6
version=4.6.5
branch_name=v$(version)
project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
archive_name=$(branch_name).tar.gz
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2 changes: 1 addition & 1 deletion src/console/Kconfig
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Expand Up @@ -220,7 +220,7 @@ config CONSOLE_QEMU_DEBUGCON_PORT

choice
prompt "Default console log level"
default DEFAULT_CONSOLE_LOGLEVEL_8
default DEFAULT_CONSOLE_LOGLEVEL_1

config DEFAULT_CONSOLE_LOGLEVEL_8
bool "8: SPEW"
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2 changes: 1 addition & 1 deletion src/mainboard/pcengines/apu2/Kconfig
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Expand Up @@ -45,7 +45,7 @@ config MAINBOARD_DIR

config MAINBOARD_PART_NUMBER
string
default "PC Engines apu2"
default "apu2"

config SVI2_SLOW_SPEED
bool "SVI2 slow speed"
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8 changes: 8 additions & 0 deletions src/mainboard/pcengines/apu2/bootorder_def
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Expand Up @@ -8,3 +8,11 @@
/pci@i0cf8/pci-bridge@2,5/*@0/drive@0/disk@0
/pci@i0cf8/pci-bridge@2,5/*@0/drive@1/disk@0
/rom@genroms/pxe.rom
pxen0
scon1
sgaen1
usben1
uartc1
uartd1
ehcien0
mpcie2_clk0
3 changes: 2 additions & 1 deletion src/mainboard/pcengines/apu2/romstage.c
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Expand Up @@ -193,7 +193,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bool scon = check_console();

if(scon){
printk(BIOS_ALERT, CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ALERT, CONFIG_MAINBOARD_SMBIOS_MANUFACTURER " "
CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ALERT, "coreboot build %s\n", COREBOOT_DMI_DATE);
printk(BIOS_ALERT, "BIOS version %s\n", COREBOOT_ORIGIN_GIT_TAG);
}
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2 changes: 1 addition & 1 deletion src/mainboard/pcengines/apu3/Kconfig
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Expand Up @@ -45,7 +45,7 @@ config MAINBOARD_DIR

config MAINBOARD_PART_NUMBER
string
default "PC Engines apu3"
default "apu3"

config SVI2_SLOW_SPEED
bool "SVI2 slow speed"
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8 changes: 8 additions & 0 deletions src/mainboard/pcengines/apu3/bootorder_def
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Expand Up @@ -8,3 +8,11 @@
/pci@i0cf8/pci-bridge@2,5/*@0/drive@0/disk@0
/pci@i0cf8/pci-bridge@2,5/*@0/drive@1/disk@0
/rom@genroms/pxe.rom
pxen0
scon1
sgaen1
usben1
uartc1
uartd1
ehcien0
mpcie2_clk0
3 changes: 2 additions & 1 deletion src/mainboard/pcengines/apu3/romstage.c
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Expand Up @@ -194,7 +194,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bool scon = check_console();

if(scon){
printk(BIOS_ALERT, CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ALERT, CONFIG_MAINBOARD_SMBIOS_MANUFACTURER " "
CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ALERT, "coreboot build %s\n", COREBOOT_DMI_DATE);
printk(BIOS_ALERT, "BIOS version %s\n", COREBOOT_ORIGIN_GIT_TAG);
}
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2 changes: 1 addition & 1 deletion src/mainboard/pcengines/apu5/Kconfig
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Expand Up @@ -45,7 +45,7 @@ config MAINBOARD_DIR

config MAINBOARD_PART_NUMBER
string
default "PC Engines apu5"
default "apu5"

config SVI2_SLOW_SPEED
bool "SVI2 slow speed"
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8 changes: 8 additions & 0 deletions src/mainboard/pcengines/apu5/bootorder_def
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Expand Up @@ -8,3 +8,11 @@
/pci@i0cf8/pci-bridge@2,5/*@0/drive@0/disk@0
/pci@i0cf8/pci-bridge@2,5/*@0/drive@1/disk@0
/rom@genroms/pxe.rom
pxen0
scon1
sgaen1
usben1
uartc1
uartd1
ehcien1
mpcie2_clk0
3 changes: 2 additions & 1 deletion src/mainboard/pcengines/apu5/romstage.c
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Expand Up @@ -194,7 +194,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bool scon = check_console();

if(scon){
printk(BIOS_ALERT, CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ALERT, CONFIG_MAINBOARD_SMBIOS_MANUFACTURER " "
CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ALERT, "coreboot build %s\n", COREBOOT_DMI_DATE);
printk(BIOS_ALERT, "BIOS version %s\n", COREBOOT_ORIGIN_GIT_TAG);
}
Expand Down