.gitlab-ci.yml

@@ -1,5 +1,3 @@
-image: pcengines/pce-fw-builder-legacy:latest
-
 services:
   - docker:dind
 
@@ -21,6 +19,7 @@ check_dependencies:
     - tags 
 
 .build_rom_apu: &build_rom_apu
+  image: pcengines/pce-fw-builder-legacy:latest
   variables:
     PLATFORM: apux
   stage: build_rom

CHANGELOG.md

@@ -8,6 +8,14 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
 
 ## [Unreleased]
 
+## [v4.0.18] - 2018-06-08
+### Changed
+- Updated SeaBIOS to 1.11.0.5
+- Updated sortbootorder to v4.6.9
+
+### Added
+- S1 button support for apu5b
+
 ## [v4.0.17] - 2018-05-11
 ### Added
 - Infrastructure to include microcode update
@@ -166,7 +174,8 @@ built externally
 - forced to use SD in 2.0 mode
 - git repository in `Makefile`
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.17...coreboot-4.0.x
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.18...coreboot-4.0.x
+[v4.0.18]: https://github.com/pcengines/coreboot/compare/v4.0.17...v4.0.18
 [v4.0.17]: https://github.com/pcengines/coreboot/compare/v4.0.16...v4.0.17
 [v4.0.16]: https://github.com/pcengines/coreboot/compare/v4.0.15...v4.0.16
 [v4.0.15]: https://github.com/pcengines/coreboot/compare/v4.0.14...v4.0.15

configs/pcengines_apu2.config

@@ -412,7 +412,7 @@ CONFIG_PAYLOAD_SEABIOS=y
 CONFIG_SEABIOS_ELTAN=y
 CONFIG_SEABIOS_STABLE=y
 # CONFIG_SEABIOS_MASTER is not set
-CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.4"
+CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.5"
 CONFIG_SEABIOS_SERIAL_CONSOLE=y
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
 CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y

configs/pcengines_apu3.config

@@ -412,7 +412,7 @@ CONFIG_PAYLOAD_SEABIOS=y
 CONFIG_SEABIOS_ELTAN=y
 CONFIG_SEABIOS_STABLE=y
 # CONFIG_SEABIOS_MASTER is not set
-CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.4"
+CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.5"
 CONFIG_SEABIOS_SERIAL_CONSOLE=y
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
 CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y

configs/pcengines_apu4.config

@@ -412,7 +412,7 @@ CONFIG_PAYLOAD_SEABIOS=y
 CONFIG_SEABIOS_ELTAN=y
 CONFIG_SEABIOS_STABLE=y
 # CONFIG_SEABIOS_MASTER is not set
-CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.4"
+CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.5"
 CONFIG_SEABIOS_SERIAL_CONSOLE=y
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
 CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y

configs/pcengines_apu5.config

@@ -412,7 +412,7 @@ CONFIG_PAYLOAD_SEABIOS=y
 CONFIG_SEABIOS_ELTAN=y
 CONFIG_SEABIOS_STABLE=y
 # CONFIG_SEABIOS_MASTER is not set
-CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.4"
+CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.5"
 CONFIG_SEABIOS_SERIAL_CONSOLE=y
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
 CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y

payloads/external/SeaBIOS/Kconfig

@@ -23,7 +23,7 @@ choice
 	depends on PAYLOAD_SEABIOS
 
 config SEABIOS_STABLE
-	bool "Stable version (1.11.0.4 for std)"
+	bool "Stable version (1.11.0.5 for std)"
 	help
 		Stable SeaBIOS version
 
@@ -39,7 +39,7 @@ config ELTAN_SEABIOS_TAG
 	depends on SEABIOS_ELTAN
 	depends on SEABIOS_STABLE
 	string  "SeaBIOS TAG"
-	default "rel-1.11.0.4"
+	default "rel-1.11.0.5"
 	help
 		Specify the SeaBIOS tag to check out
 

payloads/external/sortbootorder/Makefile.inc

@@ -1,4 +1,4 @@
-version=4.6.5
+version=4.6.9
 branch_name=v$(version)
 project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
 archive_name=$(branch_name).tar.gz

src/mainboard/pcengines/apu2/apu2.h

@@ -50,3 +50,5 @@
 #define APU5_SIMSWAP2_FUNC		Function0
 #define APU5_SIMSWAP3_GPIO		0x5A				// GENINT2_L/GPIO33
 #define APU5_SIMSWAP3_FUNC		Function0
+#define APU5_BIOS_CONSOLE_GPIO          0x09                            // GEVT22#
+#define APU5_BIOS_CONSOLE_FUNC          Function0                       

src/mainboard/pcengines/apu2/mainboard.c

@@ -172,22 +172,24 @@ static void mainboard_final(void *chip_info) {
 		printk(BIOS_INFO, "USB PORT ROUTING = EHCI PORTS ENABLED\n");
 	}
 
-#if CONFIG_BOARD_PCENGINES_APU2 || CONFIG_BOARD_PCENGINES_APU3 || CONFIG_BOARD_PCENGINES_APU4
-	bool console_enabled = check_console( );	// Get console setting from bootorder file.
+	bool console_enabled = check_console();	// Get console setting from bootorder file.
 
 	if ( !console_enabled ) {
 
 		//
 		// The console is disabled, check if S1 is pressed and enable if so
 		//
+# if CONFIG_BOARD_PCENGINES_APU5
+		if ( !ReadFchGpio(APU5_BIOS_CONSOLE_GPIO) ) {
+#else
 		if ( !ReadFchGpio(APU2_BIOS_CONSOLE_GPIO) ) {
+#endif
 
 			printk(BIOS_INFO, "S1 PRESSED\n");
 
 			enable_console();
 		}
 	}
-#endif // CONFIG_BOARD_PCENGINES_APU2/3/4
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/pcengines/apu2/romstage.c

@@ -67,8 +67,9 @@ static const GPIO_CONTROL gGpioInitTable[] = {
 		GPIO_DEFINITION (APU3_SIMSWAP_GPIO, 	APU3_SIMSWAP_FUNC,	1, 0, 0, 0),
 #endif
 #if CONFIG_BOARD_PCENGINES_APU5
-		GPIO_DEFINITION (APU5_SIMSWAP2_GPIO,   APU5_SIMSWAP2_FUNC,   1, 1, 0, 0),
-		GPIO_DEFINITION (APU5_SIMSWAP3_GPIO,   APU5_SIMSWAP3_FUNC,   1, 1, 0, 0),
+		GPIO_DEFINITION (APU5_SIMSWAP2_GPIO,   APU5_SIMSWAP2_FUNC,  	1, 1, 0, 0),
+		GPIO_DEFINITION (APU5_SIMSWAP3_GPIO,   APU5_SIMSWAP3_FUNC,  	1, 1, 0, 0),
+		GPIO_DEFINITION (APU5_BIOS_CONSOLE_GPIO, APU5_BIOS_CONSOLE_FUNC, 0, 0, 0, 0),
 #endif
 		{0xFF, 0xFF, 0xFF}									// Terminator
 	};

util/genbuild_h/genbuild_h.sh

@@ -33,6 +33,9 @@ if [ "${BUILD_TIMELESS}" = "1" ]; then
 elif [ -e "${top}/.git" -a -x "$(command -v git)" ]; then
 	GITREV=$(LANG= git log -1 --format=format:%h)
 	GITTAG=$(LANG= git describe --tags --exact-match $GITREV)
+	if [ -z $GITTAG ]; then
+		GITTAG=$KERNELVERSION
+	fi
 	TIMESOURCE=git
 	DATE=$(git log --pretty=format:%ct -1)
 else