13 changes: 12 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -7,6 +7,16 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
[this gerrit ref](https://review.coreboot.org/#/c/14138/).

## [Unreleased]
## [v4.0.21] - 2018-11-08
### Changed
- Updated SeaBIOS to rel-1.11.0.6

### Fixed
- Release date format in DMI tables

### Added
- [Console output redirection to COM2 option](https://github.com/pcengines/apu2-documentation/blob/master/docs/serial_console.md)

## [v4.0.20] - 2018-09-28
### Changed
- Updated sortbootorder to v4.6.11
Expand Down Expand Up @@ -181,7 +191,8 @@ built externally
- forced to use SD in 2.0 mode
- git repository in `Makefile`

[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.20...coreboot-4.0.x
[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.21...coreboot-4.0.x
[v4.0.21]: https://github.com/pcengines/coreboot/compare/v4.0.20...v4.0.21
[v4.0.20]: https://github.com/pcengines/coreboot/compare/v4.0.19...v4.0.20
[v4.0.19]: https://github.com/pcengines/coreboot/compare/v4.0.18...v4.0.19
[v4.0.18]: https://github.com/pcengines/coreboot/compare/v4.0.17...v4.0.18
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5 changes: 5 additions & 0 deletions Makefile.inc
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Expand Up @@ -654,6 +654,11 @@ ifeq ($(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE),y)
$(CBFSTOOL) $@.tmp add -f $(PXE_ROM_FILE) -n genroms/pxe.rom -t raw
endif

ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y)
@printf " SeaBIOS Add sercon-port file\n"
$(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
endif

ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y)
@printf " UPDATE-FIT \n"
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5 changes: 3 additions & 2 deletions configs/pcengines_apu2.config
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Expand Up @@ -412,8 +412,9 @@ CONFIG_PAYLOAD_SEABIOS=y
CONFIG_SEABIOS_ELTAN=y
CONFIG_SEABIOS_STABLE=y
# CONFIG_SEABIOS_MASTER is not set
CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.5"
CONFIG_SEABIOS_SERIAL_CONSOLE=y
CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.6"
CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y
CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
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5 changes: 3 additions & 2 deletions configs/pcengines_apu3.config
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Expand Up @@ -412,8 +412,9 @@ CONFIG_PAYLOAD_SEABIOS=y
CONFIG_SEABIOS_ELTAN=y
CONFIG_SEABIOS_STABLE=y
# CONFIG_SEABIOS_MASTER is not set
CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.5"
CONFIG_SEABIOS_SERIAL_CONSOLE=y
CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.6"
CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y
CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
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5 changes: 3 additions & 2 deletions configs/pcengines_apu4.config
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Expand Up @@ -412,8 +412,9 @@ CONFIG_PAYLOAD_SEABIOS=y
CONFIG_SEABIOS_ELTAN=y
CONFIG_SEABIOS_STABLE=y
# CONFIG_SEABIOS_MASTER is not set
CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.5"
CONFIG_SEABIOS_SERIAL_CONSOLE=y
CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.6"
CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y
CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
Expand Down
5 changes: 3 additions & 2 deletions configs/pcengines_apu5.config
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Expand Up @@ -412,8 +412,9 @@ CONFIG_PAYLOAD_SEABIOS=y
CONFIG_SEABIOS_ELTAN=y
CONFIG_SEABIOS_STABLE=y
# CONFIG_SEABIOS_MASTER is not set
CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.5"
CONFIG_SEABIOS_SERIAL_CONSOLE=y
CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.6"
CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y
CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
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25 changes: 19 additions & 6 deletions payloads/external/SeaBIOS/Kconfig
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Expand Up @@ -23,7 +23,7 @@ choice
depends on PAYLOAD_SEABIOS

config SEABIOS_STABLE
bool "Stable version (1.11.0.5 for std)"
bool "Stable version (1.11.0.6 for std)"
help
Stable SeaBIOS version

Expand All @@ -39,14 +39,27 @@ config ELTAN_SEABIOS_TAG
depends on SEABIOS_ELTAN
depends on SEABIOS_STABLE
string "SeaBIOS TAG"
default "rel-1.11.0.5"
default "rel-1.11.0.6"
help
Specify the SeaBIOS tag to check out

config SEABIOS_SERIAL_CONSOLE
bool "SeaBIOS Serial Console"
depends on SEABIOS_ELTAN
default y
config SEABIOS_ADD_SERCON_PORT_FILE
prompt "Add SeaBIOS sercon-port file to CBFS"
default n
bool
help
Select this option to enable SeaBIOS' VGA adapter emulation
on serial port.

config SEABIOS_SERCON_PORT_ADDR
hex "SeaBIOS sercon-port base address"
depends on SEABIOS_ADD_SERCON_PORT_FILE
default TTYS0_BASE
help
Set this field to the IO address of a serial port for SeaBIOS' VGA
adapter emulation.

By default primary console UART defined by TTYS0_BASE is used.

config SEABIOS_PS2_TIMEOUT
prompt "PS/2 keyboard controller initialization timeout (milliseconds)"
Expand Down
5 changes: 0 additions & 5 deletions src/mainboard/pcengines/apu2/Makefile.inc
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Expand Up @@ -56,11 +56,6 @@ etc/boot-menu-wait-file := src/mainboard/$(MAINBOARDDIR)/boot-menu-wait
etc/boot-menu-wait-type := raw
# WIV20150126 end add boot order

# add a SeaBIOS sercon-port file
cbfs-files-y += etc/sercon-port
etc/sercon-port-file := src/mainboard/$(MAINBOARDDIR)/sercon-port
etc/sercon-port-type := raw

# WIV20141001 START ADD SPD FROM FILE
## DIMM SPD for on-board memory
SPD_BIN = $(obj)/spd.bin
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36 changes: 35 additions & 1 deletion src/mainboard/pcengines/apu2/romstage.c
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Expand Up @@ -24,6 +24,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp.h>
#include <device/pnp_def.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
Expand All @@ -40,10 +41,18 @@
#include <fchgpio.h>
#include "apu2.h"
#include <northbridge/amd/pi/00730F01/eltannorthbridge.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct5104d/nct5104d.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <eltanhudson.h>
#include <build.h>
#include "bios_knobs.h"

#define SIO_PORT 0x2e
#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)

extern char coreboot_dmi_date[];
//
// GPIO Init Table
//
Expand Down Expand Up @@ -101,6 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {

u32 data, *memptr;
device_t dev;
bool mpcie2_clk;

hudson_lpc_port80();
Expand All @@ -112,6 +122,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_clk_output_48Mhz();

post_code(0x31);

dev = PCI_DEV(0, 0x14, 3);
data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);

/* COM2 on apu5 is reserved so only COM1 should be supported */
if ((CONFIG_UART_FOR_CONSOLE == 1) &&
!IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
else if (CONFIG_UART_FOR_CONSOLE == 0)
nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);

console_init();

printk(BIOS_INFO, "14-25-48Mhz Clock settings\n");
Expand Down Expand Up @@ -208,9 +231,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bool scon = check_console();

if(scon){
/*
* coreboot_dmi_date is in format mm/dd/yyyy and should remain
* unchanged to conform SMBIOS specification
* Change the order of months, days and years only locally to
* get it printed in sign-of-life in format yyyymmdd
*/
char tmp[9];
strncpy(tmp, coreboot_dmi_date+6, 4);
strncpy(tmp+4, coreboot_dmi_date+3, 2);
strncpy(tmp+6, coreboot_dmi_date, 2);
tmp[8] = '\0';
printk(BIOS_ALERT, CONFIG_MAINBOARD_SMBIOS_MANUFACTURER " "
CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ALERT, "coreboot build %s\n", COREBOOT_DMI_DATE);
printk(BIOS_ALERT, "coreboot build %s\n", tmp);
printk(BIOS_ALERT, "BIOS version %s\n", COREBOOT_ORIGIN_GIT_TAG);
}
#if CONFIG_SVI2_SLOW_SPEED
Expand Down
Binary file removed src/mainboard/pcengines/apu2/sercon-port
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Binary file not shown.
1 change: 1 addition & 0 deletions src/southbridge/amd/pi/hudson/hudson.h
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Expand Up @@ -56,6 +56,7 @@
#define SPI_ROM_ENABLE 0x02
#define SPI_BASE_ADDRESS 0xFEC10000

#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48

#define ACPI_MMIO_BASE 0xFED80000ul
#define FCH_CFG_BASE 0x000 // DWORD
Expand Down
4 changes: 2 additions & 2 deletions util/genbuild_h/genbuild_h.sh
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Expand Up @@ -51,7 +51,7 @@ NetBSD|OpenBSD|DragonFly|FreeBSD|Darwin)
date -r $1 $2
;;
*)
date -d @$1 $2 | sed -e 's/\///g'
date -d @$1 $2
esac
}

Expand All @@ -70,7 +70,7 @@ printf "#define COREBOOT_BUILD_YEAR_BCD 0x$(our_date "$DATE" +%y)\n"
printf "#define COREBOOT_BUILD_MONTH_BCD 0x$(our_date "$DATE" +%m)\n"
printf "#define COREBOOT_BUILD_DAY_BCD 0x$(our_date "$DATE" +%d)\n"
printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x$(our_date "$DATE" +%w)\n"
printf "#define COREBOOT_DMI_DATE \"$(our_date "$DATE" +%Y/%m/%d)\"\n"
printf "#define COREBOOT_DMI_DATE \"$(our_date "$DATE" +%m/%d/%Y)\"\n"
printf "\n"
printf "#define COREBOOT_COMPILE_TIME \"$(our_date "$DATE" +%T)\"\n"
printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n"
Expand Down