CHANGELOG.md

@@ -7,6 +7,20 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
 [this gerrit ref](https://review.coreboot.org/#/c/14138/).
 
 ## [Unreleased]
+## [v4.0.22] - 2018-12-03
+### Changed
+- Updated SeaBIOS to rel-1.11.0.7
+- Updated sortbootorder to v4.6.12
+
+### Added
+- [experimental option for adding microcode update](https://github.com/pcengines/apu2-documentation/blob/master/docs/microcode_patching.md)
+- [COM2 redirection runtime configuration](https://github.com/pcengines/apu2-documentation/blob/master/docs/serial_console.md)
+- SeaBIOS can be built from arbitrary revision
+- SeaBIOS debug level can be set via Kconfig
+
+### Fixed
+- generating serial number from MAC address of first NIC
+
 ## [v4.0.21] - 2018-11-08
 ### Changed
 - Updated SeaBIOS to rel-1.11.0.6
@@ -191,7 +205,8 @@ built externally
 - forced to use SD in 2.0 mode
 - git repository in `Makefile`
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.21...coreboot-4.0.x
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.22...coreboot-4.0.x
+[v4.0.22]: https://github.com/pcengines/coreboot/compare/v4.0.21...v4.0.22
 [v4.0.21]: https://github.com/pcengines/coreboot/compare/v4.0.20...v4.0.21
 [v4.0.20]: https://github.com/pcengines/coreboot/compare/v4.0.19...v4.0.20
 [v4.0.19]: https://github.com/pcengines/coreboot/compare/v4.0.18...v4.0.19

Makefile.inc

@@ -664,6 +664,9 @@ ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y)
 	@printf "    UPDATE-FIT \n"
 	$(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES)
 endif
+endif
+ifeq ($(CONFIG_AGESA_UCODE_EXPERIMENTAL),y)
+	dd if=$(CONFIG_CPU_MICROCODE_FILE) of=$@.tmp bs=1 seek=6665692 count=3424 conv=notrunc 2> /dev/null
 endif
 	mv $@.tmp $@
 	@printf "    CBFSPRINT  $(subst $(obj)/,,$(@))\n\n"

configs/pcengines_apu2.config

@@ -190,6 +190,7 @@ CONFIG_AP_SIPI_VECTOR=0xfffff000
 # CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_AGESA_UCODE_EXPERIMENTAL is not set
 
 #
 # Northbridge
@@ -409,15 +410,21 @@ CONFIG_PAYLOAD_SEABIOS=y
 # CONFIG_PAYLOAD_GRUB2 is not set
 # CONFIG_PAYLOAD_TIANOCORE is not set
 # CONFIG_SEABIOS_GENERIC is not set
-CONFIG_SEABIOS_ELTAN=y
-CONFIG_SEABIOS_STABLE=y
+CONFIG_SEABIOS_PCENGINES=y
+# CONFIG_SEABIOS_STABLE is not set
 # CONFIG_SEABIOS_MASTER is not set
-CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.6"
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
 CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
 CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y
 CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+CONFIG_SEABIOS_DEBUG_LEVEL=0
+
+#
+# SeaBIOS logging disabled
+#
 CONFIG_COMPRESSED_PAYLOAD_LZMA=y
 CONFIG_SORTBOOTORDER=y
 CONFIG_PXE=y

configs/pcengines_apu3.config

@@ -190,6 +190,7 @@ CONFIG_AP_SIPI_VECTOR=0xfffff000
 # CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_AGESA_UCODE_EXPERIMENTAL is not set
 
 #
 # Northbridge
@@ -409,15 +410,21 @@ CONFIG_PAYLOAD_SEABIOS=y
 # CONFIG_PAYLOAD_GRUB2 is not set
 # CONFIG_PAYLOAD_TIANOCORE is not set
 # CONFIG_SEABIOS_GENERIC is not set
-CONFIG_SEABIOS_ELTAN=y
-CONFIG_SEABIOS_STABLE=y
+CONFIG_SEABIOS_PCENGINES=y
+# CONFIG_SEABIOS_STABLE is not set
 # CONFIG_SEABIOS_MASTER is not set
-CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.6"
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
 CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
 CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y
 CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+CONFIG_SEABIOS_DEBUG_LEVEL=0
+
+#
+# SeaBIOS logging disabled
+#
 CONFIG_COMPRESSED_PAYLOAD_LZMA=y
 CONFIG_SORTBOOTORDER=y
 CONFIG_PXE=y

configs/pcengines_apu4.config

@@ -190,6 +190,7 @@ CONFIG_AP_SIPI_VECTOR=0xfffff000
 # CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_AGESA_UCODE_EXPERIMENTAL is not set
 
 #
 # Northbridge
@@ -409,15 +410,21 @@ CONFIG_PAYLOAD_SEABIOS=y
 # CONFIG_PAYLOAD_GRUB2 is not set
 # CONFIG_PAYLOAD_TIANOCORE is not set
 # CONFIG_SEABIOS_GENERIC is not set
-CONFIG_SEABIOS_ELTAN=y
-CONFIG_SEABIOS_STABLE=y
+CONFIG_SEABIOS_PCENGINES=y
+# CONFIG_SEABIOS_STABLE is not set
 # CONFIG_SEABIOS_MASTER is not set
-CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.6"
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
 CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
 CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y
 CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+CONFIG_SEABIOS_DEBUG_LEVEL=0
+
+#
+# SeaBIOS logging disabled
+#
 CONFIG_COMPRESSED_PAYLOAD_LZMA=y
 CONFIG_SORTBOOTORDER=y
 CONFIG_PXE=y

configs/pcengines_apu5.config

@@ -190,6 +190,7 @@ CONFIG_AP_SIPI_VECTOR=0xfffff000
 # CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_AGESA_UCODE_EXPERIMENTAL is not set
 
 #
 # Northbridge
@@ -409,15 +410,21 @@ CONFIG_PAYLOAD_SEABIOS=y
 # CONFIG_PAYLOAD_GRUB2 is not set
 # CONFIG_PAYLOAD_TIANOCORE is not set
 # CONFIG_SEABIOS_GENERIC is not set
-CONFIG_SEABIOS_ELTAN=y
-CONFIG_SEABIOS_STABLE=y
+CONFIG_SEABIOS_PCENGINES=y
+# CONFIG_SEABIOS_STABLE is not set
 # CONFIG_SEABIOS_MASTER is not set
-CONFIG_ELTAN_SEABIOS_TAG="rel-1.11.0.6"
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
 CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
 CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y
 CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+CONFIG_SEABIOS_DEBUG_LEVEL=0
+
+#
+# SeaBIOS logging disabled
+#
 CONFIG_COMPRESSED_PAYLOAD_LZMA=y
 CONFIG_SORTBOOTORDER=y
 CONFIG_PXE=y

payloads/external/SeaBIOS/Kconfig

@@ -2,18 +2,18 @@ if PAYLOAD_SEABIOS
 
 choice
 	prompt "SeaBIOS repo"
-	default SEABIOS_ELTAN
+	default SEABIOS_PCENGINES
 	depends on PAYLOAD_SEABIOS
 
 config SEABIOS_GENERIC
 	bool "SeaBiosRepo"
 	help
 		Get SeaBIOS from the master GIT repo
 
-config SEABIOS_ELTAN
-	bool "EltanRepo"
+config SEABIOS_PCENGINES
+	bool "PC Engines Repo"
 	help
-		Get SeaBIOS from the Eltan Repo
+		Get SeaBIOS from the PC Engines Repo
 
 endchoice
 
@@ -25,23 +25,31 @@ choice
 config SEABIOS_STABLE
 	bool "Stable version (1.11.0.6 for std)"
 	help
-		Stable SeaBIOS version
+	  Stable SeaBIOS version
 
 config SEABIOS_MASTER
 	bool "master"
 	help
-		Newest SeaBIOS version
+	  Newest SeaBIOS version
+
+config SEABIOS_REVISION
+	bool "git revision"
+	help
+	  Select this option if you have a specific commit or branch
+	  that you want to use as the revision from which to
+	  build SeaBIOS.
+
+	  You will be able to specify the name of a branch or a commit id
+	  later.
 
 endchoice
 
-config ELTAN_SEABIOS_TAG
-	depends on PAYLOAD_SEABIOS
-	depends on SEABIOS_ELTAN
-	depends on SEABIOS_STABLE
-	string  "SeaBIOS TAG"
-	default "rel-1.11.0.6"
+config SEABIOS_REVISION_ID
+	string "Insert a commit's SHA-1 or a branch name"
+	depends on SEABIOS_REVISION
+	default "origin/master"
 	help
-		Specify the SeaBIOS tag to check out
+	   The commit's SHA-1 or branch name of the revision to use.
 
 config SEABIOS_ADD_SERCON_PORT_FILE
 	prompt "Add SeaBIOS sercon-port file to CBFS"
@@ -113,6 +121,33 @@ config PAYLOAD_VGABIOS_FILE
 	depends on SEABIOS_VGA_COREBOOT
 	default "payloads/external/SeaBIOS/seabios/out/vgabios.bin"
 
-
+config SEABIOS_DEBUG_LEVEL
+	int "SeaBIOS debug level (verbosity)"
+	default -1
+	help
+	  The higher the number, the more verbose SeaBIOS will be. See the table
+	  below for the current values corresponding to various items as of SeaBIOS
+	  version 1.10.1. Set this value to -1 to use SeaBIOS' default.
+
+	  Output at various SeaBIOS log levels:
+	  level 0  - Logging disabled
+	  level 1  - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM
+	  level 2  - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h
+	  level 3  - bootsplash, initializations, SeaBIOS VGA BIOS interrupts
+	  level 4  - bios tables, more optionrom
+	  level 5  - Extra bootsplash, more XHCI
+	  level 6  - ATA commands, extra optionrom
+	  level 7  - extra ps2 commands, more OHCI & EHCI
+	  level 8  - extra malloc info, more AHCI
+	  level 9  - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS,
+	             USB-HID commands, SDcard commands, Floppy commands
+	  level 10 - interrupt 13h (Drives other than floppy)
+	  level 20 - interrupt 10h (Display)
+
+comment "Using default SeaBIOS log level"
+	depends on SEABIOS_DEBUG_LEVEL = -1
+
+comment "SeaBIOS logging disabled"
+	depends on SEABIOS_DEBUG_LEVEL = 0
 
 endif

payloads/external/SeaBIOS/Makefile.inc

@@ -1,21 +1,9 @@
-SEABIOSGIT-$(CONFIG_SEABIOS_GENERIC)=http://review.coreboot.org/p/seabios.git
-SEABIOSGIT-$(CONFIG_SEABIOS_ELTAN)=https://github.com/pcengines/seabios.git
+SEABIOSGIT-$(CONFIG_SEABIOS_GENERIC)=http://review.coreboot.org/seabios
+SEABIOSGIT-$(CONFIG_SEABIOS_PCENGINES)=https://github.com/pcengines/seabios.git
 
-ifeq ($(CONFIG_SEABIOS_GENERIC),y)
-#
-# Using the generic seabios
-#
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=33fbe13a3e2a01e0ba1087a8feed801a0451db21
-endif
-
-ifeq ($(CONFIG_SEABIOS_ELTAN),y)
-#
-# Using the eltan seabios
-#
-TAG-$(CONFIG_SEABIOS_MASTER)=origin/apu2-support
-TAG-$(CONFIG_SEABIOS_STABLE)=$(CONFIG_ELTAN_SEABIOS_TAG)
-endif
+TAG-$(CONFIG_SEABIOS_STABLE)=221144005cc6d01ae094c284e40be4b5fdcb6af0
+TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
 
 unexport KCONFIG_AUTOHEADER
 unexport KCONFIG_AUTOCONFIG
@@ -70,7 +58,7 @@ ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y)
 	echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config
 endif
 
-	echo "CONFIG_DEBUG_LEVEL=-1" >> seabios/.config
+	echo "CONFIG_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL)" >> seabios/.config
 
 #
 # Project specific configuration for optimized SeaBIOS

payloads/external/sortbootorder/Makefile.inc

@@ -1,4 +1,4 @@
-version=4.6.11
+version=4.6.12
 branch_name=v$(version)
 project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
 archive_name=$(branch_name).tar.gz

src/arch/x86/Makefile.inc

@@ -322,23 +322,24 @@ endif # CONFIG_ARCH_RAMSTAGE_X86_32
 
 ################################################################################
 
-seabios:
+seabios: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \
 			HOSTCC="$(HOSTCC)" \
 			CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \
 			OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \
 			AS="$(AS_x86_32)" \
 			CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \
 			CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \
+			CONFIG_SEABIOS_REVISION=$(CONFIG_SEABIOS_REVISION) \
 			CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \
 			CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \
+			CONFIG_SEABIOS_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL) \
 			CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \
 			CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \
 			CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \
 			CONFIG_SEABIOS_GENERIC=$(CONFIG_SEABIOS_GENERIC) \
-			CONFIG_SEABIOS_ELTAN=$(CONFIG_SEABIOS_ELTAN) \
-			CONFIG_SEABIOS_SERIAL_CONSOLE=$(CONFIG_SEABIOS_SERIAL_CONSOLE) \
-			CONFIG_ELTAN_SEABIOS_TAG=$(CONFIG_ELTAN_SEABIOS_TAG) \
+			CONFIG_SEABIOS_PCENGINES=$(CONFIG_SEABIOS_PCENGINES) \
+			CONFIG_SEABIOS_REVISION_ID=$(CONFIG_SEABIOS_REVISION_ID) \
 			OUT=$(abspath $(obj)) IASL="$(IASL)"
 
 sortbootorder:

src/cpu/Kconfig

@@ -12,10 +12,10 @@ source src/cpu/amd/Kconfig
 
 config CPU_INTEL_MODEL_206AX
 	bool
-	
+
 config CPU_INTEL_MODEL_2065X
 	bool
-	
+
 #source src/cpu/via/Kconfig
 #source src/cpu/qemu-x86/Kconfig
 source src/cpu/x86/Kconfig
@@ -158,11 +158,15 @@ config CPU_MICROCODE_CBFS_NONE
 	  Make sure you have a way of flashing the ROM externally before
 	  selecting this option.
 
+config AGESA_UCODE_EXPERIMENTAL
+	bool "Add microcode patch for AMD fam16h (EXPERIMENTAL)"
+	help
+
 endchoice
 
 config CPU_MICROCODE_FILE
 	  string "Path and filename of CPU microcode"
-	  depends on CPU_MICROCODE_CBFS_EXTERNAL
+	  depends on CPU_MICROCODE_CBFS_EXTERNAL || AGESA_UCODE_EXPERIMENTAL
 	  default "cpu_microcode.bin"
 	  help
 	    The path and filename of the file containing the CPU microcode.

src/cpu/amd/pi/00730F01/Makefile.inc

@@ -17,12 +17,8 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
 
-romstage-y += update_microcode.c
-
 ramstage-y += chip_name.c
 ramstage-y += model_16_init.c
-ramstage-y += update_microcode.c
-
 
 subdirs-y += ../../mtrr
 subdirs-y += ../../../x86/tsc