.gitlab-ci.yml

@@ -21,7 +21,7 @@ check_dependencies:
 .build_rom_apu: &build_rom_apu
   image: pcengines/pce-fw-builder-legacy:latest
   variables:
-    PLATFORM: apux
+    PLATFORM:
   stage: build_rom
   tags:
     - docker
@@ -30,9 +30,7 @@ check_dependencies:
     - cd /home/coreboot/pce-fw-builder
     - git checkout `git describe --tags --abbrev=0`
     - ./build.sh release-CI "${CI_COMMIT_REF_NAME}" "${PLATFORM}"
-    - cp -v /home/coreboot/release/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom ${RELEASE_DIR}
-    - ls -al ${RELEASE_DIR}
-    - sha256sum ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom
+    - cp -v /home/coreboot/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom ${RELEASE_DIR}
   artifacts:
     name: ${PLATFORM}
     paths:
@@ -59,14 +57,15 @@ check_dependencies:
   tags:
     - docker
   script:
-    - for rom in ${RELEASE_DIR}/${PLATFORM}_*.rom; do touch ${rom}_dummy_signature; done
-    - ls -la ${RELEASE_DIR}/${PLATFORM}_*.rom
+    - sha256sum ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom > ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom.SHA256 
+    - ls -la ${RELEASE_DIR}
   artifacts:
     name: ${PLATFORM}
     paths:
-      - ${RELEASE_DIR}/${PLATFORM}_*
+      - ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom.SHA256
   only:
     - tags
+    - web
 
 .publish_rom: &publish_rom
   variables:
@@ -76,10 +75,10 @@ check_dependencies:
     - docker
   script:
     - ls -al ${RELEASE_DIR}
-    - echo "curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL ${UPLOADER_URL}/${PLATFORM}/; curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL ${UPLOADER_URL}/${PLATFORM}/releases/"
-    - curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL "${UPLOADER_URL}/${PLATFORM}/"; curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL "${UPLOADER_URL}/${PLATFORM}/releases/"
-    - echo "for file in ${RELEASE_DIR}/${PLATFORM}_*.rom; do curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${file} ${UPLOADER_URL}/${PLATFORM}/releases/; done"
-    - for file in ${RELEASE_DIR}/${PLATFORM}_*.rom; do curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${file} "${UPLOADER_URL}/${PLATFORM}/releases/"; done
+    - curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL ${UPLOADER_URL}/releases/
+    - curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL "${UPLOADER_URL}/releases/${CI_COMMIT_REF_NAME}/"
+    - curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom ${UPLOADER_URL}/releases/${CI_COMMIT_REF_NAME}/
+    - curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom.SHA256 ${UPLOADER_URL}/releases/${CI_COMMIT_REF_NAME}/
   only:
     - tags
 
@@ -93,7 +92,7 @@ build:apu2:
   variables:
     PLATFORM: apu2
 
-.sign:apu2:
+sign:apu2:
   <<: *sign_rom
   variables:
     PLATFORM: apu2
@@ -114,7 +113,7 @@ build:apu3:
   variables:
     PLATFORM: apu3
 
-.sign:apu3:
+sign:apu3:
   <<: *sign_rom
   variables:
     PLATFORM: apu3
@@ -135,7 +134,7 @@ build:apu4:
   variables:
     PLATFORM: apu4
 
-.sign:apu4:
+sign:apu4:
   <<: *sign_rom
   variables:
     PLATFORM: apu4
@@ -156,7 +155,7 @@ build:apu5:
   variables:
     PLATFORM: apu5
 
-.sign:apu5:
+sign:apu5:
   <<: *sign_rom
   variables:
     PLATFORM: apu5

CHANGELOG.md

@@ -7,16 +7,28 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
 [this gerrit ref](https://review.coreboot.org/#/c/14138/).
 
 ## [Unreleased]
+## [v4.0.25] - 2019-03-07
+### Changed
+- sortbootorder updated to v4.6.13 introducing CPU boost runtime configuration
+- configured pull-ups on WLAN_DISABLE# pins on the mPCIe connectors which could
+  cause issues with certain modems when floating
+
+### Fixed
+- [memtest86+ and iPXE revisions for fully reproducible builds](https://github.com/pcengines/coreboot/issues/267)
+
+### Added
+- CPU boost runtime configuration in coreboot
+
 ## [v4.0.24] - 2019-02-04
-## Added
+### Added
 - enabled Core Performance Boost feature
 
 ## [v4.0.23] - 2019-01-09
-## Fixed
+### Fixed
 - enabled ECC
 - disabled EHCI0 controller on apu2 which caused problems with pfSense booting
 
-## Changed
+### Changed
 - updated SeaBIOS to rel-1.12.0.1
 - introduced reproducible builds by providing build ID to iPXE
 
@@ -218,7 +230,8 @@ built externally
 - forced to use SD in 2.0 mode
 - git repository in `Makefile`
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.24...coreboot-4.0.x
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.25...coreboot-4.0.x
+[v4.0.25]: https://github.com/pcengines/coreboot/compare/v4.0.24...v4.0.25
 [v4.0.24]: https://github.com/pcengines/coreboot/compare/v4.0.23...v4.0.24
 [v4.0.23]: https://github.com/pcengines/coreboot/compare/v4.0.22...v4.0.23
 [v4.0.22]: https://github.com/pcengines/coreboot/compare/v4.0.21...v4.0.22

configs/pcengines_apu2.config

@@ -434,16 +434,18 @@ CONFIG_PXE=y
 #
 # CONFIG_PXE_ROM is not set
 CONFIG_BUILD_IPXE=y
-# CONFIG_IPXE_STABLE is not set
-CONFIG_IPXE_MASTER=y
+CONFIG_IPXE_STABLE=y
+# CONFIG_IPXE_MASTER is not set
 # CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_PXE_ROM_ID="8086,157b"
 CONFIG_PXE_CUSTOM_GENERAL_H="general.h"
 CONFIG_PXE_CUSTOM_BOOTMENU_FILE="menu.ipxe"
 CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST=y
-CONFIG_MEMTEST_STABLE=y
+# CONFIG_MEMTEST_STABLE is not set
 # CONFIG_MEMTEST_MASTER is not set
+CONFIG_MEMTEST_REVISION=y
+CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
 
 #
 # Debugging

configs/pcengines_apu3.config

@@ -434,16 +434,18 @@ CONFIG_PXE=y
 #
 # CONFIG_PXE_ROM is not set
 CONFIG_BUILD_IPXE=y
-# CONFIG_IPXE_STABLE is not set
-CONFIG_IPXE_MASTER=y
+CONFIG_IPXE_STABLE=y
+# CONFIG_IPXE_MASTER is not set
 # CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_PXE_ROM_ID="8086,1539"
 CONFIG_PXE_CUSTOM_GENERAL_H="general.h"
 CONFIG_PXE_CUSTOM_BOOTMENU_FILE="menu.ipxe"
 CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST=y
-CONFIG_MEMTEST_STABLE=y
+# CONFIG_MEMTEST_STABLE is not set
 # CONFIG_MEMTEST_MASTER is not set
+CONFIG_MEMTEST_REVISION=y
+CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
 
 #
 # Debugging

configs/pcengines_apu4.config

@@ -434,16 +434,18 @@ CONFIG_PXE=y
 #
 # CONFIG_PXE_ROM is not set
 CONFIG_BUILD_IPXE=y
-# CONFIG_IPXE_STABLE is not set
-CONFIG_IPXE_MASTER=y
+CONFIG_IPXE_STABLE=y
+# CONFIG_IPXE_MASTER is not set
 # CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_PXE_ROM_ID="8086,1539"
 CONFIG_PXE_CUSTOM_GENERAL_H="general.h"
 CONFIG_PXE_CUSTOM_BOOTMENU_FILE="menu.ipxe"
 CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST=y
-CONFIG_MEMTEST_STABLE=y
+# CONFIG_MEMTEST_STABLE is not set
 # CONFIG_MEMTEST_MASTER is not set
+CONFIG_MEMTEST_REVISION=y
+CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
 
 #
 # Debugging

configs/pcengines_apu5.config

@@ -434,16 +434,18 @@ CONFIG_PXE=y
 #
 # CONFIG_PXE_ROM is not set
 CONFIG_BUILD_IPXE=y
-# CONFIG_IPXE_STABLE is not set
-CONFIG_IPXE_MASTER=y
+CONFIG_IPXE_STABLE=y
+# CONFIG_IPXE_MASTER is not set
 # CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_PXE_ROM_ID="8086,1539"
 CONFIG_PXE_CUSTOM_GENERAL_H="general.h"
 CONFIG_PXE_CUSTOM_BOOTMENU_FILE="menu.ipxe"
 CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST=y
-CONFIG_MEMTEST_STABLE=y
+# CONFIG_MEMTEST_STABLE is not set
 # CONFIG_MEMTEST_MASTER is not set
+CONFIG_MEMTEST_REVISION=y
+CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
 
 #
 # Debugging

payloads/external/Memtest86Plus/Makefile.inc

@@ -17,6 +17,7 @@ TAG-$(CONFIG_MEMTEST_MASTER)=origin/master
 NAME-$(CONFIG_MEMTEST_MASTER)=Master
 TAG-$(CONFIG_MEMTEST_STABLE)=485c4fd363fe8570b3da9f0cc5dacf20e1c40cbc
 NAME-$(CONFIG_MEMTEST_STABLE)=Stable
+TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID)
 
 project_name=Memtest86+
 project_dir=$(CURDIR)/memtest86plus
@@ -29,6 +30,14 @@ $(project_dir):
 	git clone $(project_git_repo) $(project_dir)
 
 fetch: $(project_dir)
+ifeq ($(TAG-y),)
+	echo "Error: The specified tag is invalid"
+ifeq ($(CONFIG_MEMTEST_REVISION),y)
+	echo "Error: There is no revision specified for $(project_name)"
+	false
+endif
+	false
+endif
 	-cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \
 		if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \
 		echo "    Fetching new commits from the $(project_name) git repo"; \

payloads/external/sortbootorder/Makefile.inc

@@ -1,4 +1,4 @@
-version=4.6.12
+version=4.6.13
 branch_name=v$(version)
 project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
 archive_name=$(branch_name).tar.gz

src/Kconfig

@@ -809,8 +809,26 @@ config MEMTEST_MASTER
 	  This option will fetch the newest version of the Memtest86+ code,
 	  updating as new changes are committed.  This makes the build
 	  non-reproducible, as it can fetch different code each time.
+config MEMTEST_REVISION
+	bool "git revision"
+	help
+	  Select this option if you have a specific commit or branch
+	  that you want to use as the revision from which to
+	  build Memtest86+.  This makes the build
+	  non-reproducible, as it can fetch different code each time.
+
+	  You will be able to specify the name of a branch or a commit id
+	  later.
+
 endchoice
 
+config MEMTEST_REVISION_ID
+	string "Insert a commit's SHA-1 or a branch name"
+	depends on MEMTEST_REVISION
+	default "origin/master"
+	help
+	   The commit's SHA-1 or branch name of the revision to use.
+
 endmenu
 
 menu "Debugging"

src/mainboard/pcengines/apu2/Makefile.inc

@@ -90,14 +90,16 @@ endif
 
 memtest: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/Memtest86Plus -f Makefile.inc all \
-			CC="$(CC_x86_32)" \
-			LD="$(LD_x86_32)" \
-			OBJCOPY="$(OBJCOPY_x86_32)" \
-			AS="$(AS_x86_32)" \
-			CONFIG_MEMTEST_MASTER=$(CONFIG_MEMTEST_MASTER) \
-			CONFIG_MEMTEST_STABLE=$(CONFIG_MEMTEST_STABLE) \
-			$(MEMTEST_SERIAL_OPTIONS) \
-			MFLAGS= MAKEFLAGS=
+		CC="$(CC_x86_32)" \
+		LD="$(LD_x86_32)" \
+		OBJCOPY="$(OBJCOPY_x86_32)" \
+		AS="$(AS_x86_32)" \
+		CONFIG_MEMTEST_REVISION=$(CONFIG_MEMTEST_REVISION) \
+		CONFIG_MEMTEST_REVISION_ID=$(CONFIG_MEMTEST_REVISION_ID) \
+		CONFIG_MEMTEST_MASTER=$(CONFIG_MEMTEST_MASTER) \
+		CONFIG_MEMTEST_STABLE=$(CONFIG_MEMTEST_STABLE) \
+		$(MEMTEST_SERIAL_OPTIONS) \
+		MFLAGS= MAKEFLAGS=
 
 # iPXE
 

src/mainboard/pcengines/apu2/PlatformGnbPcie.c

@@ -18,6 +18,7 @@
  */
 
 #include <northbridge/amd/pi/agesawrapper.h>
+#include "bios_knobs.h"
 
 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
@@ -123,6 +124,8 @@ OemCustomizeInitEarly (
 	)
 {
 	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->PlatformConfig.CStateMode = CStateModeC6;
-	InitEarly->PlatformConfig.CpbMode = CpbModeAuto;
+	if(check_boost()) {
+		InitEarly->PlatformConfig.CStateMode = CStateModeC6;
+		InitEarly->PlatformConfig.CpbMode = CpbModeAuto;
+	}
 }

src/mainboard/pcengines/apu2/bios_knobs.c

@@ -126,6 +126,28 @@ int check_com2(void)
  	return 0;
 }
 
+int check_boost(void)
+{
+	u8 boosten;
+ 	//
+	// Find the boost item
+	//
+	boosten = check_knob_value("boosten");
+ 	switch (boosten) {
+	case 0:
+		return 0;
+		break;
+	case 1:
+		return 1;
+		break;
+	default:
+		printk(BIOS_INFO,
+			"Missing or invalid boost knob, disable CPU boost.\n");
+		break;
+	}
+ 	return 0;
+}
+
 static bool check_uart(char uart_letter)
 {
 	u8 uarten;

src/mainboard/pcengines/apu2/bios_knobs.h

@@ -27,5 +27,6 @@ bool check_uartd(void);
 bool check_ehci0(void);
 bool check_mpcie2_clk(void);
 int check_com2(void);
+int check_boost(void);
 
 #endif

src/mainboard/pcengines/apu2/bootorder_def

@@ -13,5 +13,7 @@ scon1
 usben1
 uartc1
 uartd1
-ehcien1
+ehcien0
 mpcie2_clk0
+com2en0
+boosten1

src/mainboard/pcengines/apu2/romstage.c

@@ -64,8 +64,13 @@ static const GPIO_CONTROL gGpioInitTable[] = {
 		GPIO_DEFINITION (APU2_LED1_L_GPIO,	APU2_LED1_L_FUNC,	1, 0, 0, 0),	// Turn on the LEDs by default
 		GPIO_DEFINITION (APU2_LED2_L_GPIO,	APU2_LED2_L_FUNC,	1, 0, 0, 0),
 		GPIO_DEFINITION (APU2_LED3_L_GPIO,	APU2_LED3_L_FUNC,	1, 0, 0, 0),
+#if CONFIG_BOARD_PCENGINES_APU2 || CONFIG_BOARD_PCENGINES_APU3 || CONFIG_BOARD_PCENGINES_APU4
+		GPIO_DEFINITION (APU2_PE3_WDIS_L_GPIO,	APU2_PE3_WDIS_L_FUNC,	0, 1, 1, 0), // enable high state and pull-ups on WDIS lanes
+		GPIO_DEFINITION (APU2_PE4_WDIS_L_GPIO,	APU2_PE4_WDIS_L_FUNC,	0, 1, 1, 0),
+#else
 		GPIO_DEFINITION (APU2_PE3_WDIS_L_GPIO,	APU2_PE3_WDIS_L_FUNC,	1, 1, 0, 0),
 		GPIO_DEFINITION (APU2_PE4_WDIS_L_GPIO,	APU2_PE4_WDIS_L_FUNC,	1, 1, 0, 0),
+#endif
 // SPKR doesn't require init, left at default
 		GPIO_DEFINITION (APU2_PROCHOT_GPIO,	APU2_PROCHOT_FUNC,	0, 0, 0, 0),
 #if CONFIG_BOARD_PCENGINES_APU2 || CONFIG_BOARD_PCENGINES_APU3 || CONFIG_BOARD_PCENGINES_APU4