12 changes: 11 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -7,6 +7,15 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
[this gerrit ref](https://review.coreboot.org/#/c/14138/).

## [Unreleased]
## [v4.0.29] - 2019-10-07
### Fixed
- SD 3.0 mode is correctly configurable now

### Added
- [ACPI support for GPIOs](https://github.com/pcengines/apu2-documentation/blob/master/docs/gpios.md)
- SuperIO GPIOs are reset to default state with platform soft reset
- SuperIO GPIOs can be controlled within IO port range

## [v4.0.28] - 2019-09-09
### Fixed
- watchdog is now available on APU3
Expand Down Expand Up @@ -250,7 +259,8 @@ built externally
- forced to use SD in 2.0 mode
- git repository in `Makefile`

[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.28...coreboot-4.0.x
[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.29...coreboot-4.0.x
[v4.0.29]: https://github.com/pcengines/coreboot/compare/v4.0.28...v4.0.29
[v4.0.28]: https://github.com/pcengines/coreboot/compare/v4.0.27...v4.0.28
[v4.0.27]: https://github.com/pcengines/coreboot/compare/v4.0.26...v4.0.27
[v4.0.26]: https://github.com/pcengines/coreboot/compare/v4.0.25...v4.0.26
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60 changes: 60 additions & 0 deletions src/mainboard/pcengines/apu2/acpi/buttons.asl
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@@ -0,0 +1,60 @@
/*
* This file is part of the coreboot project.
*
* Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/
*
* Copyright (C) 2015 Tobias Diedrich, Mika Westerberg
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

Scope (\_SB.PCI0)
{
Device (BTNS)
{
Name (_HID, "PRP0001")

Name (_CRS, ResourceTemplate () {
GpioInt (Edge, ActiveLow, Shared, PullUp, ,
"\\_SB.PCI0.GPIO") {
#if CONFIG_BOARD_PCENGINES_APU5
9
#else
89
#endif
}
})

Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"compatible", "gpio-keys"},
Package () {"autorepeat", 1}
}
})

Device (BTN1)
{
Name (_HID, "PRP0001")
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"linux,code", 257},
Package () {"linux,input-type", 1},
Package () {"debounce-interval", 100},
Package () {"label", "switch1"},
Package () {"interrupts", 7},
Package () {"gpios", Package ()
{^^BTNS, 0, 0, 1}}
}
})
}
}
}
34 changes: 34 additions & 0 deletions src/mainboard/pcengines/apu2/acpi/gpio.asl
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@@ -0,0 +1,34 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

Scope (\_SB.PCI0)
{
Device (GPIO) {
Name (_HID, "AMD0030")
Name (_CID, "AMD0030")
Name (_UID, 0)
Name (_DDN, "GPIO-Controller")

Name (_CRS, ResourceTemplate () {
Interrupt(ResourceConsumer, Level, ActiveLow,
Shared, , , ) {7}
Memory32Fixed(ReadWrite, 0xFED81500, 0x300)
})

Method (_STA, 0x0, NotSerialized) {
Return (0x0F)
}
}
}
75 changes: 75 additions & 0 deletions src/mainboard/pcengines/apu2/acpi/leds.asl
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@@ -0,0 +1,75 @@
/*
* This file is part of the coreboot project.
*
* Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/
*
* Copyright (C) 2015 Tobias Diedrich, Mika Westerberg
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

Scope (\_SB.PCI0)
{
Device (LEDS)
{
Name (_HID, "PRP0001")

Name (_CRS, ResourceTemplate () {
GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer) { 68, 69, 70 }
})

Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"compatible","gpio-leds"}
}
})

Device (LED1)
{
Name (_HID, "PRP0001")
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"label", DEVICE_NAME:green:led1"},
Package () {"gpios", Package () {^^LEDS, 0, 0, 1 }},
Package () {"default-state", "on"}
}

})
}

Device (LED2)
{
Name (_HID, "PRP0001")
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"label", DEVICE_NAME:green:led2"},
Package () {"gpios", Package () {^^LEDS, 0, 1, 1 }},
Package () {"default-state", "off"}
}
})
}

Device (LED3)
{
Name (_HID, "PRP0001")
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"label", DEVICE_NAME:green:led3"},
Package () {"gpios", Package () {^^LEDS, 0, 2, 1 }},
Package () {"linux,default-trigger", "heartbeat"}
}
})
}
}
}
19 changes: 17 additions & 2 deletions src/mainboard/pcengines/apu2/dsdt.asl
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Expand Up @@ -28,6 +28,17 @@ DefinitionBlock (
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */

#if CONFIG_BOARD_PCENGINES_APU2
#define DEVICE_NAME "apu2
#elif CONFIG_BOARD_PCENGINES_APU3
#define DEVICE_NAME "apu3
#elif CONFIG_BOARD_PCENGINES_APU4
#define DEVICE_NAME "apu4
#elif CONFIG_BOARD_PCENGINES_APU5
#define DEVICE_NAME "apu5
#endif

/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */

/* Globals for the platform */
Expand Down Expand Up @@ -74,8 +85,8 @@ DefinitionBlock (
/* Describe PCI INT[A-H] for the Southbridge */
#include "acpi/pci_int.asl"



/* Describe the GPIO controller in southbridge */
#include "acpi/gpio.asl"

} /* End \_SB scope */

Expand All @@ -90,5 +101,9 @@ DefinitionBlock (

/* Define the System Indicators for the platform */
#include "acpi/si.asl"

/* GPIO buttons and leds */
#include "acpi/buttons.asl"
#include "acpi/leds.asl"
}
/* End of ASL file */
8 changes: 0 additions & 8 deletions src/mainboard/pcengines/apu2/mainboard.c
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Expand Up @@ -133,14 +133,6 @@ static void mainboard_enable(device_t dev)
sio_dev = dev_find_slot_pnp(0x2E, NCT5104D_GPIO1);
if ( sio_dev ) sio_dev->enabled = 1;
}

struct device *sd_dev = dev_find_slot(0, PCI_DEVFN(0x14, 7));

struct southbridge_amd_pi_hudson_config *sd_chip =
(struct southbridge_amd_pi_hudson_config *)(sd_dev->chip_info);

if (!check_sd3_mode())
sd_chip->sd_mode = 0;
}

static void mainboard_final(void *chip_info) {
Expand Down
5 changes: 4 additions & 1 deletion src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
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Expand Up @@ -51,6 +51,7 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d # SIO NCT5104D
register "irq_trigger_type" = "0"
register "enable_wdt1" = "0"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
Expand All @@ -70,7 +71,9 @@ chip northbridge/amd/pi/00730F01/root_complex
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 2e.8 off end
device pnp 2e.8 on
io 0x60 = 0x220
end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 on end
Expand Down
5 changes: 4 additions & 1 deletion src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
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Expand Up @@ -51,6 +51,7 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d # SIO NCT5104D
register "irq_trigger_type" = "0"
register "enable_wdt1" = "0"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
Expand All @@ -70,7 +71,9 @@ chip northbridge/amd/pi/00730F01/root_complex
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 2e.8 off end
device pnp 2e.8 on
io 0x60 = 0x220
end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 on end
Expand Down
5 changes: 4 additions & 1 deletion src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
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Expand Up @@ -50,6 +50,7 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d # SIO NCT5104D
register "irq_trigger_type" = "0"
register "enable_wdt1" = "0"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
Expand All @@ -69,7 +70,9 @@ chip northbridge/amd/pi/00730F01/root_complex
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 2e.8 off end
device pnp 2e.8 on
io 0x60 = 0x220
end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 on end
Expand Down
5 changes: 4 additions & 1 deletion src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
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Expand Up @@ -51,6 +51,7 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d # SIO NCT5104D
register "irq_trigger_type" = "0"
register "enable_wdt1" = "0"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
Expand All @@ -70,7 +71,9 @@ chip northbridge/amd/pi/00730F01/root_complex
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 2e.8 off end
device pnp 2e.8 on
io 0x60 = 0x220
end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 on end
Expand Down
4 changes: 4 additions & 0 deletions src/southbridge/amd/pi/hudson/sd.c
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Expand Up @@ -24,6 +24,7 @@
#include <device/pci_ops.h>
#include <arch/io.h>
#include "hudson.h"
#include <mainboard/pcengines/apu2/bios_knobs.h>

static void sd_init(struct device *dev)
{
Expand All @@ -35,6 +36,9 @@ static void sd_init(struct device *dev)
struct southbridge_amd_pi_hudson_config *sd_chip =
(struct southbridge_amd_pi_hudson_config *)(dev->chip_info);

if (!check_sd3_mode())
sd_chip->sd_mode = 0;

if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */
pci_write_config32(dev, 0xA4, 0x21FEC8B2);
pci_write_config32(dev, 0xA8, 0x00002503);
Expand Down
1 change: 1 addition & 0 deletions src/superio/nuvoton/nct5104d/chip.h
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Expand Up @@ -19,6 +19,7 @@

struct superio_nuvoton_nct5104d_config {
u8 irq_trigger_type;
u8 enable_wdt1;
};

#endif
7 changes: 6 additions & 1 deletion src/superio/nuvoton/nct5104d/nct5104d.h
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Expand Up @@ -34,11 +34,16 @@
#define NCT5104D_GPIO0_IO 0xE0
#define NCT5104D_GPIO1_IO 0xE4

/* LDN 0x0F specific registers */
#define NCT5104D_GPIO0_PP_OD 0xE0
#define NCT5104D_GPIO1_PP_OD 0xE1

/* Logical Device Numbers (LDN). */
#define NCT5104D_FDC 0x00 /* FDC - not pinned out */
#define NCT5104D_SP1 0x02 /* UARTA */
#define NCT5104D_SP2 0x03 /* UARTB */
#define NCT5104D_GPIO_WDT 0x08 /* GPIO WDT Interface */
#define NCT5104D_GPIO 0x07 /* GPIO In-Out Interface */
#define NCT5104D_GPIO_WDT 0x08 /* GPIO WDT Interface */
#define NCT5104D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select */
#define NCT5104D_SP3 0x10 /* UARTC */
#define NCT5104D_SP4 0x11 /* UARTD */
Expand Down