CHANGELOG.md

@@ -7,6 +7,13 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
 [this gerrit ref](https://review.coreboot.org/#/c/14138/).
 
 ## [Unreleased]
+## [v4.0.30] - 2020-02-25
+### Fixed
+- microSD card boot order on apu5
+
+### Added
+- ARM management controller interaction on apu5
+
 ## [v4.0.29] - 2019-10-07
 ### Fixed
 - SD 3.0 mode is correctly configurable now
@@ -259,7 +266,8 @@ built externally
 - forced to use SD in 2.0 mode
 - git repository in `Makefile`
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.29...coreboot-4.0.x
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.30...coreboot-4.0.x
+[v4.0.30]: https://github.com/pcengines/coreboot/compare/v4.0.29...v4.0.30
 [v4.0.29]: https://github.com/pcengines/coreboot/compare/v4.0.28...v4.0.29
 [v4.0.28]: https://github.com/pcengines/coreboot/compare/v4.0.27...v4.0.28
 [v4.0.27]: https://github.com/pcengines/coreboot/compare/v4.0.26...v4.0.27

src/mainboard/pcengines/apu2/Makefile.inc

@@ -30,11 +30,19 @@ ramstage-y += bios_knobs.c
 ramstage-y += s1_button.c
 
 cbfs-files-y += bootorder_map
+ifeq ($(CONFIG_BOARD_PCENGINES_APU5),y)
+bootorder_map-file := bootorder_map_apu5
+else
 bootorder_map-file := bootorder_map
+endif
 bootorder_map-type := raw
 
 cbfs-files-y += bootorder_def
+ifeq ($(CONFIG_BOARD_PCENGINES_APU5),y)
+bootorder_def-file := bootorder_def_apu5
+else
 bootorder_def-file := bootorder_def
+endif
 bootorder_def-type := raw
 
 # WIV20150126 add boot order

src/mainboard/pcengines/apu2/bootorder_def_apu5

@@ -0,0 +1,29 @@
+/pci@i0cf8/usb@10/usb-*@1
+/pci@i0cf8/usb@10/usb-*@2
+/pci@i0cf8/usb@10/usb-*@3
+/pci@i0cf8/usb@10/usb-*@4
+/pci@i0cf8/usb@12/usb-*@1
+/pci@i0cf8/usb@12/usb-*@2
+/pci@i0cf8/usb@12/usb-*@3
+/pci@i0cf8/usb@12/usb-*@4
+/pci@i0cf8/usb@13/usb-*@1
+/pci@i0cf8/usb@13/usb-*@2
+/pci@i0cf8/usb@13/usb-*@3
+/pci@i0cf8/usb@13/usb-*@4
+/pci@i0cf8/usb@12/hub@1/usb-*@1
+/pci@i0cf8/*@11/drive@0/disk@0
+/pci@i0cf8/*@11/drive@1/disk@0
+/pci@i0cf8/pci-bridge@2,5/*@0/drive@0/disk@0
+/pci@i0cf8/pci-bridge@2,5/*@0/drive@1/disk@0
+/rom@genroms/pxe.rom
+pxen0
+scon1
+usben1
+uartc1
+uartd1
+ehcien0
+mpcie2_clk0
+com2en0
+boosten1
+sd3mode0
+watchdog0000

src/mainboard/pcengines/apu2/bootorder_map_apu5

@@ -0,0 +1,18 @@
+a USB
+a USB
+a USB
+a USB
+a USB
+a USB
+a USB
+a USB
+a USB
+a USB
+a USB
+a USB
+b SDCARD
+c mSATA
+d SATA
+e mPCIe1 SATA1 and SATA2
+e mPCIe1 SATA1 and SATA2
+f iPXE

src/mainboard/pcengines/apu2/romstage.c

@@ -19,6 +19,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <delay.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/acpi.h>
@@ -30,6 +31,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include <console/uart.h>
 #include <cpu/amd/car.h>
 #include <agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
@@ -85,8 +87,66 @@ static const GPIO_CONTROL gGpioInitTable[] = {
 		GPIO_DEFINITION (APU5_BIOS_CONSOLE_GPIO, APU5_BIOS_CONSOLE_FUNC, 0, 0, 0, 0),
 #endif
 		{0xFF, 0xFF, 0xFF}									// Terminator
-	};
+};
 
+static void lpc_mcu_msg(void)
+{
+	unsigned int i, timeout;
+	const char *post_msg = "BIOSBOOT";
+	unsigned char sync_byte = 0;
+
+	if (!IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
+		return;
+
+	uart_init(1);
+
+	for (i = 0; i < 4; i++) {
+		uart_tx_byte(1, 0xe1);
+		uart_tx_flush(1);
+		timeout = 10;
+		while (sync_byte != 0xe1) {
+			sync_byte = uart_rx_byte(1);
+			if (timeout == 0) {
+				uart_init(CONFIG_UART_FOR_CONSOLE);
+				udelay(10000);
+				printk(BIOS_ERR, "Failed to sync with LPC"
+				       " MCU, number of retries %d\n", 3 - i);
+				udelay(10000);
+				uart_init(1);
+				udelay(10000);
+				break;
+			}
+			udelay(100);
+			timeout--;
+		}
+		if (sync_byte == 0xe1)
+			break;
+	}
+
+	if (sync_byte != 0xe1)
+		return;
+
+	uart_init(1);
+	timeout = 10;
+
+	for (i = 0; i < strlen(post_msg); i++)
+		uart_tx_byte(1, *(post_msg + i));
+
+	uart_tx_byte(1, 0xe1);
+	uart_tx_flush(1);
+
+	while (uart_rx_byte(1) != 0xe1) {
+		if (timeout == 0) {
+			uart_init(CONFIG_UART_FOR_CONSOLE);
+			printk(BIOS_ERR, "Did not receive response to BIOSBOOT\n");
+			return;
+		}
+		udelay(100);
+		timeout--;
+	}
+
+	uart_init(CONFIG_UART_FOR_CONSOLE);
+}
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -132,10 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
 		pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
 
-		/* COM2 on apu5 is reserved so only COM1 should be supported */
-		if ((check_com2() || (CONFIG_UART_FOR_CONSOLE == 1)) &&
-		    !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
+		/* Enable UARTB for LPC MCU */
+		if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
+			nuvoton_enable_serial(SERIAL2_DEV, 0x2f8);
+
+		if ((check_com2() || (CONFIG_UART_FOR_CONSOLE == 1)))
 			nuvoton_enable_serial(SERIAL2_DEV, 0x2f8);
+
 		console_init();
 
 		printk(BIOS_INFO, "14-25-48Mhz Clock settings\n");
@@ -265,6 +328,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		printk(BIOS_ALERT, "coreboot build %s\n", tmp);
 		printk(BIOS_ALERT, "BIOS version %s\n", COREBOOT_ORIGIN_GIT_TAG);
 	}
+
+	lpc_mcu_msg();
+
 #if CONFIG_SVI2_SLOW_SPEED
 	/* Force SVI2 to slow speed for APU2 */
 	val = pci_read_config32( d18f3_dev, 0xA0);