CHANGELOG.md

@@ -7,6 +7,10 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
 [this gerrit ref](https://review.coreboot.org/#/c/14138/).
 
 ## [Unreleased]
+## [v4.0.31] - 2020-06-27
+### Fixed
+- [watchdog not causing reset after cold boot](https://github.com/pcengines/coreboot/issues/380)
+
 ## [v4.0.30] - 2020-02-25
 ### Fixed
 - microSD card boot order on apu5
@@ -266,7 +270,8 @@ built externally
 - forced to use SD in 2.0 mode
 - git repository in `Makefile`
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.30...coreboot-4.0.x
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.31...coreboot-4.0.x
+[v4.0.31]: https://github.com/pcengines/coreboot/compare/v4.0.30...v4.0.31
 [v4.0.30]: https://github.com/pcengines/coreboot/compare/v4.0.29...v4.0.30
 [v4.0.29]: https://github.com/pcengines/coreboot/compare/v4.0.28...v4.0.29
 [v4.0.28]: https://github.com/pcengines/coreboot/compare/v4.0.27...v4.0.28

configs/pcengines_apu2.config

@@ -48,7 +48,7 @@ CONFIG_RAMTOP=0x1000000
 CONFIG_HEAP_SIZE=0xc0000
 CONFIG_ACPI_SSDTX_NUM=0
 CONFIG_RAMBASE=0x200000
-CONFIG_HUDSON_LEGACY_FREE=y
+CONFIG_HUDSON_LEGACY_FREE=n
 CONFIG_HUDSON_XHCI_ENABLE=y
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_AGESA_HEAP_MEMTEST=y

configs/pcengines_apu3.config

@@ -48,7 +48,7 @@ CONFIG_RAMTOP=0x1000000
 CONFIG_HEAP_SIZE=0xc0000
 CONFIG_ACPI_SSDTX_NUM=0
 CONFIG_RAMBASE=0x200000
-CONFIG_HUDSON_LEGACY_FREE=y
+CONFIG_HUDSON_LEGACY_FREE=n
 CONFIG_HUDSON_XHCI_ENABLE=y
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_AGESA_HEAP_MEMTEST=y

configs/pcengines_apu4.config

@@ -48,7 +48,7 @@ CONFIG_RAMTOP=0x1000000
 CONFIG_HEAP_SIZE=0xc0000
 CONFIG_ACPI_SSDTX_NUM=0
 CONFIG_RAMBASE=0x200000
-CONFIG_HUDSON_LEGACY_FREE=y
+CONFIG_HUDSON_LEGACY_FREE=n
 CONFIG_HUDSON_XHCI_ENABLE=y
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_AGESA_HEAP_MEMTEST=y

configs/pcengines_apu5.config

@@ -48,7 +48,7 @@ CONFIG_RAMTOP=0x1000000
 CONFIG_HEAP_SIZE=0xc0000
 CONFIG_ACPI_SSDTX_NUM=0
 CONFIG_RAMBASE=0x200000
-CONFIG_HUDSON_LEGACY_FREE=y
+CONFIG_HUDSON_LEGACY_FREE=n
 CONFIG_HUDSON_XHCI_ENABLE=y
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_AGESA_HEAP_MEMTEST=y

src/mainboard/pcengines/apu2/PlatformGnbPcie.c

@@ -19,6 +19,10 @@
 
 #include <northbridge/amd/pi/agesawrapper.h>
 #include "bios_knobs.h"
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#include <smp/node.h>
 
 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
@@ -128,4 +132,25 @@ OemCustomizeInitEarly (
 		InitEarly->PlatformConfig.CStateMode = CStateModeC6;
 		InitEarly->PlatformConfig.CpbMode = CpbModeAuto;
 	}
+
+	/* Enable or disable watchdog depending on the configuration*/
+	if (boot_cpu()){
+		volatile u32 *ptr = (u32 *)(ACPI_MMIO_BASE + WATCHDOG_BASE);
+		u16 watchdog_timeout = get_watchdog_timeout();
+
+		if (watchdog_timeout == 0) {
+			//disable watchdog
+			printk(BIOS_WARNING, "Watchdog is disabled\n");
+			*ptr |= (1 << 3);
+		} else {
+			// enable
+			*ptr &= ~(1 << 3);
+			*ptr |= (1 << 0);
+			// configure timeout
+			*(ptr + 1) = (u16) watchdog_timeout;
+			// trigger
+			*ptr |= (1 << 7);
+			printk(BIOS_WARNING, "Watchdog is enabled, state = 0x%x, time = %d\n", *ptr, *(ptr + 1));
+		}
+	}
 }

src/mainboard/pcengines/apu2/romstage.c

@@ -257,27 +257,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 //			data |= 3 << (3 * 2);	// CLK3
 //
 //			*((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG24)) = data;
-
-		volatile u32 *ptr = (u32 *)(ACPI_MMIO_BASE + WATCHDOG_BASE);
-		u16 watchdog_timeout = get_watchdog_timeout();
-
-		if (watchdog_timeout == 0) {
-			//disable watchdog
-			printk(BIOS_WARNING, "Watchdog is disabled\n");
-			*ptr |= (1 << 3);
-		} else {
-			// enable
-			*ptr &= ~(1 << 3);
-			*ptr |= (1 << 0);
-			// configure timeout
-			*(ptr + 1) = (u16) watchdog_timeout;
-			// trigger
-			*ptr |= (1 << 7);
-
-			printk(BIOS_WARNING, "Watchdog is enabled, state = 0x%x, time = %d\n", *ptr, *(ptr + 1));
-		}
 	}
-
 	/* Halt if there was a built in self test failure */
 	post_code(0x34);
 	report_bist_failure(bist);