.gitlab-ci.yml

@@ -10,6 +10,7 @@ stages:
   - test_rom
   - sign_rom
   - publish_rom
+  - run_regression
 
 check_dependencies:
   stage: check_dependencies
@@ -29,7 +30,7 @@ check_dependencies:
     - git clone https://github.com/pcengines/pce-fw-builder.git /home/coreboot/pce-fw-builder
     - cd /home/coreboot/pce-fw-builder
     - git checkout `git describe --tags --abbrev=0`
-    - ./build.sh release-CI "${CI_COMMIT_REF_NAME}" "${PLATFORM}"
+    - bash -x ./build.sh release-CI "${CI_COMMIT_REF_NAME}" "${PLATFORM}"
     - cp -v /home/coreboot/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom ${RELEASE_DIR}
   artifacts:
     name: ${PLATFORM}
@@ -58,7 +59,7 @@ check_dependencies:
     - docker
   script:
     - cd ${RELEASE_DIR}
-    - sha256sum ${PLATFORM}_${CI_COMMIT_REF_NAME}.rom > ${PLATFORM}_${CI_COMMIT_REF_NAME}.SHA256 
+    - sha256sum ${PLATFORM}_${CI_COMMIT_REF_NAME}.rom > ${PLATFORM}_${CI_COMMIT_REF_NAME}.SHA256
     - ls -la ${RELEASE_DIR}
   artifacts:
     name: ${PLATFORM}
@@ -74,15 +75,45 @@ check_dependencies:
   stage: publish_rom
   tags:
     - docker
+  before_script:
+    - apt-get update
+    - apt-get install curl
   script:
     - ls -al ${RELEASE_DIR}
     - curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL ${UPLOADER_URL}/releases/
     - curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL "${UPLOADER_URL}/releases/${CI_COMMIT_REF_NAME}/"
     - curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom ${UPLOADER_URL}/releases/${CI_COMMIT_REF_NAME}/
     - curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.SHA256 ${UPLOADER_URL}/releases/${CI_COMMIT_REF_NAME}/
+
   only:
     - tags
 
+.run_regression: &run_regression
+  image:
+    name: 3mdeb/rf-docker:0.4.2
+    # https://docs.gitlab.com/ee/ci/docker/using_docker_images.html#overriding-the-entrypoint-of-an-image
+    # https://gitlab.com/gitlab-org/gitlab-runner/-/issues/2692
+    # use EMPTY ENTRYPOINT for docker >17.06
+    entrypoint: [""]
+  variables:
+    PLATFORM:
+    RTE_IP:
+    CONFIG:
+    AUTOFILL: 1
+    FIRMWARE_VERSION: $CI_COMMIT_REF_NAME
+  stage: run_regression
+  tags:
+    - local
+  timeout: 12h
+  before_script:
+    - apt-get update
+    - apt-get install binutils
+  script:
+    - bash -x .gitlab-ci/regression.sh
+  only:
+    - tags
+
+
 build:apu2:
   <<: *build_rom_apu
   variables:
@@ -103,6 +134,13 @@ publish:apu2:
   variables:
     PLATFORM: apu2
 
+regression:apu2:
+  <<: *run_regression
+  variables:
+    PLATFORM: apu2
+    CONFIG: apu2
+    RTE_IP: $RTE_IP_APU2
+
 
 build:apu3:
   <<: *build_rom_apu
@@ -124,6 +162,13 @@ publish:apu3:
   variables:
     PLATFORM: apu3
 
+regression:apu3:
+  <<: *run_regression
+  variables:
+    PLATFORM: apu3
+    CONFIG: apu3
+    RTE_IP: $RTE_IP_APU3
+
 
 build:apu4:
   <<: *build_rom_apu
@@ -145,6 +190,13 @@ publish:apu4:
   variables:
     PLATFORM: apu4
 
+regression:apu4:
+  <<: *run_regression
+  variables:
+    PLATFORM: apu4
+    CONFIG: apu4
+    RTE_IP: $RTE_IP_APU4
+
 
 build:apu5:
   <<: *build_rom_apu
@@ -165,3 +217,10 @@ publish:apu5:
   <<: *publish_rom
   variables:
     PLATFORM: apu5
+
+regression:apu5:
+  <<: *run_regression
+  variables:
+    PLATFORM: apu5
+    CONFIG: apu5
+    RTE_IP: $RTE_IP_APU5

.gitlab-ci/regression.sh

@@ -0,0 +1,18 @@
+#!/bin/bash
+
+git clone https://$GITLAB_ROBOT_USERNAME:$GITLAB_ROBOT_TOKEN@gitlab.com/3mdeb/rte/open-firmware-rte.git
+cd open-firmware-rte
+
+git checkout gitlabci-regression
+sed -i 's+git@gitlab.com:3mdeb/rte/rtectrl-rest-api.git+https://'$GITLAB_ROBOT_USERNAME':'$GITLAB_ROBOT_TOKEN'@gitlab.com/3mdeb/rte/rtectrl-rest-api.git+' .gitmodules
+sed -i 's+git@gitlab.com:3mdeb/rte/snipeit-rest-api.git+https://'$GITLAB_ROBOT_USERNAME':'$GITLAB_ROBOT_TOKEN'@gitlab.com/3mdeb/rte/snipeit-rest-api.git+' .gitmodules
+git submodule update --init --checkout
+
+# legacy or mainline?
+if [[ $FIRMWARE_VERSION =~ v4\.0.* ]]; then
+    export FIRMWARE="l"
+else
+    export FIRMWARE="m"
+fi
+
+bash -cx "./regression.sh ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom"

CHANGELOG.md

@@ -7,6 +7,10 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
 [this gerrit ref](https://review.coreboot.org/#/c/14138/).
 
 ## [Unreleased]
+## [v4.0.32] - 2020-07-29
+### Added
+- [option in runtime config to reverse PCI addressing order](https://github.com/pcengines/coreboot/issues/392)
+
 ## [v4.0.31] - 2020-06-27
 ### Fixed
 - [watchdog not causing reset after cold boot](https://github.com/pcengines/coreboot/issues/380)
@@ -270,7 +274,8 @@ built externally
 - forced to use SD in 2.0 mode
 - git repository in `Makefile`
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.31...coreboot-4.0.x
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.32...coreboot-4.0.x
+[v4.0.32]: https://github.com/pcengines/coreboot/compare/v4.0.31...v4.0.32
 [v4.0.31]: https://github.com/pcengines/coreboot/compare/v4.0.30...v4.0.31
 [v4.0.30]: https://github.com/pcengines/coreboot/compare/v4.0.29...v4.0.30
 [v4.0.29]: https://github.com/pcengines/coreboot/compare/v4.0.28...v4.0.29

payloads/external/sortbootorder/Makefile.inc

@@ -1,4 +1,4 @@
-version=4.6.15
+version=4.6.19
 branch_name=v$(version)
 project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
 archive_name=$(branch_name).tar.gz

src/mainboard/pcengines/apu2/PlatformGnbPcie.c

@@ -78,6 +78,58 @@ const PCIe_PORT_DESCRIPTOR PortList [] = {
 	}
 };
 
+const PCIe_PORT_DESCRIPTOR PortListReverse [] = {
+	{
+		0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x01, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
+	{
+		0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x02, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+	{
+		0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x03, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x04, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+	{
+		DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x05, 0)
+	}
+};
+
 const PCIe_DDI_DESCRIPTOR DdiList [] = {
 	/* DP0 to HDMI0/DP */
 	{
@@ -106,6 +158,13 @@ const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 	.DdiLinkList  = DdiList
 };
 
+const PCIe_COMPLEX_DESCRIPTOR PcieComplexReverse = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortListReverse,
+	.DdiLinkList  = DdiList
+};
+
 /*---------------------------------------------------------------------------------------*/
 /**
  *  OemCustomizeInitEarly
@@ -127,7 +186,11 @@ OemCustomizeInitEarly (
 	IN  OUT AMD_EARLY_PARAMS    *InitEarly
 	)
 {
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	if(check_pciereverse())
+		InitEarly->GnbConfig.PcieComplexList = &PcieComplexReverse;
+	else
+		InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+
 	if(check_boost()) {
 		InitEarly->PlatformConfig.CStateMode = CStateModeC6;
 		InitEarly->PlatformConfig.CpbMode = CpbModeAuto;

src/mainboard/pcengines/apu2/bios_knobs.c

@@ -127,10 +127,29 @@ int check_com2(void)
  	return 0;
 }
 
+int check_pciereverse(void)
+{
+	u8 pciereverse;
+	pciereverse = check_knob_value("pciereverse");
+ 	switch (pciereverse) {
+	case 0:
+		return 0;
+		break;
+	case 1:
+		return 1;
+		break;
+	default:
+		printk(BIOS_INFO, "Missing or invalid pciereverse knob, "
+			"PCIe order remains unchanged.\n");
+		break;
+	}
+ 	return 0;
+}
+
 int check_boost(void)
 {
 	u8 boosten;
- 	//
+	//
 	// Find the boost item
 	//
 	boosten = check_knob_value("boosten");

src/mainboard/pcengines/apu2/bios_knobs.h

@@ -28,6 +28,7 @@ bool check_ehci0(void);
 bool check_mpcie2_clk(void);
 int check_com2(void);
 int check_boost(void);
+int check_pciereverse(void);
 bool check_sd3_mode(void);
 u16 get_watchdog_timeout(void);
 

src/mainboard/pcengines/apu2/bootorder_def

@@ -26,4 +26,5 @@ mpcie2_clk0
 com2en0
 boosten1
 sd3mode0
+pciereverse0
 watchdog0000

src/mainboard/pcengines/apu2/bootorder_def_apu5

@@ -26,4 +26,5 @@ mpcie2_clk0
 com2en0
 boosten1
 sd3mode0
+pciereverse0
 watchdog0000