Showing with 77 additions and 10 deletions.
  1. +1 −1 .gitlab-ci.yml
  2. +9 −1 CHANGELOG.md
  3. +62 −7 src/mainboard/pcengines/apu2/PlatformGnbPcie.c
  4. +5 −1 src/mainboard/pcengines/apu2/mainboard.c
2 changes: 1 addition & 1 deletion .gitlab-ci.yml
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Expand Up @@ -90,7 +90,7 @@ check_dependencies:

.run_regression: &run_regression
image:
name: 3mdeb/rf-docker:0.4.2
name: 3mdeb/rf-docker:1.0.1
# https://docs.gitlab.com/ee/ci/docker/using_docker_images.html#overriding-the-entrypoint-of-an-image
# https://gitlab.com/gitlab-org/gitlab-runner/-/issues/2692
# use EMPTY ENTRYPOINT for docker >17.06
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10 changes: 9 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -7,6 +7,13 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
[this gerrit ref](https://review.coreboot.org/#/c/14138/).

## [Unreleased]

## [v4.0.33] - 2020-10-30
### Fixed
- option in runtime config to reverse PCI addressing order, now not only mPCIe
devices, but NICs are reversed as well. The WoL capable NIC should be the
first booting in iPXE when the reverse option is enabled.

## [v4.0.32] - 2020-07-29
### Added
- [option in runtime config to reverse PCI addressing order](https://github.com/pcengines/coreboot/issues/392)
Expand Down Expand Up @@ -274,7 +281,8 @@ built externally
- forced to use SD in 2.0 mode
- git repository in `Makefile`

[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.32...coreboot-4.0.x
[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.0.33...coreboot-4.0.x
[v4.0.33]: https://github.com/pcengines/coreboot/compare/v4.0.32...v4.0.33
[v4.0.32]: https://github.com/pcengines/coreboot/compare/v4.0.31...v4.0.32
[v4.0.31]: https://github.com/pcengines/coreboot/compare/v4.0.30...v4.0.31
[v4.0.30]: https://github.com/pcengines/coreboot/compare/v4.0.29...v4.0.30
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69 changes: 62 additions & 7 deletions src/mainboard/pcengines/apu2/PlatformGnbPcie.c
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Expand Up @@ -78,7 +78,9 @@ const PCIe_PORT_DESCRIPTOR PortList [] = {
}
};

#if CONFIG_BOARD_PCENGINES_APU2
const PCIe_PORT_DESCRIPTOR PortListReverse [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2.4, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
Expand All @@ -88,17 +90,17 @@ const PCIe_PORT_DESCRIPTOR PortListReverse [] = {
PcieGenMaxSupported,
AspmDisabled, 0x01, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2.1, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x02, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2.2, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
Expand All @@ -108,17 +110,17 @@ const PCIe_PORT_DESCRIPTOR PortListReverse [] = {
PcieGenMaxSupported,
AspmDisabled, 0x03, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
/* Initialize Port descriptor (PCIe port, Lanes 0, PCI Device Number 2.3, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x04, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2.5, ...) */
{
DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
Expand All @@ -129,7 +131,60 @@ const PCIe_PORT_DESCRIPTOR PortListReverse [] = {
AspmDisabled, 0x05, 0)
}
};

#else
const PCIe_PORT_DESCRIPTOR PortListReverse [] = {
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2.5, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x01, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2.1, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x02, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2.2, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x03, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 0, PCI Device Number 2.3, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x04, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2.4, ...) */
{
DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x05, 0)
}
};
#endif
const PCIe_DDI_DESCRIPTOR DdiList [] = {
/* DP0 to HDMI0/DP */
{
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6 changes: 5 additions & 1 deletion src/mainboard/pcengines/apu2/mainboard.c
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Expand Up @@ -256,7 +256,11 @@ const char *smbios_mainboard_serial_number(void)
// bridge and the first NIC is connected to the second PCIe bridge.
// Read secondary bus number from the PCIe bridge where the first NIC is
// connected.
dev = dev_find_slot(0, PCI_DEVFN(2, 2));
if (check_pciereverse())
dev = dev_find_slot(0, PCI_DEVFN(2, 3));
else
dev = dev_find_slot(0, PCI_DEVFN(2, 2));

if ((serial[0] != 0) || !dev)
return serial;

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