Showing 2,048 changed files with 22,284 additions and 21,100 deletions.
diff --git a/.gitignore b/.gitignore
@@ -57,6 +57,7 @@ site-local
 *.\#
 *.bin
 *.debug
+!Kconfig.debug
 *.elf
 *.o
 *.out

diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
diff --git a/AUTHORS b/AUTHORS
@@ -13,19 +13,25 @@ Advanced Micro Devices, Inc.
 Alex Züpke
 Alexander Couzens
 Alexandru Gagniuc
+Analog Devices Inc.
 Andy Fleming
 ARM Limited and Contributors
 Arthur Heymans
+ASPEED Technology Inc.
+Atheros Corporation
+Atmel Corporation
 Carl-Daniel Hailfinger
 coresystems GmbH
 Damien Zammit
+David Brownell
 David Hendricks
 David Mosberger-Tang
 Denis Dowling
 DENX Software Engineering
 DMP Electronics Inc.
 Drew Eckhardt
 Egbert Eich
+Eltan B.V
 Eric Biederman
 Eswar Nallusamy
 Facebook, Inc.
@@ -37,56 +43,75 @@ Gary Jennejohn
 Gerd Hoffmann
 Google LLC
 Greg Watson
+Idwer Vollering
 Imagination Technologies
+Infineon Technologies
 Intel Corporation
 Jason Zhao
+Jonathan Neuschäfer
 Jordan Crouse
 Joseph Smith
 Keith Hui
+Keith Packard
 Kshitij
 Kyösti Mälkki
 Lei Wen
 Li-Ta Lo
 Libra Li
 Linus Torvalds
 Linux Networx, Inc.
+Luc Verhaegen
 Marc Jones
 Marek Vasut
 Marius Gröger
 Martin Mares
+Marvell International Ltd.
 Marvell Semiconductor Inc.
 MediaTek Inc.
 MontaVista Software, Inc.
 Myles Watson
+Network Appliance Inc.
 Nicholas Sielicki
 Nick Barker
 Nico Huber
+Ollie Lo
+Orion Technologies, LLC
 Patrick Georgi
 Patrick Rudolph
 PC Engines GmbH
 Per Odlund
 Peter Stuge
 Raptor Engineering, LLC
+Red Hat Inc
+Reinhard Meyer
 Richard Woodruff
 Ronald G. Minnich
 Rudolf Marek
 Russell King
 Sage Electronic Engineering, LLC
+Samsung Electronics
 SciTech Software, Inc.
+Sebastian Grzywna
 secunet Security Networks AG
 Siemens AG
 Silicon Integrated System Corporation
 Stefan Reinauer
 Steve Magnani
+ST Microelectronics
 SUSE LINUX AG
 Sven Schnelle
 Syed Mohammed Khasim
 Texas Instruments
 The Linux Foundation
+Thomas Winischhofer
 Timothy Pearson
+Tungsten Graphics, Inc.
 Tyan Computer Corp.
+ucRobotics Inc.
 Uwe Hermann
 VIA Technologies, Inc
+Vipin Kumar
+Ward Vandewege
 Wolfgang Denk
 Yinghai Lu
 
@@ -99,3 +124,4 @@ src/commonlib
 src/console
 src/cpu
 src/device
+src/drivers
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -12,6 +12,10 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
 Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
+## [v4.10.0.3] - 2019-11-08
+### Changed
+- rebased with official coreboot repository commit 2d90cb1
+
 ## [v4.10.0.2] - 2019-10-08
 ### Changed
 - rebased with official coreboot repository commit 64c14b5
@@ -344,7 +348,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.10.0.2...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.10.0.3...develop
+[v4.10.0.3]: https://github.com/pcengines/coreboot/compare/v4.10.0.2...v4.10.0.3
 [v4.10.0.2]: https://github.com/pcengines/coreboot/compare/v4.10.0.1...v4.10.0.2
 [v4.10.0.1]: https://github.com/pcengines/coreboot/compare/v4.10.0.0...v4.10.0.1
 [v4.10.0.0]: https://github.com/pcengines/coreboot/compare/v4.9.0.7...v4.10.0.0

diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
@@ -16,24 +16,36 @@ In order to add support for x86_64 the following assumptions are made:
 * The reference implementation is qemu
 * The CPU supports 1GiB hugepages
 
-## Assuptions for ARCH_ROMSTAGE_X86_64 reference implementation
-* 0-4GiB are identity mapped using 1GiB huge-pages
+## Assuptions for all stages using the reference implementation
+* 0-4GiB are identity mapped using 2MiB-pages as WB
 * Memory above 4GiB isn't accessible
-* pagetables reside in _pagetables
-* Romstage must install new pagetables in CBMEM after RAMINIT
+* page tables reside in memory mapped ROM
+* A stage can install new page tables in RAM
 
-## Assuptions for ARCH_RAMSTAGE_X86_64 reference implementation
-* Romstage installed pagetables according to memory layout
-* Memory above 4GiB is accessible
+## Page tables
+Page tables are generated by a tool in `util/pgtblgen/pgtblgen`. It writes
+the page tables to a file which is then included into the CBFS as file called
+`pagetables`.
+
+To generate the static page tables it must know the physical address where to
+place the file.
+
+The page tables contains the following structure:
+* PML4E pointing to PDPE
+* PDPE with *$n* entries each pointing to PDE
+* *$n* PDEs with 512 entries each
+
+At the moment *$n* is 4, which results in identity mapping the lower 4 GiB.
 
 ## Steps to add basic support for x86_64
 * Add x86_64 toolchain support - *DONE*
 * Fix compilation errors - *DONE*
 * Fix linker errors - *TODO*
-* Add x86_64 rmodule support - *ONGERRIT*
+* Add x86_64 rmodule support - *DONE*
 * Add x86_64 exception handlers - *TODO*
-* Setup page tables for long mode - *TODO*
-* Add assembly code for long mode - *TODO*
+* Setup page tables for long mode - *DONE*
+* Add assembly code for long mode - *DONE*
+* Add assembly code for postcar stage - *TODO*
 * Add assembly code to return to protected mode - *TODO*
 * Implement reference code for mainboard `emulation/qemu-q35` - *TODO*
 

diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md
@@ -14,18 +14,40 @@ coreboot uses [Sphinx] documentation tool. We prefer the markdown format
 over reStructuredText so only embedded ReST is supported. Checkout the
 [Markdown Guide] for more information.
 
-### Install Sphinx
+### option 1: Use the docker image
+
+The easiest way to build the documentation is using a docker image.
+To build the image run the following in the base directory:
+
+	make -C util/docker/ doc.coreboot.org
+
+Before building the documentation make sure the output directory is given
+the correct permissions before running docker.
+
+	mkdir -p Documentation/_build
+
+To build the documentation:
+
+	make -C util/docker docker-build-docs
+
+To have the documentation build and served over a web server live run:
+
+	make -C util/docker docker-livehtml-docs
+
+On the host machine, open a browser to the address <http://0.0.0.0:8000>.
+
+### option 2: Install Sphinx
 
 Please follow this official [guide] to install sphinx.
 You will also need python-recommonmark for sphinx to be able to handle
-markdown documenation.
+markdown documentation.
 
 The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and
 recommonmark 0.4.0.
 
 ### Optional
 
-Install [shpinx-autobuild] for rebuilding markdown/rst sources on the fly!
+Install [sphinx-autobuild] for rebuilding markdown/rst sources on the fly!
 
 ## Basic and simple rules
 
@@ -116,7 +138,7 @@ TOC tree.
 
 [coreboot]: https://coreboot.org
 [Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation
-[shpinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild
+[sphinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild
 [guide]: http://www.sphinx-doc.org/en/stable/install.html
 [Sphinx]: http://www.sphinx-doc.org/en/master/
 [Markdown Guide]: https://www.markdownguide.org/

diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md
@@ -7,13 +7,14 @@ Introduction and Current State in coreboot
 *libgfxinit* is a library of full-featured graphics initialization
 (aka. modesetting) drivers. It's implemented in SPARK (a subset of
 Ada with formal verification features). While not restricted to in
-any way, it currently only supports Intel's integrated gfx control-
-lers (GMA).
-
-Currently, it supports the Intel Core i3/i5/i7 processor line and
-will support HDMI and DP on the Atom successor Apollo Lake. At the
-time of writing, Sandy Bridge, Ivy Bridge, and Haswell are veri-
-fied to work within *coreboot*.
+any way, it currently only supports Intel's integrated graphics
+controllers (GMA).
+
+Currently, it supports the Intel Core i3/i5/i7 processor line, HDMI
+and DP on the Apollo Lake processors and everything but SDVO on G45
+and GM45 chipsets. At the time of writing, G45, GM45, everything
+from Arrandale to Coffee Lake, and Apollo Lake are verified to work
+within *coreboot*.
 
 GMA: Framebuffer Configuration
 ------------------------------

diff --git a/Documentation/ifdtool/index.md b/Documentation/ifdtool/index.md
@@ -1,3 +1,4 @@
+# ifdtool
 
 Contents:
 

diff --git a/Documentation/index.md b/Documentation/index.md
@@ -170,7 +170,7 @@ Contents:
 * [coreboot at conferences](community/conferences.md)
 * [Payloads](payloads.md)
 * [Distributions](distributions.md)
-* [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)
+* [Technotes](technotes/index.md)
 * [GPIO toggling in ACPI AML](acpi/gpio.md)
 * [Adding devices to a device tree](acpi/devicetree.md)
 * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)

diff --git a/Documentation/lib/flashmap.md b/Documentation/lib/flashmap.md
@@ -17,7 +17,7 @@ something else) should have its own Flashmap section, and everything else should
 normally go into CBFS.
 
 The Flashmap itself starts with a header `struct fmap` and followed by a list of
-section descriptions in `strcut fmap_area`.
+section descriptions in `struct fmap_area`.
 
 ### Header
 The header `struct fmap` has following fields:

diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md
@@ -70,7 +70,7 @@ facing towards the bottom of the board.
 - The VGA port doesn't work until the OS reinitialises the display.
 
 - There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
+  the Super I/O hardware monitor can only obtain valid CPU temperature
   readings from the PECI agent, but the required driver doesn't exist
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS.

diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md
@@ -49,7 +49,7 @@ region is not readable even by the host.
   suspend.
 
 - There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
+  the Super I/O hardware monitor can only obtain valid CPU temperature
   readings from the PECI agent, whose complete initialisation is not
   publicly documented. The `coretemp` driver can still be used for
   accurate CPU temperature readings.

diff --git a/Documentation/mainboard/asus/p8h61-m_pro.md b/Documentation/mainboard/asus/p8h61-m_pro.md
@@ -46,7 +46,7 @@ region is not readable even by the host.
 ## Known issues
 
 - There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
+  the Super I/O hardware monitor can only obtain valid CPU temperature
   readings from the PECI agent, whose complete initialisation is not
   publicly documented. The `coretemp` driver can still be used for
   accurate CPU temperature readings.

diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md
@@ -5,16 +5,17 @@ This page describes how to run coreboot on the Facebook FBG1701.
 FBG1701 are assembled with different onboard memory modules:
 	Rev 1.0	Onboard Samsung K4B8G1646D-MYKO memory
 	Rev 1.1 and 1.2	Onboard Micron MT41K512M16HA-125A memory
+	Rev 1.3	Onboard Kingston B5116ECMDXGGB memory
 
-Use make menuconfig to configure `onboard memory manufacturer` in Mainboard
-menu.
+Use make menuconfig to configure `onboard memory manufacturer Samsung` in
+Mainboard menu.
 
 ## Required blobs
 
 This board currently requires:
 fsp blob	3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd
 Microcode	Intel Braswell cpuid 1046C4 version 410
-		(Used pre-build binary retrieved from Intel site)
+		(Used pre-built binary retrieved from Intel site)
 
 ## Flashing coreboot
 
@@ -25,7 +26,7 @@ The main SPI flash can be accessed using [flashrom].
 ### External programming
 
 The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
-This chip is located to the top middle side of the board. It's located
+This chip is located on the top middle side of the board. It's located
 between SoC and Q7 connector. Use clip (or solder wires) to program
 the chip.
 Specifically, it's a Winbond W25Q64FW (1.8V), whose datasheet can be found

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -65,9 +65,18 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Mainboard codenames](lenovo/codenames.md)
 - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
+- [R60](lenovo/r60.md)
 - [T4xx common](lenovo/t4xx_series.md)
 - [X2xx common](lenovo/x2xx_series.md)
 
+### Nehalem series
+
+- [T410](lenovo/t410.md)
+
+### GM45 series
+
+- [X301](lenovo/x301.md)
+
 ### Sandy Bridge series
 
 - [T420](lenovo/t420.md)
@@ -82,6 +91,14 @@ The boards in this section are not real mainboards, but emulators.
 - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
 - [T431s](lenovo/t431s.md)
 
+### Haswell series
+
+- [T440p](lenovo/t440p.md)
+
+## Portwell
+
+- [PQ7-M107](portwell/pq7-m107.md)
+
 ## MSI
 
 - [MS-7707](msi/ms7707/ms7707.md)